1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 #include "amdgpu_dev_coredump.h" 34 #include "amdgpu_xgmi.h" 35 36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, 37 struct amdgpu_job *job) 38 { 39 int i; 40 41 dev_info(adev->dev, "Dumping IP State\n"); 42 for (i = 0; i < adev->num_ip_blocks; i++) 43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) 44 adev->ip_blocks[i].version->funcs 45 ->dump_ip_state((void *)&adev->ip_blocks[i]); 46 dev_info(adev->dev, "Dumping IP State Completed\n"); 47 48 amdgpu_coredump(adev, true, false, job); 49 } 50 51 static void amdgpu_job_core_dump(struct amdgpu_device *adev, 52 struct amdgpu_job *job) 53 { 54 struct list_head device_list, *device_list_handle = NULL; 55 struct amdgpu_device *tmp_adev = NULL; 56 struct amdgpu_hive_info *hive = NULL; 57 58 if (!amdgpu_sriov_vf(adev)) 59 hive = amdgpu_get_xgmi_hive(adev); 60 if (hive) 61 mutex_lock(&hive->hive_lock); 62 /* 63 * Reuse the logic in amdgpu_device_gpu_recover() to build list of 64 * devices for code dump 65 */ 66 INIT_LIST_HEAD(&device_list); 67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { 68 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 69 list_add_tail(&tmp_adev->reset_list, &device_list); 70 if (!list_is_first(&adev->reset_list, &device_list)) 71 list_rotate_to_front(&adev->reset_list, &device_list); 72 device_list_handle = &device_list; 73 } else { 74 list_add_tail(&adev->reset_list, &device_list); 75 device_list_handle = &device_list; 76 } 77 78 /* Do the coredump for each device */ 79 list_for_each_entry(tmp_adev, device_list_handle, reset_list) 80 amdgpu_job_do_core_dump(tmp_adev, job); 81 82 if (hive) { 83 mutex_unlock(&hive->hive_lock); 84 amdgpu_put_xgmi_hive(hive); 85 } 86 } 87 88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 89 { 90 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 91 struct amdgpu_job *job = to_amdgpu_job(s_job); 92 struct amdgpu_task_info *ti; 93 struct amdgpu_device *adev = ring->adev; 94 int idx; 95 int r; 96 97 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 98 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s", 99 __func__, s_job->sched->name); 100 101 /* Effectively the job is aborted as the device is gone */ 102 return DRM_GPU_SCHED_STAT_ENODEV; 103 } 104 105 /* 106 * Do the coredump immediately after a job timeout to get a very 107 * close dump/snapshot/representation of GPU's current error status 108 * Skip it for SRIOV, since VF FLR will be triggered by host driver 109 * before job timeout 110 */ 111 if (!amdgpu_sriov_vf(adev)) 112 amdgpu_job_core_dump(adev, job); 113 114 if (amdgpu_gpu_recovery && 115 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 116 dev_err(adev->dev, "ring %s timeout, but soft recovered\n", 117 s_job->sched->name); 118 goto exit; 119 } 120 121 dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n", 122 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 123 ring->fence_drv.sync_seq); 124 125 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid); 126 if (ti) { 127 dev_err(adev->dev, 128 "Process information: process %s pid %d thread %s pid %d\n", 129 ti->process_name, ti->tgid, ti->task_name, ti->pid); 130 amdgpu_vm_put_task_info(ti); 131 } 132 133 /* attempt a per ring reset */ 134 if (amdgpu_gpu_recovery && 135 ring->funcs->reset) { 136 bool is_guilty; 137 138 dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); 139 /* stop the scheduler, but don't mess with the 140 * bad job yet because if ring reset fails 141 * we'll fall back to full GPU reset. 142 */ 143 drm_sched_wqueue_stop(&ring->sched); 144 145 /* for engine resets, we need to reset the engine, 146 * but individual queues may be unaffected. 147 * check here to make sure the accounting is correct. 148 */ 149 if (ring->funcs->is_guilty) 150 is_guilty = ring->funcs->is_guilty(ring); 151 else 152 is_guilty = true; 153 154 if (is_guilty) 155 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 156 157 r = amdgpu_ring_reset(ring, job->vmid); 158 if (!r) { 159 if (amdgpu_ring_sched_ready(ring)) 160 drm_sched_stop(&ring->sched, s_job); 161 if (is_guilty) { 162 atomic_inc(&ring->adev->gpu_reset_counter); 163 amdgpu_fence_driver_force_completion(ring); 164 } 165 if (amdgpu_ring_sched_ready(ring)) 166 drm_sched_start(&ring->sched, 0); 167 goto exit; 168 } 169 dev_err(adev->dev, "Ring %s reset failure\n", ring->sched.name); 170 } 171 dma_fence_set_error(&s_job->s_fence->finished, -ETIME); 172 173 if (amdgpu_device_should_recover_gpu(ring->adev)) { 174 struct amdgpu_reset_context reset_context; 175 memset(&reset_context, 0, sizeof(reset_context)); 176 177 reset_context.method = AMD_RESET_METHOD_NONE; 178 reset_context.reset_req_dev = adev; 179 reset_context.src = AMDGPU_RESET_SRC_JOB; 180 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 181 182 /* 183 * To avoid an unnecessary extra coredump, as we have already 184 * got the very close representation of GPU's error status 185 */ 186 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 187 188 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 189 if (r) 190 dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); 191 } else { 192 drm_sched_suspend_timeout(&ring->sched); 193 if (amdgpu_sriov_vf(adev)) 194 adev->virt.tdr_debug = true; 195 } 196 197 exit: 198 drm_dev_exit(idx); 199 return DRM_GPU_SCHED_STAT_NOMINAL; 200 } 201 202 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, 203 struct drm_sched_entity *entity, void *owner, 204 unsigned int num_ibs, struct amdgpu_job **job) 205 { 206 if (num_ibs == 0) 207 return -EINVAL; 208 209 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 210 if (!*job) 211 return -ENOMEM; 212 213 (*job)->vm = vm; 214 215 amdgpu_sync_create(&(*job)->explicit_sync); 216 (*job)->generation = amdgpu_vm_generation(adev, vm); 217 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 218 219 if (!entity) 220 return 0; 221 222 return drm_sched_job_init(&(*job)->base, entity, 1, owner); 223 } 224 225 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 226 struct drm_sched_entity *entity, void *owner, 227 size_t size, enum amdgpu_ib_pool_type pool_type, 228 struct amdgpu_job **job) 229 { 230 int r; 231 232 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job); 233 if (r) 234 return r; 235 236 (*job)->num_ibs = 1; 237 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 238 if (r) { 239 if (entity) 240 drm_sched_job_cleanup(&(*job)->base); 241 kfree(*job); 242 } 243 244 return r; 245 } 246 247 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 248 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 249 { 250 if (gds) { 251 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 252 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 253 } 254 if (gws) { 255 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 256 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 257 } 258 if (oa) { 259 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 260 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 261 } 262 } 263 264 void amdgpu_job_free_resources(struct amdgpu_job *job) 265 { 266 struct dma_fence *f; 267 unsigned i; 268 269 /* Check if any fences where initialized */ 270 if (job->base.s_fence && job->base.s_fence->finished.ops) 271 f = &job->base.s_fence->finished; 272 else if (job->hw_fence.ops) 273 f = &job->hw_fence; 274 else 275 f = NULL; 276 277 for (i = 0; i < job->num_ibs; ++i) 278 amdgpu_ib_free(&job->ibs[i], f); 279 } 280 281 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 282 { 283 struct amdgpu_job *job = to_amdgpu_job(s_job); 284 285 drm_sched_job_cleanup(s_job); 286 287 amdgpu_sync_free(&job->explicit_sync); 288 289 /* only put the hw fence if has embedded fence */ 290 if (!job->hw_fence.ops) 291 kfree(job); 292 else 293 dma_fence_put(&job->hw_fence); 294 } 295 296 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 297 struct amdgpu_job *leader) 298 { 299 struct dma_fence *fence = &leader->base.s_fence->scheduled; 300 301 WARN_ON(job->gang_submit); 302 303 /* 304 * Don't add a reference when we are the gang leader to avoid circle 305 * dependency. 306 */ 307 if (job != leader) 308 dma_fence_get(fence); 309 job->gang_submit = fence; 310 } 311 312 void amdgpu_job_free(struct amdgpu_job *job) 313 { 314 if (job->base.entity) 315 drm_sched_job_cleanup(&job->base); 316 317 amdgpu_job_free_resources(job); 318 amdgpu_sync_free(&job->explicit_sync); 319 if (job->gang_submit != &job->base.s_fence->scheduled) 320 dma_fence_put(job->gang_submit); 321 322 if (!job->hw_fence.ops) 323 kfree(job); 324 else 325 dma_fence_put(&job->hw_fence); 326 } 327 328 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) 329 { 330 struct dma_fence *f; 331 332 drm_sched_job_arm(&job->base); 333 f = dma_fence_get(&job->base.s_fence->finished); 334 amdgpu_job_free_resources(job); 335 drm_sched_entity_push_job(&job->base); 336 337 return f; 338 } 339 340 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 341 struct dma_fence **fence) 342 { 343 int r; 344 345 job->base.sched = &ring->sched; 346 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 347 348 if (r) 349 return r; 350 351 amdgpu_job_free(job); 352 return 0; 353 } 354 355 static struct dma_fence * 356 amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 357 struct drm_sched_entity *s_entity) 358 { 359 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 360 struct amdgpu_job *job = to_amdgpu_job(sched_job); 361 struct dma_fence *fence = NULL; 362 int r; 363 364 r = drm_sched_entity_error(s_entity); 365 if (r) 366 goto error; 367 368 if (job->gang_submit) 369 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 370 371 if (!fence && job->vm && !job->vmid) { 372 r = amdgpu_vmid_grab(job->vm, ring, job, &fence); 373 if (r) { 374 dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); 375 goto error; 376 } 377 /* 378 * The VM structure might be released after the VMID is 379 * assigned, we had multiple problems with people trying to use 380 * the VM pointer so better set it to NULL. 381 */ 382 if (!fence) 383 job->vm = NULL; 384 } 385 386 return fence; 387 388 error: 389 dma_fence_set_error(&job->base.s_fence->finished, r); 390 return NULL; 391 } 392 393 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 394 { 395 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 396 struct amdgpu_device *adev = ring->adev; 397 struct dma_fence *fence = NULL, *finished; 398 struct amdgpu_job *job; 399 int r = 0; 400 401 job = to_amdgpu_job(sched_job); 402 finished = &job->base.s_fence->finished; 403 404 trace_amdgpu_sched_run_job(job); 405 406 /* Skip job if VRAM is lost and never resubmit gangs */ 407 if (job->generation != amdgpu_vm_generation(adev, job->vm) || 408 (job->job_run_counter && job->gang_submit)) 409 dma_fence_set_error(finished, -ECANCELED); 410 411 if (finished->error < 0) { 412 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)", 413 ring->name); 414 } else { 415 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 416 &fence); 417 if (r) 418 dev_err(adev->dev, 419 "Error scheduling IBs (%d) in ring(%s)", r, 420 ring->name); 421 } 422 423 job->job_run_counter++; 424 amdgpu_job_free_resources(job); 425 426 fence = r ? ERR_PTR(r) : fence; 427 return fence; 428 } 429 430 #define to_drm_sched_job(sched_job) \ 431 container_of((sched_job), struct drm_sched_job, queue_node) 432 433 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 434 { 435 struct drm_sched_job *s_job; 436 struct drm_sched_entity *s_entity = NULL; 437 int i; 438 439 /* Signal all jobs not yet scheduled */ 440 for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { 441 struct drm_sched_rq *rq = sched->sched_rq[i]; 442 spin_lock(&rq->lock); 443 list_for_each_entry(s_entity, &rq->entities, list) { 444 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 445 struct drm_sched_fence *s_fence = s_job->s_fence; 446 447 dma_fence_signal(&s_fence->scheduled); 448 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 449 dma_fence_signal(&s_fence->finished); 450 } 451 } 452 spin_unlock(&rq->lock); 453 } 454 455 /* Signal all jobs already scheduled to HW */ 456 list_for_each_entry(s_job, &sched->pending_list, list) { 457 struct drm_sched_fence *s_fence = s_job->s_fence; 458 459 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 460 dma_fence_signal(&s_fence->finished); 461 } 462 } 463 464 const struct drm_sched_backend_ops amdgpu_sched_ops = { 465 .prepare_job = amdgpu_job_prepare_job, 466 .run_job = amdgpu_job_run, 467 .timedout_job = amdgpu_job_timedout, 468 .free_job = amdgpu_job_free_cb 469 }; 470