1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/irq.h>
29 #include <drm/drmP.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_ih.h"
34 #include "atom.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_trace.h"
37 
38 #include <linux/pm_runtime.h>
39 
40 #ifdef CONFIG_DRM_AMD_DC
41 #include "amdgpu_dm_irq.h"
42 #endif
43 
44 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
45 
46 /*
47  * Handle hotplug events outside the interrupt handler proper.
48  */
49 /**
50  * amdgpu_hotplug_work_func - display hotplug work handler
51  *
52  * @work: work struct
53  *
54  * This is the hot plug event work handler (all asics).
55  * The work gets scheduled from the irq handler if there
56  * was a hot plug interrupt.  It walks the connector table
57  * and calls the hotplug handler for each one, then sends
58  * a drm hotplug event to alert userspace.
59  */
60 static void amdgpu_hotplug_work_func(struct work_struct *work)
61 {
62 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
63 						  hotplug_work);
64 	struct drm_device *dev = adev->ddev;
65 	struct drm_mode_config *mode_config = &dev->mode_config;
66 	struct drm_connector *connector;
67 
68 	mutex_lock(&mode_config->mutex);
69 	list_for_each_entry(connector, &mode_config->connector_list, head)
70 		amdgpu_connector_hotplug(connector);
71 	mutex_unlock(&mode_config->mutex);
72 	/* Just fire off a uevent and let userspace tell us what to do */
73 	drm_helper_hpd_irq_event(dev);
74 }
75 
76 /**
77  * amdgpu_irq_reset_work_func - execute gpu reset
78  *
79  * @work: work struct
80  *
81  * Execute scheduled gpu reset (cayman+).
82  * This function is called when the irq handler
83  * thinks we need a gpu reset.
84  */
85 static void amdgpu_irq_reset_work_func(struct work_struct *work)
86 {
87 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
88 						  reset_work);
89 
90 	if (!amdgpu_sriov_vf(adev))
91 		amdgpu_device_gpu_recover(adev, NULL, false);
92 }
93 
94 /* Disable *all* interrupts */
95 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
96 {
97 	unsigned long irqflags;
98 	unsigned i, j, k;
99 	int r;
100 
101 	spin_lock_irqsave(&adev->irq.lock, irqflags);
102 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
103 		if (!adev->irq.client[i].sources)
104 			continue;
105 
106 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
107 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
108 
109 			if (!src || !src->funcs->set || !src->num_types)
110 				continue;
111 
112 			for (k = 0; k < src->num_types; ++k) {
113 				atomic_set(&src->enabled_types[k], 0);
114 				r = src->funcs->set(adev, src, k,
115 						    AMDGPU_IRQ_STATE_DISABLE);
116 				if (r)
117 					DRM_ERROR("error disabling interrupt (%d)\n",
118 						  r);
119 			}
120 		}
121 	}
122 	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
123 }
124 
125 /**
126  * amdgpu_irq_handler - irq handler
127  *
128  * @int irq, void *arg: args
129  *
130  * This is the irq handler for the amdgpu driver (all asics).
131  */
132 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
133 {
134 	struct drm_device *dev = (struct drm_device *) arg;
135 	struct amdgpu_device *adev = dev->dev_private;
136 	irqreturn_t ret;
137 
138 	ret = amdgpu_ih_process(adev);
139 	if (ret == IRQ_HANDLED)
140 		pm_runtime_mark_last_busy(dev->dev);
141 	return ret;
142 }
143 
144 /**
145  * amdgpu_msi_ok - asic specific msi checks
146  *
147  * @adev: amdgpu device pointer
148  *
149  * Handles asic specific MSI checks to determine if
150  * MSIs should be enabled on a particular chip (all asics).
151  * Returns true if MSIs should be enabled, false if MSIs
152  * should not be enabled.
153  */
154 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
155 {
156 	/* force MSI on */
157 	if (amdgpu_msi == 1)
158 		return true;
159 	else if (amdgpu_msi == 0)
160 		return false;
161 
162 	return true;
163 }
164 
165 /**
166  * amdgpu_irq_init - init driver interrupt info
167  *
168  * @adev: amdgpu device pointer
169  *
170  * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
171  * Returns 0 for success, error for failure.
172  */
173 int amdgpu_irq_init(struct amdgpu_device *adev)
174 {
175 	int r = 0;
176 
177 	spin_lock_init(&adev->irq.lock);
178 
179 	/* enable msi */
180 	adev->irq.msi_enabled = false;
181 
182 	if (amdgpu_msi_ok(adev)) {
183 		int ret = pci_enable_msi(adev->pdev);
184 		if (!ret) {
185 			adev->irq.msi_enabled = true;
186 			dev_dbg(adev->dev, "amdgpu: using MSI.\n");
187 		}
188 	}
189 
190 	if (!amdgpu_device_has_dc_support(adev)) {
191 		if (!adev->enable_virtual_display)
192 			/* Disable vblank irqs aggressively for power-saving */
193 			/* XXX: can this be enabled for DC? */
194 			adev->ddev->vblank_disable_immediate = true;
195 
196 		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
197 		if (r)
198 			return r;
199 
200 		/* pre DCE11 */
201 		INIT_WORK(&adev->hotplug_work,
202 				amdgpu_hotplug_work_func);
203 	}
204 
205 	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
206 
207 	adev->irq.installed = true;
208 	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
209 	if (r) {
210 		adev->irq.installed = false;
211 		if (!amdgpu_device_has_dc_support(adev))
212 			flush_work(&adev->hotplug_work);
213 		cancel_work_sync(&adev->reset_work);
214 		return r;
215 	}
216 	adev->ddev->max_vblank_count = 0x00ffffff;
217 
218 	DRM_DEBUG("amdgpu: irq initialized.\n");
219 	return 0;
220 }
221 
222 /**
223  * amdgpu_irq_fini - tear down driver interrupt info
224  *
225  * @adev: amdgpu device pointer
226  *
227  * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
228  */
229 void amdgpu_irq_fini(struct amdgpu_device *adev)
230 {
231 	unsigned i, j;
232 
233 	if (adev->irq.installed) {
234 		drm_irq_uninstall(adev->ddev);
235 		adev->irq.installed = false;
236 		if (adev->irq.msi_enabled)
237 			pci_disable_msi(adev->pdev);
238 		if (!amdgpu_device_has_dc_support(adev))
239 			flush_work(&adev->hotplug_work);
240 		cancel_work_sync(&adev->reset_work);
241 	}
242 
243 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
244 		if (!adev->irq.client[i].sources)
245 			continue;
246 
247 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
248 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
249 
250 			if (!src)
251 				continue;
252 
253 			kfree(src->enabled_types);
254 			src->enabled_types = NULL;
255 			if (src->data) {
256 				kfree(src->data);
257 				kfree(src);
258 				adev->irq.client[i].sources[j] = NULL;
259 			}
260 		}
261 		kfree(adev->irq.client[i].sources);
262 	}
263 }
264 
265 /**
266  * amdgpu_irq_add_id - register irq source
267  *
268  * @adev: amdgpu device pointer
269  * @src_id: source id for this source
270  * @source: irq source
271  *
272  */
273 int amdgpu_irq_add_id(struct amdgpu_device *adev,
274 		      unsigned client_id, unsigned src_id,
275 		      struct amdgpu_irq_src *source)
276 {
277 	if (client_id >= AMDGPU_IH_CLIENTID_MAX)
278 		return -EINVAL;
279 
280 	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
281 		return -EINVAL;
282 
283 	if (!source->funcs)
284 		return -EINVAL;
285 
286 	if (!adev->irq.client[client_id].sources) {
287 		adev->irq.client[client_id].sources =
288 			kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
289 				sizeof(struct amdgpu_irq_src *),
290 				GFP_KERNEL);
291 		if (!adev->irq.client[client_id].sources)
292 			return -ENOMEM;
293 	}
294 
295 	if (adev->irq.client[client_id].sources[src_id] != NULL)
296 		return -EINVAL;
297 
298 	if (source->num_types && !source->enabled_types) {
299 		atomic_t *types;
300 
301 		types = kcalloc(source->num_types, sizeof(atomic_t),
302 				GFP_KERNEL);
303 		if (!types)
304 			return -ENOMEM;
305 
306 		source->enabled_types = types;
307 	}
308 
309 	adev->irq.client[client_id].sources[src_id] = source;
310 	return 0;
311 }
312 
313 /**
314  * amdgpu_irq_dispatch - dispatch irq to IP blocks
315  *
316  * @adev: amdgpu device pointer
317  * @entry: interrupt vector
318  *
319  * Dispatches the irq to the different IP blocks
320  */
321 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
322 			 struct amdgpu_iv_entry *entry)
323 {
324 	unsigned client_id = entry->client_id;
325 	unsigned src_id = entry->src_id;
326 	struct amdgpu_irq_src *src;
327 	int r;
328 
329 	trace_amdgpu_iv(entry);
330 
331 	if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
332 		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
333 		return;
334 	}
335 
336 	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
337 		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
338 		return;
339 	}
340 
341 	if (adev->irq.virq[src_id]) {
342 		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
343 	} else {
344 		if (!adev->irq.client[client_id].sources) {
345 			DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
346 				  client_id, src_id);
347 			return;
348 		}
349 
350 		src = adev->irq.client[client_id].sources[src_id];
351 		if (!src) {
352 			DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
353 			return;
354 		}
355 
356 		r = src->funcs->process(adev, src, entry);
357 		if (r)
358 			DRM_ERROR("error processing interrupt (%d)\n", r);
359 	}
360 }
361 
362 /**
363  * amdgpu_irq_update - update hw interrupt state
364  *
365  * @adev: amdgpu device pointer
366  * @src: interrupt src you want to enable
367  * @type: type of interrupt you want to update
368  *
369  * Updates the interrupt state for a specific src (all asics).
370  */
371 int amdgpu_irq_update(struct amdgpu_device *adev,
372 			     struct amdgpu_irq_src *src, unsigned type)
373 {
374 	unsigned long irqflags;
375 	enum amdgpu_interrupt_state state;
376 	int r;
377 
378 	spin_lock_irqsave(&adev->irq.lock, irqflags);
379 
380 	/* we need to determine after taking the lock, otherwise
381 	   we might disable just enabled interrupts again */
382 	if (amdgpu_irq_enabled(adev, src, type))
383 		state = AMDGPU_IRQ_STATE_ENABLE;
384 	else
385 		state = AMDGPU_IRQ_STATE_DISABLE;
386 
387 	r = src->funcs->set(adev, src, type, state);
388 	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
389 	return r;
390 }
391 
392 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
393 {
394 	int i, j, k;
395 
396 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
397 		if (!adev->irq.client[i].sources)
398 			continue;
399 
400 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
401 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
402 
403 			if (!src)
404 				continue;
405 			for (k = 0; k < src->num_types; k++)
406 				amdgpu_irq_update(adev, src, k);
407 		}
408 	}
409 }
410 
411 /**
412  * amdgpu_irq_get - enable interrupt
413  *
414  * @adev: amdgpu device pointer
415  * @src: interrupt src you want to enable
416  * @type: type of interrupt you want to enable
417  *
418  * Enables the interrupt type for a specific src (all asics).
419  */
420 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
421 		   unsigned type)
422 {
423 	if (!adev->ddev->irq_enabled)
424 		return -ENOENT;
425 
426 	if (type >= src->num_types)
427 		return -EINVAL;
428 
429 	if (!src->enabled_types || !src->funcs->set)
430 		return -EINVAL;
431 
432 	if (atomic_inc_return(&src->enabled_types[type]) == 1)
433 		return amdgpu_irq_update(adev, src, type);
434 
435 	return 0;
436 }
437 
438 /**
439  * amdgpu_irq_put - disable interrupt
440  *
441  * @adev: amdgpu device pointer
442  * @src: interrupt src you want to disable
443  * @type: type of interrupt you want to disable
444  *
445  * Disables the interrupt type for a specific src (all asics).
446  */
447 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
448 		   unsigned type)
449 {
450 	if (!adev->ddev->irq_enabled)
451 		return -ENOENT;
452 
453 	if (type >= src->num_types)
454 		return -EINVAL;
455 
456 	if (!src->enabled_types || !src->funcs->set)
457 		return -EINVAL;
458 
459 	if (atomic_dec_and_test(&src->enabled_types[type]))
460 		return amdgpu_irq_update(adev, src, type);
461 
462 	return 0;
463 }
464 
465 /**
466  * amdgpu_irq_enabled - test if irq is enabled or not
467  *
468  * @adev: amdgpu device pointer
469  * @idx: interrupt src you want to test
470  *
471  * Tests if the given interrupt source is enabled or not
472  */
473 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
474 			unsigned type)
475 {
476 	if (!adev->ddev->irq_enabled)
477 		return false;
478 
479 	if (type >= src->num_types)
480 		return false;
481 
482 	if (!src->enabled_types || !src->funcs->set)
483 		return false;
484 
485 	return !!atomic_read(&src->enabled_types[type]);
486 }
487 
488 /* gen irq */
489 static void amdgpu_irq_mask(struct irq_data *irqd)
490 {
491 	/* XXX */
492 }
493 
494 static void amdgpu_irq_unmask(struct irq_data *irqd)
495 {
496 	/* XXX */
497 }
498 
499 static struct irq_chip amdgpu_irq_chip = {
500 	.name = "amdgpu-ih",
501 	.irq_mask = amdgpu_irq_mask,
502 	.irq_unmask = amdgpu_irq_unmask,
503 };
504 
505 static int amdgpu_irqdomain_map(struct irq_domain *d,
506 				unsigned int irq, irq_hw_number_t hwirq)
507 {
508 	if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
509 		return -EPERM;
510 
511 	irq_set_chip_and_handler(irq,
512 				 &amdgpu_irq_chip, handle_simple_irq);
513 	return 0;
514 }
515 
516 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
517 	.map = amdgpu_irqdomain_map,
518 };
519 
520 /**
521  * amdgpu_irq_add_domain - create a linear irq domain
522  *
523  * @adev: amdgpu device pointer
524  *
525  * Create an irq domain for GPU interrupt sources
526  * that may be driven by another driver (e.g., ACP).
527  */
528 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
529 {
530 	adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
531 						 &amdgpu_hw_irqdomain_ops, adev);
532 	if (!adev->irq.domain) {
533 		DRM_ERROR("GPU irq add domain failed\n");
534 		return -ENODEV;
535 	}
536 
537 	return 0;
538 }
539 
540 /**
541  * amdgpu_irq_remove_domain - remove the irq domain
542  *
543  * @adev: amdgpu device pointer
544  *
545  * Remove the irq domain for GPU interrupt sources
546  * that may be driven by another driver (e.g., ACP).
547  */
548 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
549 {
550 	if (adev->irq.domain) {
551 		irq_domain_remove(adev->irq.domain);
552 		adev->irq.domain = NULL;
553 	}
554 }
555 
556 /**
557  * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
558  *                             Linux irq
559  *
560  * @adev: amdgpu device pointer
561  * @src_id: IH source id
562  *
563  * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
564  * Use this for components that generate a GPU interrupt, but are driven
565  * by a different driver (e.g., ACP).
566  * Returns the Linux irq.
567  */
568 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
569 {
570 	adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
571 
572 	return adev->irq.virq[src_id];
573 }
574