1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <drm/drmP.h>
32 #include <drm/amdgpu_drm.h>
33 #include "amdgpu.h"
34 #include "atom.h"
35 
36 /*
37  * IB
38  * IBs (Indirect Buffers) and areas of GPU accessible memory where
39  * commands are stored.  You can put a pointer to the IB in the
40  * command ring and the hw will fetch the commands from the IB
41  * and execute them.  Generally userspace acceleration drivers
42  * produce command buffers which are send to the kernel and
43  * put in IBs for execution by the requested ring.
44  */
45 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
46 
47 /**
48  * amdgpu_ib_get - request an IB (Indirect Buffer)
49  *
50  * @ring: ring index the IB is associated with
51  * @size: requested IB size
52  * @ib: IB object returned
53  *
54  * Request an IB (all asics).  IBs are allocated using the
55  * suballocator.
56  * Returns 0 on success, error on failure.
57  */
58 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
59 		  unsigned size, struct amdgpu_ib *ib)
60 {
61 	int r;
62 
63 	if (size) {
64 		r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
65 				      &ib->sa_bo, size, 256);
66 		if (r) {
67 			dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
68 			return r;
69 		}
70 
71 		ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
72 
73 		if (!vm)
74 			ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
75 	}
76 
77 	return 0;
78 }
79 
80 /**
81  * amdgpu_ib_free - free an IB (Indirect Buffer)
82  *
83  * @adev: amdgpu_device pointer
84  * @ib: IB object to free
85  * @f: the fence SA bo need wait on for the ib alloation
86  *
87  * Free an IB (all asics).
88  */
89 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
90 		    struct fence *f)
91 {
92 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
93 }
94 
95 /**
96  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
97  *
98  * @adev: amdgpu_device pointer
99  * @num_ibs: number of IBs to schedule
100  * @ibs: IB objects to schedule
101  * @f: fence created during this submission
102  *
103  * Schedule an IB on the associated ring (all asics).
104  * Returns 0 on success, error on failure.
105  *
106  * On SI, there are two parallel engines fed from the primary ring,
107  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
108  * resource descriptors have moved to memory, the CE allows you to
109  * prime the caches while the DE is updating register state so that
110  * the resource descriptors will be already in cache when the draw is
111  * processed.  To accomplish this, the userspace driver submits two
112  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
113  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
114  * to SI there was just a DE IB.
115  */
116 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
117 		       struct amdgpu_ib *ibs, struct fence *last_vm_update,
118 		       struct amdgpu_job *job, struct fence **f)
119 {
120 	struct amdgpu_device *adev = ring->adev;
121 	struct amdgpu_ib *ib = &ibs[0];
122 	bool skip_preamble, need_ctx_switch;
123 	unsigned patch_offset = ~0;
124 	struct amdgpu_vm *vm;
125 	struct fence *hwf;
126 	uint64_t ctx;
127 
128 	unsigned i;
129 	int r = 0;
130 
131 	if (num_ibs == 0)
132 		return -EINVAL;
133 
134 	/* ring tests don't use a job */
135 	if (job) {
136 		vm = job->vm;
137 		ctx = job->ctx;
138 	} else {
139 		vm = NULL;
140 		ctx = 0;
141 	}
142 
143 	if (!ring->ready) {
144 		dev_err(adev->dev, "couldn't schedule ib\n");
145 		return -EINVAL;
146 	}
147 
148 	if (vm && !job->vm_id) {
149 		dev_err(adev->dev, "VM IB without ID\n");
150 		return -EINVAL;
151 	}
152 
153 	r = amdgpu_ring_alloc(ring, 256 * num_ibs);
154 	if (r) {
155 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
156 		return r;
157 	}
158 
159 	if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec)
160 		patch_offset = amdgpu_ring_init_cond_exec(ring);
161 
162 	if (vm) {
163 		r = amdgpu_vm_flush(ring, job);
164 		if (r) {
165 			amdgpu_ring_undo(ring);
166 			return r;
167 		}
168 	}
169 
170 	if (ring->funcs->emit_hdp_flush)
171 		amdgpu_ring_emit_hdp_flush(ring);
172 
173 	/* always set cond_exec_polling to CONTINUE */
174 	*ring->cond_exe_cpu_addr = 1;
175 
176 	skip_preamble = ring->current_ctx == ctx;
177 	need_ctx_switch = ring->current_ctx != ctx;
178 	for (i = 0; i < num_ibs; ++i) {
179 		ib = &ibs[i];
180 
181 		/* drop preamble IBs if we don't have a context switch */
182 		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
183 			continue;
184 
185 		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
186 				    need_ctx_switch);
187 		need_ctx_switch = false;
188 	}
189 
190 	if (ring->funcs->emit_hdp_invalidate)
191 		amdgpu_ring_emit_hdp_invalidate(ring);
192 
193 	r = amdgpu_fence_emit(ring, &hwf);
194 	if (r) {
195 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
196 		if (job && job->vm_id)
197 			amdgpu_vm_reset_id(adev, job->vm_id);
198 		amdgpu_ring_undo(ring);
199 		return r;
200 	}
201 
202 	/* wrap the last IB with fence */
203 	if (job && job->uf_addr) {
204 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
205 				       AMDGPU_FENCE_FLAG_64BIT);
206 	}
207 
208 	if (f)
209 		*f = fence_get(hwf);
210 
211 	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
212 		amdgpu_ring_patch_cond_exec(ring, patch_offset);
213 
214 	ring->current_ctx = ctx;
215 	amdgpu_ring_commit(ring);
216 	return 0;
217 }
218 
219 /**
220  * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
221  *
222  * @adev: amdgpu_device pointer
223  *
224  * Initialize the suballocator to manage a pool of memory
225  * for use as IBs (all asics).
226  * Returns 0 on success, error on failure.
227  */
228 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
229 {
230 	int r;
231 
232 	if (adev->ib_pool_ready) {
233 		return 0;
234 	}
235 	r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
236 				      AMDGPU_IB_POOL_SIZE*64*1024,
237 				      AMDGPU_GPU_PAGE_SIZE,
238 				      AMDGPU_GEM_DOMAIN_GTT);
239 	if (r) {
240 		return r;
241 	}
242 
243 	r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
244 	if (r) {
245 		return r;
246 	}
247 
248 	adev->ib_pool_ready = true;
249 	if (amdgpu_debugfs_sa_init(adev)) {
250 		dev_err(adev->dev, "failed to register debugfs file for SA\n");
251 	}
252 	return 0;
253 }
254 
255 /**
256  * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
257  *
258  * @adev: amdgpu_device pointer
259  *
260  * Tear down the suballocator managing the pool of memory
261  * for use as IBs (all asics).
262  */
263 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
264 {
265 	if (adev->ib_pool_ready) {
266 		amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
267 		amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
268 		adev->ib_pool_ready = false;
269 	}
270 }
271 
272 /**
273  * amdgpu_ib_ring_tests - test IBs on the rings
274  *
275  * @adev: amdgpu_device pointer
276  *
277  * Test an IB (Indirect Buffer) on each ring.
278  * If the test fails, disable the ring.
279  * Returns 0 on success, error if the primary GFX ring
280  * IB test fails.
281  */
282 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
283 {
284 	unsigned i;
285 	int r;
286 
287 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
288 		struct amdgpu_ring *ring = adev->rings[i];
289 
290 		if (!ring || !ring->ready)
291 			continue;
292 
293 		r = amdgpu_ring_test_ib(ring);
294 		if (r) {
295 			ring->ready = false;
296 
297 			if (ring == &adev->gfx.gfx_ring[0]) {
298 				/* oh, oh, that's really bad */
299 				DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
300 				adev->accel_working = false;
301 				return r;
302 
303 			} else {
304 				/* still not good, but we can live with it */
305 				DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
306 			}
307 		}
308 	}
309 	return 0;
310 }
311 
312 /*
313  * Debugfs info
314  */
315 #if defined(CONFIG_DEBUG_FS)
316 
317 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
318 {
319 	struct drm_info_node *node = (struct drm_info_node *) m->private;
320 	struct drm_device *dev = node->minor->dev;
321 	struct amdgpu_device *adev = dev->dev_private;
322 
323 	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
324 
325 	return 0;
326 
327 }
328 
329 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
330 	{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
331 };
332 
333 #endif
334 
335 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
336 {
337 #if defined(CONFIG_DEBUG_FS)
338 	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
339 #else
340 	return 0;
341 #endif
342 }
343