1b291a387SHawking Zhang /*
2b291a387SHawking Zhang  * Copyright 2020 Advanced Micro Devices, Inc.
3b291a387SHawking Zhang  *
4b291a387SHawking Zhang  * Permission is hereby granted, free of charge, to any person obtaining a
5b291a387SHawking Zhang  * copy of this software and associated documentation files (the "Software"),
6b291a387SHawking Zhang  * to deal in the Software without restriction, including without limitation
7b291a387SHawking Zhang  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b291a387SHawking Zhang  * and/or sell copies of the Software, and to permit persons to whom the
9b291a387SHawking Zhang  * Software is furnished to do so, subject to the following conditions:
10b291a387SHawking Zhang  *
11b291a387SHawking Zhang  * The above copyright notice and this permission notice shall be included in
12b291a387SHawking Zhang  * all copies or substantial portions of the Software.
13b291a387SHawking Zhang  *
14b291a387SHawking Zhang  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b291a387SHawking Zhang  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b291a387SHawking Zhang  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17b291a387SHawking Zhang  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b291a387SHawking Zhang  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b291a387SHawking Zhang  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b291a387SHawking Zhang  * OTHER DEALINGS IN THE SOFTWARE.
21b291a387SHawking Zhang  *
22b291a387SHawking Zhang  */
23b291a387SHawking Zhang #ifndef __AMDGPU_HDP_H__
24b291a387SHawking Zhang #define __AMDGPU_HDP_H__
25b291a387SHawking Zhang 
268f4a9293SHawking Zhang struct amdgpu_hdp_ras_funcs {
278f4a9293SHawking Zhang 	int (*ras_late_init)(struct amdgpu_device *adev);
288f4a9293SHawking Zhang 	void (*ras_fini)(struct amdgpu_device *adev);
298f4a9293SHawking Zhang 	void (*query_ras_error_count)(struct amdgpu_device *adev,
308f4a9293SHawking Zhang 				      void *ras_error_status);
318f4a9293SHawking Zhang 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
328f4a9293SHawking Zhang };
338f4a9293SHawking Zhang 
34b291a387SHawking Zhang struct amdgpu_hdp_funcs {
35b291a387SHawking Zhang 	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
36b291a387SHawking Zhang 	void (*invalidate_hdp)(struct amdgpu_device *adev,
37b291a387SHawking Zhang 			       struct amdgpu_ring *ring);
38b291a387SHawking Zhang 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
39b291a387SHawking Zhang 	void (*update_clock_gating)(struct amdgpu_device *adev, bool enable);
40b291a387SHawking Zhang 	void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags);
41b291a387SHawking Zhang 	void (*init_registers)(struct amdgpu_device *adev);
42b291a387SHawking Zhang };
43b291a387SHawking Zhang 
44b291a387SHawking Zhang struct amdgpu_hdp {
458f4a9293SHawking Zhang 	struct ras_common_if			*ras_if;
46b291a387SHawking Zhang 	const struct amdgpu_hdp_funcs		*funcs;
478f4a9293SHawking Zhang 	const struct amdgpu_hdp_ras_funcs	*ras_funcs;
48b291a387SHawking Zhang };
49b291a387SHawking Zhang 
50*b11625f5SHawking Zhang int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
51*b11625f5SHawking Zhang void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
52b291a387SHawking Zhang #endif /* __AMDGPU_HDP_H__ */
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