1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <drm/drmP.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 33 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 34 { 35 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 36 37 if (robj) { 38 if (robj->gem_base.import_attach) 39 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 40 amdgpu_mn_unregister(robj); 41 amdgpu_bo_unref(&robj); 42 } 43 } 44 45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 46 int alignment, u32 initial_domain, 47 u64 flags, bool kernel, 48 struct drm_gem_object **obj) 49 { 50 struct amdgpu_bo *robj; 51 unsigned long max_size; 52 int r; 53 54 *obj = NULL; 55 /* At least align on page size */ 56 if (alignment < PAGE_SIZE) { 57 alignment = PAGE_SIZE; 58 } 59 60 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { 61 /* Maximum bo size is the unpinned gtt size since we use the gtt to 62 * handle vram to system pool migrations. 63 */ 64 max_size = adev->mc.gtt_size - adev->gart_pin_size; 65 if (size > max_size) { 66 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", 67 size >> 20, max_size >> 20); 68 return -ENOMEM; 69 } 70 } 71 retry: 72 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, 73 flags, NULL, NULL, &robj); 74 if (r) { 75 if (r != -ERESTARTSYS) { 76 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 77 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 78 goto retry; 79 } 80 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 81 size, initial_domain, alignment, r); 82 } 83 return r; 84 } 85 *obj = &robj->gem_base; 86 87 return 0; 88 } 89 90 void amdgpu_gem_force_release(struct amdgpu_device *adev) 91 { 92 struct drm_device *ddev = adev->ddev; 93 struct drm_file *file; 94 95 mutex_lock(&ddev->struct_mutex); 96 97 list_for_each_entry(file, &ddev->filelist, lhead) { 98 struct drm_gem_object *gobj; 99 int handle; 100 101 WARN_ONCE(1, "Still active user space clients!\n"); 102 spin_lock(&file->table_lock); 103 idr_for_each_entry(&file->object_idr, gobj, handle) { 104 WARN_ONCE(1, "And also active allocations!\n"); 105 drm_gem_object_unreference(gobj); 106 } 107 idr_destroy(&file->object_idr); 108 spin_unlock(&file->table_lock); 109 } 110 111 mutex_unlock(&ddev->struct_mutex); 112 } 113 114 /* 115 * Call from drm_gem_handle_create which appear in both new and open ioctl 116 * case. 117 */ 118 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) 119 { 120 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 121 struct amdgpu_device *adev = rbo->adev; 122 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 123 struct amdgpu_vm *vm = &fpriv->vm; 124 struct amdgpu_bo_va *bo_va; 125 int r; 126 r = amdgpu_bo_reserve(rbo, false); 127 if (r) 128 return r; 129 130 bo_va = amdgpu_vm_bo_find(vm, rbo); 131 if (!bo_va) { 132 bo_va = amdgpu_vm_bo_add(adev, vm, rbo); 133 } else { 134 ++bo_va->ref_count; 135 } 136 amdgpu_bo_unreserve(rbo); 137 return 0; 138 } 139 140 void amdgpu_gem_object_close(struct drm_gem_object *obj, 141 struct drm_file *file_priv) 142 { 143 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 144 struct amdgpu_device *adev = bo->adev; 145 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 146 struct amdgpu_vm *vm = &fpriv->vm; 147 148 struct amdgpu_bo_list_entry vm_pd; 149 struct list_head list, duplicates; 150 struct ttm_validate_buffer tv; 151 struct ww_acquire_ctx ticket; 152 struct amdgpu_bo_va *bo_va; 153 int r; 154 155 INIT_LIST_HEAD(&list); 156 INIT_LIST_HEAD(&duplicates); 157 158 tv.bo = &bo->tbo; 159 tv.shared = true; 160 list_add(&tv.head, &list); 161 162 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 163 164 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 165 if (r) { 166 dev_err(adev->dev, "leaking bo va because " 167 "we fail to reserve bo (%d)\n", r); 168 return; 169 } 170 bo_va = amdgpu_vm_bo_find(vm, bo); 171 if (bo_va) { 172 if (--bo_va->ref_count == 0) { 173 amdgpu_vm_bo_rmv(adev, bo_va); 174 } 175 } 176 ttm_eu_backoff_reservation(&ticket, &list); 177 } 178 179 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 180 { 181 if (r == -EDEADLK) { 182 r = amdgpu_gpu_reset(adev); 183 if (!r) 184 r = -EAGAIN; 185 } 186 return r; 187 } 188 189 /* 190 * GEM ioctls. 191 */ 192 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 193 struct drm_file *filp) 194 { 195 struct amdgpu_device *adev = dev->dev_private; 196 union drm_amdgpu_gem_create *args = data; 197 uint64_t size = args->in.bo_size; 198 struct drm_gem_object *gobj; 199 uint32_t handle; 200 bool kernel = false; 201 int r; 202 203 /* create a gem object to contain this object in */ 204 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 205 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 206 kernel = true; 207 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 208 size = size << AMDGPU_GDS_SHIFT; 209 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 210 size = size << AMDGPU_GWS_SHIFT; 211 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 212 size = size << AMDGPU_OA_SHIFT; 213 else { 214 r = -EINVAL; 215 goto error_unlock; 216 } 217 } 218 size = roundup(size, PAGE_SIZE); 219 220 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 221 (u32)(0xffffffff & args->in.domains), 222 args->in.domain_flags, 223 kernel, &gobj); 224 if (r) 225 goto error_unlock; 226 227 r = drm_gem_handle_create(filp, gobj, &handle); 228 /* drop reference from allocate - handle holds it now */ 229 drm_gem_object_unreference_unlocked(gobj); 230 if (r) 231 goto error_unlock; 232 233 memset(args, 0, sizeof(*args)); 234 args->out.handle = handle; 235 return 0; 236 237 error_unlock: 238 r = amdgpu_gem_handle_lockup(adev, r); 239 return r; 240 } 241 242 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 243 struct drm_file *filp) 244 { 245 struct amdgpu_device *adev = dev->dev_private; 246 struct drm_amdgpu_gem_userptr *args = data; 247 struct drm_gem_object *gobj; 248 struct amdgpu_bo *bo; 249 uint32_t handle; 250 int r; 251 252 if (offset_in_page(args->addr | args->size)) 253 return -EINVAL; 254 255 /* reject unknown flag values */ 256 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 257 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 258 AMDGPU_GEM_USERPTR_REGISTER)) 259 return -EINVAL; 260 261 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 262 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 263 264 /* if we want to write to it we must install a MMU notifier */ 265 return -EACCES; 266 } 267 268 /* create a gem object to contain this object in */ 269 r = amdgpu_gem_object_create(adev, args->size, 0, 270 AMDGPU_GEM_DOMAIN_CPU, 0, 271 0, &gobj); 272 if (r) 273 goto handle_lockup; 274 275 bo = gem_to_amdgpu_bo(gobj); 276 bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT; 277 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 278 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 279 if (r) 280 goto release_object; 281 282 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 283 r = amdgpu_mn_register(bo, args->addr); 284 if (r) 285 goto release_object; 286 } 287 288 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 289 down_read(¤t->mm->mmap_sem); 290 291 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 292 bo->tbo.ttm->pages); 293 if (r) 294 goto unlock_mmap_sem; 295 296 r = amdgpu_bo_reserve(bo, true); 297 if (r) 298 goto free_pages; 299 300 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 301 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 302 amdgpu_bo_unreserve(bo); 303 if (r) 304 goto free_pages; 305 306 up_read(¤t->mm->mmap_sem); 307 } 308 309 r = drm_gem_handle_create(filp, gobj, &handle); 310 /* drop reference from allocate - handle holds it now */ 311 drm_gem_object_unreference_unlocked(gobj); 312 if (r) 313 goto handle_lockup; 314 315 args->handle = handle; 316 return 0; 317 318 free_pages: 319 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false); 320 321 unlock_mmap_sem: 322 up_read(¤t->mm->mmap_sem); 323 324 release_object: 325 drm_gem_object_unreference_unlocked(gobj); 326 327 handle_lockup: 328 r = amdgpu_gem_handle_lockup(adev, r); 329 330 return r; 331 } 332 333 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 334 struct drm_device *dev, 335 uint32_t handle, uint64_t *offset_p) 336 { 337 struct drm_gem_object *gobj; 338 struct amdgpu_bo *robj; 339 340 gobj = drm_gem_object_lookup(dev, filp, handle); 341 if (gobj == NULL) { 342 return -ENOENT; 343 } 344 robj = gem_to_amdgpu_bo(gobj); 345 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 346 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 347 drm_gem_object_unreference_unlocked(gobj); 348 return -EPERM; 349 } 350 *offset_p = amdgpu_bo_mmap_offset(robj); 351 drm_gem_object_unreference_unlocked(gobj); 352 return 0; 353 } 354 355 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 356 struct drm_file *filp) 357 { 358 union drm_amdgpu_gem_mmap *args = data; 359 uint32_t handle = args->in.handle; 360 memset(args, 0, sizeof(*args)); 361 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 362 } 363 364 /** 365 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 366 * 367 * @timeout_ns: timeout in ns 368 * 369 * Calculate the timeout in jiffies from an absolute timeout in ns. 370 */ 371 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 372 { 373 unsigned long timeout_jiffies; 374 ktime_t timeout; 375 376 /* clamp timeout if it's to large */ 377 if (((int64_t)timeout_ns) < 0) 378 return MAX_SCHEDULE_TIMEOUT; 379 380 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 381 if (ktime_to_ns(timeout) < 0) 382 return 0; 383 384 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 385 /* clamp timeout to avoid unsigned-> signed overflow */ 386 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 387 return MAX_SCHEDULE_TIMEOUT - 1; 388 389 return timeout_jiffies; 390 } 391 392 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 393 struct drm_file *filp) 394 { 395 struct amdgpu_device *adev = dev->dev_private; 396 union drm_amdgpu_gem_wait_idle *args = data; 397 struct drm_gem_object *gobj; 398 struct amdgpu_bo *robj; 399 uint32_t handle = args->in.handle; 400 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 401 int r = 0; 402 long ret; 403 404 gobj = drm_gem_object_lookup(dev, filp, handle); 405 if (gobj == NULL) { 406 return -ENOENT; 407 } 408 robj = gem_to_amdgpu_bo(gobj); 409 if (timeout == 0) 410 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); 411 else 412 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); 413 414 /* ret == 0 means not signaled, 415 * ret > 0 means signaled 416 * ret < 0 means interrupted before timeout 417 */ 418 if (ret >= 0) { 419 memset(args, 0, sizeof(*args)); 420 args->out.status = (ret == 0); 421 } else 422 r = ret; 423 424 drm_gem_object_unreference_unlocked(gobj); 425 r = amdgpu_gem_handle_lockup(adev, r); 426 return r; 427 } 428 429 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 430 struct drm_file *filp) 431 { 432 struct drm_amdgpu_gem_metadata *args = data; 433 struct drm_gem_object *gobj; 434 struct amdgpu_bo *robj; 435 int r = -1; 436 437 DRM_DEBUG("%d \n", args->handle); 438 gobj = drm_gem_object_lookup(dev, filp, args->handle); 439 if (gobj == NULL) 440 return -ENOENT; 441 robj = gem_to_amdgpu_bo(gobj); 442 443 r = amdgpu_bo_reserve(robj, false); 444 if (unlikely(r != 0)) 445 goto out; 446 447 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 448 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 449 r = amdgpu_bo_get_metadata(robj, args->data.data, 450 sizeof(args->data.data), 451 &args->data.data_size_bytes, 452 &args->data.flags); 453 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 454 if (args->data.data_size_bytes > sizeof(args->data.data)) { 455 r = -EINVAL; 456 goto unreserve; 457 } 458 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 459 if (!r) 460 r = amdgpu_bo_set_metadata(robj, args->data.data, 461 args->data.data_size_bytes, 462 args->data.flags); 463 } 464 465 unreserve: 466 amdgpu_bo_unreserve(robj); 467 out: 468 drm_gem_object_unreference_unlocked(gobj); 469 return r; 470 } 471 472 /** 473 * amdgpu_gem_va_update_vm -update the bo_va in its VM 474 * 475 * @adev: amdgpu_device pointer 476 * @bo_va: bo_va to update 477 * 478 * Update the bo_va directly after setting it's address. Errors are not 479 * vital here, so they are not reported back to userspace. 480 */ 481 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 482 struct amdgpu_bo_va *bo_va, uint32_t operation) 483 { 484 struct ttm_validate_buffer tv, *entry; 485 struct amdgpu_bo_list_entry vm_pd; 486 struct ww_acquire_ctx ticket; 487 struct list_head list, duplicates; 488 unsigned domain; 489 int r; 490 491 INIT_LIST_HEAD(&list); 492 INIT_LIST_HEAD(&duplicates); 493 494 tv.bo = &bo_va->bo->tbo; 495 tv.shared = true; 496 list_add(&tv.head, &list); 497 498 amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd); 499 500 /* Provide duplicates to avoid -EALREADY */ 501 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 502 if (r) 503 goto error_print; 504 505 amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates); 506 list_for_each_entry(entry, &list, head) { 507 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); 508 /* if anything is swapped out don't swap it in here, 509 just abort and wait for the next CS */ 510 if (domain == AMDGPU_GEM_DOMAIN_CPU) 511 goto error_unreserve; 512 } 513 list_for_each_entry(entry, &duplicates, head) { 514 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); 515 /* if anything is swapped out don't swap it in here, 516 just abort and wait for the next CS */ 517 if (domain == AMDGPU_GEM_DOMAIN_CPU) 518 goto error_unreserve; 519 } 520 521 r = amdgpu_vm_update_page_directory(adev, bo_va->vm); 522 if (r) 523 goto error_unreserve; 524 525 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 526 if (r) 527 goto error_unreserve; 528 529 if (operation == AMDGPU_VA_OP_MAP) 530 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 531 532 error_unreserve: 533 ttm_eu_backoff_reservation(&ticket, &list); 534 535 error_print: 536 if (r && r != -ERESTARTSYS) 537 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 538 } 539 540 541 542 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 543 struct drm_file *filp) 544 { 545 struct drm_amdgpu_gem_va *args = data; 546 struct drm_gem_object *gobj; 547 struct amdgpu_device *adev = dev->dev_private; 548 struct amdgpu_fpriv *fpriv = filp->driver_priv; 549 struct amdgpu_bo *rbo; 550 struct amdgpu_bo_va *bo_va; 551 struct ttm_validate_buffer tv, tv_pd; 552 struct ww_acquire_ctx ticket; 553 struct list_head list, duplicates; 554 uint32_t invalid_flags, va_flags = 0; 555 int r = 0; 556 557 if (!adev->vm_manager.enabled) 558 return -ENOTTY; 559 560 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 561 dev_err(&dev->pdev->dev, 562 "va_address 0x%lX is in reserved area 0x%X\n", 563 (unsigned long)args->va_address, 564 AMDGPU_VA_RESERVED_SIZE); 565 return -EINVAL; 566 } 567 568 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | 569 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); 570 if ((args->flags & invalid_flags)) { 571 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", 572 args->flags, invalid_flags); 573 return -EINVAL; 574 } 575 576 switch (args->operation) { 577 case AMDGPU_VA_OP_MAP: 578 case AMDGPU_VA_OP_UNMAP: 579 break; 580 default: 581 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 582 args->operation); 583 return -EINVAL; 584 } 585 586 gobj = drm_gem_object_lookup(dev, filp, args->handle); 587 if (gobj == NULL) 588 return -ENOENT; 589 rbo = gem_to_amdgpu_bo(gobj); 590 INIT_LIST_HEAD(&list); 591 INIT_LIST_HEAD(&duplicates); 592 tv.bo = &rbo->tbo; 593 tv.shared = true; 594 list_add(&tv.head, &list); 595 596 tv_pd.bo = &fpriv->vm.page_directory->tbo; 597 tv_pd.shared = true; 598 list_add(&tv_pd.head, &list); 599 600 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 601 if (r) { 602 drm_gem_object_unreference_unlocked(gobj); 603 return r; 604 } 605 606 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 607 if (!bo_va) { 608 ttm_eu_backoff_reservation(&ticket, &list); 609 drm_gem_object_unreference_unlocked(gobj); 610 return -ENOENT; 611 } 612 613 switch (args->operation) { 614 case AMDGPU_VA_OP_MAP: 615 if (args->flags & AMDGPU_VM_PAGE_READABLE) 616 va_flags |= AMDGPU_PTE_READABLE; 617 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) 618 va_flags |= AMDGPU_PTE_WRITEABLE; 619 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) 620 va_flags |= AMDGPU_PTE_EXECUTABLE; 621 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 622 args->offset_in_bo, args->map_size, 623 va_flags); 624 break; 625 case AMDGPU_VA_OP_UNMAP: 626 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 627 break; 628 default: 629 break; 630 } 631 ttm_eu_backoff_reservation(&ticket, &list); 632 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 633 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 634 635 drm_gem_object_unreference_unlocked(gobj); 636 return r; 637 } 638 639 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 640 struct drm_file *filp) 641 { 642 struct drm_amdgpu_gem_op *args = data; 643 struct drm_gem_object *gobj; 644 struct amdgpu_bo *robj; 645 int r; 646 647 gobj = drm_gem_object_lookup(dev, filp, args->handle); 648 if (gobj == NULL) { 649 return -ENOENT; 650 } 651 robj = gem_to_amdgpu_bo(gobj); 652 653 r = amdgpu_bo_reserve(robj, false); 654 if (unlikely(r)) 655 goto out; 656 657 switch (args->op) { 658 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 659 struct drm_amdgpu_gem_create_in info; 660 void __user *out = (void __user *)(long)args->value; 661 662 info.bo_size = robj->gem_base.size; 663 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 664 info.domains = robj->prefered_domains; 665 info.domain_flags = robj->flags; 666 amdgpu_bo_unreserve(robj); 667 if (copy_to_user(out, &info, sizeof(info))) 668 r = -EFAULT; 669 break; 670 } 671 case AMDGPU_GEM_OP_SET_PLACEMENT: 672 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 673 r = -EPERM; 674 amdgpu_bo_unreserve(robj); 675 break; 676 } 677 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 678 AMDGPU_GEM_DOMAIN_GTT | 679 AMDGPU_GEM_DOMAIN_CPU); 680 robj->allowed_domains = robj->prefered_domains; 681 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 682 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 683 684 amdgpu_bo_unreserve(robj); 685 break; 686 default: 687 amdgpu_bo_unreserve(robj); 688 r = -EINVAL; 689 } 690 691 out: 692 drm_gem_object_unreference_unlocked(gobj); 693 return r; 694 } 695 696 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 697 struct drm_device *dev, 698 struct drm_mode_create_dumb *args) 699 { 700 struct amdgpu_device *adev = dev->dev_private; 701 struct drm_gem_object *gobj; 702 uint32_t handle; 703 int r; 704 705 args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); 706 args->size = (u64)args->pitch * args->height; 707 args->size = ALIGN(args->size, PAGE_SIZE); 708 709 r = amdgpu_gem_object_create(adev, args->size, 0, 710 AMDGPU_GEM_DOMAIN_VRAM, 711 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 712 ttm_bo_type_device, 713 &gobj); 714 if (r) 715 return -ENOMEM; 716 717 r = drm_gem_handle_create(file_priv, gobj, &handle); 718 /* drop reference from allocate - handle holds it now */ 719 drm_gem_object_unreference_unlocked(gobj); 720 if (r) { 721 return r; 722 } 723 args->handle = handle; 724 return 0; 725 } 726 727 #if defined(CONFIG_DEBUG_FS) 728 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 729 { 730 struct drm_gem_object *gobj = ptr; 731 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 732 struct seq_file *m = data; 733 734 unsigned domain; 735 const char *placement; 736 unsigned pin_count; 737 738 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 739 switch (domain) { 740 case AMDGPU_GEM_DOMAIN_VRAM: 741 placement = "VRAM"; 742 break; 743 case AMDGPU_GEM_DOMAIN_GTT: 744 placement = " GTT"; 745 break; 746 case AMDGPU_GEM_DOMAIN_CPU: 747 default: 748 placement = " CPU"; 749 break; 750 } 751 seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx", 752 id, amdgpu_bo_size(bo), placement, 753 amdgpu_bo_gpu_offset(bo)); 754 755 pin_count = ACCESS_ONCE(bo->pin_count); 756 if (pin_count) 757 seq_printf(m, " pin count %d", pin_count); 758 seq_printf(m, "\n"); 759 760 return 0; 761 } 762 763 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 764 { 765 struct drm_info_node *node = (struct drm_info_node *)m->private; 766 struct drm_device *dev = node->minor->dev; 767 struct drm_file *file; 768 int r; 769 770 r = mutex_lock_interruptible(&dev->struct_mutex); 771 if (r) 772 return r; 773 774 list_for_each_entry(file, &dev->filelist, lhead) { 775 struct task_struct *task; 776 777 /* 778 * Although we have a valid reference on file->pid, that does 779 * not guarantee that the task_struct who called get_pid() is 780 * still alive (e.g. get_pid(current) => fork() => exit()). 781 * Therefore, we need to protect this ->comm access using RCU. 782 */ 783 rcu_read_lock(); 784 task = pid_task(file->pid, PIDTYPE_PID); 785 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 786 task ? task->comm : "<unknown>"); 787 rcu_read_unlock(); 788 789 spin_lock(&file->table_lock); 790 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 791 spin_unlock(&file->table_lock); 792 } 793 794 mutex_unlock(&dev->struct_mutex); 795 return 0; 796 } 797 798 static struct drm_info_list amdgpu_debugfs_gem_list[] = { 799 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 800 }; 801 #endif 802 803 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) 804 { 805 #if defined(CONFIG_DEBUG_FS) 806 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 807 #endif 808 return 0; 809 } 810