1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <[email protected]> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 */ 54 #define KMS_DRIVER_MAJOR 3 55 #define KMS_DRIVER_MINOR 1 56 #define KMS_DRIVER_PATCHLEVEL 0 57 58 int amdgpu_vram_limit = 0; 59 int amdgpu_gart_size = -1; /* auto */ 60 int amdgpu_benchmarking = 0; 61 int amdgpu_testing = 0; 62 int amdgpu_audio = -1; 63 int amdgpu_disp_priority = 0; 64 int amdgpu_hw_i2c = 0; 65 int amdgpu_pcie_gen2 = -1; 66 int amdgpu_msi = -1; 67 int amdgpu_lockup_timeout = 0; 68 int amdgpu_dpm = -1; 69 int amdgpu_smc_load_fw = 1; 70 int amdgpu_aspm = -1; 71 int amdgpu_runtime_pm = -1; 72 unsigned amdgpu_ip_block_mask = 0xffffffff; 73 int amdgpu_bapm = -1; 74 int amdgpu_deep_color = 0; 75 int amdgpu_vm_size = 64; 76 int amdgpu_vm_block_size = -1; 77 int amdgpu_vm_fault_stop = 0; 78 int amdgpu_vm_debug = 0; 79 int amdgpu_exp_hw_support = 0; 80 int amdgpu_sched_jobs = 32; 81 int amdgpu_sched_hw_submission = 2; 82 int amdgpu_powerplay = -1; 83 unsigned amdgpu_pcie_gen_cap = 0; 84 unsigned amdgpu_pcie_lane_cap = 0; 85 86 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 87 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 88 89 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 90 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 91 92 MODULE_PARM_DESC(benchmark, "Run benchmark"); 93 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 94 95 MODULE_PARM_DESC(test, "Run tests"); 96 module_param_named(test, amdgpu_testing, int, 0444); 97 98 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 99 module_param_named(audio, amdgpu_audio, int, 0444); 100 101 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 102 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 103 104 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 105 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 106 107 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 108 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 109 110 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 111 module_param_named(msi, amdgpu_msi, int, 0444); 112 113 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 114 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 115 116 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 117 module_param_named(dpm, amdgpu_dpm, int, 0444); 118 119 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 120 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 121 122 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 123 module_param_named(aspm, amdgpu_aspm, int, 0444); 124 125 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 126 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 127 128 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 129 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 130 131 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 132 module_param_named(bapm, amdgpu_bapm, int, 0444); 133 134 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 135 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 136 137 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 138 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 139 140 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 141 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 142 143 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 144 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 145 146 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 147 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 148 149 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 150 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 151 152 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 153 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 154 155 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 156 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 157 158 #ifdef CONFIG_DRM_AMD_POWERPLAY 159 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 160 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 161 #endif 162 163 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 164 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 165 166 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 167 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 168 169 static const struct pci_device_id pciidlist[] = { 170 #ifdef CONFIG_DRM_AMDGPU_CIK 171 /* Kaveri */ 172 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 173 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 174 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 175 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 176 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 177 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 178 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 179 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 180 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 181 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 182 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 183 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 184 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 185 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 186 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 187 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 188 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 189 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 190 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 191 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 192 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 193 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 194 /* Bonaire */ 195 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 196 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 197 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 198 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 199 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 200 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 201 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 202 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 203 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 204 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 205 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 206 /* Hawaii */ 207 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 208 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 209 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 210 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 211 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 212 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 213 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 214 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 215 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 216 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 217 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 218 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 219 /* Kabini */ 220 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 221 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 222 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 223 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 224 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 225 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 226 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 227 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 228 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 229 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 230 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 231 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 232 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 233 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 234 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 235 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 236 /* mullins */ 237 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 238 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 239 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 240 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 242 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 244 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 245 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 246 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 247 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 248 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 249 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 250 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 251 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 252 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 253 #endif 254 /* topaz */ 255 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 256 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 257 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 258 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 259 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 260 /* tonga */ 261 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 262 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 263 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 264 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 265 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 266 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 267 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 268 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 269 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 270 /* fiji */ 271 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 272 /* carrizo */ 273 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 274 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 275 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 276 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 277 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 278 /* stoney */ 279 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 280 /* Polaris11 */ 281 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 282 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 283 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 284 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 285 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 286 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 287 /* Polaris10 */ 288 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 289 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 290 291 {0, 0, 0} 292 }; 293 294 MODULE_DEVICE_TABLE(pci, pciidlist); 295 296 static struct drm_driver kms_driver; 297 298 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 299 { 300 struct apertures_struct *ap; 301 bool primary = false; 302 303 ap = alloc_apertures(1); 304 if (!ap) 305 return -ENOMEM; 306 307 ap->ranges[0].base = pci_resource_start(pdev, 0); 308 ap->ranges[0].size = pci_resource_len(pdev, 0); 309 310 #ifdef CONFIG_X86 311 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 312 #endif 313 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 314 kfree(ap); 315 316 return 0; 317 } 318 319 static int amdgpu_pci_probe(struct pci_dev *pdev, 320 const struct pci_device_id *ent) 321 { 322 unsigned long flags = ent->driver_data; 323 int ret; 324 325 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 326 DRM_INFO("This hardware requires experimental hardware support.\n" 327 "See modparam exp_hw_support\n"); 328 return -ENODEV; 329 } 330 331 /* 332 * Initialize amdkfd before starting radeon. If it was not loaded yet, 333 * defer radeon probing 334 */ 335 ret = amdgpu_amdkfd_init(); 336 if (ret == -EPROBE_DEFER) 337 return ret; 338 339 /* Get rid of things like offb */ 340 ret = amdgpu_kick_out_firmware_fb(pdev); 341 if (ret) 342 return ret; 343 344 return drm_get_pci_dev(pdev, ent, &kms_driver); 345 } 346 347 static void 348 amdgpu_pci_remove(struct pci_dev *pdev) 349 { 350 struct drm_device *dev = pci_get_drvdata(pdev); 351 352 drm_put_dev(dev); 353 } 354 355 static int amdgpu_pmops_suspend(struct device *dev) 356 { 357 struct pci_dev *pdev = to_pci_dev(dev); 358 struct drm_device *drm_dev = pci_get_drvdata(pdev); 359 return amdgpu_suspend_kms(drm_dev, true, true); 360 } 361 362 static int amdgpu_pmops_resume(struct device *dev) 363 { 364 struct pci_dev *pdev = to_pci_dev(dev); 365 struct drm_device *drm_dev = pci_get_drvdata(pdev); 366 return amdgpu_resume_kms(drm_dev, true, true); 367 } 368 369 static int amdgpu_pmops_freeze(struct device *dev) 370 { 371 struct pci_dev *pdev = to_pci_dev(dev); 372 struct drm_device *drm_dev = pci_get_drvdata(pdev); 373 return amdgpu_suspend_kms(drm_dev, false, true); 374 } 375 376 static int amdgpu_pmops_thaw(struct device *dev) 377 { 378 struct pci_dev *pdev = to_pci_dev(dev); 379 struct drm_device *drm_dev = pci_get_drvdata(pdev); 380 return amdgpu_resume_kms(drm_dev, false, true); 381 } 382 383 static int amdgpu_pmops_runtime_suspend(struct device *dev) 384 { 385 struct pci_dev *pdev = to_pci_dev(dev); 386 struct drm_device *drm_dev = pci_get_drvdata(pdev); 387 int ret; 388 389 if (!amdgpu_device_is_px(drm_dev)) { 390 pm_runtime_forbid(dev); 391 return -EBUSY; 392 } 393 394 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 395 drm_kms_helper_poll_disable(drm_dev); 396 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 397 398 ret = amdgpu_suspend_kms(drm_dev, false, false); 399 pci_save_state(pdev); 400 pci_disable_device(pdev); 401 pci_ignore_hotplug(pdev); 402 pci_set_power_state(pdev, PCI_D3cold); 403 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 404 405 return 0; 406 } 407 408 static int amdgpu_pmops_runtime_resume(struct device *dev) 409 { 410 struct pci_dev *pdev = to_pci_dev(dev); 411 struct drm_device *drm_dev = pci_get_drvdata(pdev); 412 int ret; 413 414 if (!amdgpu_device_is_px(drm_dev)) 415 return -EINVAL; 416 417 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 418 419 pci_set_power_state(pdev, PCI_D0); 420 pci_restore_state(pdev); 421 ret = pci_enable_device(pdev); 422 if (ret) 423 return ret; 424 pci_set_master(pdev); 425 426 ret = amdgpu_resume_kms(drm_dev, false, false); 427 drm_kms_helper_poll_enable(drm_dev); 428 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 429 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 430 return 0; 431 } 432 433 static int amdgpu_pmops_runtime_idle(struct device *dev) 434 { 435 struct pci_dev *pdev = to_pci_dev(dev); 436 struct drm_device *drm_dev = pci_get_drvdata(pdev); 437 struct drm_crtc *crtc; 438 439 if (!amdgpu_device_is_px(drm_dev)) { 440 pm_runtime_forbid(dev); 441 return -EBUSY; 442 } 443 444 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 445 if (crtc->enabled) { 446 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 447 return -EBUSY; 448 } 449 } 450 451 pm_runtime_mark_last_busy(dev); 452 pm_runtime_autosuspend(dev); 453 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 454 return 1; 455 } 456 457 long amdgpu_drm_ioctl(struct file *filp, 458 unsigned int cmd, unsigned long arg) 459 { 460 struct drm_file *file_priv = filp->private_data; 461 struct drm_device *dev; 462 long ret; 463 dev = file_priv->minor->dev; 464 ret = pm_runtime_get_sync(dev->dev); 465 if (ret < 0) 466 return ret; 467 468 ret = drm_ioctl(filp, cmd, arg); 469 470 pm_runtime_mark_last_busy(dev->dev); 471 pm_runtime_put_autosuspend(dev->dev); 472 return ret; 473 } 474 475 static const struct dev_pm_ops amdgpu_pm_ops = { 476 .suspend = amdgpu_pmops_suspend, 477 .resume = amdgpu_pmops_resume, 478 .freeze = amdgpu_pmops_freeze, 479 .thaw = amdgpu_pmops_thaw, 480 .poweroff = amdgpu_pmops_freeze, 481 .restore = amdgpu_pmops_resume, 482 .runtime_suspend = amdgpu_pmops_runtime_suspend, 483 .runtime_resume = amdgpu_pmops_runtime_resume, 484 .runtime_idle = amdgpu_pmops_runtime_idle, 485 }; 486 487 static const struct file_operations amdgpu_driver_kms_fops = { 488 .owner = THIS_MODULE, 489 .open = drm_open, 490 .release = drm_release, 491 .unlocked_ioctl = amdgpu_drm_ioctl, 492 .mmap = amdgpu_mmap, 493 .poll = drm_poll, 494 .read = drm_read, 495 #ifdef CONFIG_COMPAT 496 .compat_ioctl = amdgpu_kms_compat_ioctl, 497 #endif 498 }; 499 500 static struct drm_driver kms_driver = { 501 .driver_features = 502 DRIVER_USE_AGP | 503 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 504 DRIVER_PRIME | DRIVER_RENDER, 505 .dev_priv_size = 0, 506 .load = amdgpu_driver_load_kms, 507 .open = amdgpu_driver_open_kms, 508 .preclose = amdgpu_driver_preclose_kms, 509 .postclose = amdgpu_driver_postclose_kms, 510 .lastclose = amdgpu_driver_lastclose_kms, 511 .set_busid = drm_pci_set_busid, 512 .unload = amdgpu_driver_unload_kms, 513 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 514 .enable_vblank = amdgpu_enable_vblank_kms, 515 .disable_vblank = amdgpu_disable_vblank_kms, 516 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 517 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 518 #if defined(CONFIG_DEBUG_FS) 519 .debugfs_init = amdgpu_debugfs_init, 520 .debugfs_cleanup = amdgpu_debugfs_cleanup, 521 #endif 522 .irq_preinstall = amdgpu_irq_preinstall, 523 .irq_postinstall = amdgpu_irq_postinstall, 524 .irq_uninstall = amdgpu_irq_uninstall, 525 .irq_handler = amdgpu_irq_handler, 526 .ioctls = amdgpu_ioctls_kms, 527 .gem_free_object_unlocked = amdgpu_gem_object_free, 528 .gem_open_object = amdgpu_gem_object_open, 529 .gem_close_object = amdgpu_gem_object_close, 530 .dumb_create = amdgpu_mode_dumb_create, 531 .dumb_map_offset = amdgpu_mode_dumb_mmap, 532 .dumb_destroy = drm_gem_dumb_destroy, 533 .fops = &amdgpu_driver_kms_fops, 534 535 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 536 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 537 .gem_prime_export = amdgpu_gem_prime_export, 538 .gem_prime_import = drm_gem_prime_import, 539 .gem_prime_pin = amdgpu_gem_prime_pin, 540 .gem_prime_unpin = amdgpu_gem_prime_unpin, 541 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 542 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 543 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 544 .gem_prime_vmap = amdgpu_gem_prime_vmap, 545 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 546 547 .name = DRIVER_NAME, 548 .desc = DRIVER_DESC, 549 .date = DRIVER_DATE, 550 .major = KMS_DRIVER_MAJOR, 551 .minor = KMS_DRIVER_MINOR, 552 .patchlevel = KMS_DRIVER_PATCHLEVEL, 553 }; 554 555 static struct drm_driver *driver; 556 static struct pci_driver *pdriver; 557 558 static struct pci_driver amdgpu_kms_pci_driver = { 559 .name = DRIVER_NAME, 560 .id_table = pciidlist, 561 .probe = amdgpu_pci_probe, 562 .remove = amdgpu_pci_remove, 563 .driver.pm = &amdgpu_pm_ops, 564 }; 565 566 static int __init amdgpu_init(void) 567 { 568 amdgpu_sync_init(); 569 if (vgacon_text_force()) { 570 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 571 return -EINVAL; 572 } 573 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 574 driver = &kms_driver; 575 pdriver = &amdgpu_kms_pci_driver; 576 driver->driver_features |= DRIVER_MODESET; 577 driver->num_ioctls = amdgpu_max_kms_ioctl; 578 amdgpu_register_atpx_handler(); 579 580 /* let modprobe override vga console setting */ 581 return drm_pci_init(driver, pdriver); 582 } 583 584 static void __exit amdgpu_exit(void) 585 { 586 amdgpu_amdkfd_fini(); 587 drm_pci_exit(driver, pdriver); 588 amdgpu_unregister_atpx_handler(); 589 amdgpu_sync_fini(); 590 } 591 592 module_init(amdgpu_init); 593 module_exit(amdgpu_exit); 594 595 MODULE_AUTHOR(DRIVER_AUTHOR); 596 MODULE_DESCRIPTION(DRIVER_DESC); 597 MODULE_LICENSE("GPL and additional rights"); 598