1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <[email protected]> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 */ 56 #define KMS_DRIVER_MAJOR 3 57 #define KMS_DRIVER_MINOR 2 58 #define KMS_DRIVER_PATCHLEVEL 0 59 60 int amdgpu_vram_limit = 0; 61 int amdgpu_gart_size = -1; /* auto */ 62 int amdgpu_benchmarking = 0; 63 int amdgpu_testing = 0; 64 int amdgpu_audio = -1; 65 int amdgpu_disp_priority = 0; 66 int amdgpu_hw_i2c = 0; 67 int amdgpu_pcie_gen2 = -1; 68 int amdgpu_msi = -1; 69 int amdgpu_lockup_timeout = 0; 70 int amdgpu_dpm = -1; 71 int amdgpu_smc_load_fw = 1; 72 int amdgpu_aspm = -1; 73 int amdgpu_runtime_pm = -1; 74 unsigned amdgpu_ip_block_mask = 0xffffffff; 75 int amdgpu_bapm = -1; 76 int amdgpu_deep_color = 0; 77 int amdgpu_vm_size = 64; 78 int amdgpu_vm_block_size = -1; 79 int amdgpu_vm_fault_stop = 0; 80 int amdgpu_vm_debug = 0; 81 int amdgpu_exp_hw_support = 0; 82 int amdgpu_sched_jobs = 32; 83 int amdgpu_sched_hw_submission = 2; 84 int amdgpu_powerplay = -1; 85 int amdgpu_powercontainment = 1; 86 unsigned amdgpu_pcie_gen_cap = 0; 87 unsigned amdgpu_pcie_lane_cap = 0; 88 unsigned amdgpu_cg_mask = 0xffffffff; 89 unsigned amdgpu_pg_mask = 0xffffffff; 90 char *amdgpu_disable_cu = NULL; 91 92 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 93 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 94 95 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 96 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 97 98 MODULE_PARM_DESC(benchmark, "Run benchmark"); 99 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 100 101 MODULE_PARM_DESC(test, "Run tests"); 102 module_param_named(test, amdgpu_testing, int, 0444); 103 104 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 105 module_param_named(audio, amdgpu_audio, int, 0444); 106 107 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 108 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 109 110 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 111 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 112 113 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 114 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 115 116 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 117 module_param_named(msi, amdgpu_msi, int, 0444); 118 119 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 120 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 121 122 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 123 module_param_named(dpm, amdgpu_dpm, int, 0444); 124 125 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 126 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 127 128 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 129 module_param_named(aspm, amdgpu_aspm, int, 0444); 130 131 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 132 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 133 134 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 135 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 136 137 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 138 module_param_named(bapm, amdgpu_bapm, int, 0444); 139 140 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 141 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 142 143 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 144 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 145 146 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 147 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 148 149 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 150 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 151 152 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 153 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 154 155 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 156 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 157 158 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 159 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 160 161 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 162 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 163 164 #ifdef CONFIG_DRM_AMD_POWERPLAY 165 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 166 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 167 168 MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); 169 module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); 170 #endif 171 172 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 173 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 174 175 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 176 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 177 178 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 179 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 180 181 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 182 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 183 184 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 185 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 186 187 static const struct pci_device_id pciidlist[] = { 188 #ifdef CONFIG_DRM_AMDGPU_CIK 189 /* Kaveri */ 190 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 191 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 192 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 193 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 194 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 195 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 196 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 197 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 198 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 199 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 200 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 201 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 202 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 203 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 204 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 205 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 206 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 207 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 208 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 209 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 210 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 211 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 212 /* Bonaire */ 213 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 214 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 215 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 216 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 217 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 218 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 219 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 220 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 221 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 222 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 223 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 224 /* Hawaii */ 225 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 226 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 227 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 228 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 229 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 230 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 231 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 232 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 233 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 234 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 235 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 236 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 237 /* Kabini */ 238 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 239 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 240 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 242 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 244 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 245 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 246 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 247 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 248 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 249 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 250 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 251 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 252 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 253 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 254 /* mullins */ 255 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 256 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 257 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 258 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 259 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 260 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 261 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 262 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 263 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 264 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 265 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 266 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 267 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 268 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 269 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 270 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 271 #endif 272 /* topaz */ 273 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 274 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 275 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 276 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 277 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 278 /* tonga */ 279 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 280 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 281 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 282 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 283 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 284 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 285 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 286 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 287 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 288 /* fiji */ 289 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 290 /* carrizo */ 291 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 292 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 293 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 294 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 295 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 296 /* stoney */ 297 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 298 /* Polaris11 */ 299 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 300 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 301 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 302 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 303 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 304 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 305 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 306 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 307 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 308 /* Polaris10 */ 309 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 310 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 311 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 312 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 313 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 314 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 315 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 316 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 317 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 318 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 319 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 320 321 {0, 0, 0} 322 }; 323 324 MODULE_DEVICE_TABLE(pci, pciidlist); 325 326 static struct drm_driver kms_driver; 327 328 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 329 { 330 struct apertures_struct *ap; 331 bool primary = false; 332 333 ap = alloc_apertures(1); 334 if (!ap) 335 return -ENOMEM; 336 337 ap->ranges[0].base = pci_resource_start(pdev, 0); 338 ap->ranges[0].size = pci_resource_len(pdev, 0); 339 340 #ifdef CONFIG_X86 341 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 342 #endif 343 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 344 kfree(ap); 345 346 return 0; 347 } 348 349 static int amdgpu_pci_probe(struct pci_dev *pdev, 350 const struct pci_device_id *ent) 351 { 352 unsigned long flags = ent->driver_data; 353 int ret; 354 355 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 356 DRM_INFO("This hardware requires experimental hardware support.\n" 357 "See modparam exp_hw_support\n"); 358 return -ENODEV; 359 } 360 361 /* 362 * Initialize amdkfd before starting radeon. If it was not loaded yet, 363 * defer radeon probing 364 */ 365 ret = amdgpu_amdkfd_init(); 366 if (ret == -EPROBE_DEFER) 367 return ret; 368 369 /* Get rid of things like offb */ 370 ret = amdgpu_kick_out_firmware_fb(pdev); 371 if (ret) 372 return ret; 373 374 return drm_get_pci_dev(pdev, ent, &kms_driver); 375 } 376 377 static void 378 amdgpu_pci_remove(struct pci_dev *pdev) 379 { 380 struct drm_device *dev = pci_get_drvdata(pdev); 381 382 drm_put_dev(dev); 383 } 384 385 static int amdgpu_pmops_suspend(struct device *dev) 386 { 387 struct pci_dev *pdev = to_pci_dev(dev); 388 struct drm_device *drm_dev = pci_get_drvdata(pdev); 389 return amdgpu_suspend_kms(drm_dev, true, true); 390 } 391 392 static int amdgpu_pmops_resume(struct device *dev) 393 { 394 struct pci_dev *pdev = to_pci_dev(dev); 395 struct drm_device *drm_dev = pci_get_drvdata(pdev); 396 return amdgpu_resume_kms(drm_dev, true, true); 397 } 398 399 static int amdgpu_pmops_freeze(struct device *dev) 400 { 401 struct pci_dev *pdev = to_pci_dev(dev); 402 struct drm_device *drm_dev = pci_get_drvdata(pdev); 403 return amdgpu_suspend_kms(drm_dev, false, true); 404 } 405 406 static int amdgpu_pmops_thaw(struct device *dev) 407 { 408 struct pci_dev *pdev = to_pci_dev(dev); 409 struct drm_device *drm_dev = pci_get_drvdata(pdev); 410 return amdgpu_resume_kms(drm_dev, false, true); 411 } 412 413 static int amdgpu_pmops_runtime_suspend(struct device *dev) 414 { 415 struct pci_dev *pdev = to_pci_dev(dev); 416 struct drm_device *drm_dev = pci_get_drvdata(pdev); 417 int ret; 418 419 if (!amdgpu_device_is_px(drm_dev)) { 420 pm_runtime_forbid(dev); 421 return -EBUSY; 422 } 423 424 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 425 drm_kms_helper_poll_disable(drm_dev); 426 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 427 428 ret = amdgpu_suspend_kms(drm_dev, false, false); 429 pci_save_state(pdev); 430 pci_disable_device(pdev); 431 pci_ignore_hotplug(pdev); 432 if (amdgpu_is_atpx_hybrid()) 433 pci_set_power_state(pdev, PCI_D3cold); 434 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 435 pci_set_power_state(pdev, PCI_D3hot); 436 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 437 438 return 0; 439 } 440 441 static int amdgpu_pmops_runtime_resume(struct device *dev) 442 { 443 struct pci_dev *pdev = to_pci_dev(dev); 444 struct drm_device *drm_dev = pci_get_drvdata(pdev); 445 int ret; 446 447 if (!amdgpu_device_is_px(drm_dev)) 448 return -EINVAL; 449 450 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 451 452 if (amdgpu_is_atpx_hybrid() || 453 !amdgpu_has_atpx_dgpu_power_cntl()) 454 pci_set_power_state(pdev, PCI_D0); 455 pci_restore_state(pdev); 456 ret = pci_enable_device(pdev); 457 if (ret) 458 return ret; 459 pci_set_master(pdev); 460 461 ret = amdgpu_resume_kms(drm_dev, false, false); 462 drm_kms_helper_poll_enable(drm_dev); 463 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 464 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 465 return 0; 466 } 467 468 static int amdgpu_pmops_runtime_idle(struct device *dev) 469 { 470 struct pci_dev *pdev = to_pci_dev(dev); 471 struct drm_device *drm_dev = pci_get_drvdata(pdev); 472 struct drm_crtc *crtc; 473 474 if (!amdgpu_device_is_px(drm_dev)) { 475 pm_runtime_forbid(dev); 476 return -EBUSY; 477 } 478 479 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 480 if (crtc->enabled) { 481 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 482 return -EBUSY; 483 } 484 } 485 486 pm_runtime_mark_last_busy(dev); 487 pm_runtime_autosuspend(dev); 488 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 489 return 1; 490 } 491 492 long amdgpu_drm_ioctl(struct file *filp, 493 unsigned int cmd, unsigned long arg) 494 { 495 struct drm_file *file_priv = filp->private_data; 496 struct drm_device *dev; 497 long ret; 498 dev = file_priv->minor->dev; 499 ret = pm_runtime_get_sync(dev->dev); 500 if (ret < 0) 501 return ret; 502 503 ret = drm_ioctl(filp, cmd, arg); 504 505 pm_runtime_mark_last_busy(dev->dev); 506 pm_runtime_put_autosuspend(dev->dev); 507 return ret; 508 } 509 510 static const struct dev_pm_ops amdgpu_pm_ops = { 511 .suspend = amdgpu_pmops_suspend, 512 .resume = amdgpu_pmops_resume, 513 .freeze = amdgpu_pmops_freeze, 514 .thaw = amdgpu_pmops_thaw, 515 .poweroff = amdgpu_pmops_freeze, 516 .restore = amdgpu_pmops_resume, 517 .runtime_suspend = amdgpu_pmops_runtime_suspend, 518 .runtime_resume = amdgpu_pmops_runtime_resume, 519 .runtime_idle = amdgpu_pmops_runtime_idle, 520 }; 521 522 static const struct file_operations amdgpu_driver_kms_fops = { 523 .owner = THIS_MODULE, 524 .open = drm_open, 525 .release = drm_release, 526 .unlocked_ioctl = amdgpu_drm_ioctl, 527 .mmap = amdgpu_mmap, 528 .poll = drm_poll, 529 .read = drm_read, 530 #ifdef CONFIG_COMPAT 531 .compat_ioctl = amdgpu_kms_compat_ioctl, 532 #endif 533 }; 534 535 static struct drm_driver kms_driver = { 536 .driver_features = 537 DRIVER_USE_AGP | 538 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 539 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, 540 .dev_priv_size = 0, 541 .load = amdgpu_driver_load_kms, 542 .open = amdgpu_driver_open_kms, 543 .preclose = amdgpu_driver_preclose_kms, 544 .postclose = amdgpu_driver_postclose_kms, 545 .lastclose = amdgpu_driver_lastclose_kms, 546 .set_busid = drm_pci_set_busid, 547 .unload = amdgpu_driver_unload_kms, 548 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 549 .enable_vblank = amdgpu_enable_vblank_kms, 550 .disable_vblank = amdgpu_disable_vblank_kms, 551 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 552 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 553 #if defined(CONFIG_DEBUG_FS) 554 .debugfs_init = amdgpu_debugfs_init, 555 .debugfs_cleanup = amdgpu_debugfs_cleanup, 556 #endif 557 .irq_preinstall = amdgpu_irq_preinstall, 558 .irq_postinstall = amdgpu_irq_postinstall, 559 .irq_uninstall = amdgpu_irq_uninstall, 560 .irq_handler = amdgpu_irq_handler, 561 .ioctls = amdgpu_ioctls_kms, 562 .gem_free_object_unlocked = amdgpu_gem_object_free, 563 .gem_open_object = amdgpu_gem_object_open, 564 .gem_close_object = amdgpu_gem_object_close, 565 .dumb_create = amdgpu_mode_dumb_create, 566 .dumb_map_offset = amdgpu_mode_dumb_mmap, 567 .dumb_destroy = drm_gem_dumb_destroy, 568 .fops = &amdgpu_driver_kms_fops, 569 570 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 571 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 572 .gem_prime_export = amdgpu_gem_prime_export, 573 .gem_prime_import = drm_gem_prime_import, 574 .gem_prime_pin = amdgpu_gem_prime_pin, 575 .gem_prime_unpin = amdgpu_gem_prime_unpin, 576 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 577 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 578 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 579 .gem_prime_vmap = amdgpu_gem_prime_vmap, 580 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 581 582 .name = DRIVER_NAME, 583 .desc = DRIVER_DESC, 584 .date = DRIVER_DATE, 585 .major = KMS_DRIVER_MAJOR, 586 .minor = KMS_DRIVER_MINOR, 587 .patchlevel = KMS_DRIVER_PATCHLEVEL, 588 }; 589 590 static struct drm_driver *driver; 591 static struct pci_driver *pdriver; 592 593 static struct pci_driver amdgpu_kms_pci_driver = { 594 .name = DRIVER_NAME, 595 .id_table = pciidlist, 596 .probe = amdgpu_pci_probe, 597 .remove = amdgpu_pci_remove, 598 .driver.pm = &amdgpu_pm_ops, 599 }; 600 601 602 603 static int __init amdgpu_init(void) 604 { 605 amdgpu_sync_init(); 606 amdgpu_fence_slab_init(); 607 if (vgacon_text_force()) { 608 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 609 return -EINVAL; 610 } 611 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 612 driver = &kms_driver; 613 pdriver = &amdgpu_kms_pci_driver; 614 driver->num_ioctls = amdgpu_max_kms_ioctl; 615 amdgpu_register_atpx_handler(); 616 /* let modprobe override vga console setting */ 617 return drm_pci_init(driver, pdriver); 618 } 619 620 static void __exit amdgpu_exit(void) 621 { 622 amdgpu_amdkfd_fini(); 623 drm_pci_exit(driver, pdriver); 624 amdgpu_unregister_atpx_handler(); 625 amdgpu_sync_fini(); 626 amdgpu_fence_slab_fini(); 627 } 628 629 module_init(amdgpu_init); 630 module_exit(amdgpu_exit); 631 632 MODULE_AUTHOR(DRIVER_AUTHOR); 633 MODULE_DESCRIPTION(DRIVER_DESC); 634 MODULE_LICENSE("GPL and additional rights"); 635