1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <[email protected]> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 */ 53 #define KMS_DRIVER_MAJOR 3 54 #define KMS_DRIVER_MINOR 0 55 #define KMS_DRIVER_PATCHLEVEL 0 56 57 int amdgpu_vram_limit = 0; 58 int amdgpu_gart_size = -1; /* auto */ 59 int amdgpu_benchmarking = 0; 60 int amdgpu_testing = 0; 61 int amdgpu_audio = -1; 62 int amdgpu_disp_priority = 0; 63 int amdgpu_hw_i2c = 0; 64 int amdgpu_pcie_gen2 = -1; 65 int amdgpu_msi = -1; 66 int amdgpu_lockup_timeout = 10000; 67 int amdgpu_dpm = -1; 68 int amdgpu_smc_load_fw = 1; 69 int amdgpu_aspm = -1; 70 int amdgpu_runtime_pm = -1; 71 int amdgpu_hard_reset = 0; 72 unsigned amdgpu_ip_block_mask = 0xffffffff; 73 int amdgpu_bapm = -1; 74 int amdgpu_deep_color = 0; 75 int amdgpu_vm_size = 8; 76 int amdgpu_vm_block_size = -1; 77 int amdgpu_exp_hw_support = 0; 78 79 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 80 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 81 82 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 83 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 84 85 MODULE_PARM_DESC(benchmark, "Run benchmark"); 86 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 87 88 MODULE_PARM_DESC(test, "Run tests"); 89 module_param_named(test, amdgpu_testing, int, 0444); 90 91 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 92 module_param_named(audio, amdgpu_audio, int, 0444); 93 94 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 95 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 96 97 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 98 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 99 100 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 101 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 102 103 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 104 module_param_named(msi, amdgpu_msi, int, 0444); 105 106 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 107 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 108 109 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 110 module_param_named(dpm, amdgpu_dpm, int, 0444); 111 112 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 113 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 114 115 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 116 module_param_named(aspm, amdgpu_aspm, int, 0444); 117 118 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 119 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 120 121 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 122 module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); 123 124 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 125 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 126 127 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 128 module_param_named(bapm, amdgpu_bapm, int, 0444); 129 130 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 131 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 132 133 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); 134 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 135 136 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 137 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 138 139 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 140 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 141 142 static struct pci_device_id pciidlist[] = { 143 #ifdef CONFIG_DRM_AMDGPU_CIK 144 /* Kaveri */ 145 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 146 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 147 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 148 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 149 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 150 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 151 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 152 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 153 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 154 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 155 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 156 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 157 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 158 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 159 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 160 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 161 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 162 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 163 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 164 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 165 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 166 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 167 /* Bonaire */ 168 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 169 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 170 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 171 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 172 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 173 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 174 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 175 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 176 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 177 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 178 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 179 /* Hawaii */ 180 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 181 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 182 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 183 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 184 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 185 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 186 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 187 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 188 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 189 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 190 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 191 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 192 /* Kabini */ 193 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 194 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 195 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 196 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 197 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 198 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 199 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 200 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 201 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 202 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 203 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 204 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 205 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 206 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 207 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 208 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 209 /* mullins */ 210 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 211 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 212 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 213 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 214 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 215 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 216 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 217 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 218 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 219 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 220 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 221 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 222 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 223 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 224 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 225 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 226 #endif 227 /* topaz */ 228 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 229 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 230 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 231 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 232 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 233 /* tonga */ 234 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 235 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 236 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 237 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 238 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 239 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 240 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 241 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 242 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 243 /* carrizo */ 244 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 245 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 246 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 247 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 248 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 249 250 {0, 0, 0} 251 }; 252 253 MODULE_DEVICE_TABLE(pci, pciidlist); 254 255 static struct drm_driver kms_driver; 256 257 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 258 { 259 struct apertures_struct *ap; 260 bool primary = false; 261 262 ap = alloc_apertures(1); 263 if (!ap) 264 return -ENOMEM; 265 266 ap->ranges[0].base = pci_resource_start(pdev, 0); 267 ap->ranges[0].size = pci_resource_len(pdev, 0); 268 269 #ifdef CONFIG_X86 270 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 271 #endif 272 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 273 kfree(ap); 274 275 return 0; 276 } 277 278 static int amdgpu_pci_probe(struct pci_dev *pdev, 279 const struct pci_device_id *ent) 280 { 281 unsigned long flags = ent->driver_data; 282 int ret; 283 284 if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 285 DRM_INFO("This hardware requires experimental hardware support.\n" 286 "See modparam exp_hw_support\n"); 287 return -ENODEV; 288 } 289 290 /* Get rid of things like offb */ 291 ret = amdgpu_kick_out_firmware_fb(pdev); 292 if (ret) 293 return ret; 294 295 return drm_get_pci_dev(pdev, ent, &kms_driver); 296 } 297 298 static void 299 amdgpu_pci_remove(struct pci_dev *pdev) 300 { 301 struct drm_device *dev = pci_get_drvdata(pdev); 302 303 drm_put_dev(dev); 304 } 305 306 static int amdgpu_pmops_suspend(struct device *dev) 307 { 308 struct pci_dev *pdev = to_pci_dev(dev); 309 struct drm_device *drm_dev = pci_get_drvdata(pdev); 310 return amdgpu_suspend_kms(drm_dev, true, true); 311 } 312 313 static int amdgpu_pmops_resume(struct device *dev) 314 { 315 struct pci_dev *pdev = to_pci_dev(dev); 316 struct drm_device *drm_dev = pci_get_drvdata(pdev); 317 return amdgpu_resume_kms(drm_dev, true, true); 318 } 319 320 static int amdgpu_pmops_freeze(struct device *dev) 321 { 322 struct pci_dev *pdev = to_pci_dev(dev); 323 struct drm_device *drm_dev = pci_get_drvdata(pdev); 324 return amdgpu_suspend_kms(drm_dev, false, true); 325 } 326 327 static int amdgpu_pmops_thaw(struct device *dev) 328 { 329 struct pci_dev *pdev = to_pci_dev(dev); 330 struct drm_device *drm_dev = pci_get_drvdata(pdev); 331 return amdgpu_resume_kms(drm_dev, false, true); 332 } 333 334 static int amdgpu_pmops_runtime_suspend(struct device *dev) 335 { 336 struct pci_dev *pdev = to_pci_dev(dev); 337 struct drm_device *drm_dev = pci_get_drvdata(pdev); 338 int ret; 339 340 if (!amdgpu_device_is_px(drm_dev)) { 341 pm_runtime_forbid(dev); 342 return -EBUSY; 343 } 344 345 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 346 drm_kms_helper_poll_disable(drm_dev); 347 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 348 349 ret = amdgpu_suspend_kms(drm_dev, false, false); 350 pci_save_state(pdev); 351 pci_disable_device(pdev); 352 pci_ignore_hotplug(pdev); 353 pci_set_power_state(pdev, PCI_D3cold); 354 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 355 356 return 0; 357 } 358 359 static int amdgpu_pmops_runtime_resume(struct device *dev) 360 { 361 struct pci_dev *pdev = to_pci_dev(dev); 362 struct drm_device *drm_dev = pci_get_drvdata(pdev); 363 int ret; 364 365 if (!amdgpu_device_is_px(drm_dev)) 366 return -EINVAL; 367 368 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 369 370 pci_set_power_state(pdev, PCI_D0); 371 pci_restore_state(pdev); 372 ret = pci_enable_device(pdev); 373 if (ret) 374 return ret; 375 pci_set_master(pdev); 376 377 ret = amdgpu_resume_kms(drm_dev, false, false); 378 drm_kms_helper_poll_enable(drm_dev); 379 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 380 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 381 return 0; 382 } 383 384 static int amdgpu_pmops_runtime_idle(struct device *dev) 385 { 386 struct pci_dev *pdev = to_pci_dev(dev); 387 struct drm_device *drm_dev = pci_get_drvdata(pdev); 388 struct drm_crtc *crtc; 389 390 if (!amdgpu_device_is_px(drm_dev)) { 391 pm_runtime_forbid(dev); 392 return -EBUSY; 393 } 394 395 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 396 if (crtc->enabled) { 397 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 398 return -EBUSY; 399 } 400 } 401 402 pm_runtime_mark_last_busy(dev); 403 pm_runtime_autosuspend(dev); 404 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 405 return 1; 406 } 407 408 long amdgpu_drm_ioctl(struct file *filp, 409 unsigned int cmd, unsigned long arg) 410 { 411 struct drm_file *file_priv = filp->private_data; 412 struct drm_device *dev; 413 long ret; 414 dev = file_priv->minor->dev; 415 ret = pm_runtime_get_sync(dev->dev); 416 if (ret < 0) 417 return ret; 418 419 ret = drm_ioctl(filp, cmd, arg); 420 421 pm_runtime_mark_last_busy(dev->dev); 422 pm_runtime_put_autosuspend(dev->dev); 423 return ret; 424 } 425 426 static const struct dev_pm_ops amdgpu_pm_ops = { 427 .suspend = amdgpu_pmops_suspend, 428 .resume = amdgpu_pmops_resume, 429 .freeze = amdgpu_pmops_freeze, 430 .thaw = amdgpu_pmops_thaw, 431 .poweroff = amdgpu_pmops_freeze, 432 .restore = amdgpu_pmops_resume, 433 .runtime_suspend = amdgpu_pmops_runtime_suspend, 434 .runtime_resume = amdgpu_pmops_runtime_resume, 435 .runtime_idle = amdgpu_pmops_runtime_idle, 436 }; 437 438 static const struct file_operations amdgpu_driver_kms_fops = { 439 .owner = THIS_MODULE, 440 .open = drm_open, 441 .release = drm_release, 442 .unlocked_ioctl = amdgpu_drm_ioctl, 443 .mmap = amdgpu_mmap, 444 .poll = drm_poll, 445 .read = drm_read, 446 #ifdef CONFIG_COMPAT 447 .compat_ioctl = amdgpu_kms_compat_ioctl, 448 #endif 449 }; 450 451 static struct drm_driver kms_driver = { 452 .driver_features = 453 DRIVER_USE_AGP | 454 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 455 DRIVER_PRIME | DRIVER_RENDER, 456 .dev_priv_size = 0, 457 .load = amdgpu_driver_load_kms, 458 .open = amdgpu_driver_open_kms, 459 .preclose = amdgpu_driver_preclose_kms, 460 .postclose = amdgpu_driver_postclose_kms, 461 .lastclose = amdgpu_driver_lastclose_kms, 462 .set_busid = drm_pci_set_busid, 463 .unload = amdgpu_driver_unload_kms, 464 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 465 .enable_vblank = amdgpu_enable_vblank_kms, 466 .disable_vblank = amdgpu_disable_vblank_kms, 467 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 468 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 469 #if defined(CONFIG_DEBUG_FS) 470 .debugfs_init = amdgpu_debugfs_init, 471 .debugfs_cleanup = amdgpu_debugfs_cleanup, 472 #endif 473 .irq_preinstall = amdgpu_irq_preinstall, 474 .irq_postinstall = amdgpu_irq_postinstall, 475 .irq_uninstall = amdgpu_irq_uninstall, 476 .irq_handler = amdgpu_irq_handler, 477 .ioctls = amdgpu_ioctls_kms, 478 .gem_free_object = amdgpu_gem_object_free, 479 .gem_open_object = amdgpu_gem_object_open, 480 .gem_close_object = amdgpu_gem_object_close, 481 .dumb_create = amdgpu_mode_dumb_create, 482 .dumb_map_offset = amdgpu_mode_dumb_mmap, 483 .dumb_destroy = drm_gem_dumb_destroy, 484 .fops = &amdgpu_driver_kms_fops, 485 486 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 487 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 488 .gem_prime_export = amdgpu_gem_prime_export, 489 .gem_prime_import = drm_gem_prime_import, 490 .gem_prime_pin = amdgpu_gem_prime_pin, 491 .gem_prime_unpin = amdgpu_gem_prime_unpin, 492 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 493 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 494 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 495 .gem_prime_vmap = amdgpu_gem_prime_vmap, 496 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 497 498 .name = DRIVER_NAME, 499 .desc = DRIVER_DESC, 500 .date = DRIVER_DATE, 501 .major = KMS_DRIVER_MAJOR, 502 .minor = KMS_DRIVER_MINOR, 503 .patchlevel = KMS_DRIVER_PATCHLEVEL, 504 }; 505 506 static struct drm_driver *driver; 507 static struct pci_driver *pdriver; 508 509 static struct pci_driver amdgpu_kms_pci_driver = { 510 .name = DRIVER_NAME, 511 .id_table = pciidlist, 512 .probe = amdgpu_pci_probe, 513 .remove = amdgpu_pci_remove, 514 .driver.pm = &amdgpu_pm_ops, 515 }; 516 517 static int __init amdgpu_init(void) 518 { 519 #ifdef CONFIG_VGA_CONSOLE 520 if (vgacon_text_force()) { 521 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 522 return -EINVAL; 523 } 524 #endif 525 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 526 driver = &kms_driver; 527 pdriver = &amdgpu_kms_pci_driver; 528 driver->driver_features |= DRIVER_MODESET; 529 driver->num_ioctls = amdgpu_max_kms_ioctl; 530 amdgpu_register_atpx_handler(); 531 532 amdgpu_amdkfd_init(); 533 534 /* let modprobe override vga console setting */ 535 return drm_pci_init(driver, pdriver); 536 } 537 538 static void __exit amdgpu_exit(void) 539 { 540 amdgpu_amdkfd_fini(); 541 drm_pci_exit(driver, pdriver); 542 amdgpu_unregister_atpx_handler(); 543 } 544 545 module_init(amdgpu_init); 546 module_exit(amdgpu_exit); 547 548 MODULE_AUTHOR(DRIVER_AUTHOR); 549 MODULE_DESCRIPTION(DRIVER_DESC); 550 MODULE_LICENSE("GPL and additional rights"); 551