1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_generic.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/drm_managed.h> 32 #include "amdgpu_drv.h" 33 34 #include <drm/drm_pciids.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 #include <linux/fb.h> 43 #include <linux/dynamic_debug.h> 44 45 #include "amdgpu.h" 46 #include "amdgpu_irq.h" 47 #include "amdgpu_dma_buf.h" 48 #include "amdgpu_sched.h" 49 #include "amdgpu_fdinfo.h" 50 #include "amdgpu_amdkfd.h" 51 52 #include "amdgpu_ras.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_reset.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * 3.49.0 - Add gang submit into CS IOCTL 109 */ 110 #define KMS_DRIVER_MAJOR 3 111 #define KMS_DRIVER_MINOR 49 112 #define KMS_DRIVER_PATCHLEVEL 0 113 114 int amdgpu_vram_limit; 115 int amdgpu_vis_vram_limit; 116 int amdgpu_gart_size = -1; /* auto */ 117 int amdgpu_gtt_size = -1; /* auto */ 118 int amdgpu_moverate = -1; /* auto */ 119 int amdgpu_audio = -1; 120 int amdgpu_disp_priority; 121 int amdgpu_hw_i2c; 122 int amdgpu_pcie_gen2 = -1; 123 int amdgpu_msi = -1; 124 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 125 int amdgpu_dpm = -1; 126 int amdgpu_fw_load_type = -1; 127 int amdgpu_aspm = -1; 128 int amdgpu_runtime_pm = -1; 129 uint amdgpu_ip_block_mask = 0xffffffff; 130 int amdgpu_bapm = -1; 131 int amdgpu_deep_color; 132 int amdgpu_vm_size = -1; 133 int amdgpu_vm_fragment_size = -1; 134 int amdgpu_vm_block_size = -1; 135 int amdgpu_vm_fault_stop; 136 int amdgpu_vm_debug; 137 int amdgpu_vm_update_mode = -1; 138 int amdgpu_exp_hw_support; 139 int amdgpu_dc = -1; 140 int amdgpu_sched_jobs = 32; 141 int amdgpu_sched_hw_submission = 2; 142 uint amdgpu_pcie_gen_cap; 143 uint amdgpu_pcie_lane_cap; 144 u64 amdgpu_cg_mask = 0xffffffffffffffff; 145 uint amdgpu_pg_mask = 0xffffffff; 146 uint amdgpu_sdma_phase_quantum = 32; 147 char *amdgpu_disable_cu = NULL; 148 char *amdgpu_virtual_display = NULL; 149 150 /* 151 * OverDrive(bit 14) disabled by default 152 * GFX DCS(bit 19) disabled by default 153 */ 154 uint amdgpu_pp_feature_mask = 0xfff7bfff; 155 uint amdgpu_force_long_training; 156 int amdgpu_job_hang_limit; 157 int amdgpu_lbpw = -1; 158 int amdgpu_compute_multipipe = -1; 159 int amdgpu_gpu_recovery = -1; /* auto */ 160 int amdgpu_emu_mode; 161 uint amdgpu_smu_memory_pool_size; 162 int amdgpu_smu_pptable_id = -1; 163 /* 164 * FBC (bit 0) disabled by default 165 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 166 * - With this, for multiple monitors in sync(e.g. with the same model), 167 * mclk switching will be allowed. And the mclk will be not foced to the 168 * highest. That helps saving some idle power. 169 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 170 * PSR (bit 3) disabled by default 171 * EDP NO POWER SEQUENCING (bit 4) disabled by default 172 */ 173 uint amdgpu_dc_feature_mask = 2; 174 uint amdgpu_dc_debug_mask; 175 uint amdgpu_dc_visual_confirm; 176 int amdgpu_async_gfx_ring = 1; 177 int amdgpu_mcbp; 178 int amdgpu_discovery = -1; 179 int amdgpu_mes; 180 int amdgpu_mes_kiq; 181 int amdgpu_noretry = -1; 182 int amdgpu_force_asic_type = -1; 183 int amdgpu_tmz = -1; /* auto */ 184 int amdgpu_reset_method = -1; /* auto */ 185 int amdgpu_num_kcq = -1; 186 int amdgpu_smartshift_bias; 187 int amdgpu_use_xgmi_p2p = 1; 188 int amdgpu_vcnfw_log; 189 190 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 191 192 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 193 "DRM_UT_CORE", 194 "DRM_UT_DRIVER", 195 "DRM_UT_KMS", 196 "DRM_UT_PRIME", 197 "DRM_UT_ATOMIC", 198 "DRM_UT_VBL", 199 "DRM_UT_STATE", 200 "DRM_UT_LEASE", 201 "DRM_UT_DP", 202 "DRM_UT_DRMRES"); 203 204 struct amdgpu_mgpu_info mgpu_info = { 205 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 206 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 207 mgpu_info.delayed_reset_work, 208 amdgpu_drv_delayed_reset_work_handler, 0), 209 }; 210 int amdgpu_ras_enable = -1; 211 uint amdgpu_ras_mask = 0xffffffff; 212 int amdgpu_bad_page_threshold = -1; 213 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 214 .timeout_fatal_disable = false, 215 .period = 0x0, /* default to 0x0 (timeout disable) */ 216 }; 217 218 /** 219 * DOC: vramlimit (int) 220 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 221 */ 222 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 223 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 224 225 /** 226 * DOC: vis_vramlimit (int) 227 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 228 */ 229 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 230 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 231 232 /** 233 * DOC: gartsize (uint) 234 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 235 */ 236 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 237 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 238 239 /** 240 * DOC: gttsize (int) 241 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 242 * otherwise 3/4 RAM size). 243 */ 244 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 245 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 246 247 /** 248 * DOC: moverate (int) 249 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 250 */ 251 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 252 module_param_named(moverate, amdgpu_moverate, int, 0600); 253 254 /** 255 * DOC: audio (int) 256 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 257 */ 258 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 259 module_param_named(audio, amdgpu_audio, int, 0444); 260 261 /** 262 * DOC: disp_priority (int) 263 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 264 */ 265 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 266 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 267 268 /** 269 * DOC: hw_i2c (int) 270 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 271 */ 272 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 273 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 274 275 /** 276 * DOC: pcie_gen2 (int) 277 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 278 */ 279 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 280 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 281 282 /** 283 * DOC: msi (int) 284 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 285 */ 286 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(msi, amdgpu_msi, int, 0444); 288 289 /** 290 * DOC: lockup_timeout (string) 291 * Set GPU scheduler timeout value in ms. 292 * 293 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 294 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 295 * to the default timeout. 296 * 297 * - With one value specified, the setting will apply to all non-compute jobs. 298 * - With multiple values specified, the first one will be for GFX. 299 * The second one is for Compute. The third and fourth ones are 300 * for SDMA and Video. 301 * 302 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 303 * jobs is 10000. The timeout for compute is 60000. 304 */ 305 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 306 "for passthrough or sriov, 10000 for all jobs." 307 " 0: keep default value. negative: infinity timeout), " 308 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 309 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 310 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 311 312 /** 313 * DOC: dpm (int) 314 * Override for dynamic power management setting 315 * (0 = disable, 1 = enable) 316 * The default is -1 (auto). 317 */ 318 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 319 module_param_named(dpm, amdgpu_dpm, int, 0444); 320 321 /** 322 * DOC: fw_load_type (int) 323 * Set different firmware loading type for debugging, if supported. 324 * Set to 0 to force direct loading if supported by the ASIC. Set 325 * to -1 to select the default loading mode for the ASIC, as defined 326 * by the driver. The default is -1 (auto). 327 */ 328 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 329 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 330 331 /** 332 * DOC: aspm (int) 333 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 334 */ 335 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 336 module_param_named(aspm, amdgpu_aspm, int, 0444); 337 338 /** 339 * DOC: runpm (int) 340 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 341 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 342 * Setting the value to 0 disables this functionality. 343 */ 344 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 345 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 346 347 /** 348 * DOC: ip_block_mask (uint) 349 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 350 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 351 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 352 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 353 */ 354 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 355 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 356 357 /** 358 * DOC: bapm (int) 359 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 360 * The default -1 (auto, enabled) 361 */ 362 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 363 module_param_named(bapm, amdgpu_bapm, int, 0444); 364 365 /** 366 * DOC: deep_color (int) 367 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 368 */ 369 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 370 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 371 372 /** 373 * DOC: vm_size (int) 374 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 375 */ 376 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 377 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 378 379 /** 380 * DOC: vm_fragment_size (int) 381 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 382 */ 383 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 384 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 385 386 /** 387 * DOC: vm_block_size (int) 388 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 389 */ 390 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 391 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 392 393 /** 394 * DOC: vm_fault_stop (int) 395 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 396 */ 397 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 398 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 399 400 /** 401 * DOC: vm_debug (int) 402 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 403 */ 404 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 405 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 406 407 /** 408 * DOC: vm_update_mode (int) 409 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 410 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 411 */ 412 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 413 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 414 415 /** 416 * DOC: exp_hw_support (int) 417 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 418 */ 419 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 420 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 421 422 /** 423 * DOC: dc (int) 424 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 425 */ 426 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 427 module_param_named(dc, amdgpu_dc, int, 0444); 428 429 /** 430 * DOC: sched_jobs (int) 431 * Override the max number of jobs supported in the sw queue. The default is 32. 432 */ 433 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 434 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 435 436 /** 437 * DOC: sched_hw_submission (int) 438 * Override the max number of HW submissions. The default is 2. 439 */ 440 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 441 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 442 443 /** 444 * DOC: ppfeaturemask (hexint) 445 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 446 * The default is the current set of stable power features. 447 */ 448 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 449 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 450 451 /** 452 * DOC: forcelongtraining (uint) 453 * Force long memory training in resume. 454 * The default is zero, indicates short training in resume. 455 */ 456 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 457 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 458 459 /** 460 * DOC: pcie_gen_cap (uint) 461 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 462 * The default is 0 (automatic for each asic). 463 */ 464 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 465 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 466 467 /** 468 * DOC: pcie_lane_cap (uint) 469 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 470 * The default is 0 (automatic for each asic). 471 */ 472 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 473 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 474 475 /** 476 * DOC: cg_mask (ullong) 477 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 478 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 479 */ 480 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 481 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 482 483 /** 484 * DOC: pg_mask (uint) 485 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 486 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 487 */ 488 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 489 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 490 491 /** 492 * DOC: sdma_phase_quantum (uint) 493 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 494 */ 495 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 496 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 497 498 /** 499 * DOC: disable_cu (charp) 500 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 501 */ 502 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 503 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 504 505 /** 506 * DOC: virtual_display (charp) 507 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 508 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 509 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 510 * device at 26:00.0. The default is NULL. 511 */ 512 MODULE_PARM_DESC(virtual_display, 513 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 514 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 515 516 /** 517 * DOC: job_hang_limit (int) 518 * Set how much time allow a job hang and not drop it. The default is 0. 519 */ 520 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 521 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 522 523 /** 524 * DOC: lbpw (int) 525 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 526 */ 527 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 528 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 529 530 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 532 533 /** 534 * DOC: gpu_recovery (int) 535 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 536 */ 537 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 538 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 539 540 /** 541 * DOC: emu_mode (int) 542 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 543 */ 544 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 545 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 546 547 /** 548 * DOC: ras_enable (int) 549 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 550 */ 551 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 552 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 553 554 /** 555 * DOC: ras_mask (uint) 556 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 557 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 558 */ 559 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 560 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 561 562 /** 563 * DOC: timeout_fatal_disable (bool) 564 * Disable Watchdog timeout fatal error event 565 */ 566 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 567 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 568 569 /** 570 * DOC: timeout_period (uint) 571 * Modify the watchdog timeout max_cycles as (1 << period) 572 */ 573 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 574 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 575 576 /** 577 * DOC: si_support (int) 578 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 580 * otherwise using amdgpu driver. 581 */ 582 #ifdef CONFIG_DRM_AMDGPU_SI 583 584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 585 int amdgpu_si_support = 0; 586 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 587 #else 588 int amdgpu_si_support = 1; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 590 #endif 591 592 module_param_named(si_support, amdgpu_si_support, int, 0444); 593 #endif 594 595 /** 596 * DOC: cik_support (int) 597 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 598 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 599 * otherwise using amdgpu driver. 600 */ 601 #ifdef CONFIG_DRM_AMDGPU_CIK 602 603 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 604 int amdgpu_cik_support = 0; 605 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 606 #else 607 int amdgpu_cik_support = 1; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 609 #endif 610 611 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 612 #endif 613 614 /** 615 * DOC: smu_memory_pool_size (uint) 616 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 617 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 618 */ 619 MODULE_PARM_DESC(smu_memory_pool_size, 620 "reserve gtt for smu debug usage, 0 = disable," 621 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 623 624 /** 625 * DOC: async_gfx_ring (int) 626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 627 */ 628 MODULE_PARM_DESC(async_gfx_ring, 629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 631 632 /** 633 * DOC: mcbp (int) 634 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 635 */ 636 MODULE_PARM_DESC(mcbp, 637 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 638 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 639 640 /** 641 * DOC: discovery (int) 642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 644 */ 645 MODULE_PARM_DESC(discovery, 646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 647 module_param_named(discovery, amdgpu_discovery, int, 0444); 648 649 /** 650 * DOC: mes (int) 651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 652 * (0 = disabled (default), 1 = enabled) 653 */ 654 MODULE_PARM_DESC(mes, 655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 656 module_param_named(mes, amdgpu_mes, int, 0444); 657 658 /** 659 * DOC: mes_kiq (int) 660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 661 * (0 = disabled (default), 1 = enabled) 662 */ 663 MODULE_PARM_DESC(mes_kiq, 664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 666 667 /** 668 * DOC: noretry (int) 669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 670 * do not support per-process XNACK this also disables retry page faults. 671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 672 */ 673 MODULE_PARM_DESC(noretry, 674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 675 module_param_named(noretry, amdgpu_noretry, int, 0644); 676 677 /** 678 * DOC: force_asic_type (int) 679 * A non negative value used to specify the asic type for all supported GPUs. 680 */ 681 MODULE_PARM_DESC(force_asic_type, 682 "A non negative value used to specify the asic type for all supported GPUs"); 683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 684 685 /** 686 * DOC: use_xgmi_p2p (int) 687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 688 */ 689 MODULE_PARM_DESC(use_xgmi_p2p, 690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 692 693 694 #ifdef CONFIG_HSA_AMD 695 /** 696 * DOC: sched_policy (int) 697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 699 * assigns queues to HQDs. 700 */ 701 int sched_policy = KFD_SCHED_POLICY_HWS; 702 module_param(sched_policy, int, 0444); 703 MODULE_PARM_DESC(sched_policy, 704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 705 706 /** 707 * DOC: hws_max_conc_proc (int) 708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 709 * number of VMIDs assigned to the HWS, which is also the default. 710 */ 711 int hws_max_conc_proc = -1; 712 module_param(hws_max_conc_proc, int, 0444); 713 MODULE_PARM_DESC(hws_max_conc_proc, 714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 715 716 /** 717 * DOC: cwsr_enable (int) 718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 720 * disables it. 721 */ 722 int cwsr_enable = 1; 723 module_param(cwsr_enable, int, 0444); 724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 725 726 /** 727 * DOC: max_num_of_queues_per_device (int) 728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 729 * is 4096. 730 */ 731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 732 module_param(max_num_of_queues_per_device, int, 0444); 733 MODULE_PARM_DESC(max_num_of_queues_per_device, 734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 735 736 /** 737 * DOC: send_sigterm (int) 738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 739 * but just print errors on dmesg. Setting 1 enables sending sigterm. 740 */ 741 int send_sigterm; 742 module_param(send_sigterm, int, 0444); 743 MODULE_PARM_DESC(send_sigterm, 744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 745 746 /** 747 * DOC: debug_largebar (int) 748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 749 * system. This limits the VRAM size reported to ROCm applications to the visible 750 * size, usually 256MB. 751 * Default value is 0, diabled. 752 */ 753 int debug_largebar; 754 module_param(debug_largebar, int, 0444); 755 MODULE_PARM_DESC(debug_largebar, 756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 757 758 /** 759 * DOC: ignore_crat (int) 760 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 761 * table to get information about AMD APUs. This option can serve as a workaround on 762 * systems with a broken CRAT table. 763 * 764 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 765 * whether use CRAT) 766 */ 767 int ignore_crat; 768 module_param(ignore_crat, int, 0444); 769 MODULE_PARM_DESC(ignore_crat, 770 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 771 772 /** 773 * DOC: halt_if_hws_hang (int) 774 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 775 * Setting 1 enables halt on hang. 776 */ 777 int halt_if_hws_hang; 778 module_param(halt_if_hws_hang, int, 0644); 779 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 780 781 /** 782 * DOC: hws_gws_support(bool) 783 * Assume that HWS supports GWS barriers regardless of what firmware version 784 * check says. Default value: false (rely on MEC2 firmware version check). 785 */ 786 bool hws_gws_support; 787 module_param(hws_gws_support, bool, 0444); 788 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 789 790 /** 791 * DOC: queue_preemption_timeout_ms (int) 792 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 793 */ 794 int queue_preemption_timeout_ms = 9000; 795 module_param(queue_preemption_timeout_ms, int, 0644); 796 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 797 798 /** 799 * DOC: debug_evictions(bool) 800 * Enable extra debug messages to help determine the cause of evictions 801 */ 802 bool debug_evictions; 803 module_param(debug_evictions, bool, 0644); 804 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 805 806 /** 807 * DOC: no_system_mem_limit(bool) 808 * Disable system memory limit, to support multiple process shared memory 809 */ 810 bool no_system_mem_limit; 811 module_param(no_system_mem_limit, bool, 0644); 812 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 813 814 /** 815 * DOC: no_queue_eviction_on_vm_fault (int) 816 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 817 */ 818 int amdgpu_no_queue_eviction_on_vm_fault = 0; 819 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 820 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 821 #endif 822 823 /** 824 * DOC: pcie_p2p (bool) 825 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 826 */ 827 #ifdef CONFIG_HSA_AMD_P2P 828 bool pcie_p2p = true; 829 module_param(pcie_p2p, bool, 0444); 830 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 831 #endif 832 833 /** 834 * DOC: dcfeaturemask (uint) 835 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 836 * The default is the current set of stable display features. 837 */ 838 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 839 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 840 841 /** 842 * DOC: dcdebugmask (uint) 843 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 844 */ 845 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 846 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 847 848 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 849 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 850 851 /** 852 * DOC: abmlevel (uint) 853 * Override the default ABM (Adaptive Backlight Management) level used for DC 854 * enabled hardware. Requires DMCU to be supported and loaded. 855 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 856 * default. Values 1-4 control the maximum allowable brightness reduction via 857 * the ABM algorithm, with 1 being the least reduction and 4 being the most 858 * reduction. 859 * 860 * Defaults to 0, or disabled. Userspace can still override this level later 861 * after boot. 862 */ 863 uint amdgpu_dm_abm_level; 864 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 865 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 866 867 int amdgpu_backlight = -1; 868 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 869 module_param_named(backlight, amdgpu_backlight, bint, 0444); 870 871 /** 872 * DOC: tmz (int) 873 * Trusted Memory Zone (TMZ) is a method to protect data being written 874 * to or read from memory. 875 * 876 * The default value: 0 (off). TODO: change to auto till it is completed. 877 */ 878 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 879 module_param_named(tmz, amdgpu_tmz, int, 0444); 880 881 /** 882 * DOC: reset_method (int) 883 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 884 */ 885 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 886 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 887 888 /** 889 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 890 * threshold value of faulty pages detected by RAS ECC, which may 891 * result in the GPU entering bad status when the number of total 892 * faulty pages by ECC exceeds the threshold value. 893 */ 894 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 895 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 896 897 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 898 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 899 900 /** 901 * DOC: vcnfw_log (int) 902 * Enable vcnfw log output for debugging, the default is disabled. 903 */ 904 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 905 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 906 907 /** 908 * DOC: smu_pptable_id (int) 909 * Used to override pptable id. id = 0 use VBIOS pptable. 910 * id > 0 use the soft pptable with specicfied id. 911 */ 912 MODULE_PARM_DESC(smu_pptable_id, 913 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 914 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 915 916 /* These devices are not supported by amdgpu. 917 * They are supported by the mach64, r128, radeon drivers 918 */ 919 static const u16 amdgpu_unsupported_pciidlist[] = { 920 /* mach64 */ 921 0x4354, 922 0x4358, 923 0x4554, 924 0x4742, 925 0x4744, 926 0x4749, 927 0x474C, 928 0x474D, 929 0x474E, 930 0x474F, 931 0x4750, 932 0x4751, 933 0x4752, 934 0x4753, 935 0x4754, 936 0x4755, 937 0x4756, 938 0x4757, 939 0x4758, 940 0x4759, 941 0x475A, 942 0x4C42, 943 0x4C44, 944 0x4C47, 945 0x4C49, 946 0x4C4D, 947 0x4C4E, 948 0x4C50, 949 0x4C51, 950 0x4C52, 951 0x4C53, 952 0x5654, 953 0x5655, 954 0x5656, 955 /* r128 */ 956 0x4c45, 957 0x4c46, 958 0x4d46, 959 0x4d4c, 960 0x5041, 961 0x5042, 962 0x5043, 963 0x5044, 964 0x5045, 965 0x5046, 966 0x5047, 967 0x5048, 968 0x5049, 969 0x504A, 970 0x504B, 971 0x504C, 972 0x504D, 973 0x504E, 974 0x504F, 975 0x5050, 976 0x5051, 977 0x5052, 978 0x5053, 979 0x5054, 980 0x5055, 981 0x5056, 982 0x5057, 983 0x5058, 984 0x5245, 985 0x5246, 986 0x5247, 987 0x524b, 988 0x524c, 989 0x534d, 990 0x5446, 991 0x544C, 992 0x5452, 993 /* radeon */ 994 0x3150, 995 0x3151, 996 0x3152, 997 0x3154, 998 0x3155, 999 0x3E50, 1000 0x3E54, 1001 0x4136, 1002 0x4137, 1003 0x4144, 1004 0x4145, 1005 0x4146, 1006 0x4147, 1007 0x4148, 1008 0x4149, 1009 0x414A, 1010 0x414B, 1011 0x4150, 1012 0x4151, 1013 0x4152, 1014 0x4153, 1015 0x4154, 1016 0x4155, 1017 0x4156, 1018 0x4237, 1019 0x4242, 1020 0x4336, 1021 0x4337, 1022 0x4437, 1023 0x4966, 1024 0x4967, 1025 0x4A48, 1026 0x4A49, 1027 0x4A4A, 1028 0x4A4B, 1029 0x4A4C, 1030 0x4A4D, 1031 0x4A4E, 1032 0x4A4F, 1033 0x4A50, 1034 0x4A54, 1035 0x4B48, 1036 0x4B49, 1037 0x4B4A, 1038 0x4B4B, 1039 0x4B4C, 1040 0x4C57, 1041 0x4C58, 1042 0x4C59, 1043 0x4C5A, 1044 0x4C64, 1045 0x4C66, 1046 0x4C67, 1047 0x4E44, 1048 0x4E45, 1049 0x4E46, 1050 0x4E47, 1051 0x4E48, 1052 0x4E49, 1053 0x4E4A, 1054 0x4E4B, 1055 0x4E50, 1056 0x4E51, 1057 0x4E52, 1058 0x4E53, 1059 0x4E54, 1060 0x4E56, 1061 0x5144, 1062 0x5145, 1063 0x5146, 1064 0x5147, 1065 0x5148, 1066 0x514C, 1067 0x514D, 1068 0x5157, 1069 0x5158, 1070 0x5159, 1071 0x515A, 1072 0x515E, 1073 0x5460, 1074 0x5462, 1075 0x5464, 1076 0x5548, 1077 0x5549, 1078 0x554A, 1079 0x554B, 1080 0x554C, 1081 0x554D, 1082 0x554E, 1083 0x554F, 1084 0x5550, 1085 0x5551, 1086 0x5552, 1087 0x5554, 1088 0x564A, 1089 0x564B, 1090 0x564F, 1091 0x5652, 1092 0x5653, 1093 0x5657, 1094 0x5834, 1095 0x5835, 1096 0x5954, 1097 0x5955, 1098 0x5974, 1099 0x5975, 1100 0x5960, 1101 0x5961, 1102 0x5962, 1103 0x5964, 1104 0x5965, 1105 0x5969, 1106 0x5a41, 1107 0x5a42, 1108 0x5a61, 1109 0x5a62, 1110 0x5b60, 1111 0x5b62, 1112 0x5b63, 1113 0x5b64, 1114 0x5b65, 1115 0x5c61, 1116 0x5c63, 1117 0x5d48, 1118 0x5d49, 1119 0x5d4a, 1120 0x5d4c, 1121 0x5d4d, 1122 0x5d4e, 1123 0x5d4f, 1124 0x5d50, 1125 0x5d52, 1126 0x5d57, 1127 0x5e48, 1128 0x5e4a, 1129 0x5e4b, 1130 0x5e4c, 1131 0x5e4d, 1132 0x5e4f, 1133 0x6700, 1134 0x6701, 1135 0x6702, 1136 0x6703, 1137 0x6704, 1138 0x6705, 1139 0x6706, 1140 0x6707, 1141 0x6708, 1142 0x6709, 1143 0x6718, 1144 0x6719, 1145 0x671c, 1146 0x671d, 1147 0x671f, 1148 0x6720, 1149 0x6721, 1150 0x6722, 1151 0x6723, 1152 0x6724, 1153 0x6725, 1154 0x6726, 1155 0x6727, 1156 0x6728, 1157 0x6729, 1158 0x6738, 1159 0x6739, 1160 0x673e, 1161 0x6740, 1162 0x6741, 1163 0x6742, 1164 0x6743, 1165 0x6744, 1166 0x6745, 1167 0x6746, 1168 0x6747, 1169 0x6748, 1170 0x6749, 1171 0x674A, 1172 0x6750, 1173 0x6751, 1174 0x6758, 1175 0x6759, 1176 0x675B, 1177 0x675D, 1178 0x675F, 1179 0x6760, 1180 0x6761, 1181 0x6762, 1182 0x6763, 1183 0x6764, 1184 0x6765, 1185 0x6766, 1186 0x6767, 1187 0x6768, 1188 0x6770, 1189 0x6771, 1190 0x6772, 1191 0x6778, 1192 0x6779, 1193 0x677B, 1194 0x6840, 1195 0x6841, 1196 0x6842, 1197 0x6843, 1198 0x6849, 1199 0x684C, 1200 0x6850, 1201 0x6858, 1202 0x6859, 1203 0x6880, 1204 0x6888, 1205 0x6889, 1206 0x688A, 1207 0x688C, 1208 0x688D, 1209 0x6898, 1210 0x6899, 1211 0x689b, 1212 0x689c, 1213 0x689d, 1214 0x689e, 1215 0x68a0, 1216 0x68a1, 1217 0x68a8, 1218 0x68a9, 1219 0x68b0, 1220 0x68b8, 1221 0x68b9, 1222 0x68ba, 1223 0x68be, 1224 0x68bf, 1225 0x68c0, 1226 0x68c1, 1227 0x68c7, 1228 0x68c8, 1229 0x68c9, 1230 0x68d8, 1231 0x68d9, 1232 0x68da, 1233 0x68de, 1234 0x68e0, 1235 0x68e1, 1236 0x68e4, 1237 0x68e5, 1238 0x68e8, 1239 0x68e9, 1240 0x68f1, 1241 0x68f2, 1242 0x68f8, 1243 0x68f9, 1244 0x68fa, 1245 0x68fe, 1246 0x7100, 1247 0x7101, 1248 0x7102, 1249 0x7103, 1250 0x7104, 1251 0x7105, 1252 0x7106, 1253 0x7108, 1254 0x7109, 1255 0x710A, 1256 0x710B, 1257 0x710C, 1258 0x710E, 1259 0x710F, 1260 0x7140, 1261 0x7141, 1262 0x7142, 1263 0x7143, 1264 0x7144, 1265 0x7145, 1266 0x7146, 1267 0x7147, 1268 0x7149, 1269 0x714A, 1270 0x714B, 1271 0x714C, 1272 0x714D, 1273 0x714E, 1274 0x714F, 1275 0x7151, 1276 0x7152, 1277 0x7153, 1278 0x715E, 1279 0x715F, 1280 0x7180, 1281 0x7181, 1282 0x7183, 1283 0x7186, 1284 0x7187, 1285 0x7188, 1286 0x718A, 1287 0x718B, 1288 0x718C, 1289 0x718D, 1290 0x718F, 1291 0x7193, 1292 0x7196, 1293 0x719B, 1294 0x719F, 1295 0x71C0, 1296 0x71C1, 1297 0x71C2, 1298 0x71C3, 1299 0x71C4, 1300 0x71C5, 1301 0x71C6, 1302 0x71C7, 1303 0x71CD, 1304 0x71CE, 1305 0x71D2, 1306 0x71D4, 1307 0x71D5, 1308 0x71D6, 1309 0x71DA, 1310 0x71DE, 1311 0x7200, 1312 0x7210, 1313 0x7211, 1314 0x7240, 1315 0x7243, 1316 0x7244, 1317 0x7245, 1318 0x7246, 1319 0x7247, 1320 0x7248, 1321 0x7249, 1322 0x724A, 1323 0x724B, 1324 0x724C, 1325 0x724D, 1326 0x724E, 1327 0x724F, 1328 0x7280, 1329 0x7281, 1330 0x7283, 1331 0x7284, 1332 0x7287, 1333 0x7288, 1334 0x7289, 1335 0x728B, 1336 0x728C, 1337 0x7290, 1338 0x7291, 1339 0x7293, 1340 0x7297, 1341 0x7834, 1342 0x7835, 1343 0x791e, 1344 0x791f, 1345 0x793f, 1346 0x7941, 1347 0x7942, 1348 0x796c, 1349 0x796d, 1350 0x796e, 1351 0x796f, 1352 0x9400, 1353 0x9401, 1354 0x9402, 1355 0x9403, 1356 0x9405, 1357 0x940A, 1358 0x940B, 1359 0x940F, 1360 0x94A0, 1361 0x94A1, 1362 0x94A3, 1363 0x94B1, 1364 0x94B3, 1365 0x94B4, 1366 0x94B5, 1367 0x94B9, 1368 0x9440, 1369 0x9441, 1370 0x9442, 1371 0x9443, 1372 0x9444, 1373 0x9446, 1374 0x944A, 1375 0x944B, 1376 0x944C, 1377 0x944E, 1378 0x9450, 1379 0x9452, 1380 0x9456, 1381 0x945A, 1382 0x945B, 1383 0x945E, 1384 0x9460, 1385 0x9462, 1386 0x946A, 1387 0x946B, 1388 0x947A, 1389 0x947B, 1390 0x9480, 1391 0x9487, 1392 0x9488, 1393 0x9489, 1394 0x948A, 1395 0x948F, 1396 0x9490, 1397 0x9491, 1398 0x9495, 1399 0x9498, 1400 0x949C, 1401 0x949E, 1402 0x949F, 1403 0x94C0, 1404 0x94C1, 1405 0x94C3, 1406 0x94C4, 1407 0x94C5, 1408 0x94C6, 1409 0x94C7, 1410 0x94C8, 1411 0x94C9, 1412 0x94CB, 1413 0x94CC, 1414 0x94CD, 1415 0x9500, 1416 0x9501, 1417 0x9504, 1418 0x9505, 1419 0x9506, 1420 0x9507, 1421 0x9508, 1422 0x9509, 1423 0x950F, 1424 0x9511, 1425 0x9515, 1426 0x9517, 1427 0x9519, 1428 0x9540, 1429 0x9541, 1430 0x9542, 1431 0x954E, 1432 0x954F, 1433 0x9552, 1434 0x9553, 1435 0x9555, 1436 0x9557, 1437 0x955f, 1438 0x9580, 1439 0x9581, 1440 0x9583, 1441 0x9586, 1442 0x9587, 1443 0x9588, 1444 0x9589, 1445 0x958A, 1446 0x958B, 1447 0x958C, 1448 0x958D, 1449 0x958E, 1450 0x958F, 1451 0x9590, 1452 0x9591, 1453 0x9593, 1454 0x9595, 1455 0x9596, 1456 0x9597, 1457 0x9598, 1458 0x9599, 1459 0x959B, 1460 0x95C0, 1461 0x95C2, 1462 0x95C4, 1463 0x95C5, 1464 0x95C6, 1465 0x95C7, 1466 0x95C9, 1467 0x95CC, 1468 0x95CD, 1469 0x95CE, 1470 0x95CF, 1471 0x9610, 1472 0x9611, 1473 0x9612, 1474 0x9613, 1475 0x9614, 1476 0x9615, 1477 0x9616, 1478 0x9640, 1479 0x9641, 1480 0x9642, 1481 0x9643, 1482 0x9644, 1483 0x9645, 1484 0x9647, 1485 0x9648, 1486 0x9649, 1487 0x964a, 1488 0x964b, 1489 0x964c, 1490 0x964e, 1491 0x964f, 1492 0x9710, 1493 0x9711, 1494 0x9712, 1495 0x9713, 1496 0x9714, 1497 0x9715, 1498 0x9802, 1499 0x9803, 1500 0x9804, 1501 0x9805, 1502 0x9806, 1503 0x9807, 1504 0x9808, 1505 0x9809, 1506 0x980A, 1507 0x9900, 1508 0x9901, 1509 0x9903, 1510 0x9904, 1511 0x9905, 1512 0x9906, 1513 0x9907, 1514 0x9908, 1515 0x9909, 1516 0x990A, 1517 0x990B, 1518 0x990C, 1519 0x990D, 1520 0x990E, 1521 0x990F, 1522 0x9910, 1523 0x9913, 1524 0x9917, 1525 0x9918, 1526 0x9919, 1527 0x9990, 1528 0x9991, 1529 0x9992, 1530 0x9993, 1531 0x9994, 1532 0x9995, 1533 0x9996, 1534 0x9997, 1535 0x9998, 1536 0x9999, 1537 0x999A, 1538 0x999B, 1539 0x999C, 1540 0x999D, 1541 0x99A0, 1542 0x99A2, 1543 0x99A4, 1544 /* radeon secondary ids */ 1545 0x3171, 1546 0x3e70, 1547 0x4164, 1548 0x4165, 1549 0x4166, 1550 0x4168, 1551 0x4170, 1552 0x4171, 1553 0x4172, 1554 0x4173, 1555 0x496e, 1556 0x4a69, 1557 0x4a6a, 1558 0x4a6b, 1559 0x4a70, 1560 0x4a74, 1561 0x4b69, 1562 0x4b6b, 1563 0x4b6c, 1564 0x4c6e, 1565 0x4e64, 1566 0x4e65, 1567 0x4e66, 1568 0x4e67, 1569 0x4e68, 1570 0x4e69, 1571 0x4e6a, 1572 0x4e71, 1573 0x4f73, 1574 0x5569, 1575 0x556b, 1576 0x556d, 1577 0x556f, 1578 0x5571, 1579 0x5854, 1580 0x5874, 1581 0x5940, 1582 0x5941, 1583 0x5b72, 1584 0x5b73, 1585 0x5b74, 1586 0x5b75, 1587 0x5d44, 1588 0x5d45, 1589 0x5d6d, 1590 0x5d6f, 1591 0x5d72, 1592 0x5d77, 1593 0x5e6b, 1594 0x5e6d, 1595 0x7120, 1596 0x7124, 1597 0x7129, 1598 0x712e, 1599 0x712f, 1600 0x7162, 1601 0x7163, 1602 0x7166, 1603 0x7167, 1604 0x7172, 1605 0x7173, 1606 0x71a0, 1607 0x71a1, 1608 0x71a3, 1609 0x71a7, 1610 0x71bb, 1611 0x71e0, 1612 0x71e1, 1613 0x71e2, 1614 0x71e6, 1615 0x71e7, 1616 0x71f2, 1617 0x7269, 1618 0x726b, 1619 0x726e, 1620 0x72a0, 1621 0x72a8, 1622 0x72b1, 1623 0x72b3, 1624 0x793f, 1625 }; 1626 1627 static const struct pci_device_id pciidlist[] = { 1628 #ifdef CONFIG_DRM_AMDGPU_SI 1629 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1630 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1631 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1632 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1633 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1634 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1635 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1636 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1637 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1638 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1639 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1640 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1641 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1642 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1643 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1646 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1647 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1648 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1649 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1650 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1651 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1652 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1653 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1654 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1659 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1660 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1661 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1662 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1663 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1664 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1665 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1666 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1667 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1668 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1669 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1671 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1674 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1678 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1679 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1680 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1681 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1682 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1683 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1684 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1685 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1689 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1690 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1691 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1692 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1693 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1694 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1695 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1700 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1701 #endif 1702 #ifdef CONFIG_DRM_AMDGPU_CIK 1703 /* Kaveri */ 1704 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1705 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1706 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1707 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1708 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1709 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1710 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1711 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1713 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1715 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1716 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1717 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1718 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1719 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1720 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1721 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1722 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1724 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1725 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1726 /* Bonaire */ 1727 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1730 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1732 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1733 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1734 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1735 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1736 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1737 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1738 /* Hawaii */ 1739 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1740 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1741 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1742 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1743 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1744 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1745 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1746 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1747 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1748 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1749 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1750 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1751 /* Kabini */ 1752 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1754 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1755 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1756 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1758 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1760 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1763 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1765 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1766 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1767 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1768 /* mullins */ 1769 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1775 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1777 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1785 #endif 1786 /* topaz */ 1787 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1788 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1789 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1790 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1791 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1792 /* tonga */ 1793 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1794 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1795 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1796 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1797 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1798 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1799 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1800 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1801 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1802 /* fiji */ 1803 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1804 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1805 /* carrizo */ 1806 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1807 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1808 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1809 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1810 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1811 /* stoney */ 1812 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1813 /* Polaris11 */ 1814 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1815 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1816 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1817 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1818 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1819 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1820 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1821 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1822 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1823 /* Polaris10 */ 1824 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1825 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1826 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1827 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1828 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1829 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1830 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1831 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1832 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1833 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1834 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1835 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1836 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1837 /* Polaris12 */ 1838 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1839 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1840 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1841 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1842 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1843 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1844 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1845 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1846 /* VEGAM */ 1847 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1848 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1849 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1850 /* Vega 10 */ 1851 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1852 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1853 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1854 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1855 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1856 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1857 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1858 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1859 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1860 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1861 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1862 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1863 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1864 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1865 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1866 /* Vega 12 */ 1867 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1868 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1869 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1870 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1871 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1872 /* Vega 20 */ 1873 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1874 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1875 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1876 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1877 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1878 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1879 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1880 /* Raven */ 1881 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1882 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1883 /* Arcturus */ 1884 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1885 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1886 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1887 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1888 /* Navi10 */ 1889 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1890 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1891 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1892 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1893 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1894 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1895 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1896 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1897 /* Navi14 */ 1898 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1899 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1900 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1901 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1902 1903 /* Renoir */ 1904 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1905 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1906 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1907 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1908 1909 /* Navi12 */ 1910 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1911 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1912 1913 /* Sienna_Cichlid */ 1914 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1915 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1916 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1917 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1918 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1919 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1920 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1921 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1922 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1923 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1924 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1925 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1926 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1927 1928 /* Van Gogh */ 1929 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1930 1931 /* Yellow Carp */ 1932 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1933 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1934 1935 /* Navy_Flounder */ 1936 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1937 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1938 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1939 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1940 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1941 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1942 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1943 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1944 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1945 1946 /* DIMGREY_CAVEFISH */ 1947 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1948 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1949 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1950 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1951 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1952 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1953 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1954 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1955 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1956 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1957 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1958 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1959 1960 /* Aldebaran */ 1961 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1962 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1963 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1964 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1965 1966 /* CYAN_SKILLFISH */ 1967 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1968 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1969 1970 /* BEIGE_GOBY */ 1971 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1972 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1973 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1974 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1975 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1976 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1977 1978 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1979 .class = PCI_CLASS_DISPLAY_VGA << 8, 1980 .class_mask = 0xffffff, 1981 .driver_data = CHIP_IP_DISCOVERY }, 1982 1983 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1984 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1985 .class_mask = 0xffffff, 1986 .driver_data = CHIP_IP_DISCOVERY }, 1987 1988 {0, 0, 0} 1989 }; 1990 1991 MODULE_DEVICE_TABLE(pci, pciidlist); 1992 1993 static const struct drm_driver amdgpu_kms_driver; 1994 1995 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1996 { 1997 struct pci_dev *p = NULL; 1998 int i; 1999 2000 /* 0 - GPU 2001 * 1 - audio 2002 * 2 - USB 2003 * 3 - UCSI 2004 */ 2005 for (i = 1; i < 4; i++) { 2006 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2007 adev->pdev->bus->number, i); 2008 if (p) { 2009 pm_runtime_get_sync(&p->dev); 2010 pm_runtime_mark_last_busy(&p->dev); 2011 pm_runtime_put_autosuspend(&p->dev); 2012 pci_dev_put(p); 2013 } 2014 } 2015 } 2016 2017 static int amdgpu_pci_probe(struct pci_dev *pdev, 2018 const struct pci_device_id *ent) 2019 { 2020 struct drm_device *ddev; 2021 struct amdgpu_device *adev; 2022 unsigned long flags = ent->driver_data; 2023 int ret, retry = 0, i; 2024 bool supports_atomic = false; 2025 2026 /* skip devices which are owned by radeon */ 2027 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2028 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2029 return -ENODEV; 2030 } 2031 2032 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2033 amdgpu_aspm = 0; 2034 2035 if (amdgpu_virtual_display || 2036 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2037 supports_atomic = true; 2038 2039 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2040 DRM_INFO("This hardware requires experimental hardware support.\n" 2041 "See modparam exp_hw_support\n"); 2042 return -ENODEV; 2043 } 2044 2045 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2046 * however, SME requires an indirect IOMMU mapping because the encryption 2047 * bit is beyond the DMA mask of the chip. 2048 */ 2049 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2050 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2051 dev_info(&pdev->dev, 2052 "SME is not compatible with RAVEN\n"); 2053 return -ENOTSUPP; 2054 } 2055 2056 #ifdef CONFIG_DRM_AMDGPU_SI 2057 if (!amdgpu_si_support) { 2058 switch (flags & AMD_ASIC_MASK) { 2059 case CHIP_TAHITI: 2060 case CHIP_PITCAIRN: 2061 case CHIP_VERDE: 2062 case CHIP_OLAND: 2063 case CHIP_HAINAN: 2064 dev_info(&pdev->dev, 2065 "SI support provided by radeon.\n"); 2066 dev_info(&pdev->dev, 2067 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2068 ); 2069 return -ENODEV; 2070 } 2071 } 2072 #endif 2073 #ifdef CONFIG_DRM_AMDGPU_CIK 2074 if (!amdgpu_cik_support) { 2075 switch (flags & AMD_ASIC_MASK) { 2076 case CHIP_KAVERI: 2077 case CHIP_BONAIRE: 2078 case CHIP_HAWAII: 2079 case CHIP_KABINI: 2080 case CHIP_MULLINS: 2081 dev_info(&pdev->dev, 2082 "CIK support provided by radeon.\n"); 2083 dev_info(&pdev->dev, 2084 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2085 ); 2086 return -ENODEV; 2087 } 2088 } 2089 #endif 2090 2091 /* Get rid of things like offb */ 2092 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2093 if (ret) 2094 return ret; 2095 2096 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2097 if (IS_ERR(adev)) 2098 return PTR_ERR(adev); 2099 2100 adev->dev = &pdev->dev; 2101 adev->pdev = pdev; 2102 ddev = adev_to_drm(adev); 2103 2104 if (!supports_atomic) 2105 ddev->driver_features &= ~DRIVER_ATOMIC; 2106 2107 ret = pci_enable_device(pdev); 2108 if (ret) 2109 return ret; 2110 2111 pci_set_drvdata(pdev, ddev); 2112 2113 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2114 if (ret) 2115 goto err_pci; 2116 2117 retry_init: 2118 ret = drm_dev_register(ddev, ent->driver_data); 2119 if (ret == -EAGAIN && ++retry <= 3) { 2120 DRM_INFO("retry init %d\n", retry); 2121 /* Don't request EX mode too frequently which is attacking */ 2122 msleep(5000); 2123 goto retry_init; 2124 } else if (ret) { 2125 goto err_pci; 2126 } 2127 2128 /* 2129 * 1. don't init fbdev on hw without DCE 2130 * 2. don't init fbdev if there are no connectors 2131 */ 2132 if (adev->mode_info.mode_config_initialized && 2133 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2134 /* select 8 bpp console on low vram cards */ 2135 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2136 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2137 else 2138 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2139 } 2140 2141 ret = amdgpu_debugfs_init(adev); 2142 if (ret) 2143 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2144 2145 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2146 /* only need to skip on ATPX */ 2147 if (amdgpu_device_supports_px(ddev)) 2148 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2149 /* we want direct complete for BOCO */ 2150 if (amdgpu_device_supports_boco(ddev)) 2151 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2152 DPM_FLAG_SMART_SUSPEND | 2153 DPM_FLAG_MAY_SKIP_RESUME); 2154 pm_runtime_use_autosuspend(ddev->dev); 2155 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2156 2157 pm_runtime_allow(ddev->dev); 2158 2159 pm_runtime_mark_last_busy(ddev->dev); 2160 pm_runtime_put_autosuspend(ddev->dev); 2161 2162 /* 2163 * For runpm implemented via BACO, PMFW will handle the 2164 * timing for BACO in and out: 2165 * - put ASIC into BACO state only when both video and 2166 * audio functions are in D3 state. 2167 * - pull ASIC out of BACO state when either video or 2168 * audio function is in D0 state. 2169 * Also, at startup, PMFW assumes both functions are in 2170 * D0 state. 2171 * 2172 * So if snd driver was loaded prior to amdgpu driver 2173 * and audio function was put into D3 state, there will 2174 * be no PMFW-aware D-state transition(D0->D3) on runpm 2175 * suspend. Thus the BACO will be not correctly kicked in. 2176 * 2177 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2178 * into D0 state. Then there will be a PMFW-aware D-state 2179 * transition(D0->D3) on runpm suspend. 2180 */ 2181 if (amdgpu_device_supports_baco(ddev) && 2182 !(adev->flags & AMD_IS_APU) && 2183 (adev->asic_type >= CHIP_NAVI10)) 2184 amdgpu_get_secondary_funcs(adev); 2185 } 2186 2187 return 0; 2188 2189 err_pci: 2190 pci_disable_device(pdev); 2191 return ret; 2192 } 2193 2194 static void 2195 amdgpu_pci_remove(struct pci_dev *pdev) 2196 { 2197 struct drm_device *dev = pci_get_drvdata(pdev); 2198 struct amdgpu_device *adev = drm_to_adev(dev); 2199 2200 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2201 pm_runtime_get_sync(dev->dev); 2202 pm_runtime_forbid(dev->dev); 2203 } 2204 2205 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 2206 bool need_to_reset_gpu = false; 2207 2208 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2209 struct amdgpu_hive_info *hive; 2210 2211 hive = amdgpu_get_xgmi_hive(adev); 2212 if (hive->device_remove_count == 0) 2213 need_to_reset_gpu = true; 2214 hive->device_remove_count++; 2215 amdgpu_put_xgmi_hive(hive); 2216 } else { 2217 need_to_reset_gpu = true; 2218 } 2219 2220 /* Workaround for ASICs need to reset SMU. 2221 * Called only when the first device is removed. 2222 */ 2223 if (need_to_reset_gpu) { 2224 struct amdgpu_reset_context reset_context; 2225 2226 adev->shutdown = true; 2227 memset(&reset_context, 0, sizeof(reset_context)); 2228 reset_context.method = AMD_RESET_METHOD_NONE; 2229 reset_context.reset_req_dev = adev; 2230 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2231 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2232 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2233 } 2234 } 2235 2236 amdgpu_driver_unload_kms(dev); 2237 2238 drm_dev_unplug(dev); 2239 2240 /* 2241 * Flush any in flight DMA operations from device. 2242 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2243 * StatusTransactions Pending bit. 2244 */ 2245 pci_disable_device(pdev); 2246 pci_wait_for_pending_transaction(pdev); 2247 } 2248 2249 static void 2250 amdgpu_pci_shutdown(struct pci_dev *pdev) 2251 { 2252 struct drm_device *dev = pci_get_drvdata(pdev); 2253 struct amdgpu_device *adev = drm_to_adev(dev); 2254 2255 if (amdgpu_ras_intr_triggered()) 2256 return; 2257 2258 /* if we are running in a VM, make sure the device 2259 * torn down properly on reboot/shutdown. 2260 * unfortunately we can't detect certain 2261 * hypervisors so just do this all the time. 2262 */ 2263 if (!amdgpu_passthrough(adev)) 2264 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2265 amdgpu_device_ip_suspend(adev); 2266 adev->mp1_state = PP_MP1_STATE_NONE; 2267 } 2268 2269 /** 2270 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2271 * 2272 * @work: work_struct. 2273 */ 2274 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2275 { 2276 struct list_head device_list; 2277 struct amdgpu_device *adev; 2278 int i, r; 2279 struct amdgpu_reset_context reset_context; 2280 2281 memset(&reset_context, 0, sizeof(reset_context)); 2282 2283 mutex_lock(&mgpu_info.mutex); 2284 if (mgpu_info.pending_reset == true) { 2285 mutex_unlock(&mgpu_info.mutex); 2286 return; 2287 } 2288 mgpu_info.pending_reset = true; 2289 mutex_unlock(&mgpu_info.mutex); 2290 2291 /* Use a common context, just need to make sure full reset is done */ 2292 reset_context.method = AMD_RESET_METHOD_NONE; 2293 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2294 2295 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2296 adev = mgpu_info.gpu_ins[i].adev; 2297 reset_context.reset_req_dev = adev; 2298 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2299 if (r) { 2300 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2301 r, adev_to_drm(adev)->unique); 2302 } 2303 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2304 r = -EALREADY; 2305 } 2306 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2307 adev = mgpu_info.gpu_ins[i].adev; 2308 flush_work(&adev->xgmi_reset_work); 2309 adev->gmc.xgmi.pending_reset = false; 2310 } 2311 2312 /* reset function will rebuild the xgmi hive info , clear it now */ 2313 for (i = 0; i < mgpu_info.num_dgpu; i++) 2314 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2315 2316 INIT_LIST_HEAD(&device_list); 2317 2318 for (i = 0; i < mgpu_info.num_dgpu; i++) 2319 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2320 2321 /* unregister the GPU first, reset function will add them back */ 2322 list_for_each_entry(adev, &device_list, reset_list) 2323 amdgpu_unregister_gpu_instance(adev); 2324 2325 /* Use a common context, just need to make sure full reset is done */ 2326 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2327 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2328 2329 if (r) { 2330 DRM_ERROR("reinit gpus failure"); 2331 return; 2332 } 2333 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2334 adev = mgpu_info.gpu_ins[i].adev; 2335 if (!adev->kfd.init_complete) 2336 amdgpu_amdkfd_device_init(adev); 2337 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2338 } 2339 return; 2340 } 2341 2342 static int amdgpu_pmops_prepare(struct device *dev) 2343 { 2344 struct drm_device *drm_dev = dev_get_drvdata(dev); 2345 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2346 2347 /* Return a positive number here so 2348 * DPM_FLAG_SMART_SUSPEND works properly 2349 */ 2350 if (amdgpu_device_supports_boco(drm_dev)) 2351 return pm_runtime_suspended(dev); 2352 2353 /* if we will not support s3 or s2i for the device 2354 * then skip suspend 2355 */ 2356 if (!amdgpu_acpi_is_s0ix_active(adev) && 2357 !amdgpu_acpi_is_s3_active(adev)) 2358 return 1; 2359 2360 return 0; 2361 } 2362 2363 static void amdgpu_pmops_complete(struct device *dev) 2364 { 2365 /* nothing to do */ 2366 } 2367 2368 static int amdgpu_pmops_suspend(struct device *dev) 2369 { 2370 struct drm_device *drm_dev = dev_get_drvdata(dev); 2371 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2372 2373 if (amdgpu_acpi_is_s0ix_active(adev)) 2374 adev->in_s0ix = true; 2375 else 2376 adev->in_s3 = true; 2377 return amdgpu_device_suspend(drm_dev, true); 2378 } 2379 2380 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2381 { 2382 struct drm_device *drm_dev = dev_get_drvdata(dev); 2383 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2384 2385 if (amdgpu_acpi_should_gpu_reset(adev)) 2386 return amdgpu_asic_reset(adev); 2387 2388 return 0; 2389 } 2390 2391 static int amdgpu_pmops_resume(struct device *dev) 2392 { 2393 struct drm_device *drm_dev = dev_get_drvdata(dev); 2394 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2395 int r; 2396 2397 /* Avoids registers access if device is physically gone */ 2398 if (!pci_device_is_present(adev->pdev)) 2399 adev->no_hw_access = true; 2400 2401 r = amdgpu_device_resume(drm_dev, true); 2402 if (amdgpu_acpi_is_s0ix_active(adev)) 2403 adev->in_s0ix = false; 2404 else 2405 adev->in_s3 = false; 2406 return r; 2407 } 2408 2409 static int amdgpu_pmops_freeze(struct device *dev) 2410 { 2411 struct drm_device *drm_dev = dev_get_drvdata(dev); 2412 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2413 int r; 2414 2415 adev->in_s4 = true; 2416 r = amdgpu_device_suspend(drm_dev, true); 2417 adev->in_s4 = false; 2418 if (r) 2419 return r; 2420 return amdgpu_asic_reset(adev); 2421 } 2422 2423 static int amdgpu_pmops_thaw(struct device *dev) 2424 { 2425 struct drm_device *drm_dev = dev_get_drvdata(dev); 2426 2427 return amdgpu_device_resume(drm_dev, true); 2428 } 2429 2430 static int amdgpu_pmops_poweroff(struct device *dev) 2431 { 2432 struct drm_device *drm_dev = dev_get_drvdata(dev); 2433 2434 return amdgpu_device_suspend(drm_dev, true); 2435 } 2436 2437 static int amdgpu_pmops_restore(struct device *dev) 2438 { 2439 struct drm_device *drm_dev = dev_get_drvdata(dev); 2440 2441 return amdgpu_device_resume(drm_dev, true); 2442 } 2443 2444 static int amdgpu_runtime_idle_check_display(struct device *dev) 2445 { 2446 struct pci_dev *pdev = to_pci_dev(dev); 2447 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2448 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2449 2450 if (adev->mode_info.num_crtc) { 2451 struct drm_connector *list_connector; 2452 struct drm_connector_list_iter iter; 2453 int ret = 0; 2454 2455 /* XXX: Return busy if any displays are connected to avoid 2456 * possible display wakeups after runtime resume due to 2457 * hotplug events in case any displays were connected while 2458 * the GPU was in suspend. Remove this once that is fixed. 2459 */ 2460 mutex_lock(&drm_dev->mode_config.mutex); 2461 drm_connector_list_iter_begin(drm_dev, &iter); 2462 drm_for_each_connector_iter(list_connector, &iter) { 2463 if (list_connector->status == connector_status_connected) { 2464 ret = -EBUSY; 2465 break; 2466 } 2467 } 2468 drm_connector_list_iter_end(&iter); 2469 mutex_unlock(&drm_dev->mode_config.mutex); 2470 2471 if (ret) 2472 return ret; 2473 2474 if (amdgpu_device_has_dc_support(adev)) { 2475 struct drm_crtc *crtc; 2476 2477 drm_for_each_crtc(crtc, drm_dev) { 2478 drm_modeset_lock(&crtc->mutex, NULL); 2479 if (crtc->state->active) 2480 ret = -EBUSY; 2481 drm_modeset_unlock(&crtc->mutex); 2482 if (ret < 0) 2483 break; 2484 } 2485 } else { 2486 mutex_lock(&drm_dev->mode_config.mutex); 2487 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2488 2489 drm_connector_list_iter_begin(drm_dev, &iter); 2490 drm_for_each_connector_iter(list_connector, &iter) { 2491 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2492 ret = -EBUSY; 2493 break; 2494 } 2495 } 2496 2497 drm_connector_list_iter_end(&iter); 2498 2499 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2500 mutex_unlock(&drm_dev->mode_config.mutex); 2501 } 2502 if (ret) 2503 return ret; 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2510 { 2511 struct pci_dev *pdev = to_pci_dev(dev); 2512 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2513 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2514 int ret, i; 2515 2516 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2517 pm_runtime_forbid(dev); 2518 return -EBUSY; 2519 } 2520 2521 ret = amdgpu_runtime_idle_check_display(dev); 2522 if (ret) 2523 return ret; 2524 2525 /* wait for all rings to drain before suspending */ 2526 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2527 struct amdgpu_ring *ring = adev->rings[i]; 2528 if (ring && ring->sched.ready) { 2529 ret = amdgpu_fence_wait_empty(ring); 2530 if (ret) 2531 return -EBUSY; 2532 } 2533 } 2534 2535 adev->in_runpm = true; 2536 if (amdgpu_device_supports_px(drm_dev)) 2537 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2538 2539 /* 2540 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2541 * proper cleanups and put itself into a state ready for PNP. That 2542 * can address some random resuming failure observed on BOCO capable 2543 * platforms. 2544 * TODO: this may be also needed for PX capable platform. 2545 */ 2546 if (amdgpu_device_supports_boco(drm_dev)) 2547 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2548 2549 ret = amdgpu_device_suspend(drm_dev, false); 2550 if (ret) { 2551 adev->in_runpm = false; 2552 if (amdgpu_device_supports_boco(drm_dev)) 2553 adev->mp1_state = PP_MP1_STATE_NONE; 2554 return ret; 2555 } 2556 2557 if (amdgpu_device_supports_boco(drm_dev)) 2558 adev->mp1_state = PP_MP1_STATE_NONE; 2559 2560 if (amdgpu_device_supports_px(drm_dev)) { 2561 /* Only need to handle PCI state in the driver for ATPX 2562 * PCI core handles it for _PR3. 2563 */ 2564 amdgpu_device_cache_pci_state(pdev); 2565 pci_disable_device(pdev); 2566 pci_ignore_hotplug(pdev); 2567 pci_set_power_state(pdev, PCI_D3cold); 2568 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2569 } else if (amdgpu_device_supports_boco(drm_dev)) { 2570 /* nothing to do */ 2571 } else if (amdgpu_device_supports_baco(drm_dev)) { 2572 amdgpu_device_baco_enter(drm_dev); 2573 } 2574 2575 return 0; 2576 } 2577 2578 static int amdgpu_pmops_runtime_resume(struct device *dev) 2579 { 2580 struct pci_dev *pdev = to_pci_dev(dev); 2581 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2582 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2583 int ret; 2584 2585 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2586 return -EINVAL; 2587 2588 /* Avoids registers access if device is physically gone */ 2589 if (!pci_device_is_present(adev->pdev)) 2590 adev->no_hw_access = true; 2591 2592 if (amdgpu_device_supports_px(drm_dev)) { 2593 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2594 2595 /* Only need to handle PCI state in the driver for ATPX 2596 * PCI core handles it for _PR3. 2597 */ 2598 pci_set_power_state(pdev, PCI_D0); 2599 amdgpu_device_load_pci_state(pdev); 2600 ret = pci_enable_device(pdev); 2601 if (ret) 2602 return ret; 2603 pci_set_master(pdev); 2604 } else if (amdgpu_device_supports_boco(drm_dev)) { 2605 /* Only need to handle PCI state in the driver for ATPX 2606 * PCI core handles it for _PR3. 2607 */ 2608 pci_set_master(pdev); 2609 } else if (amdgpu_device_supports_baco(drm_dev)) { 2610 amdgpu_device_baco_exit(drm_dev); 2611 } 2612 ret = amdgpu_device_resume(drm_dev, false); 2613 if (ret) { 2614 if (amdgpu_device_supports_px(drm_dev)) 2615 pci_disable_device(pdev); 2616 return ret; 2617 } 2618 2619 if (amdgpu_device_supports_px(drm_dev)) 2620 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2621 adev->in_runpm = false; 2622 return 0; 2623 } 2624 2625 static int amdgpu_pmops_runtime_idle(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2629 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2630 int ret = 1; 2631 2632 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2633 pm_runtime_forbid(dev); 2634 return -EBUSY; 2635 } 2636 2637 ret = amdgpu_runtime_idle_check_display(dev); 2638 2639 pm_runtime_mark_last_busy(dev); 2640 pm_runtime_autosuspend(dev); 2641 return ret; 2642 } 2643 2644 long amdgpu_drm_ioctl(struct file *filp, 2645 unsigned int cmd, unsigned long arg) 2646 { 2647 struct drm_file *file_priv = filp->private_data; 2648 struct drm_device *dev; 2649 long ret; 2650 dev = file_priv->minor->dev; 2651 ret = pm_runtime_get_sync(dev->dev); 2652 if (ret < 0) 2653 goto out; 2654 2655 ret = drm_ioctl(filp, cmd, arg); 2656 2657 pm_runtime_mark_last_busy(dev->dev); 2658 out: 2659 pm_runtime_put_autosuspend(dev->dev); 2660 return ret; 2661 } 2662 2663 static const struct dev_pm_ops amdgpu_pm_ops = { 2664 .prepare = amdgpu_pmops_prepare, 2665 .complete = amdgpu_pmops_complete, 2666 .suspend = amdgpu_pmops_suspend, 2667 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2668 .resume = amdgpu_pmops_resume, 2669 .freeze = amdgpu_pmops_freeze, 2670 .thaw = amdgpu_pmops_thaw, 2671 .poweroff = amdgpu_pmops_poweroff, 2672 .restore = amdgpu_pmops_restore, 2673 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2674 .runtime_resume = amdgpu_pmops_runtime_resume, 2675 .runtime_idle = amdgpu_pmops_runtime_idle, 2676 }; 2677 2678 static int amdgpu_flush(struct file *f, fl_owner_t id) 2679 { 2680 struct drm_file *file_priv = f->private_data; 2681 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2682 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2683 2684 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2685 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2686 2687 return timeout >= 0 ? 0 : timeout; 2688 } 2689 2690 static const struct file_operations amdgpu_driver_kms_fops = { 2691 .owner = THIS_MODULE, 2692 .open = drm_open, 2693 .flush = amdgpu_flush, 2694 .release = drm_release, 2695 .unlocked_ioctl = amdgpu_drm_ioctl, 2696 .mmap = drm_gem_mmap, 2697 .poll = drm_poll, 2698 .read = drm_read, 2699 #ifdef CONFIG_COMPAT 2700 .compat_ioctl = amdgpu_kms_compat_ioctl, 2701 #endif 2702 #ifdef CONFIG_PROC_FS 2703 .show_fdinfo = amdgpu_show_fdinfo 2704 #endif 2705 }; 2706 2707 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2708 { 2709 struct drm_file *file; 2710 2711 if (!filp) 2712 return -EINVAL; 2713 2714 if (filp->f_op != &amdgpu_driver_kms_fops) { 2715 return -EINVAL; 2716 } 2717 2718 file = filp->private_data; 2719 *fpriv = file->driver_priv; 2720 return 0; 2721 } 2722 2723 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2724 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2725 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2726 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2727 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2728 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2729 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2730 /* KMS */ 2731 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2732 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2733 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2734 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2735 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2736 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2737 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2738 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2739 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2740 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2741 }; 2742 2743 static const struct drm_driver amdgpu_kms_driver = { 2744 .driver_features = 2745 DRIVER_ATOMIC | 2746 DRIVER_GEM | 2747 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2748 DRIVER_SYNCOBJ_TIMELINE, 2749 .open = amdgpu_driver_open_kms, 2750 .postclose = amdgpu_driver_postclose_kms, 2751 .lastclose = amdgpu_driver_lastclose_kms, 2752 .ioctls = amdgpu_ioctls_kms, 2753 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2754 .dumb_create = amdgpu_mode_dumb_create, 2755 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2756 .fops = &amdgpu_driver_kms_fops, 2757 .release = &amdgpu_driver_release_kms, 2758 2759 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2760 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2761 .gem_prime_import = amdgpu_gem_prime_import, 2762 .gem_prime_mmap = drm_gem_prime_mmap, 2763 2764 .name = DRIVER_NAME, 2765 .desc = DRIVER_DESC, 2766 .date = DRIVER_DATE, 2767 .major = KMS_DRIVER_MAJOR, 2768 .minor = KMS_DRIVER_MINOR, 2769 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2770 }; 2771 2772 static struct pci_error_handlers amdgpu_pci_err_handler = { 2773 .error_detected = amdgpu_pci_error_detected, 2774 .mmio_enabled = amdgpu_pci_mmio_enabled, 2775 .slot_reset = amdgpu_pci_slot_reset, 2776 .resume = amdgpu_pci_resume, 2777 }; 2778 2779 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2780 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2781 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2782 2783 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2784 &amdgpu_vram_mgr_attr_group, 2785 &amdgpu_gtt_mgr_attr_group, 2786 &amdgpu_vbios_version_attr_group, 2787 NULL, 2788 }; 2789 2790 2791 static struct pci_driver amdgpu_kms_pci_driver = { 2792 .name = DRIVER_NAME, 2793 .id_table = pciidlist, 2794 .probe = amdgpu_pci_probe, 2795 .remove = amdgpu_pci_remove, 2796 .shutdown = amdgpu_pci_shutdown, 2797 .driver.pm = &amdgpu_pm_ops, 2798 .err_handler = &amdgpu_pci_err_handler, 2799 .dev_groups = amdgpu_sysfs_groups, 2800 }; 2801 2802 static int __init amdgpu_init(void) 2803 { 2804 int r; 2805 2806 if (drm_firmware_drivers_only()) 2807 return -EINVAL; 2808 2809 r = amdgpu_sync_init(); 2810 if (r) 2811 goto error_sync; 2812 2813 r = amdgpu_fence_slab_init(); 2814 if (r) 2815 goto error_fence; 2816 2817 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2818 amdgpu_register_atpx_handler(); 2819 amdgpu_acpi_detect(); 2820 2821 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2822 amdgpu_amdkfd_init(); 2823 2824 /* let modprobe override vga console setting */ 2825 return pci_register_driver(&amdgpu_kms_pci_driver); 2826 2827 error_fence: 2828 amdgpu_sync_fini(); 2829 2830 error_sync: 2831 return r; 2832 } 2833 2834 static void __exit amdgpu_exit(void) 2835 { 2836 amdgpu_amdkfd_fini(); 2837 pci_unregister_driver(&amdgpu_kms_pci_driver); 2838 amdgpu_unregister_atpx_handler(); 2839 amdgpu_sync_fini(); 2840 amdgpu_fence_slab_fini(); 2841 mmu_notifier_synchronize(); 2842 } 2843 2844 module_init(amdgpu_init); 2845 module_exit(amdgpu_exit); 2846 2847 MODULE_AUTHOR(DRIVER_AUTHOR); 2848 MODULE_DESCRIPTION(DRIVER_DESC); 2849 MODULE_LICENSE("GPL and additional rights"); 2850