1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <[email protected]> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 */ 56 #define KMS_DRIVER_MAJOR 3 57 #define KMS_DRIVER_MINOR 2 58 #define KMS_DRIVER_PATCHLEVEL 0 59 60 int amdgpu_vram_limit = 0; 61 int amdgpu_gart_size = -1; /* auto */ 62 int amdgpu_benchmarking = 0; 63 int amdgpu_testing = 0; 64 int amdgpu_audio = -1; 65 int amdgpu_disp_priority = 0; 66 int amdgpu_hw_i2c = 0; 67 int amdgpu_pcie_gen2 = -1; 68 int amdgpu_msi = -1; 69 int amdgpu_lockup_timeout = 0; 70 int amdgpu_dpm = -1; 71 int amdgpu_smc_load_fw = 1; 72 int amdgpu_aspm = -1; 73 int amdgpu_runtime_pm = -1; 74 unsigned amdgpu_ip_block_mask = 0xffffffff; 75 int amdgpu_bapm = -1; 76 int amdgpu_deep_color = 0; 77 int amdgpu_vm_size = 64; 78 int amdgpu_vm_block_size = -1; 79 int amdgpu_vm_fault_stop = 0; 80 int amdgpu_vm_debug = 0; 81 int amdgpu_exp_hw_support = 0; 82 int amdgpu_sched_jobs = 32; 83 int amdgpu_sched_hw_submission = 2; 84 int amdgpu_powerplay = -1; 85 int amdgpu_powercontainment = 1; 86 unsigned amdgpu_pcie_gen_cap = 0; 87 unsigned amdgpu_pcie_lane_cap = 0; 88 unsigned amdgpu_cg_mask = 0xffffffff; 89 unsigned amdgpu_pg_mask = 0xffffffff; 90 91 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 92 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 93 94 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 95 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 96 97 MODULE_PARM_DESC(benchmark, "Run benchmark"); 98 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 99 100 MODULE_PARM_DESC(test, "Run tests"); 101 module_param_named(test, amdgpu_testing, int, 0444); 102 103 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 104 module_param_named(audio, amdgpu_audio, int, 0444); 105 106 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 107 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 108 109 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 110 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 111 112 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 113 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 114 115 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 116 module_param_named(msi, amdgpu_msi, int, 0444); 117 118 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 119 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 120 121 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 122 module_param_named(dpm, amdgpu_dpm, int, 0444); 123 124 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 125 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 126 127 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 128 module_param_named(aspm, amdgpu_aspm, int, 0444); 129 130 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 131 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 132 133 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 134 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 135 136 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 137 module_param_named(bapm, amdgpu_bapm, int, 0444); 138 139 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 140 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 141 142 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 143 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 144 145 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 146 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 147 148 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 149 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 150 151 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 152 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 153 154 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 155 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 156 157 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 158 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 159 160 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 161 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 162 163 #ifdef CONFIG_DRM_AMD_POWERPLAY 164 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 165 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 166 167 MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); 168 module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); 169 #endif 170 171 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 172 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 173 174 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 175 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 176 177 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 178 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 179 180 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 181 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 182 183 static const struct pci_device_id pciidlist[] = { 184 #ifdef CONFIG_DRM_AMDGPU_CIK 185 /* Kaveri */ 186 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 187 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 188 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 189 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 190 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 191 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 192 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 193 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 194 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 195 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 196 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 197 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 198 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 199 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 200 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 201 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 202 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 203 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 204 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 205 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 206 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 207 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 208 /* Bonaire */ 209 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 210 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 211 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 212 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 213 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 214 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 215 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 216 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 217 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 218 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 219 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 220 /* Hawaii */ 221 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 222 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 223 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 224 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 225 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 226 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 227 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 228 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 229 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 230 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 231 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 232 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 233 /* Kabini */ 234 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 235 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 236 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 237 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 238 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 239 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 240 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 242 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 244 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 245 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 246 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 247 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 248 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 249 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 250 /* mullins */ 251 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 252 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 253 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 254 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 255 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 256 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 257 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 258 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 259 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 260 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 261 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 262 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 263 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 264 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 265 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 266 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 267 #endif 268 /* topaz */ 269 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 270 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 271 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 272 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 273 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 274 /* tonga */ 275 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 276 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 277 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 278 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 279 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 280 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 281 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 282 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 283 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 284 /* fiji */ 285 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 286 /* carrizo */ 287 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 288 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 289 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 290 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 291 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 292 /* stoney */ 293 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 294 /* Polaris11 */ 295 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 296 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 297 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 298 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 299 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 300 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 301 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 302 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 303 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 304 /* Polaris10 */ 305 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 306 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 307 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 308 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 309 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 310 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 311 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 312 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 313 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 314 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 315 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 316 317 {0, 0, 0} 318 }; 319 320 MODULE_DEVICE_TABLE(pci, pciidlist); 321 322 static struct drm_driver kms_driver; 323 324 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 325 { 326 struct apertures_struct *ap; 327 bool primary = false; 328 329 ap = alloc_apertures(1); 330 if (!ap) 331 return -ENOMEM; 332 333 ap->ranges[0].base = pci_resource_start(pdev, 0); 334 ap->ranges[0].size = pci_resource_len(pdev, 0); 335 336 #ifdef CONFIG_X86 337 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 338 #endif 339 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 340 kfree(ap); 341 342 return 0; 343 } 344 345 static int amdgpu_pci_probe(struct pci_dev *pdev, 346 const struct pci_device_id *ent) 347 { 348 unsigned long flags = ent->driver_data; 349 int ret; 350 351 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 352 DRM_INFO("This hardware requires experimental hardware support.\n" 353 "See modparam exp_hw_support\n"); 354 return -ENODEV; 355 } 356 357 /* 358 * Initialize amdkfd before starting radeon. If it was not loaded yet, 359 * defer radeon probing 360 */ 361 ret = amdgpu_amdkfd_init(); 362 if (ret == -EPROBE_DEFER) 363 return ret; 364 365 /* Get rid of things like offb */ 366 ret = amdgpu_kick_out_firmware_fb(pdev); 367 if (ret) 368 return ret; 369 370 return drm_get_pci_dev(pdev, ent, &kms_driver); 371 } 372 373 static void 374 amdgpu_pci_remove(struct pci_dev *pdev) 375 { 376 struct drm_device *dev = pci_get_drvdata(pdev); 377 378 drm_put_dev(dev); 379 } 380 381 static int amdgpu_pmops_suspend(struct device *dev) 382 { 383 struct pci_dev *pdev = to_pci_dev(dev); 384 struct drm_device *drm_dev = pci_get_drvdata(pdev); 385 return amdgpu_suspend_kms(drm_dev, true, true); 386 } 387 388 static int amdgpu_pmops_resume(struct device *dev) 389 { 390 struct pci_dev *pdev = to_pci_dev(dev); 391 struct drm_device *drm_dev = pci_get_drvdata(pdev); 392 return amdgpu_resume_kms(drm_dev, true, true); 393 } 394 395 static int amdgpu_pmops_freeze(struct device *dev) 396 { 397 struct pci_dev *pdev = to_pci_dev(dev); 398 struct drm_device *drm_dev = pci_get_drvdata(pdev); 399 return amdgpu_suspend_kms(drm_dev, false, true); 400 } 401 402 static int amdgpu_pmops_thaw(struct device *dev) 403 { 404 struct pci_dev *pdev = to_pci_dev(dev); 405 struct drm_device *drm_dev = pci_get_drvdata(pdev); 406 return amdgpu_resume_kms(drm_dev, false, true); 407 } 408 409 static int amdgpu_pmops_runtime_suspend(struct device *dev) 410 { 411 struct pci_dev *pdev = to_pci_dev(dev); 412 struct drm_device *drm_dev = pci_get_drvdata(pdev); 413 int ret; 414 415 if (!amdgpu_device_is_px(drm_dev)) { 416 pm_runtime_forbid(dev); 417 return -EBUSY; 418 } 419 420 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 421 drm_kms_helper_poll_disable(drm_dev); 422 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 423 424 ret = amdgpu_suspend_kms(drm_dev, false, false); 425 pci_save_state(pdev); 426 pci_disable_device(pdev); 427 pci_ignore_hotplug(pdev); 428 if (amdgpu_is_atpx_hybrid()) 429 pci_set_power_state(pdev, PCI_D3cold); 430 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 431 pci_set_power_state(pdev, PCI_D3hot); 432 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 433 434 return 0; 435 } 436 437 static int amdgpu_pmops_runtime_resume(struct device *dev) 438 { 439 struct pci_dev *pdev = to_pci_dev(dev); 440 struct drm_device *drm_dev = pci_get_drvdata(pdev); 441 int ret; 442 443 if (!amdgpu_device_is_px(drm_dev)) 444 return -EINVAL; 445 446 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 447 448 if (amdgpu_is_atpx_hybrid() || 449 !amdgpu_has_atpx_dgpu_power_cntl()) 450 pci_set_power_state(pdev, PCI_D0); 451 pci_restore_state(pdev); 452 ret = pci_enable_device(pdev); 453 if (ret) 454 return ret; 455 pci_set_master(pdev); 456 457 ret = amdgpu_resume_kms(drm_dev, false, false); 458 drm_kms_helper_poll_enable(drm_dev); 459 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 460 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 461 return 0; 462 } 463 464 static int amdgpu_pmops_runtime_idle(struct device *dev) 465 { 466 struct pci_dev *pdev = to_pci_dev(dev); 467 struct drm_device *drm_dev = pci_get_drvdata(pdev); 468 struct drm_crtc *crtc; 469 470 if (!amdgpu_device_is_px(drm_dev)) { 471 pm_runtime_forbid(dev); 472 return -EBUSY; 473 } 474 475 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 476 if (crtc->enabled) { 477 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 478 return -EBUSY; 479 } 480 } 481 482 pm_runtime_mark_last_busy(dev); 483 pm_runtime_autosuspend(dev); 484 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 485 return 1; 486 } 487 488 long amdgpu_drm_ioctl(struct file *filp, 489 unsigned int cmd, unsigned long arg) 490 { 491 struct drm_file *file_priv = filp->private_data; 492 struct drm_device *dev; 493 long ret; 494 dev = file_priv->minor->dev; 495 ret = pm_runtime_get_sync(dev->dev); 496 if (ret < 0) 497 return ret; 498 499 ret = drm_ioctl(filp, cmd, arg); 500 501 pm_runtime_mark_last_busy(dev->dev); 502 pm_runtime_put_autosuspend(dev->dev); 503 return ret; 504 } 505 506 static const struct dev_pm_ops amdgpu_pm_ops = { 507 .suspend = amdgpu_pmops_suspend, 508 .resume = amdgpu_pmops_resume, 509 .freeze = amdgpu_pmops_freeze, 510 .thaw = amdgpu_pmops_thaw, 511 .poweroff = amdgpu_pmops_freeze, 512 .restore = amdgpu_pmops_resume, 513 .runtime_suspend = amdgpu_pmops_runtime_suspend, 514 .runtime_resume = amdgpu_pmops_runtime_resume, 515 .runtime_idle = amdgpu_pmops_runtime_idle, 516 }; 517 518 static const struct file_operations amdgpu_driver_kms_fops = { 519 .owner = THIS_MODULE, 520 .open = drm_open, 521 .release = drm_release, 522 .unlocked_ioctl = amdgpu_drm_ioctl, 523 .mmap = amdgpu_mmap, 524 .poll = drm_poll, 525 .read = drm_read, 526 #ifdef CONFIG_COMPAT 527 .compat_ioctl = amdgpu_kms_compat_ioctl, 528 #endif 529 }; 530 531 static struct drm_driver kms_driver = { 532 .driver_features = 533 DRIVER_USE_AGP | 534 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 535 DRIVER_PRIME | DRIVER_RENDER, 536 .dev_priv_size = 0, 537 .load = amdgpu_driver_load_kms, 538 .open = amdgpu_driver_open_kms, 539 .preclose = amdgpu_driver_preclose_kms, 540 .postclose = amdgpu_driver_postclose_kms, 541 .lastclose = amdgpu_driver_lastclose_kms, 542 .set_busid = drm_pci_set_busid, 543 .unload = amdgpu_driver_unload_kms, 544 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 545 .enable_vblank = amdgpu_enable_vblank_kms, 546 .disable_vblank = amdgpu_disable_vblank_kms, 547 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 548 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 549 #if defined(CONFIG_DEBUG_FS) 550 .debugfs_init = amdgpu_debugfs_init, 551 .debugfs_cleanup = amdgpu_debugfs_cleanup, 552 #endif 553 .irq_preinstall = amdgpu_irq_preinstall, 554 .irq_postinstall = amdgpu_irq_postinstall, 555 .irq_uninstall = amdgpu_irq_uninstall, 556 .irq_handler = amdgpu_irq_handler, 557 .ioctls = amdgpu_ioctls_kms, 558 .gem_free_object_unlocked = amdgpu_gem_object_free, 559 .gem_open_object = amdgpu_gem_object_open, 560 .gem_close_object = amdgpu_gem_object_close, 561 .dumb_create = amdgpu_mode_dumb_create, 562 .dumb_map_offset = amdgpu_mode_dumb_mmap, 563 .dumb_destroy = drm_gem_dumb_destroy, 564 .fops = &amdgpu_driver_kms_fops, 565 566 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 567 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 568 .gem_prime_export = amdgpu_gem_prime_export, 569 .gem_prime_import = drm_gem_prime_import, 570 .gem_prime_pin = amdgpu_gem_prime_pin, 571 .gem_prime_unpin = amdgpu_gem_prime_unpin, 572 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 573 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 574 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 575 .gem_prime_vmap = amdgpu_gem_prime_vmap, 576 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 577 578 .name = DRIVER_NAME, 579 .desc = DRIVER_DESC, 580 .date = DRIVER_DATE, 581 .major = KMS_DRIVER_MAJOR, 582 .minor = KMS_DRIVER_MINOR, 583 .patchlevel = KMS_DRIVER_PATCHLEVEL, 584 }; 585 586 static struct drm_driver *driver; 587 static struct pci_driver *pdriver; 588 589 static struct pci_driver amdgpu_kms_pci_driver = { 590 .name = DRIVER_NAME, 591 .id_table = pciidlist, 592 .probe = amdgpu_pci_probe, 593 .remove = amdgpu_pci_remove, 594 .driver.pm = &amdgpu_pm_ops, 595 }; 596 597 598 599 static int __init amdgpu_init(void) 600 { 601 amdgpu_sync_init(); 602 amdgpu_fence_slab_init(); 603 if (vgacon_text_force()) { 604 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 605 return -EINVAL; 606 } 607 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 608 driver = &kms_driver; 609 pdriver = &amdgpu_kms_pci_driver; 610 driver->driver_features |= DRIVER_MODESET; 611 driver->num_ioctls = amdgpu_max_kms_ioctl; 612 amdgpu_register_atpx_handler(); 613 /* let modprobe override vga console setting */ 614 return drm_pci_init(driver, pdriver); 615 } 616 617 static void __exit amdgpu_exit(void) 618 { 619 amdgpu_amdkfd_fini(); 620 drm_pci_exit(driver, pdriver); 621 amdgpu_unregister_atpx_handler(); 622 amdgpu_sync_fini(); 623 amdgpu_fence_slab_fini(); 624 } 625 626 module_init(amdgpu_init); 627 module_exit(amdgpu_exit); 628 629 MODULE_AUTHOR(DRIVER_AUTHOR); 630 MODULE_DESCRIPTION(DRIVER_DESC); 631 MODULE_LICENSE("GPL and additional rights"); 632