1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 * - 3.61.0 - Contains fix for RV/PCO compute queues 124 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 125 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 126 */ 127 #define KMS_DRIVER_MAJOR 3 128 #define KMS_DRIVER_MINOR 63 129 #define KMS_DRIVER_PATCHLEVEL 0 130 131 /* 132 * amdgpu.debug module options. Are all disabled by default 133 */ 134 enum AMDGPU_DEBUG_MASK { 135 AMDGPU_DEBUG_VM = BIT(0), 136 AMDGPU_DEBUG_LARGEBAR = BIT(1), 137 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 138 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 139 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 140 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 141 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 142 }; 143 144 unsigned int amdgpu_vram_limit = UINT_MAX; 145 int amdgpu_vis_vram_limit; 146 int amdgpu_gart_size = -1; /* auto */ 147 int amdgpu_gtt_size = -1; /* auto */ 148 int amdgpu_moverate = -1; /* auto */ 149 int amdgpu_audio = -1; 150 int amdgpu_disp_priority; 151 int amdgpu_hw_i2c; 152 int amdgpu_pcie_gen2 = -1; 153 int amdgpu_msi = -1; 154 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 155 int amdgpu_dpm = -1; 156 int amdgpu_fw_load_type = -1; 157 int amdgpu_aspm = -1; 158 int amdgpu_runtime_pm = -1; 159 uint amdgpu_ip_block_mask = 0xffffffff; 160 int amdgpu_bapm = -1; 161 int amdgpu_deep_color; 162 int amdgpu_vm_size = -1; 163 int amdgpu_vm_fragment_size = -1; 164 int amdgpu_vm_block_size = -1; 165 int amdgpu_vm_fault_stop; 166 int amdgpu_vm_update_mode = -1; 167 int amdgpu_exp_hw_support; 168 int amdgpu_dc = -1; 169 int amdgpu_sched_jobs = 32; 170 int amdgpu_sched_hw_submission = 2; 171 uint amdgpu_pcie_gen_cap; 172 uint amdgpu_pcie_lane_cap; 173 u64 amdgpu_cg_mask = 0xffffffffffffffff; 174 uint amdgpu_pg_mask = 0xffffffff; 175 uint amdgpu_sdma_phase_quantum = 32; 176 char *amdgpu_disable_cu; 177 char *amdgpu_virtual_display; 178 bool enforce_isolation; 179 int amdgpu_modeset = -1; 180 181 /* Specifies the default granularity for SVM, used in buffer 182 * migration and restoration of backing memory when handling 183 * recoverable page faults. 184 * 185 * The value is given as log(numPages(buffer)); for a 2 MiB 186 * buffer it computes to be 9 187 */ 188 uint amdgpu_svm_default_granularity = 9; 189 190 /* 191 * OverDrive(bit 14) disabled by default 192 * GFX DCS(bit 19) disabled by default 193 */ 194 uint amdgpu_pp_feature_mask = 0xfff7bfff; 195 uint amdgpu_force_long_training; 196 int amdgpu_lbpw = -1; 197 int amdgpu_compute_multipipe = -1; 198 int amdgpu_gpu_recovery = -1; /* auto */ 199 int amdgpu_emu_mode; 200 uint amdgpu_smu_memory_pool_size; 201 int amdgpu_smu_pptable_id = -1; 202 /* 203 * FBC (bit 0) disabled by default 204 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 205 * - With this, for multiple monitors in sync(e.g. with the same model), 206 * mclk switching will be allowed. And the mclk will be not foced to the 207 * highest. That helps saving some idle power. 208 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 209 * PSR (bit 3) disabled by default 210 * EDP NO POWER SEQUENCING (bit 4) disabled by default 211 */ 212 uint amdgpu_dc_feature_mask = 2; 213 uint amdgpu_dc_debug_mask; 214 uint amdgpu_dc_visual_confirm; 215 int amdgpu_async_gfx_ring = 1; 216 int amdgpu_mcbp = -1; 217 int amdgpu_discovery = -1; 218 int amdgpu_mes; 219 int amdgpu_mes_log_enable = 0; 220 int amdgpu_mes_kiq; 221 int amdgpu_uni_mes = 1; 222 int amdgpu_noretry = -1; 223 int amdgpu_force_asic_type = -1; 224 int amdgpu_tmz = -1; /* auto */ 225 uint amdgpu_freesync_vid_mode; 226 int amdgpu_reset_method = -1; /* auto */ 227 int amdgpu_num_kcq = -1; 228 int amdgpu_smartshift_bias; 229 int amdgpu_use_xgmi_p2p = 1; 230 int amdgpu_vcnfw_log; 231 int amdgpu_sg_display = -1; /* auto */ 232 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 233 int amdgpu_umsch_mm; 234 int amdgpu_seamless = -1; /* auto */ 235 uint amdgpu_debug_mask; 236 int amdgpu_agp = -1; /* auto */ 237 int amdgpu_wbrf = -1; 238 int amdgpu_damage_clips = -1; /* auto */ 239 int amdgpu_umsch_mm_fwlog; 240 241 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 242 "DRM_UT_CORE", 243 "DRM_UT_DRIVER", 244 "DRM_UT_KMS", 245 "DRM_UT_PRIME", 246 "DRM_UT_ATOMIC", 247 "DRM_UT_VBL", 248 "DRM_UT_STATE", 249 "DRM_UT_LEASE", 250 "DRM_UT_DP", 251 "DRM_UT_DRMRES"); 252 253 struct amdgpu_mgpu_info mgpu_info = { 254 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 255 }; 256 int amdgpu_ras_enable = -1; 257 uint amdgpu_ras_mask = 0xffffffff; 258 int amdgpu_bad_page_threshold = -1; 259 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 260 .timeout_fatal_disable = false, 261 .period = 0x0, /* default to 0x0 (timeout disable) */ 262 }; 263 264 /** 265 * DOC: vramlimit (int) 266 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 267 */ 268 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 269 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 270 271 /** 272 * DOC: vis_vramlimit (int) 273 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 274 */ 275 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 276 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 277 278 /** 279 * DOC: gartsize (uint) 280 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 281 * The default is -1 (The size depends on asic). 282 */ 283 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 284 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 285 286 /** 287 * DOC: gttsize (int) 288 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 289 * The default is -1 (Use value specified by TTM). 290 * This parameter is deprecated and will be removed in the future. 291 */ 292 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 293 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 294 295 /** 296 * DOC: moverate (int) 297 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 298 */ 299 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 300 module_param_named(moverate, amdgpu_moverate, int, 0600); 301 302 /** 303 * DOC: audio (int) 304 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 305 */ 306 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 307 module_param_named(audio, amdgpu_audio, int, 0444); 308 309 /** 310 * DOC: disp_priority (int) 311 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 312 */ 313 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 314 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 315 316 /** 317 * DOC: hw_i2c (int) 318 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 319 */ 320 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 321 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 322 323 /** 324 * DOC: pcie_gen2 (int) 325 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 326 */ 327 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 328 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 329 330 /** 331 * DOC: msi (int) 332 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 333 */ 334 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 335 module_param_named(msi, amdgpu_msi, int, 0444); 336 337 /** 338 * DOC: svm_default_granularity (uint) 339 * Used in buffer migration and handling of recoverable page faults 340 */ 341 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 342 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 343 344 /** 345 * DOC: lockup_timeout (string) 346 * Set GPU scheduler timeout value in ms. 347 * 348 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 349 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 350 * to the default timeout. 351 * 352 * - With one value specified, the setting will apply to all non-compute jobs. 353 * - With multiple values specified, the first one will be for GFX. 354 * The second one is for Compute. The third and fourth ones are 355 * for SDMA and Video. 356 * 357 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 358 * jobs is 10000. The timeout for compute is 60000. 359 */ 360 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 361 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 362 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 363 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 364 365 /** 366 * DOC: dpm (int) 367 * Override for dynamic power management setting 368 * (0 = disable, 1 = enable) 369 * The default is -1 (auto). 370 */ 371 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 372 module_param_named(dpm, amdgpu_dpm, int, 0444); 373 374 /** 375 * DOC: fw_load_type (int) 376 * Set different firmware loading type for debugging, if supported. 377 * Set to 0 to force direct loading if supported by the ASIC. Set 378 * to -1 to select the default loading mode for the ASIC, as defined 379 * by the driver. The default is -1 (auto). 380 */ 381 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 382 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 383 384 /** 385 * DOC: aspm (int) 386 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 387 */ 388 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 389 module_param_named(aspm, amdgpu_aspm, int, 0444); 390 391 /** 392 * DOC: runpm (int) 393 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 394 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 395 * Setting the value to 0 disables this functionality. 396 * Setting the value to -2 is auto enabled with power down when displays are attached. 397 */ 398 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 399 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 400 401 /** 402 * DOC: ip_block_mask (uint) 403 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 404 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 405 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 406 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 407 */ 408 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 409 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 410 411 /** 412 * DOC: bapm (int) 413 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 414 * The default -1 (auto, enabled) 415 */ 416 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 417 module_param_named(bapm, amdgpu_bapm, int, 0444); 418 419 /** 420 * DOC: deep_color (int) 421 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 422 */ 423 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 424 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 425 426 /** 427 * DOC: vm_size (int) 428 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 429 */ 430 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 431 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 432 433 /** 434 * DOC: vm_fragment_size (int) 435 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 436 */ 437 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 438 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 439 440 /** 441 * DOC: vm_block_size (int) 442 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 443 */ 444 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 445 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 446 447 /** 448 * DOC: vm_fault_stop (int) 449 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 450 */ 451 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 452 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 453 454 /** 455 * DOC: vm_update_mode (int) 456 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 457 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 458 */ 459 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 460 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 461 462 /** 463 * DOC: exp_hw_support (int) 464 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 465 */ 466 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 467 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 468 469 /** 470 * DOC: dc (int) 471 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 472 */ 473 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 474 module_param_named(dc, amdgpu_dc, int, 0444); 475 476 /** 477 * DOC: sched_jobs (int) 478 * Override the max number of jobs supported in the sw queue. The default is 32. 479 */ 480 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 481 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 482 483 /** 484 * DOC: sched_hw_submission (int) 485 * Override the max number of HW submissions. The default is 2. 486 */ 487 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 488 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 489 490 /** 491 * DOC: ppfeaturemask (hexint) 492 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 493 * The default is the current set of stable power features. 494 */ 495 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 496 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 497 498 /** 499 * DOC: forcelongtraining (uint) 500 * Force long memory training in resume. 501 * The default is zero, indicates short training in resume. 502 */ 503 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 504 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 505 506 /** 507 * DOC: pcie_gen_cap (uint) 508 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 509 * The default is 0 (automatic for each asic). 510 */ 511 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 512 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 513 514 /** 515 * DOC: pcie_lane_cap (uint) 516 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 517 * The default is 0 (automatic for each asic). 518 */ 519 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 520 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 521 522 /** 523 * DOC: cg_mask (ullong) 524 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 525 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 526 */ 527 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 528 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 529 530 /** 531 * DOC: pg_mask (uint) 532 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 533 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 534 */ 535 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 536 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 537 538 /** 539 * DOC: sdma_phase_quantum (uint) 540 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 541 */ 542 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 543 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 544 545 /** 546 * DOC: disable_cu (charp) 547 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 548 */ 549 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 550 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 551 552 /** 553 * DOC: virtual_display (charp) 554 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 555 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 556 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 557 * device at 26:00.0. The default is NULL. 558 */ 559 MODULE_PARM_DESC(virtual_display, 560 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 561 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 562 563 /** 564 * DOC: lbpw (int) 565 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 566 */ 567 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 568 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 569 570 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 571 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 572 573 /** 574 * DOC: gpu_recovery (int) 575 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 576 */ 577 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 578 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 579 580 /** 581 * DOC: emu_mode (int) 582 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 583 */ 584 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 585 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 586 587 /** 588 * DOC: ras_enable (int) 589 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 590 */ 591 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 592 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 593 594 /** 595 * DOC: ras_mask (uint) 596 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 597 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 598 */ 599 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 600 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 601 602 /** 603 * DOC: timeout_fatal_disable (bool) 604 * Disable Watchdog timeout fatal error event 605 */ 606 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 607 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 608 609 /** 610 * DOC: timeout_period (uint) 611 * Modify the watchdog timeout max_cycles as (1 << period) 612 */ 613 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 614 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 615 616 /** 617 * DOC: si_support (int) 618 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 619 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 620 * otherwise using amdgpu driver. 621 */ 622 #ifdef CONFIG_DRM_AMDGPU_SI 623 624 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 625 int amdgpu_si_support; 626 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 627 #else 628 int amdgpu_si_support = 1; 629 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 630 #endif 631 632 module_param_named(si_support, amdgpu_si_support, int, 0444); 633 #endif 634 635 /** 636 * DOC: cik_support (int) 637 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 638 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 639 * otherwise using amdgpu driver. 640 */ 641 #ifdef CONFIG_DRM_AMDGPU_CIK 642 643 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 644 int amdgpu_cik_support; 645 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 646 #else 647 int amdgpu_cik_support = 1; 648 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 649 #endif 650 651 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 652 #endif 653 654 /** 655 * DOC: smu_memory_pool_size (uint) 656 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 657 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 658 */ 659 MODULE_PARM_DESC(smu_memory_pool_size, 660 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 661 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 662 663 /** 664 * DOC: async_gfx_ring (int) 665 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 666 */ 667 MODULE_PARM_DESC(async_gfx_ring, 668 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 669 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 670 671 /** 672 * DOC: mcbp (int) 673 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 674 */ 675 MODULE_PARM_DESC(mcbp, 676 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 677 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 678 679 /** 680 * DOC: discovery (int) 681 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 682 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 683 */ 684 MODULE_PARM_DESC(discovery, 685 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 686 module_param_named(discovery, amdgpu_discovery, int, 0444); 687 688 /** 689 * DOC: mes (int) 690 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 691 * (0 = disabled (default), 1 = enabled) 692 */ 693 MODULE_PARM_DESC(mes, 694 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 695 module_param_named(mes, amdgpu_mes, int, 0444); 696 697 /** 698 * DOC: mes_log_enable (int) 699 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 700 * (0 = disabled (default), 1 = enabled) 701 */ 702 MODULE_PARM_DESC(mes_log_enable, 703 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 704 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 705 706 /** 707 * DOC: mes_kiq (int) 708 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 709 * (0 = disabled (default), 1 = enabled) 710 */ 711 MODULE_PARM_DESC(mes_kiq, 712 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 713 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 714 715 /** 716 * DOC: uni_mes (int) 717 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 718 * (0 = disabled (default), 1 = enabled) 719 */ 720 MODULE_PARM_DESC(uni_mes, 721 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 722 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 723 724 /** 725 * DOC: noretry (int) 726 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 727 * do not support per-process XNACK this also disables retry page faults. 728 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 729 */ 730 MODULE_PARM_DESC(noretry, 731 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 732 module_param_named(noretry, amdgpu_noretry, int, 0644); 733 734 /** 735 * DOC: force_asic_type (int) 736 * A non negative value used to specify the asic type for all supported GPUs. 737 */ 738 MODULE_PARM_DESC(force_asic_type, 739 "A non negative value used to specify the asic type for all supported GPUs"); 740 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 741 742 /** 743 * DOC: use_xgmi_p2p (int) 744 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 745 */ 746 MODULE_PARM_DESC(use_xgmi_p2p, 747 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 748 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 749 750 751 #ifdef CONFIG_HSA_AMD 752 /** 753 * DOC: sched_policy (int) 754 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 755 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 756 * assigns queues to HQDs. 757 */ 758 int sched_policy = KFD_SCHED_POLICY_HWS; 759 module_param_unsafe(sched_policy, int, 0444); 760 MODULE_PARM_DESC(sched_policy, 761 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 762 763 /** 764 * DOC: hws_max_conc_proc (int) 765 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 766 * number of VMIDs assigned to the HWS, which is also the default. 767 */ 768 int hws_max_conc_proc = -1; 769 module_param(hws_max_conc_proc, int, 0444); 770 MODULE_PARM_DESC(hws_max_conc_proc, 771 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 772 773 /** 774 * DOC: cwsr_enable (int) 775 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 776 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 777 * disables it. 778 */ 779 int cwsr_enable = 1; 780 module_param(cwsr_enable, int, 0444); 781 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 782 783 /** 784 * DOC: max_num_of_queues_per_device (int) 785 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 786 * is 4096. 787 */ 788 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 789 module_param(max_num_of_queues_per_device, int, 0444); 790 MODULE_PARM_DESC(max_num_of_queues_per_device, 791 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 792 793 /** 794 * DOC: send_sigterm (int) 795 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 796 * but just print errors on dmesg. Setting 1 enables sending sigterm. 797 */ 798 int send_sigterm; 799 module_param(send_sigterm, int, 0444); 800 MODULE_PARM_DESC(send_sigterm, 801 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 802 803 /** 804 * DOC: halt_if_hws_hang (int) 805 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 806 * Setting 1 enables halt on hang. 807 */ 808 int halt_if_hws_hang; 809 module_param_unsafe(halt_if_hws_hang, int, 0644); 810 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 811 812 /** 813 * DOC: hws_gws_support(bool) 814 * Assume that HWS supports GWS barriers regardless of what firmware version 815 * check says. Default value: false (rely on MEC2 firmware version check). 816 */ 817 bool hws_gws_support; 818 module_param_unsafe(hws_gws_support, bool, 0444); 819 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 820 821 /** 822 * DOC: queue_preemption_timeout_ms (int) 823 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 824 */ 825 int queue_preemption_timeout_ms = 9000; 826 module_param(queue_preemption_timeout_ms, int, 0644); 827 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 828 829 /** 830 * DOC: debug_evictions(bool) 831 * Enable extra debug messages to help determine the cause of evictions 832 */ 833 bool debug_evictions; 834 module_param(debug_evictions, bool, 0644); 835 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 836 837 /** 838 * DOC: no_system_mem_limit(bool) 839 * Disable system memory limit, to support multiple process shared memory 840 */ 841 bool no_system_mem_limit; 842 module_param(no_system_mem_limit, bool, 0644); 843 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 844 845 /** 846 * DOC: no_queue_eviction_on_vm_fault (int) 847 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 848 */ 849 int amdgpu_no_queue_eviction_on_vm_fault; 850 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 851 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 852 #endif 853 854 /** 855 * DOC: mtype_local (int) 856 */ 857 int amdgpu_mtype_local; 858 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 859 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 860 861 /** 862 * DOC: pcie_p2p (bool) 863 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 864 */ 865 #ifdef CONFIG_HSA_AMD_P2P 866 bool pcie_p2p = true; 867 module_param(pcie_p2p, bool, 0444); 868 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 869 #endif 870 871 /** 872 * DOC: dcfeaturemask (uint) 873 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 874 * The default is the current set of stable display features. 875 */ 876 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 877 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 878 879 /** 880 * DOC: dcdebugmask (uint) 881 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 882 */ 883 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 884 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 885 886 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 887 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 888 889 /** 890 * DOC: abmlevel (uint) 891 * Override the default ABM (Adaptive Backlight Management) level used for DC 892 * enabled hardware. Requires DMCU to be supported and loaded. 893 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 894 * default. Values 1-4 control the maximum allowable brightness reduction via 895 * the ABM algorithm, with 1 being the least reduction and 4 being the most 896 * reduction. 897 * 898 * Defaults to -1, or auto. Userspace can only override this level after 899 * boot if it's set to auto. 900 */ 901 int amdgpu_dm_abm_level = -1; 902 MODULE_PARM_DESC(abmlevel, 903 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 904 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 905 906 int amdgpu_backlight = -1; 907 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 908 module_param_named(backlight, amdgpu_backlight, bint, 0444); 909 910 /** 911 * DOC: damageclips (int) 912 * Enable or disable damage clips support. If damage clips support is disabled, 913 * we will force full frame updates, irrespective of what user space sends to 914 * us. 915 * 916 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 917 */ 918 MODULE_PARM_DESC(damageclips, 919 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 920 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 921 922 /** 923 * DOC: tmz (int) 924 * Trusted Memory Zone (TMZ) is a method to protect data being written 925 * to or read from memory. 926 * 927 * The default value: 0 (off). TODO: change to auto till it is completed. 928 */ 929 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 930 module_param_named(tmz, amdgpu_tmz, int, 0444); 931 932 /** 933 * DOC: freesync_video (uint) 934 * Enable the optimization to adjust front porch timing to achieve seamless 935 * mode change experience when setting a freesync supported mode for which full 936 * modeset is not needed. 937 * 938 * The Display Core will add a set of modes derived from the base FreeSync 939 * video mode into the corresponding connector's mode list based on commonly 940 * used refresh rates and VRR range of the connected display, when users enable 941 * this feature. From the userspace perspective, they can see a seamless mode 942 * change experience when the change between different refresh rates under the 943 * same resolution. Additionally, userspace applications such as Video playback 944 * can read this modeset list and change the refresh rate based on the video 945 * frame rate. Finally, the userspace can also derive an appropriate mode for a 946 * particular refresh rate based on the FreeSync Mode and add it to the 947 * connector's mode list. 948 * 949 * Note: This is an experimental feature. 950 * 951 * The default value: 0 (off). 952 */ 953 MODULE_PARM_DESC( 954 freesync_video, 955 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 956 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 957 958 /** 959 * DOC: reset_method (int) 960 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 961 */ 962 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 963 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 964 965 /** 966 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 967 * threshold value of faulty pages detected by RAS ECC, which may 968 * result in the GPU entering bad status when the number of total 969 * faulty pages by ECC exceeds the threshold value. 970 */ 971 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 972 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 973 974 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 975 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 976 977 /** 978 * DOC: vcnfw_log (int) 979 * Enable vcnfw log output for debugging, the default is disabled. 980 */ 981 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 982 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 983 984 /** 985 * DOC: sg_display (int) 986 * Disable S/G (scatter/gather) display (i.e., display from system memory). 987 * This option is only relevant on APUs. Set this option to 0 to disable 988 * S/G display if you experience flickering or other issues under memory 989 * pressure and report the issue. 990 */ 991 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 992 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 993 994 /** 995 * DOC: umsch_mm (int) 996 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 997 * (0 = disabled (default), 1 = enabled) 998 */ 999 MODULE_PARM_DESC(umsch_mm, 1000 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1001 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1002 1003 /** 1004 * DOC: umsch_mm_fwlog (int) 1005 * Enable umschfw log output for debugging, the default is disabled. 1006 */ 1007 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1008 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1009 1010 /** 1011 * DOC: smu_pptable_id (int) 1012 * Used to override pptable id. id = 0 use VBIOS pptable. 1013 * id > 0 use the soft pptable with specicfied id. 1014 */ 1015 MODULE_PARM_DESC(smu_pptable_id, 1016 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1017 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1018 1019 /** 1020 * DOC: partition_mode (int) 1021 * Used to override the default SPX mode. 1022 */ 1023 MODULE_PARM_DESC( 1024 user_partt_mode, 1025 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1026 0 = AMDGPU_SPX_PARTITION_MODE, \ 1027 1 = AMDGPU_DPX_PARTITION_MODE, \ 1028 2 = AMDGPU_TPX_PARTITION_MODE, \ 1029 3 = AMDGPU_QPX_PARTITION_MODE, \ 1030 4 = AMDGPU_CPX_PARTITION_MODE)"); 1031 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1032 1033 1034 /** 1035 * DOC: enforce_isolation (bool) 1036 * enforce process isolation between graphics and compute via using the same reserved vmid. 1037 */ 1038 module_param(enforce_isolation, bool, 0444); 1039 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1040 1041 /** 1042 * DOC: modeset (int) 1043 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1044 */ 1045 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1046 module_param_named(modeset, amdgpu_modeset, int, 0444); 1047 1048 /** 1049 * DOC: seamless (int) 1050 * Seamless boot will keep the image on the screen during the boot process. 1051 */ 1052 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1053 module_param_named(seamless, amdgpu_seamless, int, 0444); 1054 1055 /** 1056 * DOC: debug_mask (uint) 1057 * Debug options for amdgpu, work as a binary mask with the following options: 1058 * 1059 * - 0x1: Debug VM handling 1060 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1061 * limits the VRAM size reported to ROCm applications to the visible 1062 * size, usually 256MB. 1063 * - 0x4: Disable GPU soft recovery, always do a full reset 1064 */ 1065 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1066 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1067 1068 /** 1069 * DOC: agp (int) 1070 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1071 * address space for direct access to system memory. Note that these accesses 1072 * are non-snooped, so they are only used for access to uncached memory. 1073 */ 1074 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1075 module_param_named(agp, amdgpu_agp, int, 0444); 1076 1077 /** 1078 * DOC: wbrf (int) 1079 * Enable Wifi RFI interference mitigation feature. 1080 * Due to electrical and mechanical constraints there may be likely interference of 1081 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1082 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1083 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1084 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1085 * P-state transition. However, there may be potential performance impact with this 1086 * feature enabled. 1087 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1088 */ 1089 MODULE_PARM_DESC(wbrf, 1090 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1091 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1092 1093 /* These devices are not supported by amdgpu. 1094 * They are supported by the mach64, r128, radeon drivers 1095 */ 1096 static const u16 amdgpu_unsupported_pciidlist[] = { 1097 /* mach64 */ 1098 0x4354, 1099 0x4358, 1100 0x4554, 1101 0x4742, 1102 0x4744, 1103 0x4749, 1104 0x474C, 1105 0x474D, 1106 0x474E, 1107 0x474F, 1108 0x4750, 1109 0x4751, 1110 0x4752, 1111 0x4753, 1112 0x4754, 1113 0x4755, 1114 0x4756, 1115 0x4757, 1116 0x4758, 1117 0x4759, 1118 0x475A, 1119 0x4C42, 1120 0x4C44, 1121 0x4C47, 1122 0x4C49, 1123 0x4C4D, 1124 0x4C4E, 1125 0x4C50, 1126 0x4C51, 1127 0x4C52, 1128 0x4C53, 1129 0x5654, 1130 0x5655, 1131 0x5656, 1132 /* r128 */ 1133 0x4c45, 1134 0x4c46, 1135 0x4d46, 1136 0x4d4c, 1137 0x5041, 1138 0x5042, 1139 0x5043, 1140 0x5044, 1141 0x5045, 1142 0x5046, 1143 0x5047, 1144 0x5048, 1145 0x5049, 1146 0x504A, 1147 0x504B, 1148 0x504C, 1149 0x504D, 1150 0x504E, 1151 0x504F, 1152 0x5050, 1153 0x5051, 1154 0x5052, 1155 0x5053, 1156 0x5054, 1157 0x5055, 1158 0x5056, 1159 0x5057, 1160 0x5058, 1161 0x5245, 1162 0x5246, 1163 0x5247, 1164 0x524b, 1165 0x524c, 1166 0x534d, 1167 0x5446, 1168 0x544C, 1169 0x5452, 1170 /* radeon */ 1171 0x3150, 1172 0x3151, 1173 0x3152, 1174 0x3154, 1175 0x3155, 1176 0x3E50, 1177 0x3E54, 1178 0x4136, 1179 0x4137, 1180 0x4144, 1181 0x4145, 1182 0x4146, 1183 0x4147, 1184 0x4148, 1185 0x4149, 1186 0x414A, 1187 0x414B, 1188 0x4150, 1189 0x4151, 1190 0x4152, 1191 0x4153, 1192 0x4154, 1193 0x4155, 1194 0x4156, 1195 0x4237, 1196 0x4242, 1197 0x4336, 1198 0x4337, 1199 0x4437, 1200 0x4966, 1201 0x4967, 1202 0x4A48, 1203 0x4A49, 1204 0x4A4A, 1205 0x4A4B, 1206 0x4A4C, 1207 0x4A4D, 1208 0x4A4E, 1209 0x4A4F, 1210 0x4A50, 1211 0x4A54, 1212 0x4B48, 1213 0x4B49, 1214 0x4B4A, 1215 0x4B4B, 1216 0x4B4C, 1217 0x4C57, 1218 0x4C58, 1219 0x4C59, 1220 0x4C5A, 1221 0x4C64, 1222 0x4C66, 1223 0x4C67, 1224 0x4E44, 1225 0x4E45, 1226 0x4E46, 1227 0x4E47, 1228 0x4E48, 1229 0x4E49, 1230 0x4E4A, 1231 0x4E4B, 1232 0x4E50, 1233 0x4E51, 1234 0x4E52, 1235 0x4E53, 1236 0x4E54, 1237 0x4E56, 1238 0x5144, 1239 0x5145, 1240 0x5146, 1241 0x5147, 1242 0x5148, 1243 0x514C, 1244 0x514D, 1245 0x5157, 1246 0x5158, 1247 0x5159, 1248 0x515A, 1249 0x515E, 1250 0x5460, 1251 0x5462, 1252 0x5464, 1253 0x5548, 1254 0x5549, 1255 0x554A, 1256 0x554B, 1257 0x554C, 1258 0x554D, 1259 0x554E, 1260 0x554F, 1261 0x5550, 1262 0x5551, 1263 0x5552, 1264 0x5554, 1265 0x564A, 1266 0x564B, 1267 0x564F, 1268 0x5652, 1269 0x5653, 1270 0x5657, 1271 0x5834, 1272 0x5835, 1273 0x5954, 1274 0x5955, 1275 0x5974, 1276 0x5975, 1277 0x5960, 1278 0x5961, 1279 0x5962, 1280 0x5964, 1281 0x5965, 1282 0x5969, 1283 0x5a41, 1284 0x5a42, 1285 0x5a61, 1286 0x5a62, 1287 0x5b60, 1288 0x5b62, 1289 0x5b63, 1290 0x5b64, 1291 0x5b65, 1292 0x5c61, 1293 0x5c63, 1294 0x5d48, 1295 0x5d49, 1296 0x5d4a, 1297 0x5d4c, 1298 0x5d4d, 1299 0x5d4e, 1300 0x5d4f, 1301 0x5d50, 1302 0x5d52, 1303 0x5d57, 1304 0x5e48, 1305 0x5e4a, 1306 0x5e4b, 1307 0x5e4c, 1308 0x5e4d, 1309 0x5e4f, 1310 0x6700, 1311 0x6701, 1312 0x6702, 1313 0x6703, 1314 0x6704, 1315 0x6705, 1316 0x6706, 1317 0x6707, 1318 0x6708, 1319 0x6709, 1320 0x6718, 1321 0x6719, 1322 0x671c, 1323 0x671d, 1324 0x671f, 1325 0x6720, 1326 0x6721, 1327 0x6722, 1328 0x6723, 1329 0x6724, 1330 0x6725, 1331 0x6726, 1332 0x6727, 1333 0x6728, 1334 0x6729, 1335 0x6738, 1336 0x6739, 1337 0x673e, 1338 0x6740, 1339 0x6741, 1340 0x6742, 1341 0x6743, 1342 0x6744, 1343 0x6745, 1344 0x6746, 1345 0x6747, 1346 0x6748, 1347 0x6749, 1348 0x674A, 1349 0x6750, 1350 0x6751, 1351 0x6758, 1352 0x6759, 1353 0x675B, 1354 0x675D, 1355 0x675F, 1356 0x6760, 1357 0x6761, 1358 0x6762, 1359 0x6763, 1360 0x6764, 1361 0x6765, 1362 0x6766, 1363 0x6767, 1364 0x6768, 1365 0x6770, 1366 0x6771, 1367 0x6772, 1368 0x6778, 1369 0x6779, 1370 0x677B, 1371 0x6840, 1372 0x6841, 1373 0x6842, 1374 0x6843, 1375 0x6849, 1376 0x684C, 1377 0x6850, 1378 0x6858, 1379 0x6859, 1380 0x6880, 1381 0x6888, 1382 0x6889, 1383 0x688A, 1384 0x688C, 1385 0x688D, 1386 0x6898, 1387 0x6899, 1388 0x689b, 1389 0x689c, 1390 0x689d, 1391 0x689e, 1392 0x68a0, 1393 0x68a1, 1394 0x68a8, 1395 0x68a9, 1396 0x68b0, 1397 0x68b8, 1398 0x68b9, 1399 0x68ba, 1400 0x68be, 1401 0x68bf, 1402 0x68c0, 1403 0x68c1, 1404 0x68c7, 1405 0x68c8, 1406 0x68c9, 1407 0x68d8, 1408 0x68d9, 1409 0x68da, 1410 0x68de, 1411 0x68e0, 1412 0x68e1, 1413 0x68e4, 1414 0x68e5, 1415 0x68e8, 1416 0x68e9, 1417 0x68f1, 1418 0x68f2, 1419 0x68f8, 1420 0x68f9, 1421 0x68fa, 1422 0x68fe, 1423 0x7100, 1424 0x7101, 1425 0x7102, 1426 0x7103, 1427 0x7104, 1428 0x7105, 1429 0x7106, 1430 0x7108, 1431 0x7109, 1432 0x710A, 1433 0x710B, 1434 0x710C, 1435 0x710E, 1436 0x710F, 1437 0x7140, 1438 0x7141, 1439 0x7142, 1440 0x7143, 1441 0x7144, 1442 0x7145, 1443 0x7146, 1444 0x7147, 1445 0x7149, 1446 0x714A, 1447 0x714B, 1448 0x714C, 1449 0x714D, 1450 0x714E, 1451 0x714F, 1452 0x7151, 1453 0x7152, 1454 0x7153, 1455 0x715E, 1456 0x715F, 1457 0x7180, 1458 0x7181, 1459 0x7183, 1460 0x7186, 1461 0x7187, 1462 0x7188, 1463 0x718A, 1464 0x718B, 1465 0x718C, 1466 0x718D, 1467 0x718F, 1468 0x7193, 1469 0x7196, 1470 0x719B, 1471 0x719F, 1472 0x71C0, 1473 0x71C1, 1474 0x71C2, 1475 0x71C3, 1476 0x71C4, 1477 0x71C5, 1478 0x71C6, 1479 0x71C7, 1480 0x71CD, 1481 0x71CE, 1482 0x71D2, 1483 0x71D4, 1484 0x71D5, 1485 0x71D6, 1486 0x71DA, 1487 0x71DE, 1488 0x7200, 1489 0x7210, 1490 0x7211, 1491 0x7240, 1492 0x7243, 1493 0x7244, 1494 0x7245, 1495 0x7246, 1496 0x7247, 1497 0x7248, 1498 0x7249, 1499 0x724A, 1500 0x724B, 1501 0x724C, 1502 0x724D, 1503 0x724E, 1504 0x724F, 1505 0x7280, 1506 0x7281, 1507 0x7283, 1508 0x7284, 1509 0x7287, 1510 0x7288, 1511 0x7289, 1512 0x728B, 1513 0x728C, 1514 0x7290, 1515 0x7291, 1516 0x7293, 1517 0x7297, 1518 0x7834, 1519 0x7835, 1520 0x791e, 1521 0x791f, 1522 0x793f, 1523 0x7941, 1524 0x7942, 1525 0x796c, 1526 0x796d, 1527 0x796e, 1528 0x796f, 1529 0x9400, 1530 0x9401, 1531 0x9402, 1532 0x9403, 1533 0x9405, 1534 0x940A, 1535 0x940B, 1536 0x940F, 1537 0x94A0, 1538 0x94A1, 1539 0x94A3, 1540 0x94B1, 1541 0x94B3, 1542 0x94B4, 1543 0x94B5, 1544 0x94B9, 1545 0x9440, 1546 0x9441, 1547 0x9442, 1548 0x9443, 1549 0x9444, 1550 0x9446, 1551 0x944A, 1552 0x944B, 1553 0x944C, 1554 0x944E, 1555 0x9450, 1556 0x9452, 1557 0x9456, 1558 0x945A, 1559 0x945B, 1560 0x945E, 1561 0x9460, 1562 0x9462, 1563 0x946A, 1564 0x946B, 1565 0x947A, 1566 0x947B, 1567 0x9480, 1568 0x9487, 1569 0x9488, 1570 0x9489, 1571 0x948A, 1572 0x948F, 1573 0x9490, 1574 0x9491, 1575 0x9495, 1576 0x9498, 1577 0x949C, 1578 0x949E, 1579 0x949F, 1580 0x94C0, 1581 0x94C1, 1582 0x94C3, 1583 0x94C4, 1584 0x94C5, 1585 0x94C6, 1586 0x94C7, 1587 0x94C8, 1588 0x94C9, 1589 0x94CB, 1590 0x94CC, 1591 0x94CD, 1592 0x9500, 1593 0x9501, 1594 0x9504, 1595 0x9505, 1596 0x9506, 1597 0x9507, 1598 0x9508, 1599 0x9509, 1600 0x950F, 1601 0x9511, 1602 0x9515, 1603 0x9517, 1604 0x9519, 1605 0x9540, 1606 0x9541, 1607 0x9542, 1608 0x954E, 1609 0x954F, 1610 0x9552, 1611 0x9553, 1612 0x9555, 1613 0x9557, 1614 0x955f, 1615 0x9580, 1616 0x9581, 1617 0x9583, 1618 0x9586, 1619 0x9587, 1620 0x9588, 1621 0x9589, 1622 0x958A, 1623 0x958B, 1624 0x958C, 1625 0x958D, 1626 0x958E, 1627 0x958F, 1628 0x9590, 1629 0x9591, 1630 0x9593, 1631 0x9595, 1632 0x9596, 1633 0x9597, 1634 0x9598, 1635 0x9599, 1636 0x959B, 1637 0x95C0, 1638 0x95C2, 1639 0x95C4, 1640 0x95C5, 1641 0x95C6, 1642 0x95C7, 1643 0x95C9, 1644 0x95CC, 1645 0x95CD, 1646 0x95CE, 1647 0x95CF, 1648 0x9610, 1649 0x9611, 1650 0x9612, 1651 0x9613, 1652 0x9614, 1653 0x9615, 1654 0x9616, 1655 0x9640, 1656 0x9641, 1657 0x9642, 1658 0x9643, 1659 0x9644, 1660 0x9645, 1661 0x9647, 1662 0x9648, 1663 0x9649, 1664 0x964a, 1665 0x964b, 1666 0x964c, 1667 0x964e, 1668 0x964f, 1669 0x9710, 1670 0x9711, 1671 0x9712, 1672 0x9713, 1673 0x9714, 1674 0x9715, 1675 0x9802, 1676 0x9803, 1677 0x9804, 1678 0x9805, 1679 0x9806, 1680 0x9807, 1681 0x9808, 1682 0x9809, 1683 0x980A, 1684 0x9900, 1685 0x9901, 1686 0x9903, 1687 0x9904, 1688 0x9905, 1689 0x9906, 1690 0x9907, 1691 0x9908, 1692 0x9909, 1693 0x990A, 1694 0x990B, 1695 0x990C, 1696 0x990D, 1697 0x990E, 1698 0x990F, 1699 0x9910, 1700 0x9913, 1701 0x9917, 1702 0x9918, 1703 0x9919, 1704 0x9990, 1705 0x9991, 1706 0x9992, 1707 0x9993, 1708 0x9994, 1709 0x9995, 1710 0x9996, 1711 0x9997, 1712 0x9998, 1713 0x9999, 1714 0x999A, 1715 0x999B, 1716 0x999C, 1717 0x999D, 1718 0x99A0, 1719 0x99A2, 1720 0x99A4, 1721 /* radeon secondary ids */ 1722 0x3171, 1723 0x3e70, 1724 0x4164, 1725 0x4165, 1726 0x4166, 1727 0x4168, 1728 0x4170, 1729 0x4171, 1730 0x4172, 1731 0x4173, 1732 0x496e, 1733 0x4a69, 1734 0x4a6a, 1735 0x4a6b, 1736 0x4a70, 1737 0x4a74, 1738 0x4b69, 1739 0x4b6b, 1740 0x4b6c, 1741 0x4c6e, 1742 0x4e64, 1743 0x4e65, 1744 0x4e66, 1745 0x4e67, 1746 0x4e68, 1747 0x4e69, 1748 0x4e6a, 1749 0x4e71, 1750 0x4f73, 1751 0x5569, 1752 0x556b, 1753 0x556d, 1754 0x556f, 1755 0x5571, 1756 0x5854, 1757 0x5874, 1758 0x5940, 1759 0x5941, 1760 0x5b70, 1761 0x5b72, 1762 0x5b73, 1763 0x5b74, 1764 0x5b75, 1765 0x5d44, 1766 0x5d45, 1767 0x5d6d, 1768 0x5d6f, 1769 0x5d72, 1770 0x5d77, 1771 0x5e6b, 1772 0x5e6d, 1773 0x7120, 1774 0x7124, 1775 0x7129, 1776 0x712e, 1777 0x712f, 1778 0x7162, 1779 0x7163, 1780 0x7166, 1781 0x7167, 1782 0x7172, 1783 0x7173, 1784 0x71a0, 1785 0x71a1, 1786 0x71a3, 1787 0x71a7, 1788 0x71bb, 1789 0x71e0, 1790 0x71e1, 1791 0x71e2, 1792 0x71e6, 1793 0x71e7, 1794 0x71f2, 1795 0x7269, 1796 0x726b, 1797 0x726e, 1798 0x72a0, 1799 0x72a8, 1800 0x72b1, 1801 0x72b3, 1802 0x793f, 1803 }; 1804 1805 static const struct pci_device_id pciidlist[] = { 1806 #ifdef CONFIG_DRM_AMDGPU_SI 1807 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1808 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1809 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1810 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1811 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1812 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1813 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1814 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1815 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1816 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1817 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1818 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1819 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1820 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1824 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1825 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1826 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1827 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1828 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1829 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1830 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1831 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1832 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1833 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1834 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1841 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1842 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1843 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1844 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1849 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1850 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1855 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1858 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1859 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1860 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1861 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1862 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1863 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1867 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1868 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1869 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1870 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1871 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1872 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1873 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1874 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1875 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1878 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1879 #endif 1880 #ifdef CONFIG_DRM_AMDGPU_CIK 1881 /* Kaveri */ 1882 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1883 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1884 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1885 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1886 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1887 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1888 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1889 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1890 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1891 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1892 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1893 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1894 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1895 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1896 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1897 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1898 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1899 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1900 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1901 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1902 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1903 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1904 /* Bonaire */ 1905 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1906 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1907 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1908 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1909 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1910 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1911 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1912 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1913 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1914 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1915 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1916 /* Hawaii */ 1917 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1918 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1919 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1920 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1921 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1922 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1923 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1924 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1925 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1926 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1927 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1928 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1929 /* Kabini */ 1930 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1932 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1934 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1936 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1938 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1941 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1943 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1944 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1945 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1946 /* mullins */ 1947 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1950 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1951 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1952 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1953 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1954 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1955 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1956 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1957 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1958 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1959 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1960 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1961 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1962 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1963 #endif 1964 /* topaz */ 1965 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1966 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1967 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1968 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1969 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1970 /* tonga */ 1971 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1972 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1973 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1974 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1975 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1976 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1977 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1978 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1979 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1980 /* fiji */ 1981 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1982 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1983 /* carrizo */ 1984 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1985 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1986 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1987 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1988 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1989 /* stoney */ 1990 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1991 /* Polaris11 */ 1992 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1993 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1994 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1995 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1996 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1997 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1998 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1999 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2000 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2001 /* Polaris10 */ 2002 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2003 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2004 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2005 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2006 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2007 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2008 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2009 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2010 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2011 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2012 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2013 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2014 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2015 /* Polaris12 */ 2016 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2017 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2018 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2019 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2020 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2021 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2022 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2023 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2024 /* VEGAM */ 2025 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2026 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2027 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2028 /* Vega 10 */ 2029 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2030 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2031 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2032 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2033 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2034 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2035 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2036 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2037 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2038 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2039 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2040 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2041 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2042 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2043 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2044 /* Vega 12 */ 2045 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2046 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2047 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2048 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2049 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2050 /* Vega 20 */ 2051 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2052 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2053 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2054 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2055 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2056 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2057 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2058 /* Raven */ 2059 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2060 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2061 /* Arcturus */ 2062 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2063 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2064 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2065 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2066 /* Navi10 */ 2067 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2068 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2069 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2070 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2071 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2072 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2073 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2074 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2075 /* Navi14 */ 2076 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2077 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2078 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2079 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2080 2081 /* Renoir */ 2082 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2083 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2084 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2085 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2086 2087 /* Navi12 */ 2088 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2089 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2090 2091 /* Sienna_Cichlid */ 2092 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2093 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2094 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2095 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2096 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2097 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2098 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2099 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2100 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2101 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2102 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2103 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2104 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2105 2106 /* Yellow Carp */ 2107 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2108 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2109 2110 /* Navy_Flounder */ 2111 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2112 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2113 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2114 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2115 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2116 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2117 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2118 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2119 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2120 2121 /* DIMGREY_CAVEFISH */ 2122 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2123 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2124 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2125 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2126 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2127 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2128 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2129 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2130 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2131 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2132 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2133 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2134 2135 /* Aldebaran */ 2136 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2137 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2138 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2139 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2140 2141 /* CYAN_SKILLFISH */ 2142 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2143 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2144 2145 /* BEIGE_GOBY */ 2146 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2147 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2148 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2149 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2150 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2151 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2152 2153 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2154 .class = PCI_CLASS_DISPLAY_VGA << 8, 2155 .class_mask = 0xffffff, 2156 .driver_data = CHIP_IP_DISCOVERY }, 2157 2158 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2159 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2160 .class_mask = 0xffffff, 2161 .driver_data = CHIP_IP_DISCOVERY }, 2162 2163 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2164 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2165 .class_mask = 0xffffff, 2166 .driver_data = CHIP_IP_DISCOVERY }, 2167 2168 {0, 0, 0} 2169 }; 2170 2171 MODULE_DEVICE_TABLE(pci, pciidlist); 2172 2173 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2174 /* differentiate between P10 and P11 asics with the same DID */ 2175 {0x67FF, 0xE3, CHIP_POLARIS10}, 2176 {0x67FF, 0xE7, CHIP_POLARIS10}, 2177 {0x67FF, 0xF3, CHIP_POLARIS10}, 2178 {0x67FF, 0xF7, CHIP_POLARIS10}, 2179 }; 2180 2181 static const struct drm_driver amdgpu_kms_driver; 2182 2183 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2184 { 2185 struct pci_dev *p = NULL; 2186 int i; 2187 2188 /* 0 - GPU 2189 * 1 - audio 2190 * 2 - USB 2191 * 3 - UCSI 2192 */ 2193 for (i = 1; i < 4; i++) { 2194 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2195 adev->pdev->bus->number, i); 2196 if (p) { 2197 pm_runtime_get_sync(&p->dev); 2198 pm_runtime_mark_last_busy(&p->dev); 2199 pm_runtime_put_autosuspend(&p->dev); 2200 pci_dev_put(p); 2201 } 2202 } 2203 } 2204 2205 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2206 { 2207 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2208 pr_info("debug: VM handling debug enabled\n"); 2209 adev->debug_vm = true; 2210 } 2211 2212 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2213 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2214 adev->debug_largebar = true; 2215 } 2216 2217 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2218 pr_info("debug: soft reset for GPU recovery disabled\n"); 2219 adev->debug_disable_soft_recovery = true; 2220 } 2221 2222 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2223 pr_info("debug: place fw in vram for frontdoor loading\n"); 2224 adev->debug_use_vram_fw_buf = true; 2225 } 2226 2227 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2228 pr_info("debug: enable RAS ACA\n"); 2229 adev->debug_enable_ras_aca = true; 2230 } 2231 2232 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2233 pr_info("debug: enable experimental reset features\n"); 2234 adev->debug_exp_resets = true; 2235 } 2236 2237 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2238 pr_info("debug: ring reset disabled\n"); 2239 adev->debug_disable_gpu_ring_reset = true; 2240 } 2241 } 2242 2243 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2244 { 2245 int i; 2246 2247 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2248 if (pdev->device == asic_type_quirks[i].device && 2249 pdev->revision == asic_type_quirks[i].revision) { 2250 flags &= ~AMD_ASIC_MASK; 2251 flags |= asic_type_quirks[i].type; 2252 break; 2253 } 2254 } 2255 2256 return flags; 2257 } 2258 2259 static int amdgpu_pci_probe(struct pci_dev *pdev, 2260 const struct pci_device_id *ent) 2261 { 2262 struct drm_device *ddev; 2263 struct amdgpu_device *adev; 2264 unsigned long flags = ent->driver_data; 2265 int ret, retry = 0, i; 2266 bool supports_atomic = false; 2267 2268 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2269 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2270 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2271 return -EINVAL; 2272 } 2273 2274 /* skip devices which are owned by radeon */ 2275 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2276 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2277 return -ENODEV; 2278 } 2279 2280 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2281 amdgpu_aspm = 0; 2282 2283 if (amdgpu_virtual_display || 2284 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2285 supports_atomic = true; 2286 2287 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2288 DRM_INFO("This hardware requires experimental hardware support.\n" 2289 "See modparam exp_hw_support\n"); 2290 return -ENODEV; 2291 } 2292 2293 flags = amdgpu_fix_asic_type(pdev, flags); 2294 2295 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2296 * however, SME requires an indirect IOMMU mapping because the encryption 2297 * bit is beyond the DMA mask of the chip. 2298 */ 2299 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2300 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2301 dev_info(&pdev->dev, 2302 "SME is not compatible with RAVEN\n"); 2303 return -ENOTSUPP; 2304 } 2305 2306 #ifdef CONFIG_DRM_AMDGPU_SI 2307 if (!amdgpu_si_support) { 2308 switch (flags & AMD_ASIC_MASK) { 2309 case CHIP_TAHITI: 2310 case CHIP_PITCAIRN: 2311 case CHIP_VERDE: 2312 case CHIP_OLAND: 2313 case CHIP_HAINAN: 2314 dev_info(&pdev->dev, 2315 "SI support provided by radeon.\n"); 2316 dev_info(&pdev->dev, 2317 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2318 ); 2319 return -ENODEV; 2320 } 2321 } 2322 #endif 2323 #ifdef CONFIG_DRM_AMDGPU_CIK 2324 if (!amdgpu_cik_support) { 2325 switch (flags & AMD_ASIC_MASK) { 2326 case CHIP_KAVERI: 2327 case CHIP_BONAIRE: 2328 case CHIP_HAWAII: 2329 case CHIP_KABINI: 2330 case CHIP_MULLINS: 2331 dev_info(&pdev->dev, 2332 "CIK support provided by radeon.\n"); 2333 dev_info(&pdev->dev, 2334 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2335 ); 2336 return -ENODEV; 2337 } 2338 } 2339 #endif 2340 2341 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2342 if (IS_ERR(adev)) 2343 return PTR_ERR(adev); 2344 2345 adev->dev = &pdev->dev; 2346 adev->pdev = pdev; 2347 ddev = adev_to_drm(adev); 2348 2349 if (!supports_atomic) 2350 ddev->driver_features &= ~DRIVER_ATOMIC; 2351 2352 ret = pci_enable_device(pdev); 2353 if (ret) 2354 return ret; 2355 2356 pci_set_drvdata(pdev, ddev); 2357 2358 amdgpu_init_debug_options(adev); 2359 2360 ret = amdgpu_driver_load_kms(adev, flags); 2361 if (ret) 2362 goto err_pci; 2363 2364 retry_init: 2365 ret = drm_dev_register(ddev, flags); 2366 if (ret == -EAGAIN && ++retry <= 3) { 2367 DRM_INFO("retry init %d\n", retry); 2368 /* Don't request EX mode too frequently which is attacking */ 2369 msleep(5000); 2370 goto retry_init; 2371 } else if (ret) { 2372 goto err_pci; 2373 } 2374 2375 ret = amdgpu_xcp_dev_register(adev, ent); 2376 if (ret) 2377 goto err_pci; 2378 2379 ret = amdgpu_amdkfd_drm_client_create(adev); 2380 if (ret) 2381 goto err_pci; 2382 2383 /* 2384 * 1. don't init fbdev on hw without DCE 2385 * 2. don't init fbdev if there are no connectors 2386 */ 2387 if (adev->mode_info.mode_config_initialized && 2388 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2389 const struct drm_format_info *format; 2390 2391 /* select 8 bpp console on low vram cards */ 2392 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2393 format = drm_format_info(DRM_FORMAT_C8); 2394 else 2395 format = NULL; 2396 2397 drm_client_setup(adev_to_drm(adev), format); 2398 } 2399 2400 ret = amdgpu_debugfs_init(adev); 2401 if (ret) 2402 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2403 2404 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2405 /* only need to skip on ATPX */ 2406 if (amdgpu_device_supports_px(ddev)) 2407 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2408 /* we want direct complete for BOCO */ 2409 if (amdgpu_device_supports_boco(ddev)) 2410 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2411 DPM_FLAG_SMART_SUSPEND | 2412 DPM_FLAG_MAY_SKIP_RESUME); 2413 pm_runtime_use_autosuspend(ddev->dev); 2414 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2415 2416 pm_runtime_allow(ddev->dev); 2417 2418 pm_runtime_mark_last_busy(ddev->dev); 2419 pm_runtime_put_autosuspend(ddev->dev); 2420 2421 pci_wake_from_d3(pdev, TRUE); 2422 2423 /* 2424 * For runpm implemented via BACO, PMFW will handle the 2425 * timing for BACO in and out: 2426 * - put ASIC into BACO state only when both video and 2427 * audio functions are in D3 state. 2428 * - pull ASIC out of BACO state when either video or 2429 * audio function is in D0 state. 2430 * Also, at startup, PMFW assumes both functions are in 2431 * D0 state. 2432 * 2433 * So if snd driver was loaded prior to amdgpu driver 2434 * and audio function was put into D3 state, there will 2435 * be no PMFW-aware D-state transition(D0->D3) on runpm 2436 * suspend. Thus the BACO will be not correctly kicked in. 2437 * 2438 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2439 * into D0 state. Then there will be a PMFW-aware D-state 2440 * transition(D0->D3) on runpm suspend. 2441 */ 2442 if (amdgpu_device_supports_baco(ddev) && 2443 !(adev->flags & AMD_IS_APU) && 2444 (adev->asic_type >= CHIP_NAVI10)) 2445 amdgpu_get_secondary_funcs(adev); 2446 } 2447 2448 return 0; 2449 2450 err_pci: 2451 pci_disable_device(pdev); 2452 return ret; 2453 } 2454 2455 static void 2456 amdgpu_pci_remove(struct pci_dev *pdev) 2457 { 2458 struct drm_device *dev = pci_get_drvdata(pdev); 2459 struct amdgpu_device *adev = drm_to_adev(dev); 2460 2461 amdgpu_xcp_dev_unplug(adev); 2462 amdgpu_gmc_prepare_nps_mode_change(adev); 2463 drm_dev_unplug(dev); 2464 2465 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2466 pm_runtime_get_sync(dev->dev); 2467 pm_runtime_forbid(dev->dev); 2468 } 2469 2470 amdgpu_driver_unload_kms(dev); 2471 2472 /* 2473 * Flush any in flight DMA operations from device. 2474 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2475 * StatusTransactions Pending bit. 2476 */ 2477 pci_disable_device(pdev); 2478 pci_wait_for_pending_transaction(pdev); 2479 } 2480 2481 static void 2482 amdgpu_pci_shutdown(struct pci_dev *pdev) 2483 { 2484 struct drm_device *dev = pci_get_drvdata(pdev); 2485 struct amdgpu_device *adev = drm_to_adev(dev); 2486 2487 if (amdgpu_ras_intr_triggered()) 2488 return; 2489 2490 /* if we are running in a VM, make sure the device 2491 * torn down properly on reboot/shutdown. 2492 * unfortunately we can't detect certain 2493 * hypervisors so just do this all the time. 2494 */ 2495 if (!amdgpu_passthrough(adev)) 2496 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2497 amdgpu_device_ip_suspend(adev); 2498 adev->mp1_state = PP_MP1_STATE_NONE; 2499 } 2500 2501 static int amdgpu_pmops_prepare(struct device *dev) 2502 { 2503 struct drm_device *drm_dev = dev_get_drvdata(dev); 2504 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2505 2506 /* Return a positive number here so 2507 * DPM_FLAG_SMART_SUSPEND works properly 2508 */ 2509 if (amdgpu_device_supports_boco(drm_dev) && 2510 pm_runtime_suspended(dev)) 2511 return 1; 2512 2513 /* if we will not support s3 or s2i for the device 2514 * then skip suspend 2515 */ 2516 if (!amdgpu_acpi_is_s0ix_active(adev) && 2517 !amdgpu_acpi_is_s3_active(adev)) 2518 return 1; 2519 2520 return amdgpu_device_prepare(drm_dev); 2521 } 2522 2523 static void amdgpu_pmops_complete(struct device *dev) 2524 { 2525 /* nothing to do */ 2526 } 2527 2528 static int amdgpu_pmops_suspend(struct device *dev) 2529 { 2530 struct drm_device *drm_dev = dev_get_drvdata(dev); 2531 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2532 2533 if (amdgpu_acpi_is_s0ix_active(adev)) 2534 adev->in_s0ix = true; 2535 else if (amdgpu_acpi_is_s3_active(adev)) 2536 adev->in_s3 = true; 2537 if (!adev->in_s0ix && !adev->in_s3) 2538 return 0; 2539 return amdgpu_device_suspend(drm_dev, true); 2540 } 2541 2542 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2543 { 2544 struct drm_device *drm_dev = dev_get_drvdata(dev); 2545 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2546 2547 if (amdgpu_acpi_should_gpu_reset(adev)) 2548 return amdgpu_asic_reset(adev); 2549 2550 return 0; 2551 } 2552 2553 static int amdgpu_pmops_resume(struct device *dev) 2554 { 2555 struct drm_device *drm_dev = dev_get_drvdata(dev); 2556 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2557 int r; 2558 2559 if (!adev->in_s0ix && !adev->in_s3) 2560 return 0; 2561 2562 /* Avoids registers access if device is physically gone */ 2563 if (!pci_device_is_present(adev->pdev)) 2564 adev->no_hw_access = true; 2565 2566 r = amdgpu_device_resume(drm_dev, true); 2567 if (amdgpu_acpi_is_s0ix_active(adev)) 2568 adev->in_s0ix = false; 2569 else 2570 adev->in_s3 = false; 2571 return r; 2572 } 2573 2574 static int amdgpu_pmops_freeze(struct device *dev) 2575 { 2576 struct drm_device *drm_dev = dev_get_drvdata(dev); 2577 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2578 int r; 2579 2580 r = amdgpu_device_suspend(drm_dev, true); 2581 if (r) 2582 return r; 2583 2584 if (amdgpu_acpi_should_gpu_reset(adev)) 2585 return amdgpu_asic_reset(adev); 2586 return 0; 2587 } 2588 2589 static int amdgpu_pmops_thaw(struct device *dev) 2590 { 2591 struct drm_device *drm_dev = dev_get_drvdata(dev); 2592 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2593 int r; 2594 2595 r = amdgpu_device_resume(drm_dev, true); 2596 adev->in_s4 = false; 2597 2598 return r; 2599 } 2600 2601 static int amdgpu_pmops_poweroff(struct device *dev) 2602 { 2603 struct drm_device *drm_dev = dev_get_drvdata(dev); 2604 2605 return amdgpu_device_suspend(drm_dev, true); 2606 } 2607 2608 static int amdgpu_pmops_restore(struct device *dev) 2609 { 2610 struct drm_device *drm_dev = dev_get_drvdata(dev); 2611 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2612 2613 adev->in_s4 = false; 2614 2615 return amdgpu_device_resume(drm_dev, true); 2616 } 2617 2618 static int amdgpu_runtime_idle_check_display(struct device *dev) 2619 { 2620 struct pci_dev *pdev = to_pci_dev(dev); 2621 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2622 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2623 2624 if (adev->mode_info.num_crtc) { 2625 struct drm_connector *list_connector; 2626 struct drm_connector_list_iter iter; 2627 int ret = 0; 2628 2629 if (amdgpu_runtime_pm != -2) { 2630 /* XXX: Return busy if any displays are connected to avoid 2631 * possible display wakeups after runtime resume due to 2632 * hotplug events in case any displays were connected while 2633 * the GPU was in suspend. Remove this once that is fixed. 2634 */ 2635 mutex_lock(&drm_dev->mode_config.mutex); 2636 drm_connector_list_iter_begin(drm_dev, &iter); 2637 drm_for_each_connector_iter(list_connector, &iter) { 2638 if (list_connector->status == connector_status_connected) { 2639 ret = -EBUSY; 2640 break; 2641 } 2642 } 2643 drm_connector_list_iter_end(&iter); 2644 mutex_unlock(&drm_dev->mode_config.mutex); 2645 2646 if (ret) 2647 return ret; 2648 } 2649 2650 if (adev->dc_enabled) { 2651 struct drm_crtc *crtc; 2652 2653 drm_for_each_crtc(crtc, drm_dev) { 2654 drm_modeset_lock(&crtc->mutex, NULL); 2655 if (crtc->state->active) 2656 ret = -EBUSY; 2657 drm_modeset_unlock(&crtc->mutex); 2658 if (ret < 0) 2659 break; 2660 } 2661 } else { 2662 mutex_lock(&drm_dev->mode_config.mutex); 2663 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2664 2665 drm_connector_list_iter_begin(drm_dev, &iter); 2666 drm_for_each_connector_iter(list_connector, &iter) { 2667 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2668 ret = -EBUSY; 2669 break; 2670 } 2671 } 2672 2673 drm_connector_list_iter_end(&iter); 2674 2675 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2676 mutex_unlock(&drm_dev->mode_config.mutex); 2677 } 2678 if (ret) 2679 return ret; 2680 } 2681 2682 return 0; 2683 } 2684 2685 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2686 { 2687 struct pci_dev *pdev = to_pci_dev(dev); 2688 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2689 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2690 int ret, i; 2691 2692 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2693 pm_runtime_forbid(dev); 2694 return -EBUSY; 2695 } 2696 2697 ret = amdgpu_runtime_idle_check_display(dev); 2698 if (ret) 2699 return ret; 2700 2701 /* wait for all rings to drain before suspending */ 2702 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2703 struct amdgpu_ring *ring = adev->rings[i]; 2704 2705 if (ring && ring->sched.ready) { 2706 ret = amdgpu_fence_wait_empty(ring); 2707 if (ret) 2708 return -EBUSY; 2709 } 2710 } 2711 2712 adev->in_runpm = true; 2713 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2714 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2715 2716 /* 2717 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2718 * proper cleanups and put itself into a state ready for PNP. That 2719 * can address some random resuming failure observed on BOCO capable 2720 * platforms. 2721 * TODO: this may be also needed for PX capable platform. 2722 */ 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2724 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2725 2726 ret = amdgpu_device_prepare(drm_dev); 2727 if (ret) 2728 return ret; 2729 ret = amdgpu_device_suspend(drm_dev, false); 2730 if (ret) { 2731 adev->in_runpm = false; 2732 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2733 adev->mp1_state = PP_MP1_STATE_NONE; 2734 return ret; 2735 } 2736 2737 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2738 adev->mp1_state = PP_MP1_STATE_NONE; 2739 2740 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2741 /* Only need to handle PCI state in the driver for ATPX 2742 * PCI core handles it for _PR3. 2743 */ 2744 amdgpu_device_cache_pci_state(pdev); 2745 pci_disable_device(pdev); 2746 pci_ignore_hotplug(pdev); 2747 pci_set_power_state(pdev, PCI_D3cold); 2748 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2749 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2750 /* nothing to do */ 2751 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2752 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2753 amdgpu_device_baco_enter(drm_dev); 2754 } 2755 2756 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2757 2758 return 0; 2759 } 2760 2761 static int amdgpu_pmops_runtime_resume(struct device *dev) 2762 { 2763 struct pci_dev *pdev = to_pci_dev(dev); 2764 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2765 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2766 int ret; 2767 2768 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2769 return -EINVAL; 2770 2771 /* Avoids registers access if device is physically gone */ 2772 if (!pci_device_is_present(adev->pdev)) 2773 adev->no_hw_access = true; 2774 2775 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2776 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2777 2778 /* Only need to handle PCI state in the driver for ATPX 2779 * PCI core handles it for _PR3. 2780 */ 2781 pci_set_power_state(pdev, PCI_D0); 2782 amdgpu_device_load_pci_state(pdev); 2783 ret = pci_enable_device(pdev); 2784 if (ret) 2785 return ret; 2786 pci_set_master(pdev); 2787 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2788 /* Only need to handle PCI state in the driver for ATPX 2789 * PCI core handles it for _PR3. 2790 */ 2791 pci_set_master(pdev); 2792 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2793 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2794 amdgpu_device_baco_exit(drm_dev); 2795 } 2796 ret = amdgpu_device_resume(drm_dev, false); 2797 if (ret) { 2798 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2799 pci_disable_device(pdev); 2800 return ret; 2801 } 2802 2803 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2804 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2805 adev->in_runpm = false; 2806 return 0; 2807 } 2808 2809 static int amdgpu_pmops_runtime_idle(struct device *dev) 2810 { 2811 struct drm_device *drm_dev = dev_get_drvdata(dev); 2812 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2813 int ret; 2814 2815 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2816 pm_runtime_forbid(dev); 2817 return -EBUSY; 2818 } 2819 2820 ret = amdgpu_runtime_idle_check_display(dev); 2821 2822 pm_runtime_mark_last_busy(dev); 2823 pm_runtime_autosuspend(dev); 2824 return ret; 2825 } 2826 2827 long amdgpu_drm_ioctl(struct file *filp, 2828 unsigned int cmd, unsigned long arg) 2829 { 2830 struct drm_file *file_priv = filp->private_data; 2831 struct drm_device *dev; 2832 long ret; 2833 2834 dev = file_priv->minor->dev; 2835 ret = pm_runtime_get_sync(dev->dev); 2836 if (ret < 0) 2837 goto out; 2838 2839 ret = drm_ioctl(filp, cmd, arg); 2840 2841 pm_runtime_mark_last_busy(dev->dev); 2842 out: 2843 pm_runtime_put_autosuspend(dev->dev); 2844 return ret; 2845 } 2846 2847 static const struct dev_pm_ops amdgpu_pm_ops = { 2848 .prepare = amdgpu_pmops_prepare, 2849 .complete = amdgpu_pmops_complete, 2850 .suspend = amdgpu_pmops_suspend, 2851 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2852 .resume = amdgpu_pmops_resume, 2853 .freeze = amdgpu_pmops_freeze, 2854 .thaw = amdgpu_pmops_thaw, 2855 .poweroff = amdgpu_pmops_poweroff, 2856 .restore = amdgpu_pmops_restore, 2857 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2858 .runtime_resume = amdgpu_pmops_runtime_resume, 2859 .runtime_idle = amdgpu_pmops_runtime_idle, 2860 }; 2861 2862 static int amdgpu_flush(struct file *f, fl_owner_t id) 2863 { 2864 struct drm_file *file_priv = f->private_data; 2865 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2866 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2867 2868 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2869 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2870 2871 return timeout >= 0 ? 0 : timeout; 2872 } 2873 2874 static const struct file_operations amdgpu_driver_kms_fops = { 2875 .owner = THIS_MODULE, 2876 .open = drm_open, 2877 .flush = amdgpu_flush, 2878 .release = drm_release, 2879 .unlocked_ioctl = amdgpu_drm_ioctl, 2880 .mmap = drm_gem_mmap, 2881 .poll = drm_poll, 2882 .read = drm_read, 2883 #ifdef CONFIG_COMPAT 2884 .compat_ioctl = amdgpu_kms_compat_ioctl, 2885 #endif 2886 #ifdef CONFIG_PROC_FS 2887 .show_fdinfo = drm_show_fdinfo, 2888 #endif 2889 .fop_flags = FOP_UNSIGNED_OFFSET, 2890 }; 2891 2892 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2893 { 2894 struct drm_file *file; 2895 2896 if (!filp) 2897 return -EINVAL; 2898 2899 if (filp->f_op != &amdgpu_driver_kms_fops) 2900 return -EINVAL; 2901 2902 file = filp->private_data; 2903 *fpriv = file->driver_priv; 2904 return 0; 2905 } 2906 2907 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2908 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2909 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2910 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2911 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2912 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2913 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2914 /* KMS */ 2915 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2916 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2917 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2918 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2919 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2920 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2921 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2922 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2923 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2924 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2925 }; 2926 2927 static const struct drm_driver amdgpu_kms_driver = { 2928 .driver_features = 2929 DRIVER_ATOMIC | 2930 DRIVER_GEM | 2931 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2932 DRIVER_SYNCOBJ_TIMELINE, 2933 .open = amdgpu_driver_open_kms, 2934 .postclose = amdgpu_driver_postclose_kms, 2935 .ioctls = amdgpu_ioctls_kms, 2936 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2937 .dumb_create = amdgpu_mode_dumb_create, 2938 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2939 DRM_FBDEV_TTM_DRIVER_OPS, 2940 .fops = &amdgpu_driver_kms_fops, 2941 .release = &amdgpu_driver_release_kms, 2942 #ifdef CONFIG_PROC_FS 2943 .show_fdinfo = amdgpu_show_fdinfo, 2944 #endif 2945 2946 .gem_prime_import = amdgpu_gem_prime_import, 2947 2948 .name = DRIVER_NAME, 2949 .desc = DRIVER_DESC, 2950 .major = KMS_DRIVER_MAJOR, 2951 .minor = KMS_DRIVER_MINOR, 2952 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2953 }; 2954 2955 const struct drm_driver amdgpu_partition_driver = { 2956 .driver_features = 2957 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2958 DRIVER_SYNCOBJ_TIMELINE, 2959 .open = amdgpu_driver_open_kms, 2960 .postclose = amdgpu_driver_postclose_kms, 2961 .ioctls = amdgpu_ioctls_kms, 2962 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2963 .dumb_create = amdgpu_mode_dumb_create, 2964 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2965 DRM_FBDEV_TTM_DRIVER_OPS, 2966 .fops = &amdgpu_driver_kms_fops, 2967 .release = &amdgpu_driver_release_kms, 2968 2969 .gem_prime_import = amdgpu_gem_prime_import, 2970 2971 .name = DRIVER_NAME, 2972 .desc = DRIVER_DESC, 2973 .major = KMS_DRIVER_MAJOR, 2974 .minor = KMS_DRIVER_MINOR, 2975 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2976 }; 2977 2978 static struct pci_error_handlers amdgpu_pci_err_handler = { 2979 .error_detected = amdgpu_pci_error_detected, 2980 .mmio_enabled = amdgpu_pci_mmio_enabled, 2981 .slot_reset = amdgpu_pci_slot_reset, 2982 .resume = amdgpu_pci_resume, 2983 }; 2984 2985 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2986 &amdgpu_vram_mgr_attr_group, 2987 &amdgpu_gtt_mgr_attr_group, 2988 &amdgpu_flash_attr_group, 2989 NULL, 2990 }; 2991 2992 static struct pci_driver amdgpu_kms_pci_driver = { 2993 .name = DRIVER_NAME, 2994 .id_table = pciidlist, 2995 .probe = amdgpu_pci_probe, 2996 .remove = amdgpu_pci_remove, 2997 .shutdown = amdgpu_pci_shutdown, 2998 .driver.pm = &amdgpu_pm_ops, 2999 .err_handler = &amdgpu_pci_err_handler, 3000 .dev_groups = amdgpu_sysfs_groups, 3001 }; 3002 3003 static int __init amdgpu_init(void) 3004 { 3005 int r; 3006 3007 r = amdgpu_sync_init(); 3008 if (r) 3009 goto error_sync; 3010 3011 r = amdgpu_fence_slab_init(); 3012 if (r) 3013 goto error_fence; 3014 3015 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3016 amdgpu_register_atpx_handler(); 3017 amdgpu_acpi_detect(); 3018 3019 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3020 amdgpu_amdkfd_init(); 3021 3022 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3023 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3024 pr_crit("Overdrive is enabled, please disable it before " 3025 "reporting any bugs unrelated to overdrive.\n"); 3026 } 3027 3028 /* let modprobe override vga console setting */ 3029 return pci_register_driver(&amdgpu_kms_pci_driver); 3030 3031 error_fence: 3032 amdgpu_sync_fini(); 3033 3034 error_sync: 3035 return r; 3036 } 3037 3038 static void __exit amdgpu_exit(void) 3039 { 3040 amdgpu_amdkfd_fini(); 3041 pci_unregister_driver(&amdgpu_kms_pci_driver); 3042 amdgpu_unregister_atpx_handler(); 3043 amdgpu_acpi_release(); 3044 amdgpu_sync_fini(); 3045 amdgpu_fence_slab_fini(); 3046 mmu_notifier_synchronize(); 3047 amdgpu_xcp_drv_release(); 3048 } 3049 3050 module_init(amdgpu_init); 3051 module_exit(amdgpu_exit); 3052 3053 MODULE_AUTHOR(DRIVER_AUTHOR); 3054 MODULE_DESCRIPTION(DRIVER_DESC); 3055 MODULE_LICENSE("GPL and additional rights"); 3056