1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_runtime.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_vblank.h> 43 #include <drm/drm_drv.h> 44 45 static void amdgpu_display_flip_callback(struct dma_fence *f, 46 struct dma_fence_cb *cb) 47 { 48 struct amdgpu_flip_work *work = 49 container_of(cb, struct amdgpu_flip_work, cb); 50 51 dma_fence_put(f); 52 schedule_work(&work->flip_work.work); 53 } 54 55 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 56 struct dma_fence **f) 57 { 58 struct dma_fence *fence= *f; 59 60 if (fence == NULL) 61 return false; 62 63 *f = NULL; 64 65 if (!dma_fence_add_callback(fence, &work->cb, 66 amdgpu_display_flip_callback)) 67 return true; 68 69 dma_fence_put(fence); 70 return false; 71 } 72 73 static void amdgpu_display_flip_work_func(struct work_struct *__work) 74 { 75 struct delayed_work *delayed_work = 76 container_of(__work, struct delayed_work, work); 77 struct amdgpu_flip_work *work = 78 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 79 struct amdgpu_device *adev = work->adev; 80 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 81 82 struct drm_crtc *crtc = &amdgpu_crtc->base; 83 unsigned long flags; 84 unsigned i; 85 int vpos, hpos; 86 87 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 88 return; 89 90 for (i = 0; i < work->shared_count; ++i) 91 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 92 return; 93 94 /* Wait until we're out of the vertical blank period before the one 95 * targeted by the flip 96 */ 97 if (amdgpu_crtc->enabled && 98 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 99 &vpos, &hpos, NULL, NULL, 100 &crtc->hwmode) 101 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 102 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 103 (int)(work->target_vblank - 104 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 105 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 106 return; 107 } 108 109 /* We borrow the event spin lock for protecting flip_status */ 110 spin_lock_irqsave(&crtc->dev->event_lock, flags); 111 112 /* Do the flip (mmio) */ 113 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 114 115 /* Set the flip status */ 116 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 117 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 118 119 120 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 121 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 122 123 } 124 125 /* 126 * Handle unpin events outside the interrupt handler proper. 127 */ 128 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 129 { 130 struct amdgpu_flip_work *work = 131 container_of(__work, struct amdgpu_flip_work, unpin_work); 132 int r; 133 134 /* unpin of the old buffer */ 135 r = amdgpu_bo_reserve(work->old_abo, true); 136 if (likely(r == 0)) { 137 amdgpu_bo_unpin(work->old_abo); 138 amdgpu_bo_unreserve(work->old_abo); 139 } else 140 DRM_ERROR("failed to reserve buffer after flip\n"); 141 142 amdgpu_bo_unref(&work->old_abo); 143 kfree(work->shared); 144 kfree(work); 145 } 146 147 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 148 struct drm_framebuffer *fb, 149 struct drm_pending_vblank_event *event, 150 uint32_t page_flip_flags, uint32_t target, 151 struct drm_modeset_acquire_ctx *ctx) 152 { 153 struct drm_device *dev = crtc->dev; 154 struct amdgpu_device *adev = drm_to_adev(dev); 155 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 156 struct drm_gem_object *obj; 157 struct amdgpu_flip_work *work; 158 struct amdgpu_bo *new_abo; 159 unsigned long flags; 160 u64 tiling_flags; 161 int i, r; 162 163 work = kzalloc(sizeof *work, GFP_KERNEL); 164 if (work == NULL) 165 return -ENOMEM; 166 167 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 168 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 169 170 work->event = event; 171 work->adev = adev; 172 work->crtc_id = amdgpu_crtc->crtc_id; 173 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 174 175 /* schedule unpin of the old buffer */ 176 obj = crtc->primary->fb->obj[0]; 177 178 /* take a reference to the old object */ 179 work->old_abo = gem_to_amdgpu_bo(obj); 180 amdgpu_bo_ref(work->old_abo); 181 182 obj = fb->obj[0]; 183 new_abo = gem_to_amdgpu_bo(obj); 184 185 /* pin the new buffer */ 186 r = amdgpu_bo_reserve(new_abo, false); 187 if (unlikely(r != 0)) { 188 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 189 goto cleanup; 190 } 191 192 if (!adev->enable_virtual_display) { 193 r = amdgpu_bo_pin(new_abo, 194 amdgpu_display_supported_domains(adev, new_abo->flags)); 195 if (unlikely(r != 0)) { 196 DRM_ERROR("failed to pin new abo buffer before flip\n"); 197 goto unreserve; 198 } 199 } 200 201 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 202 if (unlikely(r != 0)) { 203 DRM_ERROR("%p bind failed\n", new_abo); 204 goto unpin; 205 } 206 207 r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl, 208 &work->shared_count, &work->shared); 209 if (unlikely(r != 0)) { 210 DRM_ERROR("failed to get fences for buffer\n"); 211 goto unpin; 212 } 213 214 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 215 amdgpu_bo_unreserve(new_abo); 216 217 if (!adev->enable_virtual_display) 218 work->base = amdgpu_bo_gpu_offset(new_abo); 219 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 220 amdgpu_get_vblank_counter_kms(crtc); 221 222 /* we borrow the event spin lock for protecting flip_wrok */ 223 spin_lock_irqsave(&crtc->dev->event_lock, flags); 224 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 225 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 226 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 227 r = -EBUSY; 228 goto pflip_cleanup; 229 } 230 231 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 232 amdgpu_crtc->pflip_works = work; 233 234 235 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 236 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 237 /* update crtc fb */ 238 crtc->primary->fb = fb; 239 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 240 amdgpu_display_flip_work_func(&work->flip_work.work); 241 return 0; 242 243 pflip_cleanup: 244 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 245 DRM_ERROR("failed to reserve new abo in error path\n"); 246 goto cleanup; 247 } 248 unpin: 249 if (!adev->enable_virtual_display) 250 amdgpu_bo_unpin(new_abo); 251 252 unreserve: 253 amdgpu_bo_unreserve(new_abo); 254 255 cleanup: 256 amdgpu_bo_unref(&work->old_abo); 257 dma_fence_put(work->excl); 258 for (i = 0; i < work->shared_count; ++i) 259 dma_fence_put(work->shared[i]); 260 kfree(work->shared); 261 kfree(work); 262 263 return r; 264 } 265 266 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 267 struct drm_modeset_acquire_ctx *ctx) 268 { 269 struct drm_device *dev; 270 struct amdgpu_device *adev; 271 struct drm_crtc *crtc; 272 bool active = false; 273 int ret; 274 275 if (!set || !set->crtc) 276 return -EINVAL; 277 278 dev = set->crtc->dev; 279 280 ret = pm_runtime_get_sync(dev->dev); 281 if (ret < 0) 282 goto out; 283 284 ret = drm_crtc_helper_set_config(set, ctx); 285 286 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 287 if (crtc->enabled) 288 active = true; 289 290 pm_runtime_mark_last_busy(dev->dev); 291 292 adev = drm_to_adev(dev); 293 /* if we have active crtcs and we don't have a power ref, 294 take the current one */ 295 if (active && !adev->have_disp_power_ref) { 296 adev->have_disp_power_ref = true; 297 return ret; 298 } 299 /* if we have no active crtcs, then drop the power ref 300 we got before */ 301 if (!active && adev->have_disp_power_ref) { 302 pm_runtime_put_autosuspend(dev->dev); 303 adev->have_disp_power_ref = false; 304 } 305 306 out: 307 /* drop the power reference we got coming in here */ 308 pm_runtime_put_autosuspend(dev->dev); 309 return ret; 310 } 311 312 static const char *encoder_names[41] = { 313 "NONE", 314 "INTERNAL_LVDS", 315 "INTERNAL_TMDS1", 316 "INTERNAL_TMDS2", 317 "INTERNAL_DAC1", 318 "INTERNAL_DAC2", 319 "INTERNAL_SDVOA", 320 "INTERNAL_SDVOB", 321 "SI170B", 322 "CH7303", 323 "CH7301", 324 "INTERNAL_DVO1", 325 "EXTERNAL_SDVOA", 326 "EXTERNAL_SDVOB", 327 "TITFP513", 328 "INTERNAL_LVTM1", 329 "VT1623", 330 "HDMI_SI1930", 331 "HDMI_INTERNAL", 332 "INTERNAL_KLDSCP_TMDS1", 333 "INTERNAL_KLDSCP_DVO1", 334 "INTERNAL_KLDSCP_DAC1", 335 "INTERNAL_KLDSCP_DAC2", 336 "SI178", 337 "MVPU_FPGA", 338 "INTERNAL_DDI", 339 "VT1625", 340 "HDMI_SI1932", 341 "DP_AN9801", 342 "DP_DP501", 343 "INTERNAL_UNIPHY", 344 "INTERNAL_KLDSCP_LVTMA", 345 "INTERNAL_UNIPHY1", 346 "INTERNAL_UNIPHY2", 347 "NUTMEG", 348 "TRAVIS", 349 "INTERNAL_VCE", 350 "INTERNAL_UNIPHY3", 351 "HDMI_ANX9805", 352 "INTERNAL_AMCLK", 353 "VIRTUAL", 354 }; 355 356 static const char *hpd_names[6] = { 357 "HPD1", 358 "HPD2", 359 "HPD3", 360 "HPD4", 361 "HPD5", 362 "HPD6", 363 }; 364 365 void amdgpu_display_print_display_setup(struct drm_device *dev) 366 { 367 struct drm_connector *connector; 368 struct amdgpu_connector *amdgpu_connector; 369 struct drm_encoder *encoder; 370 struct amdgpu_encoder *amdgpu_encoder; 371 struct drm_connector_list_iter iter; 372 uint32_t devices; 373 int i = 0; 374 375 drm_connector_list_iter_begin(dev, &iter); 376 DRM_INFO("AMDGPU Display Connectors\n"); 377 drm_for_each_connector_iter(connector, &iter) { 378 amdgpu_connector = to_amdgpu_connector(connector); 379 DRM_INFO("Connector %d:\n", i); 380 DRM_INFO(" %s\n", connector->name); 381 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 382 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 383 if (amdgpu_connector->ddc_bus) { 384 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 385 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 386 amdgpu_connector->ddc_bus->rec.mask_data_reg, 387 amdgpu_connector->ddc_bus->rec.a_clk_reg, 388 amdgpu_connector->ddc_bus->rec.a_data_reg, 389 amdgpu_connector->ddc_bus->rec.en_clk_reg, 390 amdgpu_connector->ddc_bus->rec.en_data_reg, 391 amdgpu_connector->ddc_bus->rec.y_clk_reg, 392 amdgpu_connector->ddc_bus->rec.y_data_reg); 393 if (amdgpu_connector->router.ddc_valid) 394 DRM_INFO(" DDC Router 0x%x/0x%x\n", 395 amdgpu_connector->router.ddc_mux_control_pin, 396 amdgpu_connector->router.ddc_mux_state); 397 if (amdgpu_connector->router.cd_valid) 398 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 399 amdgpu_connector->router.cd_mux_control_pin, 400 amdgpu_connector->router.cd_mux_state); 401 } else { 402 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 403 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 404 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 405 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 406 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 407 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 408 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n"); 409 } 410 DRM_INFO(" Encoders:\n"); 411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 412 amdgpu_encoder = to_amdgpu_encoder(encoder); 413 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 414 if (devices) { 415 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 416 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 417 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 418 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 419 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 420 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 421 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 422 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 423 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 424 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 425 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 426 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 427 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 428 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 429 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 430 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 431 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 432 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 433 if (devices & ATOM_DEVICE_TV1_SUPPORT) 434 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 435 if (devices & ATOM_DEVICE_CV_SUPPORT) 436 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 437 } 438 } 439 i++; 440 } 441 drm_connector_list_iter_end(&iter); 442 } 443 444 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 445 bool use_aux) 446 { 447 u8 out = 0x0; 448 u8 buf[8]; 449 int ret; 450 struct i2c_msg msgs[] = { 451 { 452 .addr = DDC_ADDR, 453 .flags = 0, 454 .len = 1, 455 .buf = &out, 456 }, 457 { 458 .addr = DDC_ADDR, 459 .flags = I2C_M_RD, 460 .len = 8, 461 .buf = buf, 462 } 463 }; 464 465 /* on hw with routers, select right port */ 466 if (amdgpu_connector->router.ddc_valid) 467 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 468 469 if (use_aux) { 470 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 471 } else { 472 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 473 } 474 475 if (ret != 2) 476 /* Couldn't find an accessible DDC on this connector */ 477 return false; 478 /* Probe also for valid EDID header 479 * EDID header starts with: 480 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 481 * Only the first 6 bytes must be valid as 482 * drm_edid_block_valid() can fix the last 2 bytes */ 483 if (drm_edid_header_is_valid(buf) < 6) { 484 /* Couldn't find an accessible EDID on this 485 * connector */ 486 return false; 487 } 488 return true; 489 } 490 491 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 492 .destroy = drm_gem_fb_destroy, 493 .create_handle = drm_gem_fb_create_handle, 494 }; 495 496 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 497 uint64_t bo_flags) 498 { 499 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 500 501 #if defined(CONFIG_DRM_AMD_DC) 502 /* 503 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 504 * is not supported for this board. But this mapping is required 505 * to avoid hang caused by placement of scanout BO in GTT on certain 506 * APUs. So force the BO placement to VRAM in case this architecture 507 * will not allow USWC mappings. 508 * Also, don't allow GTT domain if the BO doesn't have USWC flag set. 509 */ 510 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 511 amdgpu_bo_support_uswc(bo_flags) && 512 amdgpu_device_asic_has_dc_support(adev->asic_type)) { 513 switch (adev->asic_type) { 514 case CHIP_CARRIZO: 515 case CHIP_STONEY: 516 domain |= AMDGPU_GEM_DOMAIN_GTT; 517 break; 518 case CHIP_RAVEN: 519 /* enable S/G on PCO and RV2 */ 520 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 521 (adev->apu_flags & AMD_APU_IS_PICASSO)) 522 domain |= AMDGPU_GEM_DOMAIN_GTT; 523 break; 524 case CHIP_RENOIR: 525 case CHIP_VANGOGH: 526 case CHIP_YELLOW_CARP: 527 domain |= AMDGPU_GEM_DOMAIN_GTT; 528 break; 529 530 default: 531 break; 532 } 533 } 534 #endif 535 536 return domain; 537 } 538 539 static const struct drm_format_info dcc_formats[] = { 540 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 541 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 542 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 543 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 544 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 545 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 546 .has_alpha = true, }, 547 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 548 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 549 .has_alpha = true, }, 550 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2, 551 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 552 .has_alpha = true, }, 553 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 554 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 555 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 556 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 557 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 558 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 559 .has_alpha = true, }, 560 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 561 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 562 .has_alpha = true, }, 563 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2, 564 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 565 }; 566 567 static const struct drm_format_info dcc_retile_formats[] = { 568 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 569 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 570 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 571 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 572 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 573 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 574 .has_alpha = true, }, 575 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 576 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 577 .has_alpha = true, }, 578 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3, 579 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 580 .has_alpha = true, }, 581 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 582 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 583 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 584 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 585 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 586 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 587 .has_alpha = true, }, 588 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 589 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 590 .has_alpha = true, }, 591 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3, 592 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 593 }; 594 595 static const struct drm_format_info * 596 lookup_format_info(const struct drm_format_info formats[], 597 int num_formats, u32 format) 598 { 599 int i; 600 601 for (i = 0; i < num_formats; i++) { 602 if (formats[i].format == format) 603 return &formats[i]; 604 } 605 606 return NULL; 607 } 608 609 const struct drm_format_info * 610 amdgpu_lookup_format_info(u32 format, uint64_t modifier) 611 { 612 if (!IS_AMD_FMT_MOD(modifier)) 613 return NULL; 614 615 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) 616 return lookup_format_info(dcc_retile_formats, 617 ARRAY_SIZE(dcc_retile_formats), 618 format); 619 620 if (AMD_FMT_MOD_GET(DCC, modifier)) 621 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats), 622 format); 623 624 /* returning NULL will cause the default format structs to be used. */ 625 return NULL; 626 } 627 628 629 /* 630 * Tries to extract the renderable DCC offset from the opaque metadata attached 631 * to the buffer. 632 */ 633 static int 634 extract_render_dcc_offset(struct amdgpu_device *adev, 635 struct drm_gem_object *obj, 636 uint64_t *offset) 637 { 638 struct amdgpu_bo *rbo; 639 int r = 0; 640 uint32_t metadata[10]; /* Something that fits a descriptor + header. */ 641 uint32_t size; 642 643 rbo = gem_to_amdgpu_bo(obj); 644 r = amdgpu_bo_reserve(rbo, false); 645 646 if (unlikely(r)) { 647 /* Don't show error message when returning -ERESTARTSYS */ 648 if (r != -ERESTARTSYS) 649 DRM_ERROR("Unable to reserve buffer: %d\n", r); 650 return r; 651 } 652 653 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); 654 amdgpu_bo_unreserve(rbo); 655 656 if (r) 657 return r; 658 659 /* 660 * The first word is the metadata version, and we need space for at least 661 * the version + pci vendor+device id + 8 words for a descriptor. 662 */ 663 if (size < 40 || metadata[0] != 1) 664 return -EINVAL; 665 666 if (adev->family >= AMDGPU_FAMILY_NV) { 667 /* resource word 6/7 META_DATA_ADDRESS{_LO} */ 668 *offset = ((u64)metadata[9] << 16u) | 669 ((metadata[8] & 0xFF000000u) >> 16); 670 } else { 671 /* resource word 5/7 META_DATA_ADDRESS */ 672 *offset = ((u64)metadata[9] << 8u) | 673 ((u64)(metadata[7] & 0x1FE0000u) << 23); 674 } 675 676 return 0; 677 } 678 679 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 680 { 681 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 682 uint64_t modifier = 0; 683 684 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 685 modifier = DRM_FORMAT_MOD_LINEAR; 686 } else { 687 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 688 bool has_xor = swizzle >= 16; 689 int block_size_bits; 690 int version; 691 int pipe_xor_bits = 0; 692 int bank_xor_bits = 0; 693 int packers = 0; 694 int rb = 0; 695 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 696 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 697 698 switch (swizzle >> 2) { 699 case 0: /* 256B */ 700 block_size_bits = 8; 701 break; 702 case 1: /* 4KiB */ 703 case 5: /* 4KiB _X */ 704 block_size_bits = 12; 705 break; 706 case 2: /* 64KiB */ 707 case 4: /* 64 KiB _T */ 708 case 6: /* 64 KiB _X */ 709 block_size_bits = 16; 710 break; 711 default: 712 /* RESERVED or VAR */ 713 return -EINVAL; 714 } 715 716 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 717 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 718 else if (adev->family == AMDGPU_FAMILY_NV) 719 version = AMD_FMT_MOD_TILE_VER_GFX10; 720 else 721 version = AMD_FMT_MOD_TILE_VER_GFX9; 722 723 switch (swizzle & 3) { 724 case 0: /* Z microtiling */ 725 return -EINVAL; 726 case 1: /* S microtiling */ 727 if (!has_xor) 728 version = AMD_FMT_MOD_TILE_VER_GFX9; 729 break; 730 case 2: 731 if (!has_xor && afb->base.format->cpp[0] != 4) 732 version = AMD_FMT_MOD_TILE_VER_GFX9; 733 break; 734 case 3: 735 break; 736 } 737 738 if (has_xor) { 739 switch (version) { 740 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 741 pipe_xor_bits = min(block_size_bits - 8, pipes); 742 packers = min(block_size_bits - 8 - pipe_xor_bits, 743 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 744 break; 745 case AMD_FMT_MOD_TILE_VER_GFX10: 746 pipe_xor_bits = min(block_size_bits - 8, pipes); 747 break; 748 case AMD_FMT_MOD_TILE_VER_GFX9: 749 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 750 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 751 pipe_xor_bits = min(block_size_bits - 8, pipes + 752 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 753 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 754 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 755 break; 756 } 757 } 758 759 modifier = AMD_FMT_MOD | 760 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 761 AMD_FMT_MOD_SET(TILE_VERSION, version) | 762 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 763 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 764 AMD_FMT_MOD_SET(PACKERS, packers); 765 766 if (dcc_offset != 0) { 767 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 768 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 769 const struct drm_format_info *format_info; 770 u64 render_dcc_offset; 771 772 /* Enable constant encode on RAVEN2 and later. */ 773 bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN || 774 (adev->asic_type == CHIP_RAVEN && 775 adev->external_rev_id >= 0x81); 776 777 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 778 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 779 AMD_FMT_MOD_DCC_BLOCK_256B; 780 781 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 782 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 783 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 784 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 785 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 786 787 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 788 afb->base.pitches[1] = 789 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 790 791 /* 792 * If the userspace driver uses retiling the tiling flags do not contain 793 * info on the renderable DCC buffer. Luckily the opaque metadata contains 794 * the info so we can try to extract it. The kernel does not use this info 795 * but we should convert it to a modifier plane for getfb2, so the 796 * userspace driver that gets it doesn't have to juggle around another DCC 797 * plane internally. 798 */ 799 if (extract_render_dcc_offset(adev, afb->base.obj[0], 800 &render_dcc_offset) == 0 && 801 render_dcc_offset != 0 && 802 render_dcc_offset != afb->base.offsets[1] && 803 render_dcc_offset < UINT_MAX) { 804 uint32_t dcc_block_bits; /* of base surface data */ 805 806 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); 807 afb->base.offsets[2] = render_dcc_offset; 808 809 if (adev->family >= AMDGPU_FAMILY_NV) { 810 int extra_pipe = 0; 811 812 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 813 pipes == packers && pipes > 1) 814 extra_pipe = 1; 815 816 dcc_block_bits = max(20, 16 + pipes + extra_pipe); 817 } else { 818 modifier |= AMD_FMT_MOD_SET(RB, rb) | 819 AMD_FMT_MOD_SET(PIPE, pipes); 820 dcc_block_bits = max(20, 18 + rb); 821 } 822 823 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); 824 afb->base.pitches[2] = ALIGN(afb->base.width, 825 1u << ((dcc_block_bits + 1) / 2)); 826 } 827 format_info = amdgpu_lookup_format_info(afb->base.format->format, 828 modifier); 829 if (!format_info) 830 return -EINVAL; 831 832 afb->base.format = format_info; 833 } 834 } 835 836 afb->base.modifier = modifier; 837 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 838 return 0; 839 } 840 841 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 842 unsigned int *width, unsigned int *height) 843 { 844 unsigned int cpp_log2 = ilog2(cpp); 845 unsigned int pixel_log2 = block_log2 - cpp_log2; 846 unsigned int width_log2 = (pixel_log2 + 1) / 2; 847 unsigned int height_log2 = pixel_log2 - width_log2; 848 849 *width = 1 << width_log2; 850 *height = 1 << height_log2; 851 } 852 853 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, 854 bool pipe_aligned) 855 { 856 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); 857 858 switch (ver) { 859 case AMD_FMT_MOD_TILE_VER_GFX9: { 860 /* 861 * TODO: for pipe aligned we may need to check the alignment of the 862 * total size of the surface, which may need to be bigger than the 863 * natural alignment due to some HW workarounds 864 */ 865 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); 866 } 867 case AMD_FMT_MOD_TILE_VER_GFX10: 868 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: { 869 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 870 871 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && 872 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) 873 ++pipes_log2; 874 875 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12); 876 } 877 default: 878 return 0; 879 } 880 } 881 882 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane, 883 const struct drm_format_info *format, 884 unsigned int block_width, unsigned int block_height, 885 unsigned int block_size_log2) 886 { 887 unsigned int width = rfb->base.width / 888 ((plane && plane < format->num_planes) ? format->hsub : 1); 889 unsigned int height = rfb->base.height / 890 ((plane && plane < format->num_planes) ? format->vsub : 1); 891 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; 892 unsigned int block_pitch = block_width * cpp; 893 unsigned int min_pitch = ALIGN(width * cpp, block_pitch); 894 unsigned int block_size = 1 << block_size_log2; 895 uint64_t size; 896 897 if (rfb->base.pitches[plane] % block_pitch) { 898 drm_dbg_kms(rfb->base.dev, 899 "pitch %d for plane %d is not a multiple of block pitch %d\n", 900 rfb->base.pitches[plane], plane, block_pitch); 901 return -EINVAL; 902 } 903 if (rfb->base.pitches[plane] < min_pitch) { 904 drm_dbg_kms(rfb->base.dev, 905 "pitch %d for plane %d is less than minimum pitch %d\n", 906 rfb->base.pitches[plane], plane, min_pitch); 907 return -EINVAL; 908 } 909 910 /* Force at least natural alignment. */ 911 if (rfb->base.offsets[plane] % block_size) { 912 drm_dbg_kms(rfb->base.dev, 913 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n", 914 rfb->base.offsets[plane], plane, block_size); 915 return -EINVAL; 916 } 917 918 size = rfb->base.offsets[plane] + 919 (uint64_t)rfb->base.pitches[plane] / block_pitch * 920 block_size * DIV_ROUND_UP(height, block_height); 921 922 if (rfb->base.obj[0]->size < size) { 923 drm_dbg_kms(rfb->base.dev, 924 "BO size 0x%zx is less than 0x%llx required for plane %d\n", 925 rfb->base.obj[0]->size, size, plane); 926 return -EINVAL; 927 } 928 929 return 0; 930 } 931 932 933 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 934 { 935 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); 936 uint64_t modifier = rfb->base.modifier; 937 int ret; 938 unsigned int i, block_width, block_height, block_size_log2; 939 940 if (!rfb->base.dev->mode_config.allow_fb_modifiers) 941 return 0; 942 943 for (i = 0; i < format_info->num_planes; ++i) { 944 if (modifier == DRM_FORMAT_MOD_LINEAR) { 945 block_width = 256 / format_info->cpp[i]; 946 block_height = 1; 947 block_size_log2 = 8; 948 } else { 949 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); 950 951 switch ((swizzle & ~3) + 1) { 952 case DC_SW_256B_S: 953 block_size_log2 = 8; 954 break; 955 case DC_SW_4KB_S: 956 case DC_SW_4KB_S_X: 957 block_size_log2 = 12; 958 break; 959 case DC_SW_64KB_S: 960 case DC_SW_64KB_S_T: 961 case DC_SW_64KB_S_X: 962 block_size_log2 = 16; 963 break; 964 default: 965 drm_dbg_kms(rfb->base.dev, 966 "Swizzle mode with unknown block size: %d\n", swizzle); 967 return -EINVAL; 968 } 969 970 get_block_dimensions(block_size_log2, format_info->cpp[i], 971 &block_width, &block_height); 972 } 973 974 ret = amdgpu_display_verify_plane(rfb, i, format_info, 975 block_width, block_height, block_size_log2); 976 if (ret) 977 return ret; 978 } 979 980 if (AMD_FMT_MOD_GET(DCC, modifier)) { 981 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { 982 block_size_log2 = get_dcc_block_size(modifier, false, false); 983 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 984 &block_width, &block_height); 985 ret = amdgpu_display_verify_plane(rfb, i, format_info, 986 block_width, block_height, 987 block_size_log2); 988 if (ret) 989 return ret; 990 991 ++i; 992 block_size_log2 = get_dcc_block_size(modifier, true, true); 993 } else { 994 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); 995 996 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); 997 } 998 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 999 &block_width, &block_height); 1000 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1001 block_width, block_height, block_size_log2); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 return 0; 1007 } 1008 1009 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1010 uint64_t *tiling_flags, bool *tmz_surface) 1011 { 1012 struct amdgpu_bo *rbo; 1013 int r; 1014 1015 if (!amdgpu_fb) { 1016 *tiling_flags = 0; 1017 *tmz_surface = false; 1018 return 0; 1019 } 1020 1021 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1022 r = amdgpu_bo_reserve(rbo, false); 1023 1024 if (unlikely(r)) { 1025 /* Don't show error message when returning -ERESTARTSYS */ 1026 if (r != -ERESTARTSYS) 1027 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1028 return r; 1029 } 1030 1031 if (tiling_flags) 1032 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1033 1034 if (tmz_surface) 1035 *tmz_surface = amdgpu_bo_encrypted(rbo); 1036 1037 amdgpu_bo_unreserve(rbo); 1038 1039 return r; 1040 } 1041 1042 int amdgpu_display_gem_fb_init(struct drm_device *dev, 1043 struct amdgpu_framebuffer *rfb, 1044 const struct drm_mode_fb_cmd2 *mode_cmd, 1045 struct drm_gem_object *obj) 1046 { 1047 int ret; 1048 1049 rfb->base.obj[0] = obj; 1050 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1051 1052 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1053 if (ret) 1054 goto err; 1055 1056 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1057 if (ret) 1058 goto err; 1059 1060 return 0; 1061 err: 1062 drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); 1063 rfb->base.obj[0] = NULL; 1064 return ret; 1065 } 1066 1067 int amdgpu_display_gem_fb_verify_and_init( 1068 struct drm_device *dev, struct amdgpu_framebuffer *rfb, 1069 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, 1070 struct drm_gem_object *obj) 1071 { 1072 int ret; 1073 1074 rfb->base.obj[0] = obj; 1075 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1076 /* Verify that the modifier is supported. */ 1077 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, 1078 mode_cmd->modifier[0])) { 1079 drm_dbg_kms(dev, 1080 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1081 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1082 1083 ret = -EINVAL; 1084 goto err; 1085 } 1086 1087 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1088 if (ret) 1089 goto err; 1090 1091 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1092 if (ret) 1093 goto err; 1094 1095 return 0; 1096 err: 1097 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1098 rfb->base.obj[0] = NULL; 1099 return ret; 1100 } 1101 1102 int amdgpu_display_framebuffer_init(struct drm_device *dev, 1103 struct amdgpu_framebuffer *rfb, 1104 const struct drm_mode_fb_cmd2 *mode_cmd, 1105 struct drm_gem_object *obj) 1106 { 1107 int ret, i; 1108 1109 /* 1110 * This needs to happen before modifier conversion as that might change 1111 * the number of planes. 1112 */ 1113 for (i = 1; i < rfb->base.format->num_planes; ++i) { 1114 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 1115 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", 1116 i, mode_cmd->handles[0], mode_cmd->handles[i]); 1117 ret = -EINVAL; 1118 return ret; 1119 } 1120 } 1121 1122 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1123 if (ret) 1124 return ret; 1125 1126 if (dev->mode_config.allow_fb_modifiers && 1127 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 1128 ret = convert_tiling_flags_to_modifier(rfb); 1129 if (ret) { 1130 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", 1131 rfb->tiling_flags); 1132 return ret; 1133 } 1134 } 1135 1136 ret = amdgpu_display_verify_sizes(rfb); 1137 if (ret) 1138 return ret; 1139 1140 for (i = 0; i < rfb->base.format->num_planes; ++i) { 1141 drm_gem_object_get(rfb->base.obj[0]); 1142 rfb->base.obj[i] = rfb->base.obj[0]; 1143 } 1144 1145 return 0; 1146 } 1147 1148 struct drm_framebuffer * 1149 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 1150 struct drm_file *file_priv, 1151 const struct drm_mode_fb_cmd2 *mode_cmd) 1152 { 1153 struct amdgpu_framebuffer *amdgpu_fb; 1154 struct drm_gem_object *obj; 1155 struct amdgpu_bo *bo; 1156 uint32_t domains; 1157 int ret; 1158 1159 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1160 if (obj == NULL) { 1161 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " 1162 "can't create framebuffer\n", mode_cmd->handles[0]); 1163 return ERR_PTR(-ENOENT); 1164 } 1165 1166 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1167 bo = gem_to_amdgpu_bo(obj); 1168 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 1169 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 1170 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 1171 drm_gem_object_put(obj); 1172 return ERR_PTR(-EINVAL); 1173 } 1174 1175 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 1176 if (amdgpu_fb == NULL) { 1177 drm_gem_object_put(obj); 1178 return ERR_PTR(-ENOMEM); 1179 } 1180 1181 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, 1182 mode_cmd, obj); 1183 if (ret) { 1184 kfree(amdgpu_fb); 1185 drm_gem_object_put(obj); 1186 return ERR_PTR(ret); 1187 } 1188 1189 drm_gem_object_put(obj); 1190 return &amdgpu_fb->base; 1191 } 1192 1193 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 1194 .fb_create = amdgpu_display_user_framebuffer_create, 1195 .output_poll_changed = drm_fb_helper_output_poll_changed, 1196 }; 1197 1198 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 1199 { { UNDERSCAN_OFF, "off" }, 1200 { UNDERSCAN_ON, "on" }, 1201 { UNDERSCAN_AUTO, "auto" }, 1202 }; 1203 1204 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 1205 { { AMDGPU_AUDIO_DISABLE, "off" }, 1206 { AMDGPU_AUDIO_ENABLE, "on" }, 1207 { AMDGPU_AUDIO_AUTO, "auto" }, 1208 }; 1209 1210 /* XXX support different dither options? spatial, temporal, both, etc. */ 1211 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 1212 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 1213 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1214 }; 1215 1216 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1217 { 1218 int sz; 1219 1220 adev->mode_info.coherent_mode_property = 1221 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 1222 if (!adev->mode_info.coherent_mode_property) 1223 return -ENOMEM; 1224 1225 adev->mode_info.load_detect_property = 1226 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 1227 if (!adev->mode_info.load_detect_property) 1228 return -ENOMEM; 1229 1230 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 1231 1232 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 1233 adev->mode_info.underscan_property = 1234 drm_property_create_enum(adev_to_drm(adev), 0, 1235 "underscan", 1236 amdgpu_underscan_enum_list, sz); 1237 1238 adev->mode_info.underscan_hborder_property = 1239 drm_property_create_range(adev_to_drm(adev), 0, 1240 "underscan hborder", 0, 128); 1241 if (!adev->mode_info.underscan_hborder_property) 1242 return -ENOMEM; 1243 1244 adev->mode_info.underscan_vborder_property = 1245 drm_property_create_range(adev_to_drm(adev), 0, 1246 "underscan vborder", 0, 128); 1247 if (!adev->mode_info.underscan_vborder_property) 1248 return -ENOMEM; 1249 1250 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 1251 adev->mode_info.audio_property = 1252 drm_property_create_enum(adev_to_drm(adev), 0, 1253 "audio", 1254 amdgpu_audio_enum_list, sz); 1255 1256 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 1257 adev->mode_info.dither_property = 1258 drm_property_create_enum(adev_to_drm(adev), 0, 1259 "dither", 1260 amdgpu_dither_enum_list, sz); 1261 1262 if (amdgpu_device_has_dc_support(adev)) { 1263 adev->mode_info.abm_level_property = 1264 drm_property_create_range(adev_to_drm(adev), 0, 1265 "abm level", 0, 4); 1266 if (!adev->mode_info.abm_level_property) 1267 return -ENOMEM; 1268 } 1269 1270 return 0; 1271 } 1272 1273 void amdgpu_display_update_priority(struct amdgpu_device *adev) 1274 { 1275 /* adjustment options for the display watermarks */ 1276 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 1277 adev->mode_info.disp_priority = 0; 1278 else 1279 adev->mode_info.disp_priority = amdgpu_disp_priority; 1280 1281 } 1282 1283 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 1284 { 1285 /* try and guess if this is a tv or a monitor */ 1286 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1287 (mode->vdisplay == 576) || /* 576p */ 1288 (mode->vdisplay == 720) || /* 720p */ 1289 (mode->vdisplay == 1080)) /* 1080p */ 1290 return true; 1291 else 1292 return false; 1293 } 1294 1295 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1296 const struct drm_display_mode *mode, 1297 struct drm_display_mode *adjusted_mode) 1298 { 1299 struct drm_device *dev = crtc->dev; 1300 struct drm_encoder *encoder; 1301 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1302 struct amdgpu_encoder *amdgpu_encoder; 1303 struct drm_connector *connector; 1304 u32 src_v = 1, dst_v = 1; 1305 u32 src_h = 1, dst_h = 1; 1306 1307 amdgpu_crtc->h_border = 0; 1308 amdgpu_crtc->v_border = 0; 1309 1310 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1311 if (encoder->crtc != crtc) 1312 continue; 1313 amdgpu_encoder = to_amdgpu_encoder(encoder); 1314 connector = amdgpu_get_connector_for_encoder(encoder); 1315 1316 /* set scaling */ 1317 if (amdgpu_encoder->rmx_type == RMX_OFF) 1318 amdgpu_crtc->rmx_type = RMX_OFF; 1319 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 1320 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 1321 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 1322 else 1323 amdgpu_crtc->rmx_type = RMX_OFF; 1324 /* copy native mode */ 1325 memcpy(&amdgpu_crtc->native_mode, 1326 &amdgpu_encoder->native_mode, 1327 sizeof(struct drm_display_mode)); 1328 src_v = crtc->mode.vdisplay; 1329 dst_v = amdgpu_crtc->native_mode.vdisplay; 1330 src_h = crtc->mode.hdisplay; 1331 dst_h = amdgpu_crtc->native_mode.hdisplay; 1332 1333 /* fix up for overscan on hdmi */ 1334 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1335 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 1336 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 1337 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 1338 amdgpu_display_is_hdtv_mode(mode)))) { 1339 if (amdgpu_encoder->underscan_hborder != 0) 1340 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 1341 else 1342 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 1343 if (amdgpu_encoder->underscan_vborder != 0) 1344 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 1345 else 1346 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 1347 amdgpu_crtc->rmx_type = RMX_FULL; 1348 src_v = crtc->mode.vdisplay; 1349 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 1350 src_h = crtc->mode.hdisplay; 1351 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 1352 } 1353 } 1354 if (amdgpu_crtc->rmx_type != RMX_OFF) { 1355 fixed20_12 a, b; 1356 a.full = dfixed_const(src_v); 1357 b.full = dfixed_const(dst_v); 1358 amdgpu_crtc->vsc.full = dfixed_div(a, b); 1359 a.full = dfixed_const(src_h); 1360 b.full = dfixed_const(dst_h); 1361 amdgpu_crtc->hsc.full = dfixed_div(a, b); 1362 } else { 1363 amdgpu_crtc->vsc.full = dfixed_const(1); 1364 amdgpu_crtc->hsc.full = dfixed_const(1); 1365 } 1366 return true; 1367 } 1368 1369 /* 1370 * Retrieve current video scanout position of crtc on a given gpu, and 1371 * an optional accurate timestamp of when query happened. 1372 * 1373 * \param dev Device to query. 1374 * \param pipe Crtc to query. 1375 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1376 * For driver internal use only also supports these flags: 1377 * 1378 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1379 * of a fudged earlier start of vblank. 1380 * 1381 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1382 * fudged earlier start of vblank in *vpos and the distance 1383 * to true start of vblank in *hpos. 1384 * 1385 * \param *vpos Location where vertical scanout position should be stored. 1386 * \param *hpos Location where horizontal scanout position should go. 1387 * \param *stime Target location for timestamp taken immediately before 1388 * scanout position query. Can be NULL to skip timestamp. 1389 * \param *etime Target location for timestamp taken immediately after 1390 * scanout position query. Can be NULL to skip timestamp. 1391 * 1392 * Returns vpos as a positive number while in active scanout area. 1393 * Returns vpos as a negative number inside vblank, counting the number 1394 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1395 * until start of active scanout / end of vblank." 1396 * 1397 * \return Flags, or'ed together as follows: 1398 * 1399 * DRM_SCANOUTPOS_VALID = Query successful. 1400 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1401 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1402 * this flag means that returned position may be offset by a constant but 1403 * unknown small number of scanlines wrt. real scanout position. 1404 * 1405 */ 1406 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 1407 unsigned int pipe, unsigned int flags, int *vpos, 1408 int *hpos, ktime_t *stime, ktime_t *etime, 1409 const struct drm_display_mode *mode) 1410 { 1411 u32 vbl = 0, position = 0; 1412 int vbl_start, vbl_end, vtotal, ret = 0; 1413 bool in_vbl = true; 1414 1415 struct amdgpu_device *adev = drm_to_adev(dev); 1416 1417 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1418 1419 /* Get optional system timestamp before query. */ 1420 if (stime) 1421 *stime = ktime_get(); 1422 1423 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 1424 ret |= DRM_SCANOUTPOS_VALID; 1425 1426 /* Get optional system timestamp after query. */ 1427 if (etime) 1428 *etime = ktime_get(); 1429 1430 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1431 1432 /* Decode into vertical and horizontal scanout position. */ 1433 *vpos = position & 0x1fff; 1434 *hpos = (position >> 16) & 0x1fff; 1435 1436 /* Valid vblank area boundaries from gpu retrieved? */ 1437 if (vbl > 0) { 1438 /* Yes: Decode. */ 1439 ret |= DRM_SCANOUTPOS_ACCURATE; 1440 vbl_start = vbl & 0x1fff; 1441 vbl_end = (vbl >> 16) & 0x1fff; 1442 } 1443 else { 1444 /* No: Fake something reasonable which gives at least ok results. */ 1445 vbl_start = mode->crtc_vdisplay; 1446 vbl_end = 0; 1447 } 1448 1449 /* Called from driver internal vblank counter query code? */ 1450 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1451 /* Caller wants distance from real vbl_start in *hpos */ 1452 *hpos = *vpos - vbl_start; 1453 } 1454 1455 /* Fudge vblank to start a few scanlines earlier to handle the 1456 * problem that vblank irqs fire a few scanlines before start 1457 * of vblank. Some driver internal callers need the true vblank 1458 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1459 * 1460 * The cause of the "early" vblank irq is that the irq is triggered 1461 * by the line buffer logic when the line buffer read position enters 1462 * the vblank, whereas our crtc scanout position naturally lags the 1463 * line buffer read position. 1464 */ 1465 if (!(flags & USE_REAL_VBLANKSTART)) 1466 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1467 1468 /* Test scanout position against vblank region. */ 1469 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1470 in_vbl = false; 1471 1472 /* In vblank? */ 1473 if (in_vbl) 1474 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1475 1476 /* Called from driver internal vblank counter query code? */ 1477 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1478 /* Caller wants distance from fudged earlier vbl_start */ 1479 *vpos -= vbl_start; 1480 return ret; 1481 } 1482 1483 /* Check if inside vblank area and apply corrective offsets: 1484 * vpos will then be >=0 in video scanout area, but negative 1485 * within vblank area, counting down the number of lines until 1486 * start of scanout. 1487 */ 1488 1489 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1490 if (in_vbl && (*vpos >= vbl_start)) { 1491 vtotal = mode->crtc_vtotal; 1492 1493 /* With variable refresh rate displays the vpos can exceed 1494 * the vtotal value. Clamp to 0 to return -vbl_end instead 1495 * of guessing the remaining number of lines until scanout. 1496 */ 1497 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1498 } 1499 1500 /* Correct for shifted end of vbl at vbl_end. */ 1501 *vpos = *vpos - vbl_end; 1502 1503 return ret; 1504 } 1505 1506 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1507 { 1508 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1509 return AMDGPU_CRTC_IRQ_NONE; 1510 1511 switch (crtc) { 1512 case 0: 1513 return AMDGPU_CRTC_IRQ_VBLANK1; 1514 case 1: 1515 return AMDGPU_CRTC_IRQ_VBLANK2; 1516 case 2: 1517 return AMDGPU_CRTC_IRQ_VBLANK3; 1518 case 3: 1519 return AMDGPU_CRTC_IRQ_VBLANK4; 1520 case 4: 1521 return AMDGPU_CRTC_IRQ_VBLANK5; 1522 case 5: 1523 return AMDGPU_CRTC_IRQ_VBLANK6; 1524 default: 1525 return AMDGPU_CRTC_IRQ_NONE; 1526 } 1527 } 1528 1529 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1530 bool in_vblank_irq, int *vpos, 1531 int *hpos, ktime_t *stime, ktime_t *etime, 1532 const struct drm_display_mode *mode) 1533 { 1534 struct drm_device *dev = crtc->dev; 1535 unsigned int pipe = crtc->index; 1536 1537 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1538 stime, etime, mode); 1539 } 1540 1541 int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1542 { 1543 struct drm_device *dev = adev_to_drm(adev); 1544 struct drm_crtc *crtc; 1545 struct drm_connector *connector; 1546 struct drm_connector_list_iter iter; 1547 struct drm_modeset_acquire_ctx ctx; 1548 int r, ret; 1549 1550 /* turn off display hw */ 1551 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); 1552 drm_connector_list_iter_begin(dev, &iter); 1553 drm_for_each_connector_iter(connector, &iter) 1554 drm_helper_connector_dpms(connector, 1555 DRM_MODE_DPMS_OFF); 1556 drm_connector_list_iter_end(&iter); 1557 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); 1558 1559 if (ret) 1560 return ret; 1561 1562 /* unpin the front buffers and cursors */ 1563 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1564 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1565 struct drm_framebuffer *fb = crtc->primary->fb; 1566 struct amdgpu_bo *robj; 1567 1568 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1569 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1570 r = amdgpu_bo_reserve(aobj, true); 1571 if (r == 0) { 1572 amdgpu_bo_unpin(aobj); 1573 amdgpu_bo_unreserve(aobj); 1574 } 1575 } 1576 1577 if (fb == NULL || fb->obj[0] == NULL) { 1578 continue; 1579 } 1580 robj = gem_to_amdgpu_bo(fb->obj[0]); 1581 /* don't unpin kernel fb objects */ 1582 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { 1583 r = amdgpu_bo_reserve(robj, true); 1584 if (r == 0) { 1585 amdgpu_bo_unpin(robj); 1586 amdgpu_bo_unreserve(robj); 1587 } 1588 } 1589 } 1590 return 0; 1591 } 1592 1593 int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1594 { 1595 struct drm_device *dev = adev_to_drm(adev); 1596 struct drm_connector *connector; 1597 struct drm_connector_list_iter iter; 1598 struct drm_crtc *crtc; 1599 struct drm_modeset_acquire_ctx ctx; 1600 int r, ret; 1601 1602 /* pin cursors */ 1603 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1604 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1605 1606 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1607 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1608 r = amdgpu_bo_reserve(aobj, true); 1609 if (r == 0) { 1610 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1611 if (r != 0) 1612 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1613 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1614 amdgpu_bo_unreserve(aobj); 1615 } 1616 } 1617 } 1618 1619 drm_helper_resume_force_mode(dev); 1620 1621 /* turn on display hw */ 1622 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); 1623 1624 drm_connector_list_iter_begin(dev, &iter); 1625 drm_for_each_connector_iter(connector, &iter) 1626 drm_helper_connector_dpms(connector, 1627 DRM_MODE_DPMS_ON); 1628 drm_connector_list_iter_end(&iter); 1629 1630 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); 1631 1632 return ret; 1633 } 1634 1635