1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "navi10_ih.h" 75 #include "ih_v6_0.h" 76 #include "ih_v6_1.h" 77 #include "ih_v7_0.h" 78 #include "gfx_v10_0.h" 79 #include "gfx_v11_0.h" 80 #include "gfx_v12_0.h" 81 #include "sdma_v5_0.h" 82 #include "sdma_v5_2.h" 83 #include "sdma_v6_0.h" 84 #include "sdma_v7_0.h" 85 #include "lsdma_v6_0.h" 86 #include "lsdma_v7_0.h" 87 #include "vcn_v2_0.h" 88 #include "jpeg_v2_0.h" 89 #include "vcn_v3_0.h" 90 #include "jpeg_v3_0.h" 91 #include "vcn_v4_0.h" 92 #include "jpeg_v4_0.h" 93 #include "vcn_v4_0_3.h" 94 #include "jpeg_v4_0_3.h" 95 #include "vcn_v4_0_5.h" 96 #include "jpeg_v4_0_5.h" 97 #include "amdgpu_vkms.h" 98 #include "mes_v11_0.h" 99 #include "mes_v12_0.h" 100 #include "smuio_v11_0.h" 101 #include "smuio_v11_0_6.h" 102 #include "smuio_v13_0.h" 103 #include "smuio_v13_0_3.h" 104 #include "smuio_v13_0_6.h" 105 #include "smuio_v14_0_2.h" 106 #include "vcn_v5_0_0.h" 107 #include "jpeg_v5_0_0.h" 108 109 #include "amdgpu_vpe.h" 110 #if defined(CONFIG_DRM_AMD_ISP) 111 #include "amdgpu_isp.h" 112 #endif 113 114 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 115 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 116 117 #define mmIP_DISCOVERY_VERSION 0x16A00 118 #define mmRCC_CONFIG_MEMSIZE 0xde3 119 #define mmMP0_SMN_C2PMSG_33 0x16061 120 #define mmMM_INDEX 0x0 121 #define mmMM_INDEX_HI 0x6 122 #define mmMM_DATA 0x1 123 124 static const char *hw_id_names[HW_ID_MAX] = { 125 [MP1_HWID] = "MP1", 126 [MP2_HWID] = "MP2", 127 [THM_HWID] = "THM", 128 [SMUIO_HWID] = "SMUIO", 129 [FUSE_HWID] = "FUSE", 130 [CLKA_HWID] = "CLKA", 131 [PWR_HWID] = "PWR", 132 [GC_HWID] = "GC", 133 [UVD_HWID] = "UVD", 134 [AUDIO_AZ_HWID] = "AUDIO_AZ", 135 [ACP_HWID] = "ACP", 136 [DCI_HWID] = "DCI", 137 [DMU_HWID] = "DMU", 138 [DCO_HWID] = "DCO", 139 [DIO_HWID] = "DIO", 140 [XDMA_HWID] = "XDMA", 141 [DCEAZ_HWID] = "DCEAZ", 142 [DAZ_HWID] = "DAZ", 143 [SDPMUX_HWID] = "SDPMUX", 144 [NTB_HWID] = "NTB", 145 [IOHC_HWID] = "IOHC", 146 [L2IMU_HWID] = "L2IMU", 147 [VCE_HWID] = "VCE", 148 [MMHUB_HWID] = "MMHUB", 149 [ATHUB_HWID] = "ATHUB", 150 [DBGU_NBIO_HWID] = "DBGU_NBIO", 151 [DFX_HWID] = "DFX", 152 [DBGU0_HWID] = "DBGU0", 153 [DBGU1_HWID] = "DBGU1", 154 [OSSSYS_HWID] = "OSSSYS", 155 [HDP_HWID] = "HDP", 156 [SDMA0_HWID] = "SDMA0", 157 [SDMA1_HWID] = "SDMA1", 158 [SDMA2_HWID] = "SDMA2", 159 [SDMA3_HWID] = "SDMA3", 160 [LSDMA_HWID] = "LSDMA", 161 [ISP_HWID] = "ISP", 162 [DBGU_IO_HWID] = "DBGU_IO", 163 [DF_HWID] = "DF", 164 [CLKB_HWID] = "CLKB", 165 [FCH_HWID] = "FCH", 166 [DFX_DAP_HWID] = "DFX_DAP", 167 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 168 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 169 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 170 [L1IMU3_HWID] = "L1IMU3", 171 [L1IMU4_HWID] = "L1IMU4", 172 [L1IMU5_HWID] = "L1IMU5", 173 [L1IMU6_HWID] = "L1IMU6", 174 [L1IMU7_HWID] = "L1IMU7", 175 [L1IMU8_HWID] = "L1IMU8", 176 [L1IMU9_HWID] = "L1IMU9", 177 [L1IMU10_HWID] = "L1IMU10", 178 [L1IMU11_HWID] = "L1IMU11", 179 [L1IMU12_HWID] = "L1IMU12", 180 [L1IMU13_HWID] = "L1IMU13", 181 [L1IMU14_HWID] = "L1IMU14", 182 [L1IMU15_HWID] = "L1IMU15", 183 [WAFLC_HWID] = "WAFLC", 184 [FCH_USB_PD_HWID] = "FCH_USB_PD", 185 [PCIE_HWID] = "PCIE", 186 [PCS_HWID] = "PCS", 187 [DDCL_HWID] = "DDCL", 188 [SST_HWID] = "SST", 189 [IOAGR_HWID] = "IOAGR", 190 [NBIF_HWID] = "NBIF", 191 [IOAPIC_HWID] = "IOAPIC", 192 [SYSTEMHUB_HWID] = "SYSTEMHUB", 193 [NTBCCP_HWID] = "NTBCCP", 194 [UMC_HWID] = "UMC", 195 [SATA_HWID] = "SATA", 196 [USB_HWID] = "USB", 197 [CCXSEC_HWID] = "CCXSEC", 198 [XGMI_HWID] = "XGMI", 199 [XGBE_HWID] = "XGBE", 200 [MP0_HWID] = "MP0", 201 [VPE_HWID] = "VPE", 202 }; 203 204 static int hw_id_map[MAX_HWIP] = { 205 [GC_HWIP] = GC_HWID, 206 [HDP_HWIP] = HDP_HWID, 207 [SDMA0_HWIP] = SDMA0_HWID, 208 [SDMA1_HWIP] = SDMA1_HWID, 209 [SDMA2_HWIP] = SDMA2_HWID, 210 [SDMA3_HWIP] = SDMA3_HWID, 211 [LSDMA_HWIP] = LSDMA_HWID, 212 [MMHUB_HWIP] = MMHUB_HWID, 213 [ATHUB_HWIP] = ATHUB_HWID, 214 [NBIO_HWIP] = NBIF_HWID, 215 [MP0_HWIP] = MP0_HWID, 216 [MP1_HWIP] = MP1_HWID, 217 [UVD_HWIP] = UVD_HWID, 218 [VCE_HWIP] = VCE_HWID, 219 [DF_HWIP] = DF_HWID, 220 [DCE_HWIP] = DMU_HWID, 221 [OSSSYS_HWIP] = OSSSYS_HWID, 222 [SMUIO_HWIP] = SMUIO_HWID, 223 [PWR_HWIP] = PWR_HWID, 224 [NBIF_HWIP] = NBIF_HWID, 225 [THM_HWIP] = THM_HWID, 226 [CLK_HWIP] = CLKA_HWID, 227 [UMC_HWIP] = UMC_HWID, 228 [XGMI_HWIP] = XGMI_HWID, 229 [DCI_HWIP] = DCI_HWID, 230 [PCIE_HWIP] = PCIE_HWID, 231 [VPE_HWIP] = VPE_HWID, 232 [ISP_HWIP] = ISP_HWID, 233 }; 234 235 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 236 { 237 u64 tmr_offset, tmr_size, pos; 238 void *discv_regn; 239 int ret; 240 241 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 242 if (ret) 243 return ret; 244 245 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 246 247 /* This region is read-only and reserved from system use */ 248 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 249 if (discv_regn) { 250 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 251 memunmap(discv_regn); 252 return 0; 253 } 254 255 return -ENOENT; 256 } 257 258 #define IP_DISCOVERY_V2 2 259 #define IP_DISCOVERY_V4 4 260 261 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 262 uint8_t *binary) 263 { 264 uint64_t vram_size; 265 u32 msg; 266 int i, ret = 0; 267 268 if (!amdgpu_sriov_vf(adev)) { 269 /* It can take up to a second for IFWI init to complete on some dGPUs, 270 * but generally it should be in the 60-100ms range. Normally this starts 271 * as soon as the device gets power so by the time the OS loads this has long 272 * completed. However, when a card is hotplugged via e.g., USB4, we need to 273 * wait for this to complete. Once the C2PMSG is updated, we can 274 * continue. 275 */ 276 277 for (i = 0; i < 1000; i++) { 278 msg = RREG32(mmMP0_SMN_C2PMSG_33); 279 if (msg & 0x80000000) 280 break; 281 msleep(1); 282 } 283 } 284 285 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 286 287 if (vram_size) { 288 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 289 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 290 adev->mman.discovery_tmr_size, false); 291 } else { 292 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 293 } 294 295 return ret; 296 } 297 298 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 299 { 300 const struct firmware *fw; 301 const char *fw_name; 302 int r; 303 304 switch (amdgpu_discovery) { 305 case 2: 306 fw_name = FIRMWARE_IP_DISCOVERY; 307 break; 308 default: 309 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 310 return -EINVAL; 311 } 312 313 r = request_firmware(&fw, fw_name, adev->dev); 314 if (r) { 315 dev_err(adev->dev, "can't load firmware \"%s\"\n", 316 fw_name); 317 return r; 318 } 319 320 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 321 release_firmware(fw); 322 323 return 0; 324 } 325 326 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 327 { 328 uint16_t checksum = 0; 329 int i; 330 331 for (i = 0; i < size; i++) 332 checksum += data[i]; 333 334 return checksum; 335 } 336 337 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 338 uint16_t expected) 339 { 340 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 341 } 342 343 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 344 { 345 struct binary_header *bhdr; 346 bhdr = (struct binary_header *)binary; 347 348 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 349 } 350 351 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 352 { 353 /* 354 * So far, apply this quirk only on those Navy Flounder boards which 355 * have a bad harvest table of VCN config. 356 */ 357 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 358 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 359 switch (adev->pdev->revision) { 360 case 0xC1: 361 case 0xC2: 362 case 0xC3: 363 case 0xC5: 364 case 0xC7: 365 case 0xCF: 366 case 0xDF: 367 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 368 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 369 break; 370 default: 371 break; 372 } 373 } 374 } 375 376 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 377 struct binary_header *bhdr) 378 { 379 struct table_info *info; 380 uint16_t checksum; 381 uint16_t offset; 382 383 info = &bhdr->table_list[NPS_INFO]; 384 offset = le16_to_cpu(info->offset); 385 checksum = le16_to_cpu(info->checksum); 386 387 struct nps_info_header *nhdr = 388 (struct nps_info_header *)(adev->mman.discovery_bin + offset); 389 390 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 391 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 392 return -EINVAL; 393 } 394 395 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 396 le32_to_cpu(nhdr->size_bytes), 397 checksum)) { 398 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 399 return -EINVAL; 400 } 401 402 return 0; 403 } 404 405 static int amdgpu_discovery_init(struct amdgpu_device *adev) 406 { 407 struct table_info *info; 408 struct binary_header *bhdr; 409 uint16_t offset; 410 uint16_t size; 411 uint16_t checksum; 412 int r; 413 414 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 415 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 416 if (!adev->mman.discovery_bin) 417 return -ENOMEM; 418 419 /* Read from file if it is the preferred option */ 420 if (amdgpu_discovery == 2) { 421 dev_info(adev->dev, "use ip discovery information from file"); 422 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 423 424 if (r) { 425 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 426 r = -EINVAL; 427 goto out; 428 } 429 430 } else { 431 r = amdgpu_discovery_read_binary_from_mem( 432 adev, adev->mman.discovery_bin); 433 if (r) 434 goto out; 435 } 436 437 /* check the ip discovery binary signature */ 438 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 439 dev_err(adev->dev, 440 "get invalid ip discovery binary signature\n"); 441 r = -EINVAL; 442 goto out; 443 } 444 445 bhdr = (struct binary_header *)adev->mman.discovery_bin; 446 447 offset = offsetof(struct binary_header, binary_checksum) + 448 sizeof(bhdr->binary_checksum); 449 size = le16_to_cpu(bhdr->binary_size) - offset; 450 checksum = le16_to_cpu(bhdr->binary_checksum); 451 452 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 453 size, checksum)) { 454 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 455 r = -EINVAL; 456 goto out; 457 } 458 459 info = &bhdr->table_list[IP_DISCOVERY]; 460 offset = le16_to_cpu(info->offset); 461 checksum = le16_to_cpu(info->checksum); 462 463 if (offset) { 464 struct ip_discovery_header *ihdr = 465 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 466 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 467 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 468 r = -EINVAL; 469 goto out; 470 } 471 472 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 473 le16_to_cpu(ihdr->size), checksum)) { 474 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 475 r = -EINVAL; 476 goto out; 477 } 478 } 479 480 info = &bhdr->table_list[GC]; 481 offset = le16_to_cpu(info->offset); 482 checksum = le16_to_cpu(info->checksum); 483 484 if (offset) { 485 struct gpu_info_header *ghdr = 486 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 487 488 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 489 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 490 r = -EINVAL; 491 goto out; 492 } 493 494 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 495 le32_to_cpu(ghdr->size), checksum)) { 496 dev_err(adev->dev, "invalid gc data table checksum\n"); 497 r = -EINVAL; 498 goto out; 499 } 500 } 501 502 info = &bhdr->table_list[HARVEST_INFO]; 503 offset = le16_to_cpu(info->offset); 504 checksum = le16_to_cpu(info->checksum); 505 506 if (offset) { 507 struct harvest_info_header *hhdr = 508 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 509 510 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 511 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 512 r = -EINVAL; 513 goto out; 514 } 515 516 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 517 sizeof(struct harvest_table), checksum)) { 518 dev_err(adev->dev, "invalid harvest data table checksum\n"); 519 r = -EINVAL; 520 goto out; 521 } 522 } 523 524 info = &bhdr->table_list[VCN_INFO]; 525 offset = le16_to_cpu(info->offset); 526 checksum = le16_to_cpu(info->checksum); 527 528 if (offset) { 529 struct vcn_info_header *vhdr = 530 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 531 532 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 533 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 534 r = -EINVAL; 535 goto out; 536 } 537 538 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 539 le32_to_cpu(vhdr->size_bytes), checksum)) { 540 dev_err(adev->dev, "invalid vcn data table checksum\n"); 541 r = -EINVAL; 542 goto out; 543 } 544 } 545 546 info = &bhdr->table_list[MALL_INFO]; 547 offset = le16_to_cpu(info->offset); 548 checksum = le16_to_cpu(info->checksum); 549 550 if (0 && offset) { 551 struct mall_info_header *mhdr = 552 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 553 554 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 555 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 556 r = -EINVAL; 557 goto out; 558 } 559 560 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 561 le32_to_cpu(mhdr->size_bytes), checksum)) { 562 dev_err(adev->dev, "invalid mall data table checksum\n"); 563 r = -EINVAL; 564 goto out; 565 } 566 } 567 568 return 0; 569 570 out: 571 kfree(adev->mman.discovery_bin); 572 adev->mman.discovery_bin = NULL; 573 if ((amdgpu_discovery != 2) && 574 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 575 amdgpu_ras_query_boot_status(adev, 4); 576 return r; 577 } 578 579 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 580 581 void amdgpu_discovery_fini(struct amdgpu_device *adev) 582 { 583 amdgpu_discovery_sysfs_fini(adev); 584 kfree(adev->mman.discovery_bin); 585 adev->mman.discovery_bin = NULL; 586 } 587 588 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 589 { 590 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 591 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 592 ip->instance_number); 593 return -EINVAL; 594 } 595 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 596 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 597 le16_to_cpu(ip->hw_id)); 598 return -EINVAL; 599 } 600 601 return 0; 602 } 603 604 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 605 uint32_t *vcn_harvest_count) 606 { 607 struct binary_header *bhdr; 608 struct ip_discovery_header *ihdr; 609 struct die_header *dhdr; 610 struct ip_v4 *ip; 611 uint16_t die_offset, ip_offset, num_dies, num_ips; 612 int i, j; 613 614 bhdr = (struct binary_header *)adev->mman.discovery_bin; 615 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 616 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 617 num_dies = le16_to_cpu(ihdr->num_dies); 618 619 /* scan harvest bit of all IP data structures */ 620 for (i = 0; i < num_dies; i++) { 621 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 622 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 623 num_ips = le16_to_cpu(dhdr->num_ips); 624 ip_offset = die_offset + sizeof(*dhdr); 625 626 for (j = 0; j < num_ips; j++) { 627 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 628 629 if (amdgpu_discovery_validate_ip(ip)) 630 goto next_ip; 631 632 if (le16_to_cpu(ip->variant) == 1) { 633 switch (le16_to_cpu(ip->hw_id)) { 634 case VCN_HWID: 635 (*vcn_harvest_count)++; 636 if (ip->instance_number == 0) { 637 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 638 adev->vcn.inst_mask &= 639 ~AMDGPU_VCN_HARVEST_VCN0; 640 adev->jpeg.inst_mask &= 641 ~AMDGPU_VCN_HARVEST_VCN0; 642 } else { 643 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 644 adev->vcn.inst_mask &= 645 ~AMDGPU_VCN_HARVEST_VCN1; 646 adev->jpeg.inst_mask &= 647 ~AMDGPU_VCN_HARVEST_VCN1; 648 } 649 break; 650 case DMU_HWID: 651 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 652 break; 653 default: 654 break; 655 } 656 } 657 next_ip: 658 if (ihdr->base_addr_64_bit) 659 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 660 else 661 ip_offset += struct_size(ip, base_address, ip->num_base_address); 662 } 663 } 664 } 665 666 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 667 uint32_t *vcn_harvest_count, 668 uint32_t *umc_harvest_count) 669 { 670 struct binary_header *bhdr; 671 struct harvest_table *harvest_info; 672 u16 offset; 673 int i; 674 uint32_t umc_harvest_config = 0; 675 676 bhdr = (struct binary_header *)adev->mman.discovery_bin; 677 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 678 679 if (!offset) { 680 dev_err(adev->dev, "invalid harvest table offset\n"); 681 return; 682 } 683 684 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 685 686 for (i = 0; i < 32; i++) { 687 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 688 break; 689 690 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 691 case VCN_HWID: 692 (*vcn_harvest_count)++; 693 adev->vcn.harvest_config |= 694 (1 << harvest_info->list[i].number_instance); 695 adev->jpeg.harvest_config |= 696 (1 << harvest_info->list[i].number_instance); 697 698 adev->vcn.inst_mask &= 699 ~(1U << harvest_info->list[i].number_instance); 700 adev->jpeg.inst_mask &= 701 ~(1U << harvest_info->list[i].number_instance); 702 break; 703 case DMU_HWID: 704 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 705 break; 706 case UMC_HWID: 707 umc_harvest_config |= 708 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 709 (*umc_harvest_count)++; 710 break; 711 case GC_HWID: 712 adev->gfx.xcc_mask &= 713 ~(1U << harvest_info->list[i].number_instance); 714 break; 715 case SDMA0_HWID: 716 adev->sdma.sdma_mask &= 717 ~(1U << harvest_info->list[i].number_instance); 718 break; 719 #if defined(CONFIG_DRM_AMD_ISP) 720 case ISP_HWID: 721 adev->isp.harvest_config |= 722 ~(1U << harvest_info->list[i].number_instance); 723 break; 724 #endif 725 default: 726 break; 727 } 728 } 729 730 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 731 ~umc_harvest_config; 732 } 733 734 /* ================================================== */ 735 736 struct ip_hw_instance { 737 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 738 739 int hw_id; 740 u8 num_instance; 741 u8 major, minor, revision; 742 u8 harvest; 743 744 int num_base_addresses; 745 u32 base_addr[] __counted_by(num_base_addresses); 746 }; 747 748 struct ip_hw_id { 749 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 750 int hw_id; 751 }; 752 753 struct ip_die_entry { 754 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 755 u16 num_ips; 756 }; 757 758 /* -------------------------------------------------- */ 759 760 struct ip_hw_instance_attr { 761 struct attribute attr; 762 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 763 }; 764 765 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 766 { 767 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 768 } 769 770 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 771 { 772 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 773 } 774 775 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 776 { 777 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 778 } 779 780 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 781 { 782 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 783 } 784 785 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 786 { 787 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 788 } 789 790 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 791 { 792 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 793 } 794 795 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 796 { 797 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 798 } 799 800 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 801 { 802 ssize_t res, at; 803 int ii; 804 805 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 806 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 807 */ 808 if (at + 12 > PAGE_SIZE) 809 break; 810 res = sysfs_emit_at(buf, at, "0x%08X\n", 811 ip_hw_instance->base_addr[ii]); 812 if (res <= 0) 813 break; 814 at += res; 815 } 816 817 return res < 0 ? res : at; 818 } 819 820 static struct ip_hw_instance_attr ip_hw_attr[] = { 821 __ATTR_RO(hw_id), 822 __ATTR_RO(num_instance), 823 __ATTR_RO(major), 824 __ATTR_RO(minor), 825 __ATTR_RO(revision), 826 __ATTR_RO(harvest), 827 __ATTR_RO(num_base_addresses), 828 __ATTR_RO(base_addr), 829 }; 830 831 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 832 ATTRIBUTE_GROUPS(ip_hw_instance); 833 834 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 835 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 836 837 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 838 struct attribute *attr, 839 char *buf) 840 { 841 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 842 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 843 844 if (!ip_hw_attr->show) 845 return -EIO; 846 847 return ip_hw_attr->show(ip_hw_instance, buf); 848 } 849 850 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 851 .show = ip_hw_instance_attr_show, 852 }; 853 854 static void ip_hw_instance_release(struct kobject *kobj) 855 { 856 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 857 858 kfree(ip_hw_instance); 859 } 860 861 static const struct kobj_type ip_hw_instance_ktype = { 862 .release = ip_hw_instance_release, 863 .sysfs_ops = &ip_hw_instance_sysfs_ops, 864 .default_groups = ip_hw_instance_groups, 865 }; 866 867 /* -------------------------------------------------- */ 868 869 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 870 871 static void ip_hw_id_release(struct kobject *kobj) 872 { 873 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 874 875 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 876 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 877 kfree(ip_hw_id); 878 } 879 880 static const struct kobj_type ip_hw_id_ktype = { 881 .release = ip_hw_id_release, 882 .sysfs_ops = &kobj_sysfs_ops, 883 }; 884 885 /* -------------------------------------------------- */ 886 887 static void die_kobj_release(struct kobject *kobj); 888 static void ip_disc_release(struct kobject *kobj); 889 890 struct ip_die_entry_attribute { 891 struct attribute attr; 892 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 893 }; 894 895 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 896 897 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 898 { 899 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 900 } 901 902 /* If there are more ip_die_entry attrs, other than the number of IPs, 903 * we can make this intro an array of attrs, and then initialize 904 * ip_die_entry_attrs in a loop. 905 */ 906 static struct ip_die_entry_attribute num_ips_attr = 907 __ATTR_RO(num_ips); 908 909 static struct attribute *ip_die_entry_attrs[] = { 910 &num_ips_attr.attr, 911 NULL, 912 }; 913 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 914 915 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 916 917 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 918 struct attribute *attr, 919 char *buf) 920 { 921 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 922 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 923 924 if (!ip_die_entry_attr->show) 925 return -EIO; 926 927 return ip_die_entry_attr->show(ip_die_entry, buf); 928 } 929 930 static void ip_die_entry_release(struct kobject *kobj) 931 { 932 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 933 934 if (!list_empty(&ip_die_entry->ip_kset.list)) 935 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 936 kfree(ip_die_entry); 937 } 938 939 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 940 .show = ip_die_entry_attr_show, 941 }; 942 943 static const struct kobj_type ip_die_entry_ktype = { 944 .release = ip_die_entry_release, 945 .sysfs_ops = &ip_die_entry_sysfs_ops, 946 .default_groups = ip_die_entry_groups, 947 }; 948 949 static const struct kobj_type die_kobj_ktype = { 950 .release = die_kobj_release, 951 .sysfs_ops = &kobj_sysfs_ops, 952 }; 953 954 static const struct kobj_type ip_discovery_ktype = { 955 .release = ip_disc_release, 956 .sysfs_ops = &kobj_sysfs_ops, 957 }; 958 959 struct ip_discovery_top { 960 struct kobject kobj; /* ip_discovery/ */ 961 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 962 struct amdgpu_device *adev; 963 }; 964 965 static void die_kobj_release(struct kobject *kobj) 966 { 967 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 968 struct ip_discovery_top, 969 die_kset); 970 if (!list_empty(&ip_top->die_kset.list)) 971 DRM_ERROR("ip_top->die_kset is not empty"); 972 } 973 974 static void ip_disc_release(struct kobject *kobj) 975 { 976 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 977 kobj); 978 struct amdgpu_device *adev = ip_top->adev; 979 980 adev->ip_top = NULL; 981 kfree(ip_top); 982 } 983 984 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 985 uint16_t hw_id, uint8_t inst) 986 { 987 uint8_t harvest = 0; 988 989 /* Until a uniform way is figured, get mask based on hwid */ 990 switch (hw_id) { 991 case VCN_HWID: 992 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 993 break; 994 case DMU_HWID: 995 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 996 harvest = 0x1; 997 break; 998 case UMC_HWID: 999 /* TODO: It needs another parsing; for now, ignore.*/ 1000 break; 1001 case GC_HWID: 1002 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1003 break; 1004 case SDMA0_HWID: 1005 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1006 break; 1007 default: 1008 break; 1009 } 1010 1011 return harvest; 1012 } 1013 1014 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1015 struct ip_die_entry *ip_die_entry, 1016 const size_t _ip_offset, const int num_ips, 1017 bool reg_base_64) 1018 { 1019 int ii, jj, kk, res; 1020 1021 DRM_DEBUG("num_ips:%d", num_ips); 1022 1023 /* Find all IPs of a given HW ID, and add their instance to 1024 * #die/#hw_id/#instance/<attributes> 1025 */ 1026 for (ii = 0; ii < HW_ID_MAX; ii++) { 1027 struct ip_hw_id *ip_hw_id = NULL; 1028 size_t ip_offset = _ip_offset; 1029 1030 for (jj = 0; jj < num_ips; jj++) { 1031 struct ip_v4 *ip; 1032 struct ip_hw_instance *ip_hw_instance; 1033 1034 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1035 if (amdgpu_discovery_validate_ip(ip) || 1036 le16_to_cpu(ip->hw_id) != ii) 1037 goto next_ip; 1038 1039 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1040 1041 /* We have a hw_id match; register the hw 1042 * block if not yet registered. 1043 */ 1044 if (!ip_hw_id) { 1045 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1046 if (!ip_hw_id) 1047 return -ENOMEM; 1048 ip_hw_id->hw_id = ii; 1049 1050 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1051 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1052 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1053 res = kset_register(&ip_hw_id->hw_id_kset); 1054 if (res) { 1055 DRM_ERROR("Couldn't register ip_hw_id kset"); 1056 kfree(ip_hw_id); 1057 return res; 1058 } 1059 if (hw_id_names[ii]) { 1060 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1061 &ip_hw_id->hw_id_kset.kobj, 1062 hw_id_names[ii]); 1063 if (res) { 1064 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1065 hw_id_names[ii], 1066 kobject_name(&ip_die_entry->ip_kset.kobj)); 1067 } 1068 } 1069 } 1070 1071 /* Now register its instance. 1072 */ 1073 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1074 base_addr, 1075 ip->num_base_address), 1076 GFP_KERNEL); 1077 if (!ip_hw_instance) { 1078 DRM_ERROR("no memory for ip_hw_instance"); 1079 return -ENOMEM; 1080 } 1081 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1082 ip_hw_instance->num_instance = ip->instance_number; 1083 ip_hw_instance->major = ip->major; 1084 ip_hw_instance->minor = ip->minor; 1085 ip_hw_instance->revision = ip->revision; 1086 ip_hw_instance->harvest = 1087 amdgpu_discovery_get_harvest_info( 1088 adev, ip_hw_instance->hw_id, 1089 ip_hw_instance->num_instance); 1090 ip_hw_instance->num_base_addresses = ip->num_base_address; 1091 1092 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1093 if (reg_base_64) 1094 ip_hw_instance->base_addr[kk] = 1095 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1096 else 1097 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1098 } 1099 1100 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1101 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1102 res = kobject_add(&ip_hw_instance->kobj, NULL, 1103 "%d", ip_hw_instance->num_instance); 1104 next_ip: 1105 if (reg_base_64) 1106 ip_offset += struct_size(ip, base_address_64, 1107 ip->num_base_address); 1108 else 1109 ip_offset += struct_size(ip, base_address, 1110 ip->num_base_address); 1111 } 1112 } 1113 1114 return 0; 1115 } 1116 1117 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1118 { 1119 struct binary_header *bhdr; 1120 struct ip_discovery_header *ihdr; 1121 struct die_header *dhdr; 1122 struct kset *die_kset = &adev->ip_top->die_kset; 1123 u16 num_dies, die_offset, num_ips; 1124 size_t ip_offset; 1125 int ii, res; 1126 1127 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1128 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1129 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1130 num_dies = le16_to_cpu(ihdr->num_dies); 1131 1132 DRM_DEBUG("number of dies: %d\n", num_dies); 1133 1134 for (ii = 0; ii < num_dies; ii++) { 1135 struct ip_die_entry *ip_die_entry; 1136 1137 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1138 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1139 num_ips = le16_to_cpu(dhdr->num_ips); 1140 ip_offset = die_offset + sizeof(*dhdr); 1141 1142 /* Add the die to the kset. 1143 * 1144 * dhdr->die_id == ii, which was checked in 1145 * amdgpu_discovery_reg_base_init(). 1146 */ 1147 1148 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1149 if (!ip_die_entry) 1150 return -ENOMEM; 1151 1152 ip_die_entry->num_ips = num_ips; 1153 1154 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1155 ip_die_entry->ip_kset.kobj.kset = die_kset; 1156 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1157 res = kset_register(&ip_die_entry->ip_kset); 1158 if (res) { 1159 DRM_ERROR("Couldn't register ip_die_entry kset"); 1160 kfree(ip_die_entry); 1161 return res; 1162 } 1163 1164 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1171 { 1172 struct kset *die_kset; 1173 int res, ii; 1174 1175 if (!adev->mman.discovery_bin) 1176 return -EINVAL; 1177 1178 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1179 if (!adev->ip_top) 1180 return -ENOMEM; 1181 1182 adev->ip_top->adev = adev; 1183 1184 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1185 &adev->dev->kobj, "ip_discovery"); 1186 if (res) { 1187 DRM_ERROR("Couldn't init and add ip_discovery/"); 1188 goto Err; 1189 } 1190 1191 die_kset = &adev->ip_top->die_kset; 1192 kobject_set_name(&die_kset->kobj, "%s", "die"); 1193 die_kset->kobj.parent = &adev->ip_top->kobj; 1194 die_kset->kobj.ktype = &die_kobj_ktype; 1195 res = kset_register(&adev->ip_top->die_kset); 1196 if (res) { 1197 DRM_ERROR("Couldn't register die_kset"); 1198 goto Err; 1199 } 1200 1201 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1202 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1203 ip_hw_instance_attrs[ii] = NULL; 1204 1205 res = amdgpu_discovery_sysfs_recurse(adev); 1206 1207 return res; 1208 Err: 1209 kobject_put(&adev->ip_top->kobj); 1210 return res; 1211 } 1212 1213 /* -------------------------------------------------- */ 1214 1215 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1216 1217 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1218 { 1219 struct list_head *el, *tmp; 1220 struct kset *hw_id_kset; 1221 1222 hw_id_kset = &ip_hw_id->hw_id_kset; 1223 spin_lock(&hw_id_kset->list_lock); 1224 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1225 list_del_init(el); 1226 spin_unlock(&hw_id_kset->list_lock); 1227 /* kobject is embedded in ip_hw_instance */ 1228 kobject_put(list_to_kobj(el)); 1229 spin_lock(&hw_id_kset->list_lock); 1230 } 1231 spin_unlock(&hw_id_kset->list_lock); 1232 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1233 } 1234 1235 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1236 { 1237 struct list_head *el, *tmp; 1238 struct kset *ip_kset; 1239 1240 ip_kset = &ip_die_entry->ip_kset; 1241 spin_lock(&ip_kset->list_lock); 1242 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1243 list_del_init(el); 1244 spin_unlock(&ip_kset->list_lock); 1245 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1246 spin_lock(&ip_kset->list_lock); 1247 } 1248 spin_unlock(&ip_kset->list_lock); 1249 kobject_put(&ip_die_entry->ip_kset.kobj); 1250 } 1251 1252 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1253 { 1254 struct list_head *el, *tmp; 1255 struct kset *die_kset; 1256 1257 die_kset = &adev->ip_top->die_kset; 1258 spin_lock(&die_kset->list_lock); 1259 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1260 list_del_init(el); 1261 spin_unlock(&die_kset->list_lock); 1262 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1263 spin_lock(&die_kset->list_lock); 1264 } 1265 spin_unlock(&die_kset->list_lock); 1266 kobject_put(&adev->ip_top->die_kset.kobj); 1267 kobject_put(&adev->ip_top->kobj); 1268 } 1269 1270 /* ================================================== */ 1271 1272 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1273 { 1274 uint8_t num_base_address, subrev, variant; 1275 struct binary_header *bhdr; 1276 struct ip_discovery_header *ihdr; 1277 struct die_header *dhdr; 1278 struct ip_v4 *ip; 1279 uint16_t die_offset; 1280 uint16_t ip_offset; 1281 uint16_t num_dies; 1282 uint16_t num_ips; 1283 int hw_ip; 1284 int i, j, k; 1285 int r; 1286 1287 r = amdgpu_discovery_init(adev); 1288 if (r) { 1289 DRM_ERROR("amdgpu_discovery_init failed\n"); 1290 return r; 1291 } 1292 1293 adev->gfx.xcc_mask = 0; 1294 adev->sdma.sdma_mask = 0; 1295 adev->vcn.inst_mask = 0; 1296 adev->jpeg.inst_mask = 0; 1297 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1298 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1299 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1300 num_dies = le16_to_cpu(ihdr->num_dies); 1301 1302 DRM_DEBUG("number of dies: %d\n", num_dies); 1303 1304 for (i = 0; i < num_dies; i++) { 1305 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1306 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1307 num_ips = le16_to_cpu(dhdr->num_ips); 1308 ip_offset = die_offset + sizeof(*dhdr); 1309 1310 if (le16_to_cpu(dhdr->die_id) != i) { 1311 DRM_ERROR("invalid die id %d, expected %d\n", 1312 le16_to_cpu(dhdr->die_id), i); 1313 return -EINVAL; 1314 } 1315 1316 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1317 le16_to_cpu(dhdr->die_id), num_ips); 1318 1319 for (j = 0; j < num_ips; j++) { 1320 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1321 1322 if (amdgpu_discovery_validate_ip(ip)) 1323 goto next_ip; 1324 1325 num_base_address = ip->num_base_address; 1326 1327 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1328 hw_id_names[le16_to_cpu(ip->hw_id)], 1329 le16_to_cpu(ip->hw_id), 1330 ip->instance_number, 1331 ip->major, ip->minor, 1332 ip->revision); 1333 1334 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1335 /* Bit [5:0]: original revision value 1336 * Bit [7:6]: en/decode capability: 1337 * 0b00 : VCN function normally 1338 * 0b10 : encode is disabled 1339 * 0b01 : decode is disabled 1340 */ 1341 if (adev->vcn.num_vcn_inst < 1342 AMDGPU_MAX_VCN_INSTANCES) { 1343 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1344 ip->revision & 0xc0; 1345 adev->vcn.num_vcn_inst++; 1346 adev->vcn.inst_mask |= 1347 (1U << ip->instance_number); 1348 adev->jpeg.inst_mask |= 1349 (1U << ip->instance_number); 1350 } else { 1351 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1352 adev->vcn.num_vcn_inst + 1, 1353 AMDGPU_MAX_VCN_INSTANCES); 1354 } 1355 ip->revision &= ~0xc0; 1356 } 1357 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1358 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1359 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1360 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1361 if (adev->sdma.num_instances < 1362 AMDGPU_MAX_SDMA_INSTANCES) { 1363 adev->sdma.num_instances++; 1364 adev->sdma.sdma_mask |= 1365 (1U << ip->instance_number); 1366 } else { 1367 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1368 adev->sdma.num_instances + 1, 1369 AMDGPU_MAX_SDMA_INSTANCES); 1370 } 1371 } 1372 1373 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1374 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1375 adev->vpe.num_instances++; 1376 else 1377 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1378 adev->vpe.num_instances + 1, 1379 AMDGPU_MAX_VPE_INSTANCES); 1380 } 1381 1382 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1383 adev->gmc.num_umc++; 1384 adev->umc.node_inst_num++; 1385 } 1386 1387 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1388 adev->gfx.xcc_mask |= 1389 (1U << ip->instance_number); 1390 1391 for (k = 0; k < num_base_address; k++) { 1392 /* 1393 * convert the endianness of base addresses in place, 1394 * so that we don't need to convert them when accessing adev->reg_offset. 1395 */ 1396 if (ihdr->base_addr_64_bit) 1397 /* Truncate the 64bit base address from ip discovery 1398 * and only store lower 32bit ip base in reg_offset[]. 1399 * Bits > 32 follows ASIC specific format, thus just 1400 * discard them and handle it within specific ASIC. 1401 * By this way reg_offset[] and related helpers can 1402 * stay unchanged. 1403 * The base address is in dwords, thus clear the 1404 * highest 2 bits to store. 1405 */ 1406 ip->base_address[k] = 1407 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1408 else 1409 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1410 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1411 } 1412 1413 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1414 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1415 hw_id_map[hw_ip] != 0) { 1416 DRM_DEBUG("set register base offset for %s\n", 1417 hw_id_names[le16_to_cpu(ip->hw_id)]); 1418 adev->reg_offset[hw_ip][ip->instance_number] = 1419 ip->base_address; 1420 /* Instance support is somewhat inconsistent. 1421 * SDMA is a good example. Sienna cichlid has 4 total 1422 * SDMA instances, each enumerated separately (HWIDs 1423 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1424 * but they are enumerated as multiple instances of the 1425 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1426 * example. On most chips there are multiple instances 1427 * with the same HWID. 1428 */ 1429 1430 if (ihdr->version < 3) { 1431 subrev = 0; 1432 variant = 0; 1433 } else { 1434 subrev = ip->sub_revision; 1435 variant = ip->variant; 1436 } 1437 1438 adev->ip_versions[hw_ip] 1439 [ip->instance_number] = 1440 IP_VERSION_FULL(ip->major, 1441 ip->minor, 1442 ip->revision, 1443 variant, 1444 subrev); 1445 } 1446 } 1447 1448 next_ip: 1449 if (ihdr->base_addr_64_bit) 1450 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1451 else 1452 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1453 } 1454 } 1455 1456 return 0; 1457 } 1458 1459 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1460 { 1461 int vcn_harvest_count = 0; 1462 int umc_harvest_count = 0; 1463 1464 /* 1465 * Harvest table does not fit Navi1x and legacy GPUs, 1466 * so read harvest bit per IP data structure to set 1467 * harvest configuration. 1468 */ 1469 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1470 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1471 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) { 1472 if ((adev->pdev->device == 0x731E && 1473 (adev->pdev->revision == 0xC6 || 1474 adev->pdev->revision == 0xC7)) || 1475 (adev->pdev->device == 0x7340 && 1476 adev->pdev->revision == 0xC9) || 1477 (adev->pdev->device == 0x7360 && 1478 adev->pdev->revision == 0xC7)) 1479 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1480 &vcn_harvest_count); 1481 } else { 1482 amdgpu_discovery_read_from_harvest_table(adev, 1483 &vcn_harvest_count, 1484 &umc_harvest_count); 1485 } 1486 1487 amdgpu_discovery_harvest_config_quirk(adev); 1488 1489 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1490 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1491 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1492 } 1493 1494 if (umc_harvest_count < adev->gmc.num_umc) { 1495 adev->gmc.num_umc -= umc_harvest_count; 1496 } 1497 } 1498 1499 union gc_info { 1500 struct gc_info_v1_0 v1; 1501 struct gc_info_v1_1 v1_1; 1502 struct gc_info_v1_2 v1_2; 1503 struct gc_info_v1_3 v1_3; 1504 struct gc_info_v2_0 v2; 1505 struct gc_info_v2_1 v2_1; 1506 }; 1507 1508 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1509 { 1510 struct binary_header *bhdr; 1511 union gc_info *gc_info; 1512 u16 offset; 1513 1514 if (!adev->mman.discovery_bin) { 1515 DRM_ERROR("ip discovery uninitialized\n"); 1516 return -EINVAL; 1517 } 1518 1519 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1520 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1521 1522 if (!offset) 1523 return 0; 1524 1525 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1526 1527 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1528 case 1: 1529 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1530 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1531 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1532 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1533 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1534 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1535 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1536 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1537 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1538 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1539 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1540 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1541 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1542 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1543 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1544 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1545 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1546 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1547 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1548 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1549 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1550 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1551 } 1552 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1553 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1554 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1555 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1556 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1557 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1558 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1559 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1560 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1561 } 1562 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1563 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1564 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1565 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1566 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1567 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1568 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1569 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1570 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1571 } 1572 break; 1573 case 2: 1574 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1575 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1576 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1577 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1578 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1579 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1580 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1581 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1582 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1583 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1584 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1585 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1586 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1587 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1588 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1589 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1590 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1591 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1592 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1593 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1594 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1595 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1596 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1597 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1598 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1599 } 1600 break; 1601 default: 1602 dev_err(adev->dev, 1603 "Unhandled GC info table %d.%d\n", 1604 le16_to_cpu(gc_info->v1.header.version_major), 1605 le16_to_cpu(gc_info->v1.header.version_minor)); 1606 return -EINVAL; 1607 } 1608 return 0; 1609 } 1610 1611 union mall_info { 1612 struct mall_info_v1_0 v1; 1613 struct mall_info_v2_0 v2; 1614 }; 1615 1616 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1617 { 1618 struct binary_header *bhdr; 1619 union mall_info *mall_info; 1620 u32 u, mall_size_per_umc, m_s_present, half_use; 1621 u64 mall_size; 1622 u16 offset; 1623 1624 if (!adev->mman.discovery_bin) { 1625 DRM_ERROR("ip discovery uninitialized\n"); 1626 return -EINVAL; 1627 } 1628 1629 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1630 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1631 1632 if (!offset) 1633 return 0; 1634 1635 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1636 1637 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1638 case 1: 1639 mall_size = 0; 1640 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1641 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1642 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1643 for (u = 0; u < adev->gmc.num_umc; u++) { 1644 if (m_s_present & (1 << u)) 1645 mall_size += mall_size_per_umc * 2; 1646 else if (half_use & (1 << u)) 1647 mall_size += mall_size_per_umc / 2; 1648 else 1649 mall_size += mall_size_per_umc; 1650 } 1651 adev->gmc.mall_size = mall_size; 1652 adev->gmc.m_half_use = half_use; 1653 break; 1654 case 2: 1655 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1656 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1657 break; 1658 default: 1659 dev_err(adev->dev, 1660 "Unhandled MALL info table %d.%d\n", 1661 le16_to_cpu(mall_info->v1.header.version_major), 1662 le16_to_cpu(mall_info->v1.header.version_minor)); 1663 return -EINVAL; 1664 } 1665 return 0; 1666 } 1667 1668 union vcn_info { 1669 struct vcn_info_v1_0 v1; 1670 }; 1671 1672 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1673 { 1674 struct binary_header *bhdr; 1675 union vcn_info *vcn_info; 1676 u16 offset; 1677 int v; 1678 1679 if (!adev->mman.discovery_bin) { 1680 DRM_ERROR("ip discovery uninitialized\n"); 1681 return -EINVAL; 1682 } 1683 1684 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1685 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1686 * but that may change in the future with new GPUs so keep this 1687 * check for defensive purposes. 1688 */ 1689 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1690 dev_err(adev->dev, "invalid vcn instances\n"); 1691 return -EINVAL; 1692 } 1693 1694 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1695 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1696 1697 if (!offset) 1698 return 0; 1699 1700 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1701 1702 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1703 case 1: 1704 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1705 * so this won't overflow. 1706 */ 1707 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1708 adev->vcn.inst[v].vcn_codec_disable_mask = 1709 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1710 } 1711 break; 1712 default: 1713 dev_err(adev->dev, 1714 "Unhandled VCN info table %d.%d\n", 1715 le16_to_cpu(vcn_info->v1.header.version_major), 1716 le16_to_cpu(vcn_info->v1.header.version_minor)); 1717 return -EINVAL; 1718 } 1719 return 0; 1720 } 1721 1722 union nps_info { 1723 struct nps_info_v1_0 v1; 1724 }; 1725 1726 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1727 union nps_info *nps_data) 1728 { 1729 uint64_t vram_size, pos, offset; 1730 struct nps_info_header *nhdr; 1731 struct binary_header bhdr; 1732 uint16_t checksum; 1733 1734 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1735 pos = vram_size - DISCOVERY_TMR_OFFSET; 1736 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1737 1738 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1739 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1740 1741 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1742 sizeof(*nps_data), false); 1743 1744 nhdr = (struct nps_info_header *)(nps_data); 1745 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1746 le32_to_cpu(nhdr->size_bytes), 1747 checksum)) { 1748 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1749 return -EINVAL; 1750 } 1751 1752 return 0; 1753 } 1754 1755 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1756 uint32_t *nps_type, 1757 struct amdgpu_gmc_memrange **ranges, 1758 int *range_cnt, bool refresh) 1759 { 1760 struct amdgpu_gmc_memrange *mem_ranges; 1761 struct binary_header *bhdr; 1762 union nps_info *nps_info; 1763 union nps_info nps_data; 1764 u16 offset; 1765 int i, r; 1766 1767 if (!nps_type || !range_cnt || !ranges) 1768 return -EINVAL; 1769 1770 if (refresh) { 1771 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1772 if (r) 1773 return r; 1774 nps_info = &nps_data; 1775 } else { 1776 if (!adev->mman.discovery_bin) { 1777 dev_err(adev->dev, 1778 "fetch mem range failed, ip discovery uninitialized\n"); 1779 return -EINVAL; 1780 } 1781 1782 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1783 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1784 1785 if (!offset) 1786 return -ENOENT; 1787 1788 /* If verification fails, return as if NPS table doesn't exist */ 1789 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1790 return -ENOENT; 1791 1792 nps_info = 1793 (union nps_info *)(adev->mman.discovery_bin + offset); 1794 } 1795 1796 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1797 case 1: 1798 mem_ranges = kvcalloc(nps_info->v1.count, 1799 sizeof(*mem_ranges), 1800 GFP_KERNEL); 1801 if (!mem_ranges) 1802 return -ENOMEM; 1803 *nps_type = nps_info->v1.nps_type; 1804 *range_cnt = nps_info->v1.count; 1805 for (i = 0; i < *range_cnt; i++) { 1806 mem_ranges[i].base_address = 1807 nps_info->v1.instance_info[i].base_address; 1808 mem_ranges[i].limit_address = 1809 nps_info->v1.instance_info[i].limit_address; 1810 mem_ranges[i].nid_mask = -1; 1811 mem_ranges[i].flags = 0; 1812 } 1813 *ranges = mem_ranges; 1814 break; 1815 default: 1816 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1817 le16_to_cpu(nps_info->v1.header.version_major), 1818 le16_to_cpu(nps_info->v1.header.version_minor)); 1819 return -EINVAL; 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1826 { 1827 /* what IP to use for this? */ 1828 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1829 case IP_VERSION(9, 0, 1): 1830 case IP_VERSION(9, 1, 0): 1831 case IP_VERSION(9, 2, 1): 1832 case IP_VERSION(9, 2, 2): 1833 case IP_VERSION(9, 3, 0): 1834 case IP_VERSION(9, 4, 0): 1835 case IP_VERSION(9, 4, 1): 1836 case IP_VERSION(9, 4, 2): 1837 case IP_VERSION(9, 4, 3): 1838 case IP_VERSION(9, 4, 4): 1839 case IP_VERSION(9, 5, 0): 1840 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1841 break; 1842 case IP_VERSION(10, 1, 10): 1843 case IP_VERSION(10, 1, 1): 1844 case IP_VERSION(10, 1, 2): 1845 case IP_VERSION(10, 1, 3): 1846 case IP_VERSION(10, 1, 4): 1847 case IP_VERSION(10, 3, 0): 1848 case IP_VERSION(10, 3, 1): 1849 case IP_VERSION(10, 3, 2): 1850 case IP_VERSION(10, 3, 3): 1851 case IP_VERSION(10, 3, 4): 1852 case IP_VERSION(10, 3, 5): 1853 case IP_VERSION(10, 3, 6): 1854 case IP_VERSION(10, 3, 7): 1855 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1856 break; 1857 case IP_VERSION(11, 0, 0): 1858 case IP_VERSION(11, 0, 1): 1859 case IP_VERSION(11, 0, 2): 1860 case IP_VERSION(11, 0, 3): 1861 case IP_VERSION(11, 0, 4): 1862 case IP_VERSION(11, 5, 0): 1863 case IP_VERSION(11, 5, 1): 1864 case IP_VERSION(11, 5, 2): 1865 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1866 break; 1867 case IP_VERSION(12, 0, 0): 1868 case IP_VERSION(12, 0, 1): 1869 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1870 break; 1871 default: 1872 dev_err(adev->dev, 1873 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1874 amdgpu_ip_version(adev, GC_HWIP, 0)); 1875 return -EINVAL; 1876 } 1877 return 0; 1878 } 1879 1880 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1881 { 1882 /* use GC or MMHUB IP version */ 1883 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1884 case IP_VERSION(9, 0, 1): 1885 case IP_VERSION(9, 1, 0): 1886 case IP_VERSION(9, 2, 1): 1887 case IP_VERSION(9, 2, 2): 1888 case IP_VERSION(9, 3, 0): 1889 case IP_VERSION(9, 4, 0): 1890 case IP_VERSION(9, 4, 1): 1891 case IP_VERSION(9, 4, 2): 1892 case IP_VERSION(9, 4, 3): 1893 case IP_VERSION(9, 4, 4): 1894 case IP_VERSION(9, 5, 0): 1895 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1896 break; 1897 case IP_VERSION(10, 1, 10): 1898 case IP_VERSION(10, 1, 1): 1899 case IP_VERSION(10, 1, 2): 1900 case IP_VERSION(10, 1, 3): 1901 case IP_VERSION(10, 1, 4): 1902 case IP_VERSION(10, 3, 0): 1903 case IP_VERSION(10, 3, 1): 1904 case IP_VERSION(10, 3, 2): 1905 case IP_VERSION(10, 3, 3): 1906 case IP_VERSION(10, 3, 4): 1907 case IP_VERSION(10, 3, 5): 1908 case IP_VERSION(10, 3, 6): 1909 case IP_VERSION(10, 3, 7): 1910 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1911 break; 1912 case IP_VERSION(11, 0, 0): 1913 case IP_VERSION(11, 0, 1): 1914 case IP_VERSION(11, 0, 2): 1915 case IP_VERSION(11, 0, 3): 1916 case IP_VERSION(11, 0, 4): 1917 case IP_VERSION(11, 5, 0): 1918 case IP_VERSION(11, 5, 1): 1919 case IP_VERSION(11, 5, 2): 1920 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1921 break; 1922 case IP_VERSION(12, 0, 0): 1923 case IP_VERSION(12, 0, 1): 1924 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 1925 break; 1926 default: 1927 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1928 amdgpu_ip_version(adev, GC_HWIP, 0)); 1929 return -EINVAL; 1930 } 1931 return 0; 1932 } 1933 1934 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1935 { 1936 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1937 case IP_VERSION(4, 0, 0): 1938 case IP_VERSION(4, 0, 1): 1939 case IP_VERSION(4, 1, 0): 1940 case IP_VERSION(4, 1, 1): 1941 case IP_VERSION(4, 3, 0): 1942 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1943 break; 1944 case IP_VERSION(4, 2, 0): 1945 case IP_VERSION(4, 2, 1): 1946 case IP_VERSION(4, 4, 0): 1947 case IP_VERSION(4, 4, 2): 1948 case IP_VERSION(4, 4, 5): 1949 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1950 break; 1951 case IP_VERSION(5, 0, 0): 1952 case IP_VERSION(5, 0, 1): 1953 case IP_VERSION(5, 0, 2): 1954 case IP_VERSION(5, 0, 3): 1955 case IP_VERSION(5, 2, 0): 1956 case IP_VERSION(5, 2, 1): 1957 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1958 break; 1959 case IP_VERSION(6, 0, 0): 1960 case IP_VERSION(6, 0, 1): 1961 case IP_VERSION(6, 0, 2): 1962 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1963 break; 1964 case IP_VERSION(6, 1, 0): 1965 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1966 break; 1967 case IP_VERSION(7, 0, 0): 1968 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1969 break; 1970 default: 1971 dev_err(adev->dev, 1972 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1973 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1974 return -EINVAL; 1975 } 1976 return 0; 1977 } 1978 1979 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1980 { 1981 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1982 case IP_VERSION(9, 0, 0): 1983 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1984 break; 1985 case IP_VERSION(10, 0, 0): 1986 case IP_VERSION(10, 0, 1): 1987 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1988 break; 1989 case IP_VERSION(11, 0, 0): 1990 case IP_VERSION(11, 0, 2): 1991 case IP_VERSION(11, 0, 4): 1992 case IP_VERSION(11, 0, 5): 1993 case IP_VERSION(11, 0, 9): 1994 case IP_VERSION(11, 0, 7): 1995 case IP_VERSION(11, 0, 11): 1996 case IP_VERSION(11, 0, 12): 1997 case IP_VERSION(11, 0, 13): 1998 case IP_VERSION(11, 5, 0): 1999 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2000 break; 2001 case IP_VERSION(11, 0, 8): 2002 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2003 break; 2004 case IP_VERSION(11, 0, 3): 2005 case IP_VERSION(12, 0, 1): 2006 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2007 break; 2008 case IP_VERSION(13, 0, 0): 2009 case IP_VERSION(13, 0, 1): 2010 case IP_VERSION(13, 0, 2): 2011 case IP_VERSION(13, 0, 3): 2012 case IP_VERSION(13, 0, 5): 2013 case IP_VERSION(13, 0, 6): 2014 case IP_VERSION(13, 0, 7): 2015 case IP_VERSION(13, 0, 8): 2016 case IP_VERSION(13, 0, 10): 2017 case IP_VERSION(13, 0, 11): 2018 case IP_VERSION(13, 0, 12): 2019 case IP_VERSION(13, 0, 14): 2020 case IP_VERSION(14, 0, 0): 2021 case IP_VERSION(14, 0, 1): 2022 case IP_VERSION(14, 0, 4): 2023 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2024 break; 2025 case IP_VERSION(13, 0, 4): 2026 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2027 break; 2028 case IP_VERSION(14, 0, 2): 2029 case IP_VERSION(14, 0, 3): 2030 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2031 break; 2032 default: 2033 dev_err(adev->dev, 2034 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2035 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2036 return -EINVAL; 2037 } 2038 return 0; 2039 } 2040 2041 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2042 { 2043 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2044 case IP_VERSION(9, 0, 0): 2045 case IP_VERSION(10, 0, 0): 2046 case IP_VERSION(10, 0, 1): 2047 case IP_VERSION(11, 0, 2): 2048 if (adev->asic_type == CHIP_ARCTURUS) 2049 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2050 else 2051 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2052 break; 2053 case IP_VERSION(11, 0, 0): 2054 case IP_VERSION(11, 0, 5): 2055 case IP_VERSION(11, 0, 9): 2056 case IP_VERSION(11, 0, 7): 2057 case IP_VERSION(11, 0, 8): 2058 case IP_VERSION(11, 0, 11): 2059 case IP_VERSION(11, 0, 12): 2060 case IP_VERSION(11, 0, 13): 2061 case IP_VERSION(11, 5, 0): 2062 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2063 break; 2064 case IP_VERSION(12, 0, 0): 2065 case IP_VERSION(12, 0, 1): 2066 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2067 break; 2068 case IP_VERSION(13, 0, 0): 2069 case IP_VERSION(13, 0, 1): 2070 case IP_VERSION(13, 0, 2): 2071 case IP_VERSION(13, 0, 3): 2072 case IP_VERSION(13, 0, 4): 2073 case IP_VERSION(13, 0, 5): 2074 case IP_VERSION(13, 0, 6): 2075 case IP_VERSION(13, 0, 7): 2076 case IP_VERSION(13, 0, 8): 2077 case IP_VERSION(13, 0, 10): 2078 case IP_VERSION(13, 0, 11): 2079 case IP_VERSION(13, 0, 14): 2080 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2081 break; 2082 case IP_VERSION(14, 0, 0): 2083 case IP_VERSION(14, 0, 1): 2084 case IP_VERSION(14, 0, 2): 2085 case IP_VERSION(14, 0, 3): 2086 case IP_VERSION(14, 0, 4): 2087 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2088 break; 2089 default: 2090 dev_err(adev->dev, 2091 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2092 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2093 return -EINVAL; 2094 } 2095 return 0; 2096 } 2097 2098 #if defined(CONFIG_DRM_AMD_DC) 2099 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2100 { 2101 amdgpu_device_set_sriov_virtual_display(adev); 2102 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2103 } 2104 #endif 2105 2106 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2107 { 2108 if (adev->enable_virtual_display) { 2109 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2110 return 0; 2111 } 2112 2113 if (!amdgpu_device_has_dc_support(adev)) 2114 return 0; 2115 2116 #if defined(CONFIG_DRM_AMD_DC) 2117 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2118 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2119 case IP_VERSION(1, 0, 0): 2120 case IP_VERSION(1, 0, 1): 2121 case IP_VERSION(2, 0, 2): 2122 case IP_VERSION(2, 0, 0): 2123 case IP_VERSION(2, 0, 3): 2124 case IP_VERSION(2, 1, 0): 2125 case IP_VERSION(3, 0, 0): 2126 case IP_VERSION(3, 0, 2): 2127 case IP_VERSION(3, 0, 3): 2128 case IP_VERSION(3, 0, 1): 2129 case IP_VERSION(3, 1, 2): 2130 case IP_VERSION(3, 1, 3): 2131 case IP_VERSION(3, 1, 4): 2132 case IP_VERSION(3, 1, 5): 2133 case IP_VERSION(3, 1, 6): 2134 case IP_VERSION(3, 2, 0): 2135 case IP_VERSION(3, 2, 1): 2136 case IP_VERSION(3, 5, 0): 2137 case IP_VERSION(3, 5, 1): 2138 case IP_VERSION(4, 1, 0): 2139 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2140 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2141 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2142 2143 if (amdgpu_sriov_vf(adev)) 2144 amdgpu_discovery_set_sriov_display(adev); 2145 else 2146 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2147 break; 2148 default: 2149 dev_err(adev->dev, 2150 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2151 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2152 return -EINVAL; 2153 } 2154 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2155 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2156 case IP_VERSION(12, 0, 0): 2157 case IP_VERSION(12, 0, 1): 2158 case IP_VERSION(12, 1, 0): 2159 if (amdgpu_sriov_vf(adev)) 2160 amdgpu_discovery_set_sriov_display(adev); 2161 else 2162 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2163 break; 2164 default: 2165 dev_err(adev->dev, 2166 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2167 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2168 return -EINVAL; 2169 } 2170 } 2171 #endif 2172 return 0; 2173 } 2174 2175 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2176 { 2177 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2178 case IP_VERSION(9, 0, 1): 2179 case IP_VERSION(9, 1, 0): 2180 case IP_VERSION(9, 2, 1): 2181 case IP_VERSION(9, 2, 2): 2182 case IP_VERSION(9, 3, 0): 2183 case IP_VERSION(9, 4, 0): 2184 case IP_VERSION(9, 4, 1): 2185 case IP_VERSION(9, 4, 2): 2186 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2187 break; 2188 case IP_VERSION(9, 4, 3): 2189 case IP_VERSION(9, 4, 4): 2190 case IP_VERSION(9, 5, 0): 2191 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2192 break; 2193 case IP_VERSION(10, 1, 10): 2194 case IP_VERSION(10, 1, 2): 2195 case IP_VERSION(10, 1, 1): 2196 case IP_VERSION(10, 1, 3): 2197 case IP_VERSION(10, 1, 4): 2198 case IP_VERSION(10, 3, 0): 2199 case IP_VERSION(10, 3, 2): 2200 case IP_VERSION(10, 3, 1): 2201 case IP_VERSION(10, 3, 4): 2202 case IP_VERSION(10, 3, 5): 2203 case IP_VERSION(10, 3, 6): 2204 case IP_VERSION(10, 3, 3): 2205 case IP_VERSION(10, 3, 7): 2206 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2207 break; 2208 case IP_VERSION(11, 0, 0): 2209 case IP_VERSION(11, 0, 1): 2210 case IP_VERSION(11, 0, 2): 2211 case IP_VERSION(11, 0, 3): 2212 case IP_VERSION(11, 0, 4): 2213 case IP_VERSION(11, 5, 0): 2214 case IP_VERSION(11, 5, 1): 2215 case IP_VERSION(11, 5, 2): 2216 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2217 break; 2218 case IP_VERSION(12, 0, 0): 2219 case IP_VERSION(12, 0, 1): 2220 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2221 break; 2222 default: 2223 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2224 amdgpu_ip_version(adev, GC_HWIP, 0)); 2225 return -EINVAL; 2226 } 2227 return 0; 2228 } 2229 2230 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2231 { 2232 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2233 case IP_VERSION(4, 0, 0): 2234 case IP_VERSION(4, 0, 1): 2235 case IP_VERSION(4, 1, 0): 2236 case IP_VERSION(4, 1, 1): 2237 case IP_VERSION(4, 1, 2): 2238 case IP_VERSION(4, 2, 0): 2239 case IP_VERSION(4, 2, 2): 2240 case IP_VERSION(4, 4, 0): 2241 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2242 break; 2243 case IP_VERSION(4, 4, 2): 2244 case IP_VERSION(4, 4, 5): 2245 case IP_VERSION(4, 4, 4): 2246 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2247 break; 2248 case IP_VERSION(5, 0, 0): 2249 case IP_VERSION(5, 0, 1): 2250 case IP_VERSION(5, 0, 2): 2251 case IP_VERSION(5, 0, 5): 2252 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2253 break; 2254 case IP_VERSION(5, 2, 0): 2255 case IP_VERSION(5, 2, 2): 2256 case IP_VERSION(5, 2, 4): 2257 case IP_VERSION(5, 2, 5): 2258 case IP_VERSION(5, 2, 6): 2259 case IP_VERSION(5, 2, 3): 2260 case IP_VERSION(5, 2, 1): 2261 case IP_VERSION(5, 2, 7): 2262 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2263 break; 2264 case IP_VERSION(6, 0, 0): 2265 case IP_VERSION(6, 0, 1): 2266 case IP_VERSION(6, 0, 2): 2267 case IP_VERSION(6, 0, 3): 2268 case IP_VERSION(6, 1, 0): 2269 case IP_VERSION(6, 1, 1): 2270 case IP_VERSION(6, 1, 2): 2271 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2272 break; 2273 case IP_VERSION(7, 0, 0): 2274 case IP_VERSION(7, 0, 1): 2275 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2276 break; 2277 default: 2278 dev_err(adev->dev, 2279 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2280 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2281 return -EINVAL; 2282 } 2283 return 0; 2284 } 2285 2286 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2287 { 2288 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2289 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2290 case IP_VERSION(7, 0, 0): 2291 case IP_VERSION(7, 2, 0): 2292 /* UVD is not supported on vega20 SR-IOV */ 2293 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2294 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2295 break; 2296 default: 2297 dev_err(adev->dev, 2298 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2299 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2300 return -EINVAL; 2301 } 2302 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2303 case IP_VERSION(4, 0, 0): 2304 case IP_VERSION(4, 1, 0): 2305 /* VCE is not supported on vega20 SR-IOV */ 2306 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2307 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2308 break; 2309 default: 2310 dev_err(adev->dev, 2311 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2312 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2313 return -EINVAL; 2314 } 2315 } else { 2316 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2317 case IP_VERSION(1, 0, 0): 2318 case IP_VERSION(1, 0, 1): 2319 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2320 break; 2321 case IP_VERSION(2, 0, 0): 2322 case IP_VERSION(2, 0, 2): 2323 case IP_VERSION(2, 2, 0): 2324 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2325 if (!amdgpu_sriov_vf(adev)) 2326 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2327 break; 2328 case IP_VERSION(2, 0, 3): 2329 break; 2330 case IP_VERSION(2, 5, 0): 2331 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2332 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2333 break; 2334 case IP_VERSION(2, 6, 0): 2335 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2336 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2337 break; 2338 case IP_VERSION(3, 0, 0): 2339 case IP_VERSION(3, 0, 16): 2340 case IP_VERSION(3, 1, 1): 2341 case IP_VERSION(3, 1, 2): 2342 case IP_VERSION(3, 0, 2): 2343 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2344 if (!amdgpu_sriov_vf(adev)) 2345 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2346 break; 2347 case IP_VERSION(3, 0, 33): 2348 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2349 break; 2350 case IP_VERSION(4, 0, 0): 2351 case IP_VERSION(4, 0, 2): 2352 case IP_VERSION(4, 0, 4): 2353 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2354 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2355 break; 2356 case IP_VERSION(4, 0, 3): 2357 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2358 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2359 break; 2360 case IP_VERSION(4, 0, 5): 2361 case IP_VERSION(4, 0, 6): 2362 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2363 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2364 break; 2365 case IP_VERSION(5, 0, 0): 2366 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2367 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2368 break; 2369 default: 2370 dev_err(adev->dev, 2371 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2372 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2373 return -EINVAL; 2374 } 2375 } 2376 return 0; 2377 } 2378 2379 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2380 { 2381 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2382 case IP_VERSION(11, 0, 0): 2383 case IP_VERSION(11, 0, 1): 2384 case IP_VERSION(11, 0, 2): 2385 case IP_VERSION(11, 0, 3): 2386 case IP_VERSION(11, 0, 4): 2387 case IP_VERSION(11, 5, 0): 2388 case IP_VERSION(11, 5, 1): 2389 case IP_VERSION(11, 5, 2): 2390 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2391 adev->enable_mes = true; 2392 adev->enable_mes_kiq = true; 2393 break; 2394 case IP_VERSION(12, 0, 0): 2395 case IP_VERSION(12, 0, 1): 2396 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2397 adev->enable_mes = true; 2398 adev->enable_mes_kiq = true; 2399 if (amdgpu_uni_mes) 2400 adev->enable_uni_mes = true; 2401 break; 2402 default: 2403 break; 2404 } 2405 return 0; 2406 } 2407 2408 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2409 { 2410 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2411 case IP_VERSION(9, 4, 3): 2412 case IP_VERSION(9, 4, 4): 2413 case IP_VERSION(9, 5, 0): 2414 aqua_vanjaram_init_soc_config(adev); 2415 break; 2416 default: 2417 break; 2418 } 2419 } 2420 2421 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2422 { 2423 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2424 case IP_VERSION(6, 1, 0): 2425 case IP_VERSION(6, 1, 1): 2426 case IP_VERSION(6, 1, 3): 2427 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2428 break; 2429 default: 2430 break; 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2437 { 2438 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2439 case IP_VERSION(4, 0, 5): 2440 case IP_VERSION(4, 0, 6): 2441 if (amdgpu_umsch_mm & 0x1) { 2442 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2443 adev->enable_umsch_mm = true; 2444 } 2445 break; 2446 default: 2447 break; 2448 } 2449 2450 return 0; 2451 } 2452 2453 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2454 { 2455 #if defined(CONFIG_DRM_AMD_ISP) 2456 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2457 case IP_VERSION(4, 1, 0): 2458 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2459 break; 2460 case IP_VERSION(4, 1, 1): 2461 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2462 break; 2463 default: 2464 break; 2465 } 2466 #endif 2467 2468 return 0; 2469 } 2470 2471 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2472 { 2473 int r; 2474 2475 switch (adev->asic_type) { 2476 case CHIP_VEGA10: 2477 vega10_reg_base_init(adev); 2478 adev->sdma.num_instances = 2; 2479 adev->gmc.num_umc = 4; 2480 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2481 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2482 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2483 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2484 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2485 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2486 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2487 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2488 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2489 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2490 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2491 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2492 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2493 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2494 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2495 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2496 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2497 break; 2498 case CHIP_VEGA12: 2499 vega10_reg_base_init(adev); 2500 adev->sdma.num_instances = 2; 2501 adev->gmc.num_umc = 4; 2502 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2503 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2504 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2505 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2506 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2507 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2508 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2509 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2510 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2511 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2512 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2513 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2514 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2515 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2516 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2517 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2518 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2519 break; 2520 case CHIP_RAVEN: 2521 vega10_reg_base_init(adev); 2522 adev->sdma.num_instances = 1; 2523 adev->vcn.num_vcn_inst = 1; 2524 adev->gmc.num_umc = 2; 2525 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2526 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2527 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2528 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2529 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2530 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2531 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2532 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2533 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2534 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2535 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2536 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2537 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2538 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2539 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2540 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2541 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2542 } else { 2543 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2544 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2545 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2546 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2547 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2548 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2549 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2550 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2551 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2552 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2553 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2554 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2555 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2556 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2557 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2558 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2559 } 2560 break; 2561 case CHIP_VEGA20: 2562 vega20_reg_base_init(adev); 2563 adev->sdma.num_instances = 2; 2564 adev->gmc.num_umc = 8; 2565 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2566 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2567 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2568 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2569 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2570 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2571 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2572 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2573 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2574 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2575 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2576 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2577 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2578 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2579 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2580 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2581 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2582 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2583 break; 2584 case CHIP_ARCTURUS: 2585 arct_reg_base_init(adev); 2586 adev->sdma.num_instances = 8; 2587 adev->vcn.num_vcn_inst = 2; 2588 adev->gmc.num_umc = 8; 2589 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2590 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2591 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2592 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2593 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2594 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2595 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2596 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2597 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2598 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2599 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2600 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2601 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2602 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2603 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2604 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2605 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2606 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2607 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2608 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2609 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2610 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2611 break; 2612 case CHIP_ALDEBARAN: 2613 aldebaran_reg_base_init(adev); 2614 adev->sdma.num_instances = 5; 2615 adev->vcn.num_vcn_inst = 2; 2616 adev->gmc.num_umc = 4; 2617 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2618 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2619 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2620 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2621 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2622 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2623 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2624 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2625 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2626 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2627 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2628 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2629 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2630 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2631 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2632 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2633 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2634 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2635 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2636 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2637 break; 2638 default: 2639 r = amdgpu_discovery_reg_base_init(adev); 2640 if (r) 2641 return -EINVAL; 2642 2643 amdgpu_discovery_harvest_ip(adev); 2644 amdgpu_discovery_get_gfx_info(adev); 2645 amdgpu_discovery_get_mall_info(adev); 2646 amdgpu_discovery_get_vcn_info(adev); 2647 break; 2648 } 2649 2650 amdgpu_discovery_init_soc_config(adev); 2651 amdgpu_discovery_sysfs_init(adev); 2652 2653 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2654 case IP_VERSION(9, 0, 1): 2655 case IP_VERSION(9, 2, 1): 2656 case IP_VERSION(9, 4, 0): 2657 case IP_VERSION(9, 4, 1): 2658 case IP_VERSION(9, 4, 2): 2659 case IP_VERSION(9, 4, 3): 2660 case IP_VERSION(9, 4, 4): 2661 case IP_VERSION(9, 5, 0): 2662 adev->family = AMDGPU_FAMILY_AI; 2663 break; 2664 case IP_VERSION(9, 1, 0): 2665 case IP_VERSION(9, 2, 2): 2666 case IP_VERSION(9, 3, 0): 2667 adev->family = AMDGPU_FAMILY_RV; 2668 break; 2669 case IP_VERSION(10, 1, 10): 2670 case IP_VERSION(10, 1, 1): 2671 case IP_VERSION(10, 1, 2): 2672 case IP_VERSION(10, 1, 3): 2673 case IP_VERSION(10, 1, 4): 2674 case IP_VERSION(10, 3, 0): 2675 case IP_VERSION(10, 3, 2): 2676 case IP_VERSION(10, 3, 4): 2677 case IP_VERSION(10, 3, 5): 2678 adev->family = AMDGPU_FAMILY_NV; 2679 break; 2680 case IP_VERSION(10, 3, 1): 2681 adev->family = AMDGPU_FAMILY_VGH; 2682 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2683 break; 2684 case IP_VERSION(10, 3, 3): 2685 adev->family = AMDGPU_FAMILY_YC; 2686 break; 2687 case IP_VERSION(10, 3, 6): 2688 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2689 break; 2690 case IP_VERSION(10, 3, 7): 2691 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2692 break; 2693 case IP_VERSION(11, 0, 0): 2694 case IP_VERSION(11, 0, 2): 2695 case IP_VERSION(11, 0, 3): 2696 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2697 break; 2698 case IP_VERSION(11, 0, 1): 2699 case IP_VERSION(11, 0, 4): 2700 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2701 break; 2702 case IP_VERSION(11, 5, 0): 2703 case IP_VERSION(11, 5, 1): 2704 case IP_VERSION(11, 5, 2): 2705 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2706 break; 2707 case IP_VERSION(12, 0, 0): 2708 case IP_VERSION(12, 0, 1): 2709 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2710 break; 2711 default: 2712 return -EINVAL; 2713 } 2714 2715 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2716 case IP_VERSION(9, 1, 0): 2717 case IP_VERSION(9, 2, 2): 2718 case IP_VERSION(9, 3, 0): 2719 case IP_VERSION(10, 1, 3): 2720 case IP_VERSION(10, 1, 4): 2721 case IP_VERSION(10, 3, 1): 2722 case IP_VERSION(10, 3, 3): 2723 case IP_VERSION(10, 3, 6): 2724 case IP_VERSION(10, 3, 7): 2725 case IP_VERSION(11, 0, 1): 2726 case IP_VERSION(11, 0, 4): 2727 case IP_VERSION(11, 5, 0): 2728 case IP_VERSION(11, 5, 1): 2729 case IP_VERSION(11, 5, 2): 2730 adev->flags |= AMD_IS_APU; 2731 break; 2732 default: 2733 break; 2734 } 2735 2736 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2737 adev->gmc.xgmi.supported = true; 2738 2739 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2740 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2741 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2742 2743 /* set NBIO version */ 2744 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2745 case IP_VERSION(6, 1, 0): 2746 case IP_VERSION(6, 2, 0): 2747 adev->nbio.funcs = &nbio_v6_1_funcs; 2748 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2749 break; 2750 case IP_VERSION(7, 0, 0): 2751 case IP_VERSION(7, 0, 1): 2752 case IP_VERSION(2, 5, 0): 2753 adev->nbio.funcs = &nbio_v7_0_funcs; 2754 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2755 break; 2756 case IP_VERSION(7, 4, 0): 2757 case IP_VERSION(7, 4, 1): 2758 case IP_VERSION(7, 4, 4): 2759 adev->nbio.funcs = &nbio_v7_4_funcs; 2760 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2761 break; 2762 case IP_VERSION(7, 9, 0): 2763 adev->nbio.funcs = &nbio_v7_9_funcs; 2764 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2765 break; 2766 case IP_VERSION(7, 11, 0): 2767 case IP_VERSION(7, 11, 1): 2768 case IP_VERSION(7, 11, 3): 2769 adev->nbio.funcs = &nbio_v7_11_funcs; 2770 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2771 break; 2772 case IP_VERSION(7, 2, 0): 2773 case IP_VERSION(7, 2, 1): 2774 case IP_VERSION(7, 3, 0): 2775 case IP_VERSION(7, 5, 0): 2776 case IP_VERSION(7, 5, 1): 2777 adev->nbio.funcs = &nbio_v7_2_funcs; 2778 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2779 break; 2780 case IP_VERSION(2, 1, 1): 2781 case IP_VERSION(2, 3, 0): 2782 case IP_VERSION(2, 3, 1): 2783 case IP_VERSION(2, 3, 2): 2784 case IP_VERSION(3, 3, 0): 2785 case IP_VERSION(3, 3, 1): 2786 case IP_VERSION(3, 3, 2): 2787 case IP_VERSION(3, 3, 3): 2788 adev->nbio.funcs = &nbio_v2_3_funcs; 2789 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2790 break; 2791 case IP_VERSION(4, 3, 0): 2792 case IP_VERSION(4, 3, 1): 2793 if (amdgpu_sriov_vf(adev)) 2794 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2795 else 2796 adev->nbio.funcs = &nbio_v4_3_funcs; 2797 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2798 break; 2799 case IP_VERSION(7, 7, 0): 2800 case IP_VERSION(7, 7, 1): 2801 adev->nbio.funcs = &nbio_v7_7_funcs; 2802 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2803 break; 2804 case IP_VERSION(6, 3, 1): 2805 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2806 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2807 break; 2808 default: 2809 break; 2810 } 2811 2812 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2813 case IP_VERSION(4, 0, 0): 2814 case IP_VERSION(4, 0, 1): 2815 case IP_VERSION(4, 1, 0): 2816 case IP_VERSION(4, 1, 1): 2817 case IP_VERSION(4, 1, 2): 2818 case IP_VERSION(4, 2, 0): 2819 case IP_VERSION(4, 2, 1): 2820 case IP_VERSION(4, 4, 0): 2821 case IP_VERSION(4, 4, 2): 2822 case IP_VERSION(4, 4, 5): 2823 adev->hdp.funcs = &hdp_v4_0_funcs; 2824 break; 2825 case IP_VERSION(5, 0, 0): 2826 case IP_VERSION(5, 0, 1): 2827 case IP_VERSION(5, 0, 2): 2828 case IP_VERSION(5, 0, 3): 2829 case IP_VERSION(5, 0, 4): 2830 case IP_VERSION(5, 2, 0): 2831 adev->hdp.funcs = &hdp_v5_0_funcs; 2832 break; 2833 case IP_VERSION(5, 2, 1): 2834 adev->hdp.funcs = &hdp_v5_2_funcs; 2835 break; 2836 case IP_VERSION(6, 0, 0): 2837 case IP_VERSION(6, 0, 1): 2838 case IP_VERSION(6, 1, 0): 2839 adev->hdp.funcs = &hdp_v6_0_funcs; 2840 break; 2841 case IP_VERSION(7, 0, 0): 2842 adev->hdp.funcs = &hdp_v7_0_funcs; 2843 break; 2844 default: 2845 break; 2846 } 2847 2848 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2849 case IP_VERSION(3, 6, 0): 2850 case IP_VERSION(3, 6, 1): 2851 case IP_VERSION(3, 6, 2): 2852 adev->df.funcs = &df_v3_6_funcs; 2853 break; 2854 case IP_VERSION(2, 1, 0): 2855 case IP_VERSION(2, 1, 1): 2856 case IP_VERSION(2, 5, 0): 2857 case IP_VERSION(3, 5, 1): 2858 case IP_VERSION(3, 5, 2): 2859 adev->df.funcs = &df_v1_7_funcs; 2860 break; 2861 case IP_VERSION(4, 3, 0): 2862 adev->df.funcs = &df_v4_3_funcs; 2863 break; 2864 case IP_VERSION(4, 6, 2): 2865 adev->df.funcs = &df_v4_6_2_funcs; 2866 break; 2867 case IP_VERSION(4, 15, 0): 2868 case IP_VERSION(4, 15, 1): 2869 adev->df.funcs = &df_v4_15_funcs; 2870 break; 2871 default: 2872 break; 2873 } 2874 2875 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2876 case IP_VERSION(9, 0, 0): 2877 case IP_VERSION(9, 0, 1): 2878 case IP_VERSION(10, 0, 0): 2879 case IP_VERSION(10, 0, 1): 2880 case IP_VERSION(10, 0, 2): 2881 adev->smuio.funcs = &smuio_v9_0_funcs; 2882 break; 2883 case IP_VERSION(11, 0, 0): 2884 case IP_VERSION(11, 0, 2): 2885 case IP_VERSION(11, 0, 3): 2886 case IP_VERSION(11, 0, 4): 2887 case IP_VERSION(11, 0, 7): 2888 case IP_VERSION(11, 0, 8): 2889 adev->smuio.funcs = &smuio_v11_0_funcs; 2890 break; 2891 case IP_VERSION(11, 0, 6): 2892 case IP_VERSION(11, 0, 10): 2893 case IP_VERSION(11, 0, 11): 2894 case IP_VERSION(11, 5, 0): 2895 case IP_VERSION(13, 0, 1): 2896 case IP_VERSION(13, 0, 9): 2897 case IP_VERSION(13, 0, 10): 2898 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2899 break; 2900 case IP_VERSION(13, 0, 2): 2901 adev->smuio.funcs = &smuio_v13_0_funcs; 2902 break; 2903 case IP_VERSION(13, 0, 3): 2904 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2905 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2906 adev->flags |= AMD_IS_APU; 2907 } 2908 break; 2909 case IP_VERSION(13, 0, 6): 2910 case IP_VERSION(13, 0, 8): 2911 case IP_VERSION(14, 0, 0): 2912 case IP_VERSION(14, 0, 1): 2913 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2914 break; 2915 case IP_VERSION(14, 0, 2): 2916 adev->smuio.funcs = &smuio_v14_0_2_funcs; 2917 break; 2918 default: 2919 break; 2920 } 2921 2922 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2923 case IP_VERSION(6, 0, 0): 2924 case IP_VERSION(6, 0, 1): 2925 case IP_VERSION(6, 0, 2): 2926 case IP_VERSION(6, 0, 3): 2927 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2928 break; 2929 case IP_VERSION(7, 0, 0): 2930 case IP_VERSION(7, 0, 1): 2931 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2932 break; 2933 default: 2934 break; 2935 } 2936 2937 r = amdgpu_discovery_set_common_ip_blocks(adev); 2938 if (r) 2939 return r; 2940 2941 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2942 if (r) 2943 return r; 2944 2945 /* For SR-IOV, PSP needs to be initialized before IH */ 2946 if (amdgpu_sriov_vf(adev)) { 2947 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2948 if (r) 2949 return r; 2950 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2951 if (r) 2952 return r; 2953 } else { 2954 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2955 if (r) 2956 return r; 2957 2958 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2959 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2960 if (r) 2961 return r; 2962 } 2963 } 2964 2965 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2966 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2967 if (r) 2968 return r; 2969 } 2970 2971 r = amdgpu_discovery_set_display_ip_blocks(adev); 2972 if (r) 2973 return r; 2974 2975 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2976 if (r) 2977 return r; 2978 2979 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2980 if (r) 2981 return r; 2982 2983 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2984 !amdgpu_sriov_vf(adev)) || 2985 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2986 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2987 if (r) 2988 return r; 2989 } 2990 2991 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2992 if (r) 2993 return r; 2994 2995 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2996 if (r) 2997 return r; 2998 2999 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3000 if (r) 3001 return r; 3002 3003 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3004 if (r) 3005 return r; 3006 3007 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3008 if (r) 3009 return r; 3010 return 0; 3011 } 3012 3013