1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "nbio_v6_1.h" 41 #include "nbio_v7_0.h" 42 #include "nbio_v7_4.h" 43 #include "nbio_v7_9.h" 44 #include "nbio_v7_11.h" 45 #include "hdp_v4_0.h" 46 #include "vega10_ih.h" 47 #include "vega20_ih.h" 48 #include "sdma_v4_0.h" 49 #include "sdma_v4_4_2.h" 50 #include "uvd_v7_0.h" 51 #include "vce_v4_0.h" 52 #include "vcn_v1_0.h" 53 #include "vcn_v2_5.h" 54 #include "jpeg_v2_5.h" 55 #include "smuio_v9_0.h" 56 #include "gmc_v10_0.h" 57 #include "gmc_v11_0.h" 58 #include "gfxhub_v2_0.h" 59 #include "mmhub_v2_0.h" 60 #include "nbio_v2_3.h" 61 #include "nbio_v4_3.h" 62 #include "nbio_v7_2.h" 63 #include "nbio_v7_7.h" 64 #include "nbif_v6_3_1.h" 65 #include "hdp_v5_0.h" 66 #include "hdp_v5_2.h" 67 #include "hdp_v6_0.h" 68 #include "hdp_v7_0.h" 69 #include "nv.h" 70 #include "soc21.h" 71 #include "soc24.h" 72 #include "navi10_ih.h" 73 #include "ih_v6_0.h" 74 #include "ih_v6_1.h" 75 #include "ih_v7_0.h" 76 #include "gfx_v10_0.h" 77 #include "gfx_v11_0.h" 78 #include "sdma_v5_0.h" 79 #include "sdma_v5_2.h" 80 #include "sdma_v6_0.h" 81 #include "lsdma_v6_0.h" 82 #include "lsdma_v7_0.h" 83 #include "vcn_v2_0.h" 84 #include "jpeg_v2_0.h" 85 #include "vcn_v3_0.h" 86 #include "jpeg_v3_0.h" 87 #include "vcn_v4_0.h" 88 #include "jpeg_v4_0.h" 89 #include "vcn_v4_0_3.h" 90 #include "jpeg_v4_0_3.h" 91 #include "vcn_v4_0_5.h" 92 #include "jpeg_v4_0_5.h" 93 #include "amdgpu_vkms.h" 94 #include "mes_v10_1.h" 95 #include "mes_v11_0.h" 96 #include "smuio_v11_0.h" 97 #include "smuio_v11_0_6.h" 98 #include "smuio_v13_0.h" 99 #include "smuio_v13_0_3.h" 100 #include "smuio_v13_0_6.h" 101 #include "smuio_v14_0_2.h" 102 #include "vcn_v5_0_0.h" 103 #include "jpeg_v5_0_0.h" 104 105 #include "amdgpu_vpe.h" 106 107 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 108 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 109 110 #define mmIP_DISCOVERY_VERSION 0x16A00 111 #define mmRCC_CONFIG_MEMSIZE 0xde3 112 #define mmMP0_SMN_C2PMSG_33 0x16061 113 #define mmMM_INDEX 0x0 114 #define mmMM_INDEX_HI 0x6 115 #define mmMM_DATA 0x1 116 117 static const char *hw_id_names[HW_ID_MAX] = { 118 [MP1_HWID] = "MP1", 119 [MP2_HWID] = "MP2", 120 [THM_HWID] = "THM", 121 [SMUIO_HWID] = "SMUIO", 122 [FUSE_HWID] = "FUSE", 123 [CLKA_HWID] = "CLKA", 124 [PWR_HWID] = "PWR", 125 [GC_HWID] = "GC", 126 [UVD_HWID] = "UVD", 127 [AUDIO_AZ_HWID] = "AUDIO_AZ", 128 [ACP_HWID] = "ACP", 129 [DCI_HWID] = "DCI", 130 [DMU_HWID] = "DMU", 131 [DCO_HWID] = "DCO", 132 [DIO_HWID] = "DIO", 133 [XDMA_HWID] = "XDMA", 134 [DCEAZ_HWID] = "DCEAZ", 135 [DAZ_HWID] = "DAZ", 136 [SDPMUX_HWID] = "SDPMUX", 137 [NTB_HWID] = "NTB", 138 [IOHC_HWID] = "IOHC", 139 [L2IMU_HWID] = "L2IMU", 140 [VCE_HWID] = "VCE", 141 [MMHUB_HWID] = "MMHUB", 142 [ATHUB_HWID] = "ATHUB", 143 [DBGU_NBIO_HWID] = "DBGU_NBIO", 144 [DFX_HWID] = "DFX", 145 [DBGU0_HWID] = "DBGU0", 146 [DBGU1_HWID] = "DBGU1", 147 [OSSSYS_HWID] = "OSSSYS", 148 [HDP_HWID] = "HDP", 149 [SDMA0_HWID] = "SDMA0", 150 [SDMA1_HWID] = "SDMA1", 151 [SDMA2_HWID] = "SDMA2", 152 [SDMA3_HWID] = "SDMA3", 153 [LSDMA_HWID] = "LSDMA", 154 [ISP_HWID] = "ISP", 155 [DBGU_IO_HWID] = "DBGU_IO", 156 [DF_HWID] = "DF", 157 [CLKB_HWID] = "CLKB", 158 [FCH_HWID] = "FCH", 159 [DFX_DAP_HWID] = "DFX_DAP", 160 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 161 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 162 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 163 [L1IMU3_HWID] = "L1IMU3", 164 [L1IMU4_HWID] = "L1IMU4", 165 [L1IMU5_HWID] = "L1IMU5", 166 [L1IMU6_HWID] = "L1IMU6", 167 [L1IMU7_HWID] = "L1IMU7", 168 [L1IMU8_HWID] = "L1IMU8", 169 [L1IMU9_HWID] = "L1IMU9", 170 [L1IMU10_HWID] = "L1IMU10", 171 [L1IMU11_HWID] = "L1IMU11", 172 [L1IMU12_HWID] = "L1IMU12", 173 [L1IMU13_HWID] = "L1IMU13", 174 [L1IMU14_HWID] = "L1IMU14", 175 [L1IMU15_HWID] = "L1IMU15", 176 [WAFLC_HWID] = "WAFLC", 177 [FCH_USB_PD_HWID] = "FCH_USB_PD", 178 [PCIE_HWID] = "PCIE", 179 [PCS_HWID] = "PCS", 180 [DDCL_HWID] = "DDCL", 181 [SST_HWID] = "SST", 182 [IOAGR_HWID] = "IOAGR", 183 [NBIF_HWID] = "NBIF", 184 [IOAPIC_HWID] = "IOAPIC", 185 [SYSTEMHUB_HWID] = "SYSTEMHUB", 186 [NTBCCP_HWID] = "NTBCCP", 187 [UMC_HWID] = "UMC", 188 [SATA_HWID] = "SATA", 189 [USB_HWID] = "USB", 190 [CCXSEC_HWID] = "CCXSEC", 191 [XGMI_HWID] = "XGMI", 192 [XGBE_HWID] = "XGBE", 193 [MP0_HWID] = "MP0", 194 [VPE_HWID] = "VPE", 195 }; 196 197 static int hw_id_map[MAX_HWIP] = { 198 [GC_HWIP] = GC_HWID, 199 [HDP_HWIP] = HDP_HWID, 200 [SDMA0_HWIP] = SDMA0_HWID, 201 [SDMA1_HWIP] = SDMA1_HWID, 202 [SDMA2_HWIP] = SDMA2_HWID, 203 [SDMA3_HWIP] = SDMA3_HWID, 204 [LSDMA_HWIP] = LSDMA_HWID, 205 [MMHUB_HWIP] = MMHUB_HWID, 206 [ATHUB_HWIP] = ATHUB_HWID, 207 [NBIO_HWIP] = NBIF_HWID, 208 [MP0_HWIP] = MP0_HWID, 209 [MP1_HWIP] = MP1_HWID, 210 [UVD_HWIP] = UVD_HWID, 211 [VCE_HWIP] = VCE_HWID, 212 [DF_HWIP] = DF_HWID, 213 [DCE_HWIP] = DMU_HWID, 214 [OSSSYS_HWIP] = OSSSYS_HWID, 215 [SMUIO_HWIP] = SMUIO_HWID, 216 [PWR_HWIP] = PWR_HWID, 217 [NBIF_HWIP] = NBIF_HWID, 218 [THM_HWIP] = THM_HWID, 219 [CLK_HWIP] = CLKA_HWID, 220 [UMC_HWIP] = UMC_HWID, 221 [XGMI_HWIP] = XGMI_HWID, 222 [DCI_HWIP] = DCI_HWID, 223 [PCIE_HWIP] = PCIE_HWID, 224 [VPE_HWIP] = VPE_HWID, 225 }; 226 227 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 228 { 229 u64 tmr_offset, tmr_size, pos; 230 void *discv_regn; 231 int ret; 232 233 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 234 if (ret) 235 return ret; 236 237 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 238 239 /* This region is read-only and reserved from system use */ 240 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 241 if (discv_regn) { 242 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 243 memunmap(discv_regn); 244 return 0; 245 } 246 247 return -ENOENT; 248 } 249 250 #define IP_DISCOVERY_V2 2 251 #define IP_DISCOVERY_V4 4 252 253 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 254 uint8_t *binary) 255 { 256 uint64_t vram_size; 257 u32 msg; 258 int i, ret = 0; 259 260 /* It can take up to a second for IFWI init to complete on some dGPUs, 261 * but generally it should be in the 60-100ms range. Normally this starts 262 * as soon as the device gets power so by the time the OS loads this has long 263 * completed. However, when a card is hotplugged via e.g., USB4, we need to 264 * wait for this to complete. Once the C2PMSG is updated, we can 265 * continue. 266 */ 267 268 for (i = 0; i < 1000; i++) { 269 msg = RREG32(mmMP0_SMN_C2PMSG_33); 270 if (msg & 0x80000000) 271 break; 272 usleep_range(1000, 1100); 273 } 274 275 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 276 277 if (vram_size) { 278 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 279 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 280 adev->mman.discovery_tmr_size, false); 281 } else { 282 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 283 } 284 285 return ret; 286 } 287 288 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 289 { 290 const struct firmware *fw; 291 const char *fw_name; 292 int r; 293 294 switch (amdgpu_discovery) { 295 case 2: 296 fw_name = FIRMWARE_IP_DISCOVERY; 297 break; 298 default: 299 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 300 return -EINVAL; 301 } 302 303 r = request_firmware(&fw, fw_name, adev->dev); 304 if (r) { 305 dev_err(adev->dev, "can't load firmware \"%s\"\n", 306 fw_name); 307 return r; 308 } 309 310 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 311 release_firmware(fw); 312 313 return 0; 314 } 315 316 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 317 { 318 uint16_t checksum = 0; 319 int i; 320 321 for (i = 0; i < size; i++) 322 checksum += data[i]; 323 324 return checksum; 325 } 326 327 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 328 uint16_t expected) 329 { 330 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 331 } 332 333 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 334 { 335 struct binary_header *bhdr; 336 bhdr = (struct binary_header *)binary; 337 338 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 339 } 340 341 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 342 { 343 /* 344 * So far, apply this quirk only on those Navy Flounder boards which 345 * have a bad harvest table of VCN config. 346 */ 347 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 348 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 349 switch (adev->pdev->revision) { 350 case 0xC1: 351 case 0xC2: 352 case 0xC3: 353 case 0xC5: 354 case 0xC7: 355 case 0xCF: 356 case 0xDF: 357 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 358 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 359 break; 360 default: 361 break; 362 } 363 } 364 } 365 366 static int amdgpu_discovery_init(struct amdgpu_device *adev) 367 { 368 struct table_info *info; 369 struct binary_header *bhdr; 370 uint16_t offset; 371 uint16_t size; 372 uint16_t checksum; 373 int r; 374 375 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 376 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 377 if (!adev->mman.discovery_bin) 378 return -ENOMEM; 379 380 /* Read from file if it is the preferred option */ 381 if (amdgpu_discovery == 2) { 382 dev_info(adev->dev, "use ip discovery information from file"); 383 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 384 385 if (r) { 386 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 387 r = -EINVAL; 388 goto out; 389 } 390 391 } else { 392 r = amdgpu_discovery_read_binary_from_mem( 393 adev, adev->mman.discovery_bin); 394 if (r) 395 goto out; 396 } 397 398 /* check the ip discovery binary signature */ 399 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 400 dev_err(adev->dev, 401 "get invalid ip discovery binary signature\n"); 402 r = -EINVAL; 403 goto out; 404 } 405 406 bhdr = (struct binary_header *)adev->mman.discovery_bin; 407 408 offset = offsetof(struct binary_header, binary_checksum) + 409 sizeof(bhdr->binary_checksum); 410 size = le16_to_cpu(bhdr->binary_size) - offset; 411 checksum = le16_to_cpu(bhdr->binary_checksum); 412 413 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 414 size, checksum)) { 415 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 416 r = -EINVAL; 417 goto out; 418 } 419 420 info = &bhdr->table_list[IP_DISCOVERY]; 421 offset = le16_to_cpu(info->offset); 422 checksum = le16_to_cpu(info->checksum); 423 424 if (offset) { 425 struct ip_discovery_header *ihdr = 426 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 427 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 428 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 429 r = -EINVAL; 430 goto out; 431 } 432 433 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 434 le16_to_cpu(ihdr->size), checksum)) { 435 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 436 r = -EINVAL; 437 goto out; 438 } 439 } 440 441 info = &bhdr->table_list[GC]; 442 offset = le16_to_cpu(info->offset); 443 checksum = le16_to_cpu(info->checksum); 444 445 if (offset) { 446 struct gpu_info_header *ghdr = 447 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 448 449 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 450 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 451 r = -EINVAL; 452 goto out; 453 } 454 455 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 456 le32_to_cpu(ghdr->size), checksum)) { 457 dev_err(adev->dev, "invalid gc data table checksum\n"); 458 r = -EINVAL; 459 goto out; 460 } 461 } 462 463 info = &bhdr->table_list[HARVEST_INFO]; 464 offset = le16_to_cpu(info->offset); 465 checksum = le16_to_cpu(info->checksum); 466 467 if (offset) { 468 struct harvest_info_header *hhdr = 469 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 470 471 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 472 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 473 r = -EINVAL; 474 goto out; 475 } 476 477 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 478 sizeof(struct harvest_table), checksum)) { 479 dev_err(adev->dev, "invalid harvest data table checksum\n"); 480 r = -EINVAL; 481 goto out; 482 } 483 } 484 485 info = &bhdr->table_list[VCN_INFO]; 486 offset = le16_to_cpu(info->offset); 487 checksum = le16_to_cpu(info->checksum); 488 489 if (offset) { 490 struct vcn_info_header *vhdr = 491 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 492 493 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 494 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 495 r = -EINVAL; 496 goto out; 497 } 498 499 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 500 le32_to_cpu(vhdr->size_bytes), checksum)) { 501 dev_err(adev->dev, "invalid vcn data table checksum\n"); 502 r = -EINVAL; 503 goto out; 504 } 505 } 506 507 info = &bhdr->table_list[MALL_INFO]; 508 offset = le16_to_cpu(info->offset); 509 checksum = le16_to_cpu(info->checksum); 510 511 if (0 && offset) { 512 struct mall_info_header *mhdr = 513 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 514 515 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 516 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 517 r = -EINVAL; 518 goto out; 519 } 520 521 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 522 le32_to_cpu(mhdr->size_bytes), checksum)) { 523 dev_err(adev->dev, "invalid mall data table checksum\n"); 524 r = -EINVAL; 525 goto out; 526 } 527 } 528 529 return 0; 530 531 out: 532 kfree(adev->mman.discovery_bin); 533 adev->mman.discovery_bin = NULL; 534 if ((amdgpu_discovery != 2) && 535 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 536 amdgpu_ras_query_boot_status(adev, 4); 537 return r; 538 } 539 540 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 541 542 void amdgpu_discovery_fini(struct amdgpu_device *adev) 543 { 544 amdgpu_discovery_sysfs_fini(adev); 545 kfree(adev->mman.discovery_bin); 546 adev->mman.discovery_bin = NULL; 547 } 548 549 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 550 { 551 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 552 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 553 ip->instance_number); 554 return -EINVAL; 555 } 556 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 557 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 558 le16_to_cpu(ip->hw_id)); 559 return -EINVAL; 560 } 561 562 return 0; 563 } 564 565 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 566 uint32_t *vcn_harvest_count) 567 { 568 struct binary_header *bhdr; 569 struct ip_discovery_header *ihdr; 570 struct die_header *dhdr; 571 struct ip_v4 *ip; 572 uint16_t die_offset, ip_offset, num_dies, num_ips; 573 int i, j; 574 575 bhdr = (struct binary_header *)adev->mman.discovery_bin; 576 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 577 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 578 num_dies = le16_to_cpu(ihdr->num_dies); 579 580 /* scan harvest bit of all IP data structures */ 581 for (i = 0; i < num_dies; i++) { 582 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 583 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 584 num_ips = le16_to_cpu(dhdr->num_ips); 585 ip_offset = die_offset + sizeof(*dhdr); 586 587 for (j = 0; j < num_ips; j++) { 588 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 589 590 if (amdgpu_discovery_validate_ip(ip)) 591 goto next_ip; 592 593 if (le16_to_cpu(ip->variant) == 1) { 594 switch (le16_to_cpu(ip->hw_id)) { 595 case VCN_HWID: 596 (*vcn_harvest_count)++; 597 if (ip->instance_number == 0) { 598 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 599 adev->vcn.inst_mask &= 600 ~AMDGPU_VCN_HARVEST_VCN0; 601 adev->jpeg.inst_mask &= 602 ~AMDGPU_VCN_HARVEST_VCN0; 603 } else { 604 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 605 adev->vcn.inst_mask &= 606 ~AMDGPU_VCN_HARVEST_VCN1; 607 adev->jpeg.inst_mask &= 608 ~AMDGPU_VCN_HARVEST_VCN1; 609 } 610 break; 611 case DMU_HWID: 612 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 613 break; 614 default: 615 break; 616 } 617 } 618 next_ip: 619 if (ihdr->base_addr_64_bit) 620 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 621 else 622 ip_offset += struct_size(ip, base_address, ip->num_base_address); 623 } 624 } 625 } 626 627 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 628 uint32_t *vcn_harvest_count, 629 uint32_t *umc_harvest_count) 630 { 631 struct binary_header *bhdr; 632 struct harvest_table *harvest_info; 633 u16 offset; 634 int i; 635 uint32_t umc_harvest_config = 0; 636 637 bhdr = (struct binary_header *)adev->mman.discovery_bin; 638 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 639 640 if (!offset) { 641 dev_err(adev->dev, "invalid harvest table offset\n"); 642 return; 643 } 644 645 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 646 647 for (i = 0; i < 32; i++) { 648 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 649 break; 650 651 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 652 case VCN_HWID: 653 (*vcn_harvest_count)++; 654 adev->vcn.harvest_config |= 655 (1 << harvest_info->list[i].number_instance); 656 adev->jpeg.harvest_config |= 657 (1 << harvest_info->list[i].number_instance); 658 659 adev->vcn.inst_mask &= 660 ~(1U << harvest_info->list[i].number_instance); 661 adev->jpeg.inst_mask &= 662 ~(1U << harvest_info->list[i].number_instance); 663 break; 664 case DMU_HWID: 665 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 666 break; 667 case UMC_HWID: 668 umc_harvest_config |= 669 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 670 (*umc_harvest_count)++; 671 break; 672 case GC_HWID: 673 adev->gfx.xcc_mask &= 674 ~(1U << harvest_info->list[i].number_instance); 675 break; 676 case SDMA0_HWID: 677 adev->sdma.sdma_mask &= 678 ~(1U << harvest_info->list[i].number_instance); 679 break; 680 default: 681 break; 682 } 683 } 684 685 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 686 ~umc_harvest_config; 687 } 688 689 /* ================================================== */ 690 691 struct ip_hw_instance { 692 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 693 694 int hw_id; 695 u8 num_instance; 696 u8 major, minor, revision; 697 u8 harvest; 698 699 int num_base_addresses; 700 u32 base_addr[] __counted_by(num_base_addresses); 701 }; 702 703 struct ip_hw_id { 704 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 705 int hw_id; 706 }; 707 708 struct ip_die_entry { 709 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 710 u16 num_ips; 711 }; 712 713 /* -------------------------------------------------- */ 714 715 struct ip_hw_instance_attr { 716 struct attribute attr; 717 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 718 }; 719 720 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 721 { 722 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 723 } 724 725 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 726 { 727 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 728 } 729 730 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 731 { 732 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 733 } 734 735 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 736 { 737 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 738 } 739 740 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 741 { 742 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 743 } 744 745 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 746 { 747 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 748 } 749 750 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 751 { 752 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 753 } 754 755 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 756 { 757 ssize_t res, at; 758 int ii; 759 760 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 761 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 762 */ 763 if (at + 12 > PAGE_SIZE) 764 break; 765 res = sysfs_emit_at(buf, at, "0x%08X\n", 766 ip_hw_instance->base_addr[ii]); 767 if (res <= 0) 768 break; 769 at += res; 770 } 771 772 return res < 0 ? res : at; 773 } 774 775 static struct ip_hw_instance_attr ip_hw_attr[] = { 776 __ATTR_RO(hw_id), 777 __ATTR_RO(num_instance), 778 __ATTR_RO(major), 779 __ATTR_RO(minor), 780 __ATTR_RO(revision), 781 __ATTR_RO(harvest), 782 __ATTR_RO(num_base_addresses), 783 __ATTR_RO(base_addr), 784 }; 785 786 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 787 ATTRIBUTE_GROUPS(ip_hw_instance); 788 789 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 790 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 791 792 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 793 struct attribute *attr, 794 char *buf) 795 { 796 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 797 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 798 799 if (!ip_hw_attr->show) 800 return -EIO; 801 802 return ip_hw_attr->show(ip_hw_instance, buf); 803 } 804 805 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 806 .show = ip_hw_instance_attr_show, 807 }; 808 809 static void ip_hw_instance_release(struct kobject *kobj) 810 { 811 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 812 813 kfree(ip_hw_instance); 814 } 815 816 static const struct kobj_type ip_hw_instance_ktype = { 817 .release = ip_hw_instance_release, 818 .sysfs_ops = &ip_hw_instance_sysfs_ops, 819 .default_groups = ip_hw_instance_groups, 820 }; 821 822 /* -------------------------------------------------- */ 823 824 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 825 826 static void ip_hw_id_release(struct kobject *kobj) 827 { 828 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 829 830 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 831 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 832 kfree(ip_hw_id); 833 } 834 835 static const struct kobj_type ip_hw_id_ktype = { 836 .release = ip_hw_id_release, 837 .sysfs_ops = &kobj_sysfs_ops, 838 }; 839 840 /* -------------------------------------------------- */ 841 842 static void die_kobj_release(struct kobject *kobj); 843 static void ip_disc_release(struct kobject *kobj); 844 845 struct ip_die_entry_attribute { 846 struct attribute attr; 847 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 848 }; 849 850 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 851 852 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 853 { 854 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 855 } 856 857 /* If there are more ip_die_entry attrs, other than the number of IPs, 858 * we can make this intro an array of attrs, and then initialize 859 * ip_die_entry_attrs in a loop. 860 */ 861 static struct ip_die_entry_attribute num_ips_attr = 862 __ATTR_RO(num_ips); 863 864 static struct attribute *ip_die_entry_attrs[] = { 865 &num_ips_attr.attr, 866 NULL, 867 }; 868 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 869 870 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 871 872 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 873 struct attribute *attr, 874 char *buf) 875 { 876 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 877 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 878 879 if (!ip_die_entry_attr->show) 880 return -EIO; 881 882 return ip_die_entry_attr->show(ip_die_entry, buf); 883 } 884 885 static void ip_die_entry_release(struct kobject *kobj) 886 { 887 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 888 889 if (!list_empty(&ip_die_entry->ip_kset.list)) 890 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 891 kfree(ip_die_entry); 892 } 893 894 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 895 .show = ip_die_entry_attr_show, 896 }; 897 898 static const struct kobj_type ip_die_entry_ktype = { 899 .release = ip_die_entry_release, 900 .sysfs_ops = &ip_die_entry_sysfs_ops, 901 .default_groups = ip_die_entry_groups, 902 }; 903 904 static const struct kobj_type die_kobj_ktype = { 905 .release = die_kobj_release, 906 .sysfs_ops = &kobj_sysfs_ops, 907 }; 908 909 static const struct kobj_type ip_discovery_ktype = { 910 .release = ip_disc_release, 911 .sysfs_ops = &kobj_sysfs_ops, 912 }; 913 914 struct ip_discovery_top { 915 struct kobject kobj; /* ip_discovery/ */ 916 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 917 struct amdgpu_device *adev; 918 }; 919 920 static void die_kobj_release(struct kobject *kobj) 921 { 922 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 923 struct ip_discovery_top, 924 die_kset); 925 if (!list_empty(&ip_top->die_kset.list)) 926 DRM_ERROR("ip_top->die_kset is not empty"); 927 } 928 929 static void ip_disc_release(struct kobject *kobj) 930 { 931 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 932 kobj); 933 struct amdgpu_device *adev = ip_top->adev; 934 935 adev->ip_top = NULL; 936 kfree(ip_top); 937 } 938 939 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 940 uint16_t hw_id, uint8_t inst) 941 { 942 uint8_t harvest = 0; 943 944 /* Until a uniform way is figured, get mask based on hwid */ 945 switch (hw_id) { 946 case VCN_HWID: 947 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 948 break; 949 case DMU_HWID: 950 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 951 harvest = 0x1; 952 break; 953 case UMC_HWID: 954 /* TODO: It needs another parsing; for now, ignore.*/ 955 break; 956 case GC_HWID: 957 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 958 break; 959 case SDMA0_HWID: 960 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 961 break; 962 default: 963 break; 964 } 965 966 return harvest; 967 } 968 969 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 970 struct ip_die_entry *ip_die_entry, 971 const size_t _ip_offset, const int num_ips, 972 bool reg_base_64) 973 { 974 int ii, jj, kk, res; 975 976 DRM_DEBUG("num_ips:%d", num_ips); 977 978 /* Find all IPs of a given HW ID, and add their instance to 979 * #die/#hw_id/#instance/<attributes> 980 */ 981 for (ii = 0; ii < HW_ID_MAX; ii++) { 982 struct ip_hw_id *ip_hw_id = NULL; 983 size_t ip_offset = _ip_offset; 984 985 for (jj = 0; jj < num_ips; jj++) { 986 struct ip_v4 *ip; 987 struct ip_hw_instance *ip_hw_instance; 988 989 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 990 if (amdgpu_discovery_validate_ip(ip) || 991 le16_to_cpu(ip->hw_id) != ii) 992 goto next_ip; 993 994 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 995 996 /* We have a hw_id match; register the hw 997 * block if not yet registered. 998 */ 999 if (!ip_hw_id) { 1000 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1001 if (!ip_hw_id) 1002 return -ENOMEM; 1003 ip_hw_id->hw_id = ii; 1004 1005 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1006 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1007 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1008 res = kset_register(&ip_hw_id->hw_id_kset); 1009 if (res) { 1010 DRM_ERROR("Couldn't register ip_hw_id kset"); 1011 kfree(ip_hw_id); 1012 return res; 1013 } 1014 if (hw_id_names[ii]) { 1015 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1016 &ip_hw_id->hw_id_kset.kobj, 1017 hw_id_names[ii]); 1018 if (res) { 1019 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1020 hw_id_names[ii], 1021 kobject_name(&ip_die_entry->ip_kset.kobj)); 1022 } 1023 } 1024 } 1025 1026 /* Now register its instance. 1027 */ 1028 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1029 base_addr, 1030 ip->num_base_address), 1031 GFP_KERNEL); 1032 if (!ip_hw_instance) { 1033 DRM_ERROR("no memory for ip_hw_instance"); 1034 return -ENOMEM; 1035 } 1036 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1037 ip_hw_instance->num_instance = ip->instance_number; 1038 ip_hw_instance->major = ip->major; 1039 ip_hw_instance->minor = ip->minor; 1040 ip_hw_instance->revision = ip->revision; 1041 ip_hw_instance->harvest = 1042 amdgpu_discovery_get_harvest_info( 1043 adev, ip_hw_instance->hw_id, 1044 ip_hw_instance->num_instance); 1045 ip_hw_instance->num_base_addresses = ip->num_base_address; 1046 1047 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1048 if (reg_base_64) 1049 ip_hw_instance->base_addr[kk] = 1050 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1051 else 1052 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1053 } 1054 1055 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1056 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1057 res = kobject_add(&ip_hw_instance->kobj, NULL, 1058 "%d", ip_hw_instance->num_instance); 1059 next_ip: 1060 if (reg_base_64) 1061 ip_offset += struct_size(ip, base_address_64, 1062 ip->num_base_address); 1063 else 1064 ip_offset += struct_size(ip, base_address, 1065 ip->num_base_address); 1066 } 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1073 { 1074 struct binary_header *bhdr; 1075 struct ip_discovery_header *ihdr; 1076 struct die_header *dhdr; 1077 struct kset *die_kset = &adev->ip_top->die_kset; 1078 u16 num_dies, die_offset, num_ips; 1079 size_t ip_offset; 1080 int ii, res; 1081 1082 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1083 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1084 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1085 num_dies = le16_to_cpu(ihdr->num_dies); 1086 1087 DRM_DEBUG("number of dies: %d\n", num_dies); 1088 1089 for (ii = 0; ii < num_dies; ii++) { 1090 struct ip_die_entry *ip_die_entry; 1091 1092 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1093 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1094 num_ips = le16_to_cpu(dhdr->num_ips); 1095 ip_offset = die_offset + sizeof(*dhdr); 1096 1097 /* Add the die to the kset. 1098 * 1099 * dhdr->die_id == ii, which was checked in 1100 * amdgpu_discovery_reg_base_init(). 1101 */ 1102 1103 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1104 if (!ip_die_entry) 1105 return -ENOMEM; 1106 1107 ip_die_entry->num_ips = num_ips; 1108 1109 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1110 ip_die_entry->ip_kset.kobj.kset = die_kset; 1111 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1112 res = kset_register(&ip_die_entry->ip_kset); 1113 if (res) { 1114 DRM_ERROR("Couldn't register ip_die_entry kset"); 1115 kfree(ip_die_entry); 1116 return res; 1117 } 1118 1119 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1126 { 1127 struct kset *die_kset; 1128 int res, ii; 1129 1130 if (!adev->mman.discovery_bin) 1131 return -EINVAL; 1132 1133 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1134 if (!adev->ip_top) 1135 return -ENOMEM; 1136 1137 adev->ip_top->adev = adev; 1138 1139 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1140 &adev->dev->kobj, "ip_discovery"); 1141 if (res) { 1142 DRM_ERROR("Couldn't init and add ip_discovery/"); 1143 goto Err; 1144 } 1145 1146 die_kset = &adev->ip_top->die_kset; 1147 kobject_set_name(&die_kset->kobj, "%s", "die"); 1148 die_kset->kobj.parent = &adev->ip_top->kobj; 1149 die_kset->kobj.ktype = &die_kobj_ktype; 1150 res = kset_register(&adev->ip_top->die_kset); 1151 if (res) { 1152 DRM_ERROR("Couldn't register die_kset"); 1153 goto Err; 1154 } 1155 1156 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1157 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1158 ip_hw_instance_attrs[ii] = NULL; 1159 1160 res = amdgpu_discovery_sysfs_recurse(adev); 1161 1162 return res; 1163 Err: 1164 kobject_put(&adev->ip_top->kobj); 1165 return res; 1166 } 1167 1168 /* -------------------------------------------------- */ 1169 1170 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1171 1172 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1173 { 1174 struct list_head *el, *tmp; 1175 struct kset *hw_id_kset; 1176 1177 hw_id_kset = &ip_hw_id->hw_id_kset; 1178 spin_lock(&hw_id_kset->list_lock); 1179 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1180 list_del_init(el); 1181 spin_unlock(&hw_id_kset->list_lock); 1182 /* kobject is embedded in ip_hw_instance */ 1183 kobject_put(list_to_kobj(el)); 1184 spin_lock(&hw_id_kset->list_lock); 1185 } 1186 spin_unlock(&hw_id_kset->list_lock); 1187 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1188 } 1189 1190 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1191 { 1192 struct list_head *el, *tmp; 1193 struct kset *ip_kset; 1194 1195 ip_kset = &ip_die_entry->ip_kset; 1196 spin_lock(&ip_kset->list_lock); 1197 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1198 list_del_init(el); 1199 spin_unlock(&ip_kset->list_lock); 1200 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1201 spin_lock(&ip_kset->list_lock); 1202 } 1203 spin_unlock(&ip_kset->list_lock); 1204 kobject_put(&ip_die_entry->ip_kset.kobj); 1205 } 1206 1207 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1208 { 1209 struct list_head *el, *tmp; 1210 struct kset *die_kset; 1211 1212 die_kset = &adev->ip_top->die_kset; 1213 spin_lock(&die_kset->list_lock); 1214 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1215 list_del_init(el); 1216 spin_unlock(&die_kset->list_lock); 1217 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1218 spin_lock(&die_kset->list_lock); 1219 } 1220 spin_unlock(&die_kset->list_lock); 1221 kobject_put(&adev->ip_top->die_kset.kobj); 1222 kobject_put(&adev->ip_top->kobj); 1223 } 1224 1225 /* ================================================== */ 1226 1227 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1228 { 1229 uint8_t num_base_address, subrev, variant; 1230 struct binary_header *bhdr; 1231 struct ip_discovery_header *ihdr; 1232 struct die_header *dhdr; 1233 struct ip_v4 *ip; 1234 uint16_t die_offset; 1235 uint16_t ip_offset; 1236 uint16_t num_dies; 1237 uint16_t num_ips; 1238 int hw_ip; 1239 int i, j, k; 1240 int r; 1241 1242 r = amdgpu_discovery_init(adev); 1243 if (r) { 1244 DRM_ERROR("amdgpu_discovery_init failed\n"); 1245 return r; 1246 } 1247 1248 adev->gfx.xcc_mask = 0; 1249 adev->sdma.sdma_mask = 0; 1250 adev->vcn.inst_mask = 0; 1251 adev->jpeg.inst_mask = 0; 1252 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1253 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1254 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1255 num_dies = le16_to_cpu(ihdr->num_dies); 1256 1257 DRM_DEBUG("number of dies: %d\n", num_dies); 1258 1259 for (i = 0; i < num_dies; i++) { 1260 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1261 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1262 num_ips = le16_to_cpu(dhdr->num_ips); 1263 ip_offset = die_offset + sizeof(*dhdr); 1264 1265 if (le16_to_cpu(dhdr->die_id) != i) { 1266 DRM_ERROR("invalid die id %d, expected %d\n", 1267 le16_to_cpu(dhdr->die_id), i); 1268 return -EINVAL; 1269 } 1270 1271 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1272 le16_to_cpu(dhdr->die_id), num_ips); 1273 1274 for (j = 0; j < num_ips; j++) { 1275 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1276 1277 if (amdgpu_discovery_validate_ip(ip)) 1278 goto next_ip; 1279 1280 num_base_address = ip->num_base_address; 1281 1282 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1283 hw_id_names[le16_to_cpu(ip->hw_id)], 1284 le16_to_cpu(ip->hw_id), 1285 ip->instance_number, 1286 ip->major, ip->minor, 1287 ip->revision); 1288 1289 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1290 /* Bit [5:0]: original revision value 1291 * Bit [7:6]: en/decode capability: 1292 * 0b00 : VCN function normally 1293 * 0b10 : encode is disabled 1294 * 0b01 : decode is disabled 1295 */ 1296 if (adev->vcn.num_vcn_inst < 1297 AMDGPU_MAX_VCN_INSTANCES) { 1298 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1299 ip->revision & 0xc0; 1300 adev->vcn.num_vcn_inst++; 1301 adev->vcn.inst_mask |= 1302 (1U << ip->instance_number); 1303 adev->jpeg.inst_mask |= 1304 (1U << ip->instance_number); 1305 } else { 1306 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1307 adev->vcn.num_vcn_inst + 1, 1308 AMDGPU_MAX_VCN_INSTANCES); 1309 } 1310 ip->revision &= ~0xc0; 1311 } 1312 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1313 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1314 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1315 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1316 if (adev->sdma.num_instances < 1317 AMDGPU_MAX_SDMA_INSTANCES) { 1318 adev->sdma.num_instances++; 1319 adev->sdma.sdma_mask |= 1320 (1U << ip->instance_number); 1321 } else { 1322 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1323 adev->sdma.num_instances + 1, 1324 AMDGPU_MAX_SDMA_INSTANCES); 1325 } 1326 } 1327 1328 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1329 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1330 adev->vpe.num_instances++; 1331 else 1332 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1333 adev->vpe.num_instances + 1, 1334 AMDGPU_MAX_VPE_INSTANCES); 1335 } 1336 1337 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1338 adev->gmc.num_umc++; 1339 adev->umc.node_inst_num++; 1340 } 1341 1342 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1343 adev->gfx.xcc_mask |= 1344 (1U << ip->instance_number); 1345 1346 for (k = 0; k < num_base_address; k++) { 1347 /* 1348 * convert the endianness of base addresses in place, 1349 * so that we don't need to convert them when accessing adev->reg_offset. 1350 */ 1351 if (ihdr->base_addr_64_bit) 1352 /* Truncate the 64bit base address from ip discovery 1353 * and only store lower 32bit ip base in reg_offset[]. 1354 * Bits > 32 follows ASIC specific format, thus just 1355 * discard them and handle it within specific ASIC. 1356 * By this way reg_offset[] and related helpers can 1357 * stay unchanged. 1358 * The base address is in dwords, thus clear the 1359 * highest 2 bits to store. 1360 */ 1361 ip->base_address[k] = 1362 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1363 else 1364 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1365 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1366 } 1367 1368 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1369 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1370 hw_id_map[hw_ip] != 0) { 1371 DRM_DEBUG("set register base offset for %s\n", 1372 hw_id_names[le16_to_cpu(ip->hw_id)]); 1373 adev->reg_offset[hw_ip][ip->instance_number] = 1374 ip->base_address; 1375 /* Instance support is somewhat inconsistent. 1376 * SDMA is a good example. Sienna cichlid has 4 total 1377 * SDMA instances, each enumerated separately (HWIDs 1378 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1379 * but they are enumerated as multiple instances of the 1380 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1381 * example. On most chips there are multiple instances 1382 * with the same HWID. 1383 */ 1384 1385 if (ihdr->version < 3) { 1386 subrev = 0; 1387 variant = 0; 1388 } else { 1389 subrev = ip->sub_revision; 1390 variant = ip->variant; 1391 } 1392 1393 adev->ip_versions[hw_ip] 1394 [ip->instance_number] = 1395 IP_VERSION_FULL(ip->major, 1396 ip->minor, 1397 ip->revision, 1398 variant, 1399 subrev); 1400 } 1401 } 1402 1403 next_ip: 1404 if (ihdr->base_addr_64_bit) 1405 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1406 else 1407 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1408 } 1409 } 1410 1411 return 0; 1412 } 1413 1414 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1415 { 1416 int vcn_harvest_count = 0; 1417 int umc_harvest_count = 0; 1418 1419 /* 1420 * Harvest table does not fit Navi1x and legacy GPUs, 1421 * so read harvest bit per IP data structure to set 1422 * harvest configuration. 1423 */ 1424 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1425 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) { 1426 if ((adev->pdev->device == 0x731E && 1427 (adev->pdev->revision == 0xC6 || 1428 adev->pdev->revision == 0xC7)) || 1429 (adev->pdev->device == 0x7340 && 1430 adev->pdev->revision == 0xC9) || 1431 (adev->pdev->device == 0x7360 && 1432 adev->pdev->revision == 0xC7)) 1433 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1434 &vcn_harvest_count); 1435 } else { 1436 amdgpu_discovery_read_from_harvest_table(adev, 1437 &vcn_harvest_count, 1438 &umc_harvest_count); 1439 } 1440 1441 amdgpu_discovery_harvest_config_quirk(adev); 1442 1443 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1444 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1445 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1446 } 1447 1448 if (umc_harvest_count < adev->gmc.num_umc) { 1449 adev->gmc.num_umc -= umc_harvest_count; 1450 } 1451 } 1452 1453 union gc_info { 1454 struct gc_info_v1_0 v1; 1455 struct gc_info_v1_1 v1_1; 1456 struct gc_info_v1_2 v1_2; 1457 struct gc_info_v2_0 v2; 1458 struct gc_info_v2_1 v2_1; 1459 }; 1460 1461 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1462 { 1463 struct binary_header *bhdr; 1464 union gc_info *gc_info; 1465 u16 offset; 1466 1467 if (!adev->mman.discovery_bin) { 1468 DRM_ERROR("ip discovery uninitialized\n"); 1469 return -EINVAL; 1470 } 1471 1472 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1473 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1474 1475 if (!offset) 1476 return 0; 1477 1478 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1479 1480 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1481 case 1: 1482 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1483 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1484 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1485 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1486 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1487 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1488 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1489 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1490 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1491 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1492 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1493 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1494 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1495 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1496 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1497 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1498 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1499 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1500 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1501 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1502 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1503 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1504 } 1505 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1506 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1507 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1508 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1509 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1510 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1511 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1512 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1513 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1514 } 1515 break; 1516 case 2: 1517 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1518 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1519 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1520 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1521 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1522 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1523 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1524 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1525 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1526 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1527 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1528 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1529 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1530 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1531 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1532 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1533 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1534 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1535 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1536 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1537 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1538 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1539 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1540 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1541 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1542 } 1543 break; 1544 default: 1545 dev_err(adev->dev, 1546 "Unhandled GC info table %d.%d\n", 1547 le16_to_cpu(gc_info->v1.header.version_major), 1548 le16_to_cpu(gc_info->v1.header.version_minor)); 1549 return -EINVAL; 1550 } 1551 return 0; 1552 } 1553 1554 union mall_info { 1555 struct mall_info_v1_0 v1; 1556 struct mall_info_v2_0 v2; 1557 }; 1558 1559 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1560 { 1561 struct binary_header *bhdr; 1562 union mall_info *mall_info; 1563 u32 u, mall_size_per_umc, m_s_present, half_use; 1564 u64 mall_size; 1565 u16 offset; 1566 1567 if (!adev->mman.discovery_bin) { 1568 DRM_ERROR("ip discovery uninitialized\n"); 1569 return -EINVAL; 1570 } 1571 1572 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1573 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1574 1575 if (!offset) 1576 return 0; 1577 1578 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1579 1580 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1581 case 1: 1582 mall_size = 0; 1583 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1584 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1585 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1586 for (u = 0; u < adev->gmc.num_umc; u++) { 1587 if (m_s_present & (1 << u)) 1588 mall_size += mall_size_per_umc * 2; 1589 else if (half_use & (1 << u)) 1590 mall_size += mall_size_per_umc / 2; 1591 else 1592 mall_size += mall_size_per_umc; 1593 } 1594 adev->gmc.mall_size = mall_size; 1595 adev->gmc.m_half_use = half_use; 1596 break; 1597 case 2: 1598 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1599 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; 1600 break; 1601 default: 1602 dev_err(adev->dev, 1603 "Unhandled MALL info table %d.%d\n", 1604 le16_to_cpu(mall_info->v1.header.version_major), 1605 le16_to_cpu(mall_info->v1.header.version_minor)); 1606 return -EINVAL; 1607 } 1608 return 0; 1609 } 1610 1611 union vcn_info { 1612 struct vcn_info_v1_0 v1; 1613 }; 1614 1615 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1616 { 1617 struct binary_header *bhdr; 1618 union vcn_info *vcn_info; 1619 u16 offset; 1620 int v; 1621 1622 if (!adev->mman.discovery_bin) { 1623 DRM_ERROR("ip discovery uninitialized\n"); 1624 return -EINVAL; 1625 } 1626 1627 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1628 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1629 * but that may change in the future with new GPUs so keep this 1630 * check for defensive purposes. 1631 */ 1632 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1633 dev_err(adev->dev, "invalid vcn instances\n"); 1634 return -EINVAL; 1635 } 1636 1637 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1638 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1639 1640 if (!offset) 1641 return 0; 1642 1643 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1644 1645 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1646 case 1: 1647 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1648 * so this won't overflow. 1649 */ 1650 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1651 adev->vcn.vcn_codec_disable_mask[v] = 1652 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1653 } 1654 break; 1655 default: 1656 dev_err(adev->dev, 1657 "Unhandled VCN info table %d.%d\n", 1658 le16_to_cpu(vcn_info->v1.header.version_major), 1659 le16_to_cpu(vcn_info->v1.header.version_minor)); 1660 return -EINVAL; 1661 } 1662 return 0; 1663 } 1664 1665 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1666 { 1667 /* what IP to use for this? */ 1668 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1669 case IP_VERSION(9, 0, 1): 1670 case IP_VERSION(9, 1, 0): 1671 case IP_VERSION(9, 2, 1): 1672 case IP_VERSION(9, 2, 2): 1673 case IP_VERSION(9, 3, 0): 1674 case IP_VERSION(9, 4, 0): 1675 case IP_VERSION(9, 4, 1): 1676 case IP_VERSION(9, 4, 2): 1677 case IP_VERSION(9, 4, 3): 1678 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1679 break; 1680 case IP_VERSION(10, 1, 10): 1681 case IP_VERSION(10, 1, 1): 1682 case IP_VERSION(10, 1, 2): 1683 case IP_VERSION(10, 1, 3): 1684 case IP_VERSION(10, 1, 4): 1685 case IP_VERSION(10, 3, 0): 1686 case IP_VERSION(10, 3, 1): 1687 case IP_VERSION(10, 3, 2): 1688 case IP_VERSION(10, 3, 3): 1689 case IP_VERSION(10, 3, 4): 1690 case IP_VERSION(10, 3, 5): 1691 case IP_VERSION(10, 3, 6): 1692 case IP_VERSION(10, 3, 7): 1693 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1694 break; 1695 case IP_VERSION(11, 0, 0): 1696 case IP_VERSION(11, 0, 1): 1697 case IP_VERSION(11, 0, 2): 1698 case IP_VERSION(11, 0, 3): 1699 case IP_VERSION(11, 0, 4): 1700 case IP_VERSION(11, 5, 0): 1701 case IP_VERSION(11, 5, 1): 1702 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1703 break; 1704 case IP_VERSION(12, 0, 0): 1705 case IP_VERSION(12, 0, 1): 1706 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1707 break; 1708 default: 1709 dev_err(adev->dev, 1710 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1711 amdgpu_ip_version(adev, GC_HWIP, 0)); 1712 return -EINVAL; 1713 } 1714 return 0; 1715 } 1716 1717 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1718 { 1719 /* use GC or MMHUB IP version */ 1720 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1721 case IP_VERSION(9, 0, 1): 1722 case IP_VERSION(9, 1, 0): 1723 case IP_VERSION(9, 2, 1): 1724 case IP_VERSION(9, 2, 2): 1725 case IP_VERSION(9, 3, 0): 1726 case IP_VERSION(9, 4, 0): 1727 case IP_VERSION(9, 4, 1): 1728 case IP_VERSION(9, 4, 2): 1729 case IP_VERSION(9, 4, 3): 1730 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1731 break; 1732 case IP_VERSION(10, 1, 10): 1733 case IP_VERSION(10, 1, 1): 1734 case IP_VERSION(10, 1, 2): 1735 case IP_VERSION(10, 1, 3): 1736 case IP_VERSION(10, 1, 4): 1737 case IP_VERSION(10, 3, 0): 1738 case IP_VERSION(10, 3, 1): 1739 case IP_VERSION(10, 3, 2): 1740 case IP_VERSION(10, 3, 3): 1741 case IP_VERSION(10, 3, 4): 1742 case IP_VERSION(10, 3, 5): 1743 case IP_VERSION(10, 3, 6): 1744 case IP_VERSION(10, 3, 7): 1745 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1746 break; 1747 case IP_VERSION(11, 0, 0): 1748 case IP_VERSION(11, 0, 1): 1749 case IP_VERSION(11, 0, 2): 1750 case IP_VERSION(11, 0, 3): 1751 case IP_VERSION(11, 0, 4): 1752 case IP_VERSION(11, 5, 0): 1753 case IP_VERSION(11, 5, 1): 1754 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1755 break; 1756 default: 1757 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1758 amdgpu_ip_version(adev, GC_HWIP, 0)); 1759 return -EINVAL; 1760 } 1761 return 0; 1762 } 1763 1764 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1765 { 1766 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1767 case IP_VERSION(4, 0, 0): 1768 case IP_VERSION(4, 0, 1): 1769 case IP_VERSION(4, 1, 0): 1770 case IP_VERSION(4, 1, 1): 1771 case IP_VERSION(4, 3, 0): 1772 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1773 break; 1774 case IP_VERSION(4, 2, 0): 1775 case IP_VERSION(4, 2, 1): 1776 case IP_VERSION(4, 4, 0): 1777 case IP_VERSION(4, 4, 2): 1778 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1779 break; 1780 case IP_VERSION(5, 0, 0): 1781 case IP_VERSION(5, 0, 1): 1782 case IP_VERSION(5, 0, 2): 1783 case IP_VERSION(5, 0, 3): 1784 case IP_VERSION(5, 2, 0): 1785 case IP_VERSION(5, 2, 1): 1786 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1787 break; 1788 case IP_VERSION(6, 0, 0): 1789 case IP_VERSION(6, 0, 1): 1790 case IP_VERSION(6, 0, 2): 1791 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1792 break; 1793 case IP_VERSION(6, 1, 0): 1794 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1795 break; 1796 case IP_VERSION(7, 0, 0): 1797 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1798 break; 1799 default: 1800 dev_err(adev->dev, 1801 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1802 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1803 return -EINVAL; 1804 } 1805 return 0; 1806 } 1807 1808 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1809 { 1810 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1811 case IP_VERSION(9, 0, 0): 1812 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1813 break; 1814 case IP_VERSION(10, 0, 0): 1815 case IP_VERSION(10, 0, 1): 1816 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1817 break; 1818 case IP_VERSION(11, 0, 0): 1819 case IP_VERSION(11, 0, 2): 1820 case IP_VERSION(11, 0, 4): 1821 case IP_VERSION(11, 0, 5): 1822 case IP_VERSION(11, 0, 9): 1823 case IP_VERSION(11, 0, 7): 1824 case IP_VERSION(11, 0, 11): 1825 case IP_VERSION(11, 0, 12): 1826 case IP_VERSION(11, 0, 13): 1827 case IP_VERSION(11, 5, 0): 1828 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1829 break; 1830 case IP_VERSION(11, 0, 8): 1831 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1832 break; 1833 case IP_VERSION(11, 0, 3): 1834 case IP_VERSION(12, 0, 1): 1835 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1836 break; 1837 case IP_VERSION(13, 0, 0): 1838 case IP_VERSION(13, 0, 1): 1839 case IP_VERSION(13, 0, 2): 1840 case IP_VERSION(13, 0, 3): 1841 case IP_VERSION(13, 0, 5): 1842 case IP_VERSION(13, 0, 6): 1843 case IP_VERSION(13, 0, 7): 1844 case IP_VERSION(13, 0, 8): 1845 case IP_VERSION(13, 0, 10): 1846 case IP_VERSION(13, 0, 11): 1847 case IP_VERSION(14, 0, 0): 1848 case IP_VERSION(14, 0, 1): 1849 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1850 break; 1851 case IP_VERSION(13, 0, 4): 1852 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1853 break; 1854 case IP_VERSION(14, 0, 2): 1855 case IP_VERSION(14, 0, 3): 1856 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 1857 break; 1858 default: 1859 dev_err(adev->dev, 1860 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1861 amdgpu_ip_version(adev, MP0_HWIP, 0)); 1862 return -EINVAL; 1863 } 1864 return 0; 1865 } 1866 1867 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1868 { 1869 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1870 case IP_VERSION(9, 0, 0): 1871 case IP_VERSION(10, 0, 0): 1872 case IP_VERSION(10, 0, 1): 1873 case IP_VERSION(11, 0, 2): 1874 if (adev->asic_type == CHIP_ARCTURUS) 1875 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1876 else 1877 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1878 break; 1879 case IP_VERSION(11, 0, 0): 1880 case IP_VERSION(11, 0, 5): 1881 case IP_VERSION(11, 0, 9): 1882 case IP_VERSION(11, 0, 7): 1883 case IP_VERSION(11, 0, 8): 1884 case IP_VERSION(11, 0, 11): 1885 case IP_VERSION(11, 0, 12): 1886 case IP_VERSION(11, 0, 13): 1887 case IP_VERSION(11, 5, 0): 1888 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1889 break; 1890 case IP_VERSION(12, 0, 0): 1891 case IP_VERSION(12, 0, 1): 1892 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1893 break; 1894 case IP_VERSION(13, 0, 0): 1895 case IP_VERSION(13, 0, 1): 1896 case IP_VERSION(13, 0, 2): 1897 case IP_VERSION(13, 0, 3): 1898 case IP_VERSION(13, 0, 4): 1899 case IP_VERSION(13, 0, 5): 1900 case IP_VERSION(13, 0, 6): 1901 case IP_VERSION(13, 0, 7): 1902 case IP_VERSION(13, 0, 8): 1903 case IP_VERSION(13, 0, 10): 1904 case IP_VERSION(13, 0, 11): 1905 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1906 break; 1907 case IP_VERSION(14, 0, 0): 1908 case IP_VERSION(14, 0, 1): 1909 case IP_VERSION(14, 0, 2): 1910 case IP_VERSION(14, 0, 3): 1911 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 1912 break; 1913 default: 1914 dev_err(adev->dev, 1915 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1916 amdgpu_ip_version(adev, MP1_HWIP, 0)); 1917 return -EINVAL; 1918 } 1919 return 0; 1920 } 1921 1922 #if defined(CONFIG_DRM_AMD_DC) 1923 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1924 { 1925 amdgpu_device_set_sriov_virtual_display(adev); 1926 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1927 } 1928 #endif 1929 1930 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1931 { 1932 if (adev->enable_virtual_display) { 1933 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1934 return 0; 1935 } 1936 1937 if (!amdgpu_device_has_dc_support(adev)) 1938 return 0; 1939 1940 #if defined(CONFIG_DRM_AMD_DC) 1941 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1942 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1943 case IP_VERSION(1, 0, 0): 1944 case IP_VERSION(1, 0, 1): 1945 case IP_VERSION(2, 0, 2): 1946 case IP_VERSION(2, 0, 0): 1947 case IP_VERSION(2, 0, 3): 1948 case IP_VERSION(2, 1, 0): 1949 case IP_VERSION(3, 0, 0): 1950 case IP_VERSION(3, 0, 2): 1951 case IP_VERSION(3, 0, 3): 1952 case IP_VERSION(3, 0, 1): 1953 case IP_VERSION(3, 1, 2): 1954 case IP_VERSION(3, 1, 3): 1955 case IP_VERSION(3, 1, 4): 1956 case IP_VERSION(3, 1, 5): 1957 case IP_VERSION(3, 1, 6): 1958 case IP_VERSION(3, 2, 0): 1959 case IP_VERSION(3, 2, 1): 1960 case IP_VERSION(3, 5, 0): 1961 case IP_VERSION(3, 5, 1): 1962 if (amdgpu_sriov_vf(adev)) 1963 amdgpu_discovery_set_sriov_display(adev); 1964 else 1965 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1966 break; 1967 default: 1968 dev_err(adev->dev, 1969 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1970 amdgpu_ip_version(adev, DCE_HWIP, 0)); 1971 return -EINVAL; 1972 } 1973 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1974 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1975 case IP_VERSION(12, 0, 0): 1976 case IP_VERSION(12, 0, 1): 1977 case IP_VERSION(12, 1, 0): 1978 if (amdgpu_sriov_vf(adev)) 1979 amdgpu_discovery_set_sriov_display(adev); 1980 else 1981 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1982 break; 1983 default: 1984 dev_err(adev->dev, 1985 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1986 amdgpu_ip_version(adev, DCI_HWIP, 0)); 1987 return -EINVAL; 1988 } 1989 } 1990 #endif 1991 return 0; 1992 } 1993 1994 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1995 { 1996 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1997 case IP_VERSION(9, 0, 1): 1998 case IP_VERSION(9, 1, 0): 1999 case IP_VERSION(9, 2, 1): 2000 case IP_VERSION(9, 2, 2): 2001 case IP_VERSION(9, 3, 0): 2002 case IP_VERSION(9, 4, 0): 2003 case IP_VERSION(9, 4, 1): 2004 case IP_VERSION(9, 4, 2): 2005 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2006 break; 2007 case IP_VERSION(9, 4, 3): 2008 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2009 break; 2010 case IP_VERSION(10, 1, 10): 2011 case IP_VERSION(10, 1, 2): 2012 case IP_VERSION(10, 1, 1): 2013 case IP_VERSION(10, 1, 3): 2014 case IP_VERSION(10, 1, 4): 2015 case IP_VERSION(10, 3, 0): 2016 case IP_VERSION(10, 3, 2): 2017 case IP_VERSION(10, 3, 1): 2018 case IP_VERSION(10, 3, 4): 2019 case IP_VERSION(10, 3, 5): 2020 case IP_VERSION(10, 3, 6): 2021 case IP_VERSION(10, 3, 3): 2022 case IP_VERSION(10, 3, 7): 2023 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2024 break; 2025 case IP_VERSION(11, 0, 0): 2026 case IP_VERSION(11, 0, 1): 2027 case IP_VERSION(11, 0, 2): 2028 case IP_VERSION(11, 0, 3): 2029 case IP_VERSION(11, 0, 4): 2030 case IP_VERSION(11, 5, 0): 2031 case IP_VERSION(11, 5, 1): 2032 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2033 break; 2034 default: 2035 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2036 amdgpu_ip_version(adev, GC_HWIP, 0)); 2037 return -EINVAL; 2038 } 2039 return 0; 2040 } 2041 2042 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2043 { 2044 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2045 case IP_VERSION(4, 0, 0): 2046 case IP_VERSION(4, 0, 1): 2047 case IP_VERSION(4, 1, 0): 2048 case IP_VERSION(4, 1, 1): 2049 case IP_VERSION(4, 1, 2): 2050 case IP_VERSION(4, 2, 0): 2051 case IP_VERSION(4, 2, 2): 2052 case IP_VERSION(4, 4, 0): 2053 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2054 break; 2055 case IP_VERSION(4, 4, 2): 2056 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2057 break; 2058 case IP_VERSION(5, 0, 0): 2059 case IP_VERSION(5, 0, 1): 2060 case IP_VERSION(5, 0, 2): 2061 case IP_VERSION(5, 0, 5): 2062 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2063 break; 2064 case IP_VERSION(5, 2, 0): 2065 case IP_VERSION(5, 2, 2): 2066 case IP_VERSION(5, 2, 4): 2067 case IP_VERSION(5, 2, 5): 2068 case IP_VERSION(5, 2, 6): 2069 case IP_VERSION(5, 2, 3): 2070 case IP_VERSION(5, 2, 1): 2071 case IP_VERSION(5, 2, 7): 2072 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2073 break; 2074 case IP_VERSION(6, 0, 0): 2075 case IP_VERSION(6, 0, 1): 2076 case IP_VERSION(6, 0, 2): 2077 case IP_VERSION(6, 0, 3): 2078 case IP_VERSION(6, 1, 0): 2079 case IP_VERSION(6, 1, 1): 2080 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2081 break; 2082 default: 2083 dev_err(adev->dev, 2084 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2085 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2086 return -EINVAL; 2087 } 2088 return 0; 2089 } 2090 2091 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2092 { 2093 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2094 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2095 case IP_VERSION(7, 0, 0): 2096 case IP_VERSION(7, 2, 0): 2097 /* UVD is not supported on vega20 SR-IOV */ 2098 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2099 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2100 break; 2101 default: 2102 dev_err(adev->dev, 2103 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2104 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2105 return -EINVAL; 2106 } 2107 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2108 case IP_VERSION(4, 0, 0): 2109 case IP_VERSION(4, 1, 0): 2110 /* VCE is not supported on vega20 SR-IOV */ 2111 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2112 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2113 break; 2114 default: 2115 dev_err(adev->dev, 2116 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2117 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2118 return -EINVAL; 2119 } 2120 } else { 2121 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2122 case IP_VERSION(1, 0, 0): 2123 case IP_VERSION(1, 0, 1): 2124 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2125 break; 2126 case IP_VERSION(2, 0, 0): 2127 case IP_VERSION(2, 0, 2): 2128 case IP_VERSION(2, 2, 0): 2129 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2130 if (!amdgpu_sriov_vf(adev)) 2131 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2132 break; 2133 case IP_VERSION(2, 0, 3): 2134 break; 2135 case IP_VERSION(2, 5, 0): 2136 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2137 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2138 break; 2139 case IP_VERSION(2, 6, 0): 2140 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2141 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2142 break; 2143 case IP_VERSION(3, 0, 0): 2144 case IP_VERSION(3, 0, 16): 2145 case IP_VERSION(3, 1, 1): 2146 case IP_VERSION(3, 1, 2): 2147 case IP_VERSION(3, 0, 2): 2148 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2149 if (!amdgpu_sriov_vf(adev)) 2150 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2151 break; 2152 case IP_VERSION(3, 0, 33): 2153 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2154 break; 2155 case IP_VERSION(4, 0, 0): 2156 case IP_VERSION(4, 0, 2): 2157 case IP_VERSION(4, 0, 4): 2158 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2159 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2160 break; 2161 case IP_VERSION(4, 0, 3): 2162 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2163 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2164 break; 2165 case IP_VERSION(4, 0, 5): 2166 case IP_VERSION(4, 0, 6): 2167 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2168 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2169 break; 2170 case IP_VERSION(5, 0, 0): 2171 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2172 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2173 break; 2174 default: 2175 dev_err(adev->dev, 2176 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2177 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2178 return -EINVAL; 2179 } 2180 } 2181 return 0; 2182 } 2183 2184 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2185 { 2186 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2187 case IP_VERSION(10, 1, 10): 2188 case IP_VERSION(10, 1, 1): 2189 case IP_VERSION(10, 1, 2): 2190 case IP_VERSION(10, 1, 3): 2191 case IP_VERSION(10, 1, 4): 2192 case IP_VERSION(10, 3, 0): 2193 case IP_VERSION(10, 3, 1): 2194 case IP_VERSION(10, 3, 2): 2195 case IP_VERSION(10, 3, 3): 2196 case IP_VERSION(10, 3, 4): 2197 case IP_VERSION(10, 3, 5): 2198 case IP_VERSION(10, 3, 6): 2199 if (amdgpu_mes) { 2200 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 2201 adev->enable_mes = true; 2202 if (amdgpu_mes_kiq) 2203 adev->enable_mes_kiq = true; 2204 } 2205 break; 2206 case IP_VERSION(11, 0, 0): 2207 case IP_VERSION(11, 0, 1): 2208 case IP_VERSION(11, 0, 2): 2209 case IP_VERSION(11, 0, 3): 2210 case IP_VERSION(11, 0, 4): 2211 case IP_VERSION(11, 5, 0): 2212 case IP_VERSION(11, 5, 1): 2213 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2214 adev->enable_mes = true; 2215 adev->enable_mes_kiq = true; 2216 break; 2217 default: 2218 break; 2219 } 2220 return 0; 2221 } 2222 2223 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2224 { 2225 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2226 case IP_VERSION(9, 4, 3): 2227 aqua_vanjaram_init_soc_config(adev); 2228 break; 2229 default: 2230 break; 2231 } 2232 } 2233 2234 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2235 { 2236 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2237 case IP_VERSION(6, 1, 0): 2238 case IP_VERSION(6, 1, 1): 2239 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2240 break; 2241 default: 2242 break; 2243 } 2244 2245 return 0; 2246 } 2247 2248 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2249 { 2250 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2251 case IP_VERSION(4, 0, 5): 2252 case IP_VERSION(4, 0, 6): 2253 if (amdgpu_umsch_mm & 0x1) { 2254 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2255 adev->enable_umsch_mm = true; 2256 } 2257 break; 2258 default: 2259 break; 2260 } 2261 2262 return 0; 2263 } 2264 2265 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2266 { 2267 int r; 2268 2269 switch (adev->asic_type) { 2270 case CHIP_VEGA10: 2271 vega10_reg_base_init(adev); 2272 adev->sdma.num_instances = 2; 2273 adev->gmc.num_umc = 4; 2274 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2275 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2276 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2277 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2278 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2279 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2280 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2281 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2282 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2283 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2284 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2285 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2286 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2287 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2288 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2289 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2290 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2291 break; 2292 case CHIP_VEGA12: 2293 vega10_reg_base_init(adev); 2294 adev->sdma.num_instances = 2; 2295 adev->gmc.num_umc = 4; 2296 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2297 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2298 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2299 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2300 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2301 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2302 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2303 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2304 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2305 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2306 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2307 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2308 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2309 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2310 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2311 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2312 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2313 break; 2314 case CHIP_RAVEN: 2315 vega10_reg_base_init(adev); 2316 adev->sdma.num_instances = 1; 2317 adev->vcn.num_vcn_inst = 1; 2318 adev->gmc.num_umc = 2; 2319 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2320 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2321 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2322 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2323 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2324 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2325 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2326 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2327 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2328 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2329 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2330 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2331 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2332 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2333 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2334 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2335 } else { 2336 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2337 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2338 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2339 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2340 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2341 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2342 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2343 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2344 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2345 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2346 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2347 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2348 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2349 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2350 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2351 } 2352 break; 2353 case CHIP_VEGA20: 2354 vega20_reg_base_init(adev); 2355 adev->sdma.num_instances = 2; 2356 adev->gmc.num_umc = 8; 2357 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2358 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2359 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2360 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2361 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2362 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2363 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2364 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2365 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2366 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2367 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2368 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2369 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2370 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2371 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2372 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2373 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2374 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2375 break; 2376 case CHIP_ARCTURUS: 2377 arct_reg_base_init(adev); 2378 adev->sdma.num_instances = 8; 2379 adev->vcn.num_vcn_inst = 2; 2380 adev->gmc.num_umc = 8; 2381 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2382 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2383 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2384 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2385 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2386 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2387 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2388 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2389 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2390 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2391 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2392 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2393 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2394 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2395 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2396 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2397 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2398 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2399 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2400 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2401 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2402 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2403 break; 2404 case CHIP_ALDEBARAN: 2405 aldebaran_reg_base_init(adev); 2406 adev->sdma.num_instances = 5; 2407 adev->vcn.num_vcn_inst = 2; 2408 adev->gmc.num_umc = 4; 2409 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2410 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2411 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2412 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2413 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2414 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2415 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2416 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2417 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2418 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2419 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2420 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2421 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2422 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2423 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2424 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2425 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2426 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2427 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2428 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2429 break; 2430 default: 2431 r = amdgpu_discovery_reg_base_init(adev); 2432 if (r) 2433 return -EINVAL; 2434 2435 amdgpu_discovery_harvest_ip(adev); 2436 amdgpu_discovery_get_gfx_info(adev); 2437 amdgpu_discovery_get_mall_info(adev); 2438 amdgpu_discovery_get_vcn_info(adev); 2439 break; 2440 } 2441 2442 amdgpu_discovery_init_soc_config(adev); 2443 amdgpu_discovery_sysfs_init(adev); 2444 2445 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2446 case IP_VERSION(9, 0, 1): 2447 case IP_VERSION(9, 2, 1): 2448 case IP_VERSION(9, 4, 0): 2449 case IP_VERSION(9, 4, 1): 2450 case IP_VERSION(9, 4, 2): 2451 case IP_VERSION(9, 4, 3): 2452 adev->family = AMDGPU_FAMILY_AI; 2453 break; 2454 case IP_VERSION(9, 1, 0): 2455 case IP_VERSION(9, 2, 2): 2456 case IP_VERSION(9, 3, 0): 2457 adev->family = AMDGPU_FAMILY_RV; 2458 break; 2459 case IP_VERSION(10, 1, 10): 2460 case IP_VERSION(10, 1, 1): 2461 case IP_VERSION(10, 1, 2): 2462 case IP_VERSION(10, 1, 3): 2463 case IP_VERSION(10, 1, 4): 2464 case IP_VERSION(10, 3, 0): 2465 case IP_VERSION(10, 3, 2): 2466 case IP_VERSION(10, 3, 4): 2467 case IP_VERSION(10, 3, 5): 2468 adev->family = AMDGPU_FAMILY_NV; 2469 break; 2470 case IP_VERSION(10, 3, 1): 2471 adev->family = AMDGPU_FAMILY_VGH; 2472 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2473 break; 2474 case IP_VERSION(10, 3, 3): 2475 adev->family = AMDGPU_FAMILY_YC; 2476 break; 2477 case IP_VERSION(10, 3, 6): 2478 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2479 break; 2480 case IP_VERSION(10, 3, 7): 2481 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2482 break; 2483 case IP_VERSION(11, 0, 0): 2484 case IP_VERSION(11, 0, 2): 2485 case IP_VERSION(11, 0, 3): 2486 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2487 break; 2488 case IP_VERSION(11, 0, 1): 2489 case IP_VERSION(11, 0, 4): 2490 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2491 break; 2492 case IP_VERSION(11, 5, 0): 2493 case IP_VERSION(11, 5, 1): 2494 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2495 break; 2496 default: 2497 return -EINVAL; 2498 } 2499 2500 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2501 case IP_VERSION(9, 1, 0): 2502 case IP_VERSION(9, 2, 2): 2503 case IP_VERSION(9, 3, 0): 2504 case IP_VERSION(10, 1, 3): 2505 case IP_VERSION(10, 1, 4): 2506 case IP_VERSION(10, 3, 1): 2507 case IP_VERSION(10, 3, 3): 2508 case IP_VERSION(10, 3, 6): 2509 case IP_VERSION(10, 3, 7): 2510 case IP_VERSION(11, 0, 1): 2511 case IP_VERSION(11, 0, 4): 2512 case IP_VERSION(11, 5, 0): 2513 case IP_VERSION(11, 5, 1): 2514 adev->flags |= AMD_IS_APU; 2515 break; 2516 default: 2517 break; 2518 } 2519 2520 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2521 adev->gmc.xgmi.supported = true; 2522 2523 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2524 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2525 2526 /* set NBIO version */ 2527 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2528 case IP_VERSION(6, 1, 0): 2529 case IP_VERSION(6, 2, 0): 2530 adev->nbio.funcs = &nbio_v6_1_funcs; 2531 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2532 break; 2533 case IP_VERSION(7, 0, 0): 2534 case IP_VERSION(7, 0, 1): 2535 case IP_VERSION(2, 5, 0): 2536 adev->nbio.funcs = &nbio_v7_0_funcs; 2537 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2538 break; 2539 case IP_VERSION(7, 4, 0): 2540 case IP_VERSION(7, 4, 1): 2541 case IP_VERSION(7, 4, 4): 2542 adev->nbio.funcs = &nbio_v7_4_funcs; 2543 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2544 break; 2545 case IP_VERSION(7, 9, 0): 2546 adev->nbio.funcs = &nbio_v7_9_funcs; 2547 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2548 break; 2549 case IP_VERSION(7, 11, 0): 2550 case IP_VERSION(7, 11, 1): 2551 adev->nbio.funcs = &nbio_v7_11_funcs; 2552 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2553 break; 2554 case IP_VERSION(7, 2, 0): 2555 case IP_VERSION(7, 2, 1): 2556 case IP_VERSION(7, 3, 0): 2557 case IP_VERSION(7, 5, 0): 2558 case IP_VERSION(7, 5, 1): 2559 adev->nbio.funcs = &nbio_v7_2_funcs; 2560 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2561 break; 2562 case IP_VERSION(2, 1, 1): 2563 case IP_VERSION(2, 3, 0): 2564 case IP_VERSION(2, 3, 1): 2565 case IP_VERSION(2, 3, 2): 2566 case IP_VERSION(3, 3, 0): 2567 case IP_VERSION(3, 3, 1): 2568 case IP_VERSION(3, 3, 2): 2569 case IP_VERSION(3, 3, 3): 2570 adev->nbio.funcs = &nbio_v2_3_funcs; 2571 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2572 break; 2573 case IP_VERSION(4, 3, 0): 2574 case IP_VERSION(4, 3, 1): 2575 if (amdgpu_sriov_vf(adev)) 2576 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2577 else 2578 adev->nbio.funcs = &nbio_v4_3_funcs; 2579 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2580 break; 2581 case IP_VERSION(7, 7, 0): 2582 case IP_VERSION(7, 7, 1): 2583 adev->nbio.funcs = &nbio_v7_7_funcs; 2584 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2585 break; 2586 case IP_VERSION(6, 3, 1): 2587 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2588 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2589 break; 2590 default: 2591 break; 2592 } 2593 2594 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2595 case IP_VERSION(4, 0, 0): 2596 case IP_VERSION(4, 0, 1): 2597 case IP_VERSION(4, 1, 0): 2598 case IP_VERSION(4, 1, 1): 2599 case IP_VERSION(4, 1, 2): 2600 case IP_VERSION(4, 2, 0): 2601 case IP_VERSION(4, 2, 1): 2602 case IP_VERSION(4, 4, 0): 2603 case IP_VERSION(4, 4, 2): 2604 adev->hdp.funcs = &hdp_v4_0_funcs; 2605 break; 2606 case IP_VERSION(5, 0, 0): 2607 case IP_VERSION(5, 0, 1): 2608 case IP_VERSION(5, 0, 2): 2609 case IP_VERSION(5, 0, 3): 2610 case IP_VERSION(5, 0, 4): 2611 case IP_VERSION(5, 2, 0): 2612 adev->hdp.funcs = &hdp_v5_0_funcs; 2613 break; 2614 case IP_VERSION(5, 2, 1): 2615 adev->hdp.funcs = &hdp_v5_2_funcs; 2616 break; 2617 case IP_VERSION(6, 0, 0): 2618 case IP_VERSION(6, 0, 1): 2619 case IP_VERSION(6, 1, 0): 2620 adev->hdp.funcs = &hdp_v6_0_funcs; 2621 break; 2622 case IP_VERSION(7, 0, 0): 2623 adev->hdp.funcs = &hdp_v7_0_funcs; 2624 break; 2625 default: 2626 break; 2627 } 2628 2629 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2630 case IP_VERSION(3, 6, 0): 2631 case IP_VERSION(3, 6, 1): 2632 case IP_VERSION(3, 6, 2): 2633 adev->df.funcs = &df_v3_6_funcs; 2634 break; 2635 case IP_VERSION(2, 1, 0): 2636 case IP_VERSION(2, 1, 1): 2637 case IP_VERSION(2, 5, 0): 2638 case IP_VERSION(3, 5, 1): 2639 case IP_VERSION(3, 5, 2): 2640 adev->df.funcs = &df_v1_7_funcs; 2641 break; 2642 case IP_VERSION(4, 3, 0): 2643 adev->df.funcs = &df_v4_3_funcs; 2644 break; 2645 case IP_VERSION(4, 6, 2): 2646 adev->df.funcs = &df_v4_6_2_funcs; 2647 break; 2648 default: 2649 break; 2650 } 2651 2652 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2653 case IP_VERSION(9, 0, 0): 2654 case IP_VERSION(9, 0, 1): 2655 case IP_VERSION(10, 0, 0): 2656 case IP_VERSION(10, 0, 1): 2657 case IP_VERSION(10, 0, 2): 2658 adev->smuio.funcs = &smuio_v9_0_funcs; 2659 break; 2660 case IP_VERSION(11, 0, 0): 2661 case IP_VERSION(11, 0, 2): 2662 case IP_VERSION(11, 0, 3): 2663 case IP_VERSION(11, 0, 4): 2664 case IP_VERSION(11, 0, 7): 2665 case IP_VERSION(11, 0, 8): 2666 adev->smuio.funcs = &smuio_v11_0_funcs; 2667 break; 2668 case IP_VERSION(11, 0, 6): 2669 case IP_VERSION(11, 0, 10): 2670 case IP_VERSION(11, 0, 11): 2671 case IP_VERSION(11, 5, 0): 2672 case IP_VERSION(13, 0, 1): 2673 case IP_VERSION(13, 0, 9): 2674 case IP_VERSION(13, 0, 10): 2675 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2676 break; 2677 case IP_VERSION(13, 0, 2): 2678 adev->smuio.funcs = &smuio_v13_0_funcs; 2679 break; 2680 case IP_VERSION(13, 0, 3): 2681 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2682 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2683 adev->flags |= AMD_IS_APU; 2684 } 2685 break; 2686 case IP_VERSION(13, 0, 6): 2687 case IP_VERSION(13, 0, 8): 2688 case IP_VERSION(14, 0, 0): 2689 case IP_VERSION(14, 0, 1): 2690 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2691 break; 2692 case IP_VERSION(14, 0, 2): 2693 adev->smuio.funcs = &smuio_v14_0_2_funcs; 2694 break; 2695 default: 2696 break; 2697 } 2698 2699 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2700 case IP_VERSION(6, 0, 0): 2701 case IP_VERSION(6, 0, 1): 2702 case IP_VERSION(6, 0, 2): 2703 case IP_VERSION(6, 0, 3): 2704 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2705 break; 2706 case IP_VERSION(7, 0, 0): 2707 case IP_VERSION(7, 0, 1): 2708 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2709 break; 2710 default: 2711 break; 2712 } 2713 2714 r = amdgpu_discovery_set_common_ip_blocks(adev); 2715 if (r) 2716 return r; 2717 2718 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2719 if (r) 2720 return r; 2721 2722 /* For SR-IOV, PSP needs to be initialized before IH */ 2723 if (amdgpu_sriov_vf(adev)) { 2724 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2725 if (r) 2726 return r; 2727 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2728 if (r) 2729 return r; 2730 } else { 2731 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2732 if (r) 2733 return r; 2734 2735 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2736 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2737 if (r) 2738 return r; 2739 } 2740 } 2741 2742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2743 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2744 if (r) 2745 return r; 2746 } 2747 2748 r = amdgpu_discovery_set_display_ip_blocks(adev); 2749 if (r) 2750 return r; 2751 2752 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2753 if (r) 2754 return r; 2755 2756 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2757 if (r) 2758 return r; 2759 2760 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2761 !amdgpu_sriov_vf(adev)) || 2762 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2763 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2764 if (r) 2765 return r; 2766 } 2767 2768 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2769 if (r) 2770 return r; 2771 2772 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2773 if (r) 2774 return r; 2775 2776 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 2777 if (r) 2778 return r; 2779 2780 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 2781 if (r) 2782 return r; 2783 2784 return 0; 2785 } 2786 2787