1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "nbio_v6_1.h" 41 #include "nbio_v7_0.h" 42 #include "nbio_v7_4.h" 43 #include "nbio_v7_9.h" 44 #include "nbio_v7_11.h" 45 #include "hdp_v4_0.h" 46 #include "vega10_ih.h" 47 #include "vega20_ih.h" 48 #include "sdma_v4_0.h" 49 #include "sdma_v4_4_2.h" 50 #include "uvd_v7_0.h" 51 #include "vce_v4_0.h" 52 #include "vcn_v1_0.h" 53 #include "vcn_v2_5.h" 54 #include "jpeg_v2_5.h" 55 #include "smuio_v9_0.h" 56 #include "gmc_v10_0.h" 57 #include "gmc_v11_0.h" 58 #include "gfxhub_v2_0.h" 59 #include "mmhub_v2_0.h" 60 #include "nbio_v2_3.h" 61 #include "nbio_v4_3.h" 62 #include "nbio_v7_2.h" 63 #include "nbio_v7_7.h" 64 #include "nbif_v6_3_1.h" 65 #include "hdp_v5_0.h" 66 #include "hdp_v5_2.h" 67 #include "hdp_v6_0.h" 68 #include "hdp_v7_0.h" 69 #include "nv.h" 70 #include "soc21.h" 71 #include "navi10_ih.h" 72 #include "ih_v6_0.h" 73 #include "ih_v6_1.h" 74 #include "ih_v7_0.h" 75 #include "gfx_v10_0.h" 76 #include "gfx_v11_0.h" 77 #include "sdma_v5_0.h" 78 #include "sdma_v5_2.h" 79 #include "sdma_v6_0.h" 80 #include "lsdma_v6_0.h" 81 #include "lsdma_v7_0.h" 82 #include "vcn_v2_0.h" 83 #include "jpeg_v2_0.h" 84 #include "vcn_v3_0.h" 85 #include "jpeg_v3_0.h" 86 #include "vcn_v4_0.h" 87 #include "jpeg_v4_0.h" 88 #include "vcn_v4_0_3.h" 89 #include "jpeg_v4_0_3.h" 90 #include "vcn_v4_0_5.h" 91 #include "jpeg_v4_0_5.h" 92 #include "amdgpu_vkms.h" 93 #include "mes_v10_1.h" 94 #include "mes_v11_0.h" 95 #include "smuio_v11_0.h" 96 #include "smuio_v11_0_6.h" 97 #include "smuio_v13_0.h" 98 #include "smuio_v13_0_3.h" 99 #include "smuio_v13_0_6.h" 100 #include "smuio_v14_0_2.h" 101 #include "vcn_v5_0_0.h" 102 #include "jpeg_v5_0_0.h" 103 104 #include "amdgpu_vpe.h" 105 106 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 107 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 108 109 #define mmIP_DISCOVERY_VERSION 0x16A00 110 #define mmRCC_CONFIG_MEMSIZE 0xde3 111 #define mmMP0_SMN_C2PMSG_33 0x16061 112 #define mmMM_INDEX 0x0 113 #define mmMM_INDEX_HI 0x6 114 #define mmMM_DATA 0x1 115 116 static const char *hw_id_names[HW_ID_MAX] = { 117 [MP1_HWID] = "MP1", 118 [MP2_HWID] = "MP2", 119 [THM_HWID] = "THM", 120 [SMUIO_HWID] = "SMUIO", 121 [FUSE_HWID] = "FUSE", 122 [CLKA_HWID] = "CLKA", 123 [PWR_HWID] = "PWR", 124 [GC_HWID] = "GC", 125 [UVD_HWID] = "UVD", 126 [AUDIO_AZ_HWID] = "AUDIO_AZ", 127 [ACP_HWID] = "ACP", 128 [DCI_HWID] = "DCI", 129 [DMU_HWID] = "DMU", 130 [DCO_HWID] = "DCO", 131 [DIO_HWID] = "DIO", 132 [XDMA_HWID] = "XDMA", 133 [DCEAZ_HWID] = "DCEAZ", 134 [DAZ_HWID] = "DAZ", 135 [SDPMUX_HWID] = "SDPMUX", 136 [NTB_HWID] = "NTB", 137 [IOHC_HWID] = "IOHC", 138 [L2IMU_HWID] = "L2IMU", 139 [VCE_HWID] = "VCE", 140 [MMHUB_HWID] = "MMHUB", 141 [ATHUB_HWID] = "ATHUB", 142 [DBGU_NBIO_HWID] = "DBGU_NBIO", 143 [DFX_HWID] = "DFX", 144 [DBGU0_HWID] = "DBGU0", 145 [DBGU1_HWID] = "DBGU1", 146 [OSSSYS_HWID] = "OSSSYS", 147 [HDP_HWID] = "HDP", 148 [SDMA0_HWID] = "SDMA0", 149 [SDMA1_HWID] = "SDMA1", 150 [SDMA2_HWID] = "SDMA2", 151 [SDMA3_HWID] = "SDMA3", 152 [LSDMA_HWID] = "LSDMA", 153 [ISP_HWID] = "ISP", 154 [DBGU_IO_HWID] = "DBGU_IO", 155 [DF_HWID] = "DF", 156 [CLKB_HWID] = "CLKB", 157 [FCH_HWID] = "FCH", 158 [DFX_DAP_HWID] = "DFX_DAP", 159 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 160 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 161 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 162 [L1IMU3_HWID] = "L1IMU3", 163 [L1IMU4_HWID] = "L1IMU4", 164 [L1IMU5_HWID] = "L1IMU5", 165 [L1IMU6_HWID] = "L1IMU6", 166 [L1IMU7_HWID] = "L1IMU7", 167 [L1IMU8_HWID] = "L1IMU8", 168 [L1IMU9_HWID] = "L1IMU9", 169 [L1IMU10_HWID] = "L1IMU10", 170 [L1IMU11_HWID] = "L1IMU11", 171 [L1IMU12_HWID] = "L1IMU12", 172 [L1IMU13_HWID] = "L1IMU13", 173 [L1IMU14_HWID] = "L1IMU14", 174 [L1IMU15_HWID] = "L1IMU15", 175 [WAFLC_HWID] = "WAFLC", 176 [FCH_USB_PD_HWID] = "FCH_USB_PD", 177 [PCIE_HWID] = "PCIE", 178 [PCS_HWID] = "PCS", 179 [DDCL_HWID] = "DDCL", 180 [SST_HWID] = "SST", 181 [IOAGR_HWID] = "IOAGR", 182 [NBIF_HWID] = "NBIF", 183 [IOAPIC_HWID] = "IOAPIC", 184 [SYSTEMHUB_HWID] = "SYSTEMHUB", 185 [NTBCCP_HWID] = "NTBCCP", 186 [UMC_HWID] = "UMC", 187 [SATA_HWID] = "SATA", 188 [USB_HWID] = "USB", 189 [CCXSEC_HWID] = "CCXSEC", 190 [XGMI_HWID] = "XGMI", 191 [XGBE_HWID] = "XGBE", 192 [MP0_HWID] = "MP0", 193 [VPE_HWID] = "VPE", 194 }; 195 196 static int hw_id_map[MAX_HWIP] = { 197 [GC_HWIP] = GC_HWID, 198 [HDP_HWIP] = HDP_HWID, 199 [SDMA0_HWIP] = SDMA0_HWID, 200 [SDMA1_HWIP] = SDMA1_HWID, 201 [SDMA2_HWIP] = SDMA2_HWID, 202 [SDMA3_HWIP] = SDMA3_HWID, 203 [LSDMA_HWIP] = LSDMA_HWID, 204 [MMHUB_HWIP] = MMHUB_HWID, 205 [ATHUB_HWIP] = ATHUB_HWID, 206 [NBIO_HWIP] = NBIF_HWID, 207 [MP0_HWIP] = MP0_HWID, 208 [MP1_HWIP] = MP1_HWID, 209 [UVD_HWIP] = UVD_HWID, 210 [VCE_HWIP] = VCE_HWID, 211 [DF_HWIP] = DF_HWID, 212 [DCE_HWIP] = DMU_HWID, 213 [OSSSYS_HWIP] = OSSSYS_HWID, 214 [SMUIO_HWIP] = SMUIO_HWID, 215 [PWR_HWIP] = PWR_HWID, 216 [NBIF_HWIP] = NBIF_HWID, 217 [THM_HWIP] = THM_HWID, 218 [CLK_HWIP] = CLKA_HWID, 219 [UMC_HWIP] = UMC_HWID, 220 [XGMI_HWIP] = XGMI_HWID, 221 [DCI_HWIP] = DCI_HWID, 222 [PCIE_HWIP] = PCIE_HWID, 223 [VPE_HWIP] = VPE_HWID, 224 }; 225 226 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 227 { 228 u64 tmr_offset, tmr_size, pos; 229 void *discv_regn; 230 int ret; 231 232 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 233 if (ret) 234 return ret; 235 236 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 237 238 /* This region is read-only and reserved from system use */ 239 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 240 if (discv_regn) { 241 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 242 memunmap(discv_regn); 243 return 0; 244 } 245 246 return -ENOENT; 247 } 248 249 #define IP_DISCOVERY_V2 2 250 #define IP_DISCOVERY_V4 4 251 252 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 253 uint8_t *binary) 254 { 255 uint64_t vram_size; 256 u32 msg; 257 int i, ret = 0; 258 int ip_discovery_ver = 0; 259 260 /* It can take up to a second for IFWI init to complete on some dGPUs, 261 * but generally it should be in the 60-100ms range. Normally this starts 262 * as soon as the device gets power so by the time the OS loads this has long 263 * completed. However, when a card is hotplugged via e.g., USB4, we need to 264 * wait for this to complete. Once the C2PMSG is updated, we can 265 * continue. 266 */ 267 268 ip_discovery_ver = RREG32(mmIP_DISCOVERY_VERSION); 269 if ((dev_is_removable(&adev->pdev->dev)) || 270 (ip_discovery_ver == IP_DISCOVERY_V2) || 271 (ip_discovery_ver == IP_DISCOVERY_V4)) { 272 for (i = 0; i < 1000; i++) { 273 msg = RREG32(mmMP0_SMN_C2PMSG_33); 274 if (msg & 0x80000000) 275 break; 276 msleep(1); 277 } 278 } 279 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 280 281 if (vram_size) { 282 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 283 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 284 adev->mman.discovery_tmr_size, false); 285 } else { 286 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 287 } 288 289 return ret; 290 } 291 292 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 293 { 294 const struct firmware *fw; 295 const char *fw_name; 296 int r; 297 298 switch (amdgpu_discovery) { 299 case 2: 300 fw_name = FIRMWARE_IP_DISCOVERY; 301 break; 302 default: 303 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 304 return -EINVAL; 305 } 306 307 r = request_firmware(&fw, fw_name, adev->dev); 308 if (r) { 309 dev_err(adev->dev, "can't load firmware \"%s\"\n", 310 fw_name); 311 return r; 312 } 313 314 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 315 release_firmware(fw); 316 317 return 0; 318 } 319 320 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 321 { 322 uint16_t checksum = 0; 323 int i; 324 325 for (i = 0; i < size; i++) 326 checksum += data[i]; 327 328 return checksum; 329 } 330 331 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 332 uint16_t expected) 333 { 334 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 335 } 336 337 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 338 { 339 struct binary_header *bhdr; 340 bhdr = (struct binary_header *)binary; 341 342 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 343 } 344 345 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 346 { 347 /* 348 * So far, apply this quirk only on those Navy Flounder boards which 349 * have a bad harvest table of VCN config. 350 */ 351 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 352 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 353 switch (adev->pdev->revision) { 354 case 0xC1: 355 case 0xC2: 356 case 0xC3: 357 case 0xC5: 358 case 0xC7: 359 case 0xCF: 360 case 0xDF: 361 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 362 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 363 break; 364 default: 365 break; 366 } 367 } 368 } 369 370 static int amdgpu_discovery_init(struct amdgpu_device *adev) 371 { 372 struct table_info *info; 373 struct binary_header *bhdr; 374 uint16_t offset; 375 uint16_t size; 376 uint16_t checksum; 377 int r; 378 379 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 380 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 381 if (!adev->mman.discovery_bin) 382 return -ENOMEM; 383 384 /* Read from file if it is the preferred option */ 385 if (amdgpu_discovery == 2) { 386 dev_info(adev->dev, "use ip discovery information from file"); 387 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 388 389 if (r) { 390 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 391 r = -EINVAL; 392 goto out; 393 } 394 395 } else { 396 r = amdgpu_discovery_read_binary_from_mem( 397 adev, adev->mman.discovery_bin); 398 if (r) 399 goto out; 400 } 401 402 /* check the ip discovery binary signature */ 403 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 404 dev_err(adev->dev, 405 "get invalid ip discovery binary signature\n"); 406 r = -EINVAL; 407 goto out; 408 } 409 410 bhdr = (struct binary_header *)adev->mman.discovery_bin; 411 412 offset = offsetof(struct binary_header, binary_checksum) + 413 sizeof(bhdr->binary_checksum); 414 size = le16_to_cpu(bhdr->binary_size) - offset; 415 checksum = le16_to_cpu(bhdr->binary_checksum); 416 417 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 418 size, checksum)) { 419 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 420 r = -EINVAL; 421 goto out; 422 } 423 424 info = &bhdr->table_list[IP_DISCOVERY]; 425 offset = le16_to_cpu(info->offset); 426 checksum = le16_to_cpu(info->checksum); 427 428 if (offset) { 429 struct ip_discovery_header *ihdr = 430 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 431 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 432 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 433 r = -EINVAL; 434 goto out; 435 } 436 437 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 438 le16_to_cpu(ihdr->size), checksum)) { 439 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 440 r = -EINVAL; 441 goto out; 442 } 443 } 444 445 info = &bhdr->table_list[GC]; 446 offset = le16_to_cpu(info->offset); 447 checksum = le16_to_cpu(info->checksum); 448 449 if (offset) { 450 struct gpu_info_header *ghdr = 451 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 452 453 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 454 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 455 r = -EINVAL; 456 goto out; 457 } 458 459 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 460 le32_to_cpu(ghdr->size), checksum)) { 461 dev_err(adev->dev, "invalid gc data table checksum\n"); 462 r = -EINVAL; 463 goto out; 464 } 465 } 466 467 info = &bhdr->table_list[HARVEST_INFO]; 468 offset = le16_to_cpu(info->offset); 469 checksum = le16_to_cpu(info->checksum); 470 471 if (offset) { 472 struct harvest_info_header *hhdr = 473 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 474 475 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 476 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 477 r = -EINVAL; 478 goto out; 479 } 480 481 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 482 sizeof(struct harvest_table), checksum)) { 483 dev_err(adev->dev, "invalid harvest data table checksum\n"); 484 r = -EINVAL; 485 goto out; 486 } 487 } 488 489 info = &bhdr->table_list[VCN_INFO]; 490 offset = le16_to_cpu(info->offset); 491 checksum = le16_to_cpu(info->checksum); 492 493 if (offset) { 494 struct vcn_info_header *vhdr = 495 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 496 497 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 498 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 499 r = -EINVAL; 500 goto out; 501 } 502 503 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 504 le32_to_cpu(vhdr->size_bytes), checksum)) { 505 dev_err(adev->dev, "invalid vcn data table checksum\n"); 506 r = -EINVAL; 507 goto out; 508 } 509 } 510 511 info = &bhdr->table_list[MALL_INFO]; 512 offset = le16_to_cpu(info->offset); 513 checksum = le16_to_cpu(info->checksum); 514 515 if (0 && offset) { 516 struct mall_info_header *mhdr = 517 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 518 519 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 520 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 521 r = -EINVAL; 522 goto out; 523 } 524 525 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 526 le32_to_cpu(mhdr->size_bytes), checksum)) { 527 dev_err(adev->dev, "invalid mall data table checksum\n"); 528 r = -EINVAL; 529 goto out; 530 } 531 } 532 533 return 0; 534 535 out: 536 kfree(adev->mman.discovery_bin); 537 adev->mman.discovery_bin = NULL; 538 if ((amdgpu_discovery != 2) && 539 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 540 amdgpu_ras_query_boot_status(adev, 4); 541 return r; 542 } 543 544 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 545 546 void amdgpu_discovery_fini(struct amdgpu_device *adev) 547 { 548 amdgpu_discovery_sysfs_fini(adev); 549 kfree(adev->mman.discovery_bin); 550 adev->mman.discovery_bin = NULL; 551 } 552 553 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 554 { 555 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 556 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 557 ip->instance_number); 558 return -EINVAL; 559 } 560 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 561 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 562 le16_to_cpu(ip->hw_id)); 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 570 uint32_t *vcn_harvest_count) 571 { 572 struct binary_header *bhdr; 573 struct ip_discovery_header *ihdr; 574 struct die_header *dhdr; 575 struct ip_v4 *ip; 576 uint16_t die_offset, ip_offset, num_dies, num_ips; 577 int i, j; 578 579 bhdr = (struct binary_header *)adev->mman.discovery_bin; 580 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 581 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 582 num_dies = le16_to_cpu(ihdr->num_dies); 583 584 /* scan harvest bit of all IP data structures */ 585 for (i = 0; i < num_dies; i++) { 586 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 587 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 588 num_ips = le16_to_cpu(dhdr->num_ips); 589 ip_offset = die_offset + sizeof(*dhdr); 590 591 for (j = 0; j < num_ips; j++) { 592 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 593 594 if (amdgpu_discovery_validate_ip(ip)) 595 goto next_ip; 596 597 if (le16_to_cpu(ip->variant) == 1) { 598 switch (le16_to_cpu(ip->hw_id)) { 599 case VCN_HWID: 600 (*vcn_harvest_count)++; 601 if (ip->instance_number == 0) { 602 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 603 adev->vcn.inst_mask &= 604 ~AMDGPU_VCN_HARVEST_VCN0; 605 adev->jpeg.inst_mask &= 606 ~AMDGPU_VCN_HARVEST_VCN0; 607 } else { 608 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 609 adev->vcn.inst_mask &= 610 ~AMDGPU_VCN_HARVEST_VCN1; 611 adev->jpeg.inst_mask &= 612 ~AMDGPU_VCN_HARVEST_VCN1; 613 } 614 break; 615 case DMU_HWID: 616 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 617 break; 618 default: 619 break; 620 } 621 } 622 next_ip: 623 if (ihdr->base_addr_64_bit) 624 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 625 else 626 ip_offset += struct_size(ip, base_address, ip->num_base_address); 627 } 628 } 629 } 630 631 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 632 uint32_t *vcn_harvest_count, 633 uint32_t *umc_harvest_count) 634 { 635 struct binary_header *bhdr; 636 struct harvest_table *harvest_info; 637 u16 offset; 638 int i; 639 uint32_t umc_harvest_config = 0; 640 641 bhdr = (struct binary_header *)adev->mman.discovery_bin; 642 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 643 644 if (!offset) { 645 dev_err(adev->dev, "invalid harvest table offset\n"); 646 return; 647 } 648 649 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 650 651 for (i = 0; i < 32; i++) { 652 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 653 break; 654 655 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 656 case VCN_HWID: 657 (*vcn_harvest_count)++; 658 adev->vcn.harvest_config |= 659 (1 << harvest_info->list[i].number_instance); 660 adev->jpeg.harvest_config |= 661 (1 << harvest_info->list[i].number_instance); 662 663 adev->vcn.inst_mask &= 664 ~(1U << harvest_info->list[i].number_instance); 665 adev->jpeg.inst_mask &= 666 ~(1U << harvest_info->list[i].number_instance); 667 break; 668 case DMU_HWID: 669 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 670 break; 671 case UMC_HWID: 672 umc_harvest_config |= 673 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 674 (*umc_harvest_count)++; 675 break; 676 case GC_HWID: 677 adev->gfx.xcc_mask &= 678 ~(1U << harvest_info->list[i].number_instance); 679 break; 680 case SDMA0_HWID: 681 adev->sdma.sdma_mask &= 682 ~(1U << harvest_info->list[i].number_instance); 683 break; 684 default: 685 break; 686 } 687 } 688 689 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 690 ~umc_harvest_config; 691 } 692 693 /* ================================================== */ 694 695 struct ip_hw_instance { 696 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 697 698 int hw_id; 699 u8 num_instance; 700 u8 major, minor, revision; 701 u8 harvest; 702 703 int num_base_addresses; 704 u32 base_addr[] __counted_by(num_base_addresses); 705 }; 706 707 struct ip_hw_id { 708 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 709 int hw_id; 710 }; 711 712 struct ip_die_entry { 713 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 714 u16 num_ips; 715 }; 716 717 /* -------------------------------------------------- */ 718 719 struct ip_hw_instance_attr { 720 struct attribute attr; 721 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 722 }; 723 724 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 725 { 726 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 727 } 728 729 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 730 { 731 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 732 } 733 734 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 735 { 736 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 737 } 738 739 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 740 { 741 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 742 } 743 744 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 745 { 746 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 747 } 748 749 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 750 { 751 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 752 } 753 754 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 755 { 756 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 757 } 758 759 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 760 { 761 ssize_t res, at; 762 int ii; 763 764 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 765 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 766 */ 767 if (at + 12 > PAGE_SIZE) 768 break; 769 res = sysfs_emit_at(buf, at, "0x%08X\n", 770 ip_hw_instance->base_addr[ii]); 771 if (res <= 0) 772 break; 773 at += res; 774 } 775 776 return res < 0 ? res : at; 777 } 778 779 static struct ip_hw_instance_attr ip_hw_attr[] = { 780 __ATTR_RO(hw_id), 781 __ATTR_RO(num_instance), 782 __ATTR_RO(major), 783 __ATTR_RO(minor), 784 __ATTR_RO(revision), 785 __ATTR_RO(harvest), 786 __ATTR_RO(num_base_addresses), 787 __ATTR_RO(base_addr), 788 }; 789 790 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 791 ATTRIBUTE_GROUPS(ip_hw_instance); 792 793 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 794 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 795 796 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 797 struct attribute *attr, 798 char *buf) 799 { 800 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 801 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 802 803 if (!ip_hw_attr->show) 804 return -EIO; 805 806 return ip_hw_attr->show(ip_hw_instance, buf); 807 } 808 809 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 810 .show = ip_hw_instance_attr_show, 811 }; 812 813 static void ip_hw_instance_release(struct kobject *kobj) 814 { 815 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 816 817 kfree(ip_hw_instance); 818 } 819 820 static const struct kobj_type ip_hw_instance_ktype = { 821 .release = ip_hw_instance_release, 822 .sysfs_ops = &ip_hw_instance_sysfs_ops, 823 .default_groups = ip_hw_instance_groups, 824 }; 825 826 /* -------------------------------------------------- */ 827 828 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 829 830 static void ip_hw_id_release(struct kobject *kobj) 831 { 832 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 833 834 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 835 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 836 kfree(ip_hw_id); 837 } 838 839 static const struct kobj_type ip_hw_id_ktype = { 840 .release = ip_hw_id_release, 841 .sysfs_ops = &kobj_sysfs_ops, 842 }; 843 844 /* -------------------------------------------------- */ 845 846 static void die_kobj_release(struct kobject *kobj); 847 static void ip_disc_release(struct kobject *kobj); 848 849 struct ip_die_entry_attribute { 850 struct attribute attr; 851 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 852 }; 853 854 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 855 856 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 857 { 858 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 859 } 860 861 /* If there are more ip_die_entry attrs, other than the number of IPs, 862 * we can make this intro an array of attrs, and then initialize 863 * ip_die_entry_attrs in a loop. 864 */ 865 static struct ip_die_entry_attribute num_ips_attr = 866 __ATTR_RO(num_ips); 867 868 static struct attribute *ip_die_entry_attrs[] = { 869 &num_ips_attr.attr, 870 NULL, 871 }; 872 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 873 874 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 875 876 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 877 struct attribute *attr, 878 char *buf) 879 { 880 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 881 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 882 883 if (!ip_die_entry_attr->show) 884 return -EIO; 885 886 return ip_die_entry_attr->show(ip_die_entry, buf); 887 } 888 889 static void ip_die_entry_release(struct kobject *kobj) 890 { 891 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 892 893 if (!list_empty(&ip_die_entry->ip_kset.list)) 894 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 895 kfree(ip_die_entry); 896 } 897 898 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 899 .show = ip_die_entry_attr_show, 900 }; 901 902 static const struct kobj_type ip_die_entry_ktype = { 903 .release = ip_die_entry_release, 904 .sysfs_ops = &ip_die_entry_sysfs_ops, 905 .default_groups = ip_die_entry_groups, 906 }; 907 908 static const struct kobj_type die_kobj_ktype = { 909 .release = die_kobj_release, 910 .sysfs_ops = &kobj_sysfs_ops, 911 }; 912 913 static const struct kobj_type ip_discovery_ktype = { 914 .release = ip_disc_release, 915 .sysfs_ops = &kobj_sysfs_ops, 916 }; 917 918 struct ip_discovery_top { 919 struct kobject kobj; /* ip_discovery/ */ 920 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 921 struct amdgpu_device *adev; 922 }; 923 924 static void die_kobj_release(struct kobject *kobj) 925 { 926 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 927 struct ip_discovery_top, 928 die_kset); 929 if (!list_empty(&ip_top->die_kset.list)) 930 DRM_ERROR("ip_top->die_kset is not empty"); 931 } 932 933 static void ip_disc_release(struct kobject *kobj) 934 { 935 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 936 kobj); 937 struct amdgpu_device *adev = ip_top->adev; 938 939 adev->ip_top = NULL; 940 kfree(ip_top); 941 } 942 943 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 944 uint16_t hw_id, uint8_t inst) 945 { 946 uint8_t harvest = 0; 947 948 /* Until a uniform way is figured, get mask based on hwid */ 949 switch (hw_id) { 950 case VCN_HWID: 951 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 952 break; 953 case DMU_HWID: 954 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 955 harvest = 0x1; 956 break; 957 case UMC_HWID: 958 /* TODO: It needs another parsing; for now, ignore.*/ 959 break; 960 case GC_HWID: 961 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 962 break; 963 case SDMA0_HWID: 964 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 965 break; 966 default: 967 break; 968 } 969 970 return harvest; 971 } 972 973 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 974 struct ip_die_entry *ip_die_entry, 975 const size_t _ip_offset, const int num_ips, 976 bool reg_base_64) 977 { 978 int ii, jj, kk, res; 979 980 DRM_DEBUG("num_ips:%d", num_ips); 981 982 /* Find all IPs of a given HW ID, and add their instance to 983 * #die/#hw_id/#instance/<attributes> 984 */ 985 for (ii = 0; ii < HW_ID_MAX; ii++) { 986 struct ip_hw_id *ip_hw_id = NULL; 987 size_t ip_offset = _ip_offset; 988 989 for (jj = 0; jj < num_ips; jj++) { 990 struct ip_v4 *ip; 991 struct ip_hw_instance *ip_hw_instance; 992 993 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 994 if (amdgpu_discovery_validate_ip(ip) || 995 le16_to_cpu(ip->hw_id) != ii) 996 goto next_ip; 997 998 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 999 1000 /* We have a hw_id match; register the hw 1001 * block if not yet registered. 1002 */ 1003 if (!ip_hw_id) { 1004 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1005 if (!ip_hw_id) 1006 return -ENOMEM; 1007 ip_hw_id->hw_id = ii; 1008 1009 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1010 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1011 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1012 res = kset_register(&ip_hw_id->hw_id_kset); 1013 if (res) { 1014 DRM_ERROR("Couldn't register ip_hw_id kset"); 1015 kfree(ip_hw_id); 1016 return res; 1017 } 1018 if (hw_id_names[ii]) { 1019 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1020 &ip_hw_id->hw_id_kset.kobj, 1021 hw_id_names[ii]); 1022 if (res) { 1023 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1024 hw_id_names[ii], 1025 kobject_name(&ip_die_entry->ip_kset.kobj)); 1026 } 1027 } 1028 } 1029 1030 /* Now register its instance. 1031 */ 1032 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1033 base_addr, 1034 ip->num_base_address), 1035 GFP_KERNEL); 1036 if (!ip_hw_instance) { 1037 DRM_ERROR("no memory for ip_hw_instance"); 1038 return -ENOMEM; 1039 } 1040 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1041 ip_hw_instance->num_instance = ip->instance_number; 1042 ip_hw_instance->major = ip->major; 1043 ip_hw_instance->minor = ip->minor; 1044 ip_hw_instance->revision = ip->revision; 1045 ip_hw_instance->harvest = 1046 amdgpu_discovery_get_harvest_info( 1047 adev, ip_hw_instance->hw_id, 1048 ip_hw_instance->num_instance); 1049 ip_hw_instance->num_base_addresses = ip->num_base_address; 1050 1051 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1052 if (reg_base_64) 1053 ip_hw_instance->base_addr[kk] = 1054 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1055 else 1056 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1057 } 1058 1059 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1060 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1061 res = kobject_add(&ip_hw_instance->kobj, NULL, 1062 "%d", ip_hw_instance->num_instance); 1063 next_ip: 1064 if (reg_base_64) 1065 ip_offset += struct_size(ip, base_address_64, 1066 ip->num_base_address); 1067 else 1068 ip_offset += struct_size(ip, base_address, 1069 ip->num_base_address); 1070 } 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1077 { 1078 struct binary_header *bhdr; 1079 struct ip_discovery_header *ihdr; 1080 struct die_header *dhdr; 1081 struct kset *die_kset = &adev->ip_top->die_kset; 1082 u16 num_dies, die_offset, num_ips; 1083 size_t ip_offset; 1084 int ii, res; 1085 1086 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1087 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1088 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1089 num_dies = le16_to_cpu(ihdr->num_dies); 1090 1091 DRM_DEBUG("number of dies: %d\n", num_dies); 1092 1093 for (ii = 0; ii < num_dies; ii++) { 1094 struct ip_die_entry *ip_die_entry; 1095 1096 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1097 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1098 num_ips = le16_to_cpu(dhdr->num_ips); 1099 ip_offset = die_offset + sizeof(*dhdr); 1100 1101 /* Add the die to the kset. 1102 * 1103 * dhdr->die_id == ii, which was checked in 1104 * amdgpu_discovery_reg_base_init(). 1105 */ 1106 1107 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1108 if (!ip_die_entry) 1109 return -ENOMEM; 1110 1111 ip_die_entry->num_ips = num_ips; 1112 1113 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1114 ip_die_entry->ip_kset.kobj.kset = die_kset; 1115 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1116 res = kset_register(&ip_die_entry->ip_kset); 1117 if (res) { 1118 DRM_ERROR("Couldn't register ip_die_entry kset"); 1119 kfree(ip_die_entry); 1120 return res; 1121 } 1122 1123 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1124 } 1125 1126 return 0; 1127 } 1128 1129 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1130 { 1131 struct kset *die_kset; 1132 int res, ii; 1133 1134 if (!adev->mman.discovery_bin) 1135 return -EINVAL; 1136 1137 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1138 if (!adev->ip_top) 1139 return -ENOMEM; 1140 1141 adev->ip_top->adev = adev; 1142 1143 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1144 &adev->dev->kobj, "ip_discovery"); 1145 if (res) { 1146 DRM_ERROR("Couldn't init and add ip_discovery/"); 1147 goto Err; 1148 } 1149 1150 die_kset = &adev->ip_top->die_kset; 1151 kobject_set_name(&die_kset->kobj, "%s", "die"); 1152 die_kset->kobj.parent = &adev->ip_top->kobj; 1153 die_kset->kobj.ktype = &die_kobj_ktype; 1154 res = kset_register(&adev->ip_top->die_kset); 1155 if (res) { 1156 DRM_ERROR("Couldn't register die_kset"); 1157 goto Err; 1158 } 1159 1160 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1161 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1162 ip_hw_instance_attrs[ii] = NULL; 1163 1164 res = amdgpu_discovery_sysfs_recurse(adev); 1165 1166 return res; 1167 Err: 1168 kobject_put(&adev->ip_top->kobj); 1169 return res; 1170 } 1171 1172 /* -------------------------------------------------- */ 1173 1174 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1175 1176 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1177 { 1178 struct list_head *el, *tmp; 1179 struct kset *hw_id_kset; 1180 1181 hw_id_kset = &ip_hw_id->hw_id_kset; 1182 spin_lock(&hw_id_kset->list_lock); 1183 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1184 list_del_init(el); 1185 spin_unlock(&hw_id_kset->list_lock); 1186 /* kobject is embedded in ip_hw_instance */ 1187 kobject_put(list_to_kobj(el)); 1188 spin_lock(&hw_id_kset->list_lock); 1189 } 1190 spin_unlock(&hw_id_kset->list_lock); 1191 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1192 } 1193 1194 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1195 { 1196 struct list_head *el, *tmp; 1197 struct kset *ip_kset; 1198 1199 ip_kset = &ip_die_entry->ip_kset; 1200 spin_lock(&ip_kset->list_lock); 1201 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1202 list_del_init(el); 1203 spin_unlock(&ip_kset->list_lock); 1204 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1205 spin_lock(&ip_kset->list_lock); 1206 } 1207 spin_unlock(&ip_kset->list_lock); 1208 kobject_put(&ip_die_entry->ip_kset.kobj); 1209 } 1210 1211 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1212 { 1213 struct list_head *el, *tmp; 1214 struct kset *die_kset; 1215 1216 die_kset = &adev->ip_top->die_kset; 1217 spin_lock(&die_kset->list_lock); 1218 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1219 list_del_init(el); 1220 spin_unlock(&die_kset->list_lock); 1221 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1222 spin_lock(&die_kset->list_lock); 1223 } 1224 spin_unlock(&die_kset->list_lock); 1225 kobject_put(&adev->ip_top->die_kset.kobj); 1226 kobject_put(&adev->ip_top->kobj); 1227 } 1228 1229 /* ================================================== */ 1230 1231 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1232 { 1233 uint8_t num_base_address, subrev, variant; 1234 struct binary_header *bhdr; 1235 struct ip_discovery_header *ihdr; 1236 struct die_header *dhdr; 1237 struct ip_v4 *ip; 1238 uint16_t die_offset; 1239 uint16_t ip_offset; 1240 uint16_t num_dies; 1241 uint16_t num_ips; 1242 int hw_ip; 1243 int i, j, k; 1244 int r; 1245 1246 r = amdgpu_discovery_init(adev); 1247 if (r) { 1248 DRM_ERROR("amdgpu_discovery_init failed\n"); 1249 return r; 1250 } 1251 1252 adev->gfx.xcc_mask = 0; 1253 adev->sdma.sdma_mask = 0; 1254 adev->vcn.inst_mask = 0; 1255 adev->jpeg.inst_mask = 0; 1256 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1257 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1258 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1259 num_dies = le16_to_cpu(ihdr->num_dies); 1260 1261 DRM_DEBUG("number of dies: %d\n", num_dies); 1262 1263 for (i = 0; i < num_dies; i++) { 1264 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1265 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1266 num_ips = le16_to_cpu(dhdr->num_ips); 1267 ip_offset = die_offset + sizeof(*dhdr); 1268 1269 if (le16_to_cpu(dhdr->die_id) != i) { 1270 DRM_ERROR("invalid die id %d, expected %d\n", 1271 le16_to_cpu(dhdr->die_id), i); 1272 return -EINVAL; 1273 } 1274 1275 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1276 le16_to_cpu(dhdr->die_id), num_ips); 1277 1278 for (j = 0; j < num_ips; j++) { 1279 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1280 1281 if (amdgpu_discovery_validate_ip(ip)) 1282 goto next_ip; 1283 1284 num_base_address = ip->num_base_address; 1285 1286 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1287 hw_id_names[le16_to_cpu(ip->hw_id)], 1288 le16_to_cpu(ip->hw_id), 1289 ip->instance_number, 1290 ip->major, ip->minor, 1291 ip->revision); 1292 1293 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1294 /* Bit [5:0]: original revision value 1295 * Bit [7:6]: en/decode capability: 1296 * 0b00 : VCN function normally 1297 * 0b10 : encode is disabled 1298 * 0b01 : decode is disabled 1299 */ 1300 if (adev->vcn.num_vcn_inst < 1301 AMDGPU_MAX_VCN_INSTANCES) { 1302 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1303 ip->revision & 0xc0; 1304 adev->vcn.num_vcn_inst++; 1305 adev->vcn.inst_mask |= 1306 (1U << ip->instance_number); 1307 adev->jpeg.inst_mask |= 1308 (1U << ip->instance_number); 1309 } else { 1310 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1311 adev->vcn.num_vcn_inst + 1, 1312 AMDGPU_MAX_VCN_INSTANCES); 1313 } 1314 ip->revision &= ~0xc0; 1315 } 1316 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1317 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1318 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1319 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1320 if (adev->sdma.num_instances < 1321 AMDGPU_MAX_SDMA_INSTANCES) { 1322 adev->sdma.num_instances++; 1323 adev->sdma.sdma_mask |= 1324 (1U << ip->instance_number); 1325 } else { 1326 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1327 adev->sdma.num_instances + 1, 1328 AMDGPU_MAX_SDMA_INSTANCES); 1329 } 1330 } 1331 1332 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1333 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1334 adev->vpe.num_instances++; 1335 else 1336 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1337 adev->vpe.num_instances + 1, 1338 AMDGPU_MAX_VPE_INSTANCES); 1339 } 1340 1341 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1342 adev->gmc.num_umc++; 1343 adev->umc.node_inst_num++; 1344 } 1345 1346 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1347 adev->gfx.xcc_mask |= 1348 (1U << ip->instance_number); 1349 1350 for (k = 0; k < num_base_address; k++) { 1351 /* 1352 * convert the endianness of base addresses in place, 1353 * so that we don't need to convert them when accessing adev->reg_offset. 1354 */ 1355 if (ihdr->base_addr_64_bit) 1356 /* Truncate the 64bit base address from ip discovery 1357 * and only store lower 32bit ip base in reg_offset[]. 1358 * Bits > 32 follows ASIC specific format, thus just 1359 * discard them and handle it within specific ASIC. 1360 * By this way reg_offset[] and related helpers can 1361 * stay unchanged. 1362 * The base address is in dwords, thus clear the 1363 * highest 2 bits to store. 1364 */ 1365 ip->base_address[k] = 1366 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1367 else 1368 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1369 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1370 } 1371 1372 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1373 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1374 hw_id_map[hw_ip] != 0) { 1375 DRM_DEBUG("set register base offset for %s\n", 1376 hw_id_names[le16_to_cpu(ip->hw_id)]); 1377 adev->reg_offset[hw_ip][ip->instance_number] = 1378 ip->base_address; 1379 /* Instance support is somewhat inconsistent. 1380 * SDMA is a good example. Sienna cichlid has 4 total 1381 * SDMA instances, each enumerated separately (HWIDs 1382 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1383 * but they are enumerated as multiple instances of the 1384 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1385 * example. On most chips there are multiple instances 1386 * with the same HWID. 1387 */ 1388 1389 if (ihdr->version < 3) { 1390 subrev = 0; 1391 variant = 0; 1392 } else { 1393 subrev = ip->sub_revision; 1394 variant = ip->variant; 1395 } 1396 1397 adev->ip_versions[hw_ip] 1398 [ip->instance_number] = 1399 IP_VERSION_FULL(ip->major, 1400 ip->minor, 1401 ip->revision, 1402 variant, 1403 subrev); 1404 } 1405 } 1406 1407 next_ip: 1408 if (ihdr->base_addr_64_bit) 1409 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1410 else 1411 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1412 } 1413 } 1414 1415 return 0; 1416 } 1417 1418 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1419 { 1420 int vcn_harvest_count = 0; 1421 int umc_harvest_count = 0; 1422 1423 /* 1424 * Harvest table does not fit Navi1x and legacy GPUs, 1425 * so read harvest bit per IP data structure to set 1426 * harvest configuration. 1427 */ 1428 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1429 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) { 1430 if ((adev->pdev->device == 0x731E && 1431 (adev->pdev->revision == 0xC6 || 1432 adev->pdev->revision == 0xC7)) || 1433 (adev->pdev->device == 0x7340 && 1434 adev->pdev->revision == 0xC9) || 1435 (adev->pdev->device == 0x7360 && 1436 adev->pdev->revision == 0xC7)) 1437 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1438 &vcn_harvest_count); 1439 } else { 1440 amdgpu_discovery_read_from_harvest_table(adev, 1441 &vcn_harvest_count, 1442 &umc_harvest_count); 1443 } 1444 1445 amdgpu_discovery_harvest_config_quirk(adev); 1446 1447 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1448 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1449 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1450 } 1451 1452 if (umc_harvest_count < adev->gmc.num_umc) { 1453 adev->gmc.num_umc -= umc_harvest_count; 1454 } 1455 } 1456 1457 union gc_info { 1458 struct gc_info_v1_0 v1; 1459 struct gc_info_v1_1 v1_1; 1460 struct gc_info_v1_2 v1_2; 1461 struct gc_info_v2_0 v2; 1462 struct gc_info_v2_1 v2_1; 1463 }; 1464 1465 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1466 { 1467 struct binary_header *bhdr; 1468 union gc_info *gc_info; 1469 u16 offset; 1470 1471 if (!adev->mman.discovery_bin) { 1472 DRM_ERROR("ip discovery uninitialized\n"); 1473 return -EINVAL; 1474 } 1475 1476 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1477 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1478 1479 if (!offset) 1480 return 0; 1481 1482 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1483 1484 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1485 case 1: 1486 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1487 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1488 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1489 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1490 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1491 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1492 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1493 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1494 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1495 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1496 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1497 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1498 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1499 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1500 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1501 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1502 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1503 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1504 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1505 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1506 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1507 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1508 } 1509 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1510 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1511 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1512 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1513 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1514 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1515 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1516 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1517 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1518 } 1519 break; 1520 case 2: 1521 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1522 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1523 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1524 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1525 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1526 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1527 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1528 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1529 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1530 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1531 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1532 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1533 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1534 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1535 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1536 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1537 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1538 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1539 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1540 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1541 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1542 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1543 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1544 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1545 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1546 } 1547 break; 1548 default: 1549 dev_err(adev->dev, 1550 "Unhandled GC info table %d.%d\n", 1551 le16_to_cpu(gc_info->v1.header.version_major), 1552 le16_to_cpu(gc_info->v1.header.version_minor)); 1553 return -EINVAL; 1554 } 1555 return 0; 1556 } 1557 1558 union mall_info { 1559 struct mall_info_v1_0 v1; 1560 struct mall_info_v2_0 v2; 1561 }; 1562 1563 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1564 { 1565 struct binary_header *bhdr; 1566 union mall_info *mall_info; 1567 u32 u, mall_size_per_umc, m_s_present, half_use; 1568 u64 mall_size; 1569 u16 offset; 1570 1571 if (!adev->mman.discovery_bin) { 1572 DRM_ERROR("ip discovery uninitialized\n"); 1573 return -EINVAL; 1574 } 1575 1576 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1577 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1578 1579 if (!offset) 1580 return 0; 1581 1582 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1583 1584 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1585 case 1: 1586 mall_size = 0; 1587 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1588 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1589 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1590 for (u = 0; u < adev->gmc.num_umc; u++) { 1591 if (m_s_present & (1 << u)) 1592 mall_size += mall_size_per_umc * 2; 1593 else if (half_use & (1 << u)) 1594 mall_size += mall_size_per_umc / 2; 1595 else 1596 mall_size += mall_size_per_umc; 1597 } 1598 adev->gmc.mall_size = mall_size; 1599 adev->gmc.m_half_use = half_use; 1600 break; 1601 case 2: 1602 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1603 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; 1604 break; 1605 default: 1606 dev_err(adev->dev, 1607 "Unhandled MALL info table %d.%d\n", 1608 le16_to_cpu(mall_info->v1.header.version_major), 1609 le16_to_cpu(mall_info->v1.header.version_minor)); 1610 return -EINVAL; 1611 } 1612 return 0; 1613 } 1614 1615 union vcn_info { 1616 struct vcn_info_v1_0 v1; 1617 }; 1618 1619 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1620 { 1621 struct binary_header *bhdr; 1622 union vcn_info *vcn_info; 1623 u16 offset; 1624 int v; 1625 1626 if (!adev->mman.discovery_bin) { 1627 DRM_ERROR("ip discovery uninitialized\n"); 1628 return -EINVAL; 1629 } 1630 1631 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1632 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1633 * but that may change in the future with new GPUs so keep this 1634 * check for defensive purposes. 1635 */ 1636 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1637 dev_err(adev->dev, "invalid vcn instances\n"); 1638 return -EINVAL; 1639 } 1640 1641 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1642 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1643 1644 if (!offset) 1645 return 0; 1646 1647 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1648 1649 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1650 case 1: 1651 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1652 * so this won't overflow. 1653 */ 1654 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1655 adev->vcn.vcn_codec_disable_mask[v] = 1656 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1657 } 1658 break; 1659 default: 1660 dev_err(adev->dev, 1661 "Unhandled VCN info table %d.%d\n", 1662 le16_to_cpu(vcn_info->v1.header.version_major), 1663 le16_to_cpu(vcn_info->v1.header.version_minor)); 1664 return -EINVAL; 1665 } 1666 return 0; 1667 } 1668 1669 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1670 { 1671 /* what IP to use for this? */ 1672 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1673 case IP_VERSION(9, 0, 1): 1674 case IP_VERSION(9, 1, 0): 1675 case IP_VERSION(9, 2, 1): 1676 case IP_VERSION(9, 2, 2): 1677 case IP_VERSION(9, 3, 0): 1678 case IP_VERSION(9, 4, 0): 1679 case IP_VERSION(9, 4, 1): 1680 case IP_VERSION(9, 4, 2): 1681 case IP_VERSION(9, 4, 3): 1682 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1683 break; 1684 case IP_VERSION(10, 1, 10): 1685 case IP_VERSION(10, 1, 1): 1686 case IP_VERSION(10, 1, 2): 1687 case IP_VERSION(10, 1, 3): 1688 case IP_VERSION(10, 1, 4): 1689 case IP_VERSION(10, 3, 0): 1690 case IP_VERSION(10, 3, 1): 1691 case IP_VERSION(10, 3, 2): 1692 case IP_VERSION(10, 3, 3): 1693 case IP_VERSION(10, 3, 4): 1694 case IP_VERSION(10, 3, 5): 1695 case IP_VERSION(10, 3, 6): 1696 case IP_VERSION(10, 3, 7): 1697 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1698 break; 1699 case IP_VERSION(11, 0, 0): 1700 case IP_VERSION(11, 0, 1): 1701 case IP_VERSION(11, 0, 2): 1702 case IP_VERSION(11, 0, 3): 1703 case IP_VERSION(11, 0, 4): 1704 case IP_VERSION(11, 5, 0): 1705 case IP_VERSION(11, 5, 1): 1706 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1707 break; 1708 default: 1709 dev_err(adev->dev, 1710 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1711 amdgpu_ip_version(adev, GC_HWIP, 0)); 1712 return -EINVAL; 1713 } 1714 return 0; 1715 } 1716 1717 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1718 { 1719 /* use GC or MMHUB IP version */ 1720 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1721 case IP_VERSION(9, 0, 1): 1722 case IP_VERSION(9, 1, 0): 1723 case IP_VERSION(9, 2, 1): 1724 case IP_VERSION(9, 2, 2): 1725 case IP_VERSION(9, 3, 0): 1726 case IP_VERSION(9, 4, 0): 1727 case IP_VERSION(9, 4, 1): 1728 case IP_VERSION(9, 4, 2): 1729 case IP_VERSION(9, 4, 3): 1730 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1731 break; 1732 case IP_VERSION(10, 1, 10): 1733 case IP_VERSION(10, 1, 1): 1734 case IP_VERSION(10, 1, 2): 1735 case IP_VERSION(10, 1, 3): 1736 case IP_VERSION(10, 1, 4): 1737 case IP_VERSION(10, 3, 0): 1738 case IP_VERSION(10, 3, 1): 1739 case IP_VERSION(10, 3, 2): 1740 case IP_VERSION(10, 3, 3): 1741 case IP_VERSION(10, 3, 4): 1742 case IP_VERSION(10, 3, 5): 1743 case IP_VERSION(10, 3, 6): 1744 case IP_VERSION(10, 3, 7): 1745 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1746 break; 1747 case IP_VERSION(11, 0, 0): 1748 case IP_VERSION(11, 0, 1): 1749 case IP_VERSION(11, 0, 2): 1750 case IP_VERSION(11, 0, 3): 1751 case IP_VERSION(11, 0, 4): 1752 case IP_VERSION(11, 5, 0): 1753 case IP_VERSION(11, 5, 1): 1754 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1755 break; 1756 default: 1757 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1758 amdgpu_ip_version(adev, GC_HWIP, 0)); 1759 return -EINVAL; 1760 } 1761 return 0; 1762 } 1763 1764 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1765 { 1766 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1767 case IP_VERSION(4, 0, 0): 1768 case IP_VERSION(4, 0, 1): 1769 case IP_VERSION(4, 1, 0): 1770 case IP_VERSION(4, 1, 1): 1771 case IP_VERSION(4, 3, 0): 1772 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1773 break; 1774 case IP_VERSION(4, 2, 0): 1775 case IP_VERSION(4, 2, 1): 1776 case IP_VERSION(4, 4, 0): 1777 case IP_VERSION(4, 4, 2): 1778 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1779 break; 1780 case IP_VERSION(5, 0, 0): 1781 case IP_VERSION(5, 0, 1): 1782 case IP_VERSION(5, 0, 2): 1783 case IP_VERSION(5, 0, 3): 1784 case IP_VERSION(5, 2, 0): 1785 case IP_VERSION(5, 2, 1): 1786 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1787 break; 1788 case IP_VERSION(6, 0, 0): 1789 case IP_VERSION(6, 0, 1): 1790 case IP_VERSION(6, 0, 2): 1791 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1792 break; 1793 case IP_VERSION(6, 1, 0): 1794 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1795 break; 1796 case IP_VERSION(7, 0, 0): 1797 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1798 break; 1799 default: 1800 dev_err(adev->dev, 1801 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1802 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1803 return -EINVAL; 1804 } 1805 return 0; 1806 } 1807 1808 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1809 { 1810 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1811 case IP_VERSION(9, 0, 0): 1812 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1813 break; 1814 case IP_VERSION(10, 0, 0): 1815 case IP_VERSION(10, 0, 1): 1816 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1817 break; 1818 case IP_VERSION(11, 0, 0): 1819 case IP_VERSION(11, 0, 2): 1820 case IP_VERSION(11, 0, 4): 1821 case IP_VERSION(11, 0, 5): 1822 case IP_VERSION(11, 0, 9): 1823 case IP_VERSION(11, 0, 7): 1824 case IP_VERSION(11, 0, 11): 1825 case IP_VERSION(11, 0, 12): 1826 case IP_VERSION(11, 0, 13): 1827 case IP_VERSION(11, 5, 0): 1828 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1829 break; 1830 case IP_VERSION(11, 0, 8): 1831 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1832 break; 1833 case IP_VERSION(11, 0, 3): 1834 case IP_VERSION(12, 0, 1): 1835 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1836 break; 1837 case IP_VERSION(13, 0, 0): 1838 case IP_VERSION(13, 0, 1): 1839 case IP_VERSION(13, 0, 2): 1840 case IP_VERSION(13, 0, 3): 1841 case IP_VERSION(13, 0, 5): 1842 case IP_VERSION(13, 0, 6): 1843 case IP_VERSION(13, 0, 7): 1844 case IP_VERSION(13, 0, 8): 1845 case IP_VERSION(13, 0, 10): 1846 case IP_VERSION(13, 0, 11): 1847 case IP_VERSION(14, 0, 0): 1848 case IP_VERSION(14, 0, 1): 1849 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1850 break; 1851 case IP_VERSION(13, 0, 4): 1852 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1853 break; 1854 case IP_VERSION(14, 0, 2): 1855 case IP_VERSION(14, 0, 3): 1856 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 1857 break; 1858 default: 1859 dev_err(adev->dev, 1860 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1861 amdgpu_ip_version(adev, MP0_HWIP, 0)); 1862 return -EINVAL; 1863 } 1864 return 0; 1865 } 1866 1867 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1868 { 1869 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1870 case IP_VERSION(9, 0, 0): 1871 case IP_VERSION(10, 0, 0): 1872 case IP_VERSION(10, 0, 1): 1873 case IP_VERSION(11, 0, 2): 1874 if (adev->asic_type == CHIP_ARCTURUS) 1875 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1876 else 1877 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1878 break; 1879 case IP_VERSION(11, 0, 0): 1880 case IP_VERSION(11, 0, 5): 1881 case IP_VERSION(11, 0, 9): 1882 case IP_VERSION(11, 0, 7): 1883 case IP_VERSION(11, 0, 8): 1884 case IP_VERSION(11, 0, 11): 1885 case IP_VERSION(11, 0, 12): 1886 case IP_VERSION(11, 0, 13): 1887 case IP_VERSION(11, 5, 0): 1888 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1889 break; 1890 case IP_VERSION(12, 0, 0): 1891 case IP_VERSION(12, 0, 1): 1892 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1893 break; 1894 case IP_VERSION(13, 0, 0): 1895 case IP_VERSION(13, 0, 1): 1896 case IP_VERSION(13, 0, 2): 1897 case IP_VERSION(13, 0, 3): 1898 case IP_VERSION(13, 0, 4): 1899 case IP_VERSION(13, 0, 5): 1900 case IP_VERSION(13, 0, 6): 1901 case IP_VERSION(13, 0, 7): 1902 case IP_VERSION(13, 0, 8): 1903 case IP_VERSION(13, 0, 10): 1904 case IP_VERSION(13, 0, 11): 1905 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1906 break; 1907 case IP_VERSION(14, 0, 0): 1908 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 1909 break; 1910 default: 1911 dev_err(adev->dev, 1912 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1913 amdgpu_ip_version(adev, MP1_HWIP, 0)); 1914 return -EINVAL; 1915 } 1916 return 0; 1917 } 1918 1919 #if defined(CONFIG_DRM_AMD_DC) 1920 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1921 { 1922 amdgpu_device_set_sriov_virtual_display(adev); 1923 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1924 } 1925 #endif 1926 1927 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1928 { 1929 if (adev->enable_virtual_display) { 1930 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1931 return 0; 1932 } 1933 1934 if (!amdgpu_device_has_dc_support(adev)) 1935 return 0; 1936 1937 #if defined(CONFIG_DRM_AMD_DC) 1938 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1939 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1940 case IP_VERSION(1, 0, 0): 1941 case IP_VERSION(1, 0, 1): 1942 case IP_VERSION(2, 0, 2): 1943 case IP_VERSION(2, 0, 0): 1944 case IP_VERSION(2, 0, 3): 1945 case IP_VERSION(2, 1, 0): 1946 case IP_VERSION(3, 0, 0): 1947 case IP_VERSION(3, 0, 2): 1948 case IP_VERSION(3, 0, 3): 1949 case IP_VERSION(3, 0, 1): 1950 case IP_VERSION(3, 1, 2): 1951 case IP_VERSION(3, 1, 3): 1952 case IP_VERSION(3, 1, 4): 1953 case IP_VERSION(3, 1, 5): 1954 case IP_VERSION(3, 1, 6): 1955 case IP_VERSION(3, 2, 0): 1956 case IP_VERSION(3, 2, 1): 1957 case IP_VERSION(3, 5, 0): 1958 case IP_VERSION(3, 5, 1): 1959 if (amdgpu_sriov_vf(adev)) 1960 amdgpu_discovery_set_sriov_display(adev); 1961 else 1962 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1963 break; 1964 default: 1965 dev_err(adev->dev, 1966 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1967 amdgpu_ip_version(adev, DCE_HWIP, 0)); 1968 return -EINVAL; 1969 } 1970 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1971 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1972 case IP_VERSION(12, 0, 0): 1973 case IP_VERSION(12, 0, 1): 1974 case IP_VERSION(12, 1, 0): 1975 if (amdgpu_sriov_vf(adev)) 1976 amdgpu_discovery_set_sriov_display(adev); 1977 else 1978 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1979 break; 1980 default: 1981 dev_err(adev->dev, 1982 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1983 amdgpu_ip_version(adev, DCI_HWIP, 0)); 1984 return -EINVAL; 1985 } 1986 } 1987 #endif 1988 return 0; 1989 } 1990 1991 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1992 { 1993 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1994 case IP_VERSION(9, 0, 1): 1995 case IP_VERSION(9, 1, 0): 1996 case IP_VERSION(9, 2, 1): 1997 case IP_VERSION(9, 2, 2): 1998 case IP_VERSION(9, 3, 0): 1999 case IP_VERSION(9, 4, 0): 2000 case IP_VERSION(9, 4, 1): 2001 case IP_VERSION(9, 4, 2): 2002 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2003 break; 2004 case IP_VERSION(9, 4, 3): 2005 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2006 break; 2007 case IP_VERSION(10, 1, 10): 2008 case IP_VERSION(10, 1, 2): 2009 case IP_VERSION(10, 1, 1): 2010 case IP_VERSION(10, 1, 3): 2011 case IP_VERSION(10, 1, 4): 2012 case IP_VERSION(10, 3, 0): 2013 case IP_VERSION(10, 3, 2): 2014 case IP_VERSION(10, 3, 1): 2015 case IP_VERSION(10, 3, 4): 2016 case IP_VERSION(10, 3, 5): 2017 case IP_VERSION(10, 3, 6): 2018 case IP_VERSION(10, 3, 3): 2019 case IP_VERSION(10, 3, 7): 2020 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2021 break; 2022 case IP_VERSION(11, 0, 0): 2023 case IP_VERSION(11, 0, 1): 2024 case IP_VERSION(11, 0, 2): 2025 case IP_VERSION(11, 0, 3): 2026 case IP_VERSION(11, 0, 4): 2027 case IP_VERSION(11, 5, 0): 2028 case IP_VERSION(11, 5, 1): 2029 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2030 break; 2031 default: 2032 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2033 amdgpu_ip_version(adev, GC_HWIP, 0)); 2034 return -EINVAL; 2035 } 2036 return 0; 2037 } 2038 2039 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2040 { 2041 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2042 case IP_VERSION(4, 0, 0): 2043 case IP_VERSION(4, 0, 1): 2044 case IP_VERSION(4, 1, 0): 2045 case IP_VERSION(4, 1, 1): 2046 case IP_VERSION(4, 1, 2): 2047 case IP_VERSION(4, 2, 0): 2048 case IP_VERSION(4, 2, 2): 2049 case IP_VERSION(4, 4, 0): 2050 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2051 break; 2052 case IP_VERSION(4, 4, 2): 2053 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2054 break; 2055 case IP_VERSION(5, 0, 0): 2056 case IP_VERSION(5, 0, 1): 2057 case IP_VERSION(5, 0, 2): 2058 case IP_VERSION(5, 0, 5): 2059 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2060 break; 2061 case IP_VERSION(5, 2, 0): 2062 case IP_VERSION(5, 2, 2): 2063 case IP_VERSION(5, 2, 4): 2064 case IP_VERSION(5, 2, 5): 2065 case IP_VERSION(5, 2, 6): 2066 case IP_VERSION(5, 2, 3): 2067 case IP_VERSION(5, 2, 1): 2068 case IP_VERSION(5, 2, 7): 2069 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2070 break; 2071 case IP_VERSION(6, 0, 0): 2072 case IP_VERSION(6, 0, 1): 2073 case IP_VERSION(6, 0, 2): 2074 case IP_VERSION(6, 0, 3): 2075 case IP_VERSION(6, 1, 0): 2076 case IP_VERSION(6, 1, 1): 2077 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2078 break; 2079 default: 2080 dev_err(adev->dev, 2081 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2082 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2083 return -EINVAL; 2084 } 2085 return 0; 2086 } 2087 2088 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2089 { 2090 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2091 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2092 case IP_VERSION(7, 0, 0): 2093 case IP_VERSION(7, 2, 0): 2094 /* UVD is not supported on vega20 SR-IOV */ 2095 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2096 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2097 break; 2098 default: 2099 dev_err(adev->dev, 2100 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2101 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2102 return -EINVAL; 2103 } 2104 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2105 case IP_VERSION(4, 0, 0): 2106 case IP_VERSION(4, 1, 0): 2107 /* VCE is not supported on vega20 SR-IOV */ 2108 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2109 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2110 break; 2111 default: 2112 dev_err(adev->dev, 2113 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2114 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2115 return -EINVAL; 2116 } 2117 } else { 2118 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2119 case IP_VERSION(1, 0, 0): 2120 case IP_VERSION(1, 0, 1): 2121 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2122 break; 2123 case IP_VERSION(2, 0, 0): 2124 case IP_VERSION(2, 0, 2): 2125 case IP_VERSION(2, 2, 0): 2126 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2127 if (!amdgpu_sriov_vf(adev)) 2128 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2129 break; 2130 case IP_VERSION(2, 0, 3): 2131 break; 2132 case IP_VERSION(2, 5, 0): 2133 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2134 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2135 break; 2136 case IP_VERSION(2, 6, 0): 2137 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2138 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2139 break; 2140 case IP_VERSION(3, 0, 0): 2141 case IP_VERSION(3, 0, 16): 2142 case IP_VERSION(3, 1, 1): 2143 case IP_VERSION(3, 1, 2): 2144 case IP_VERSION(3, 0, 2): 2145 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2146 if (!amdgpu_sriov_vf(adev)) 2147 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2148 break; 2149 case IP_VERSION(3, 0, 33): 2150 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2151 break; 2152 case IP_VERSION(4, 0, 0): 2153 case IP_VERSION(4, 0, 2): 2154 case IP_VERSION(4, 0, 4): 2155 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2156 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2157 break; 2158 case IP_VERSION(4, 0, 3): 2159 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2160 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2161 break; 2162 case IP_VERSION(4, 0, 5): 2163 case IP_VERSION(4, 0, 6): 2164 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2165 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2166 break; 2167 case IP_VERSION(5, 0, 0): 2168 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2169 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2170 break; 2171 default: 2172 dev_err(adev->dev, 2173 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2174 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2175 return -EINVAL; 2176 } 2177 } 2178 return 0; 2179 } 2180 2181 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2182 { 2183 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2184 case IP_VERSION(10, 1, 10): 2185 case IP_VERSION(10, 1, 1): 2186 case IP_VERSION(10, 1, 2): 2187 case IP_VERSION(10, 1, 3): 2188 case IP_VERSION(10, 1, 4): 2189 case IP_VERSION(10, 3, 0): 2190 case IP_VERSION(10, 3, 1): 2191 case IP_VERSION(10, 3, 2): 2192 case IP_VERSION(10, 3, 3): 2193 case IP_VERSION(10, 3, 4): 2194 case IP_VERSION(10, 3, 5): 2195 case IP_VERSION(10, 3, 6): 2196 if (amdgpu_mes) { 2197 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 2198 adev->enable_mes = true; 2199 if (amdgpu_mes_kiq) 2200 adev->enable_mes_kiq = true; 2201 } 2202 break; 2203 case IP_VERSION(11, 0, 0): 2204 case IP_VERSION(11, 0, 1): 2205 case IP_VERSION(11, 0, 2): 2206 case IP_VERSION(11, 0, 3): 2207 case IP_VERSION(11, 0, 4): 2208 case IP_VERSION(11, 5, 0): 2209 case IP_VERSION(11, 5, 1): 2210 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2211 adev->enable_mes = true; 2212 adev->enable_mes_kiq = true; 2213 break; 2214 default: 2215 break; 2216 } 2217 return 0; 2218 } 2219 2220 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2221 { 2222 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2223 case IP_VERSION(9, 4, 3): 2224 aqua_vanjaram_init_soc_config(adev); 2225 break; 2226 default: 2227 break; 2228 } 2229 } 2230 2231 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2232 { 2233 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2234 case IP_VERSION(6, 1, 0): 2235 case IP_VERSION(6, 1, 1): 2236 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 return 0; 2243 } 2244 2245 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2246 { 2247 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2248 case IP_VERSION(4, 0, 5): 2249 case IP_VERSION(4, 0, 6): 2250 if (amdgpu_umsch_mm & 0x1) { 2251 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2252 adev->enable_umsch_mm = true; 2253 } 2254 break; 2255 default: 2256 break; 2257 } 2258 2259 return 0; 2260 } 2261 2262 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2263 { 2264 int r; 2265 2266 switch (adev->asic_type) { 2267 case CHIP_VEGA10: 2268 vega10_reg_base_init(adev); 2269 adev->sdma.num_instances = 2; 2270 adev->gmc.num_umc = 4; 2271 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2272 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2273 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2274 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2275 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2276 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2277 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2278 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2279 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2280 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2281 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2282 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2283 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2284 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2285 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2286 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2287 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2288 break; 2289 case CHIP_VEGA12: 2290 vega10_reg_base_init(adev); 2291 adev->sdma.num_instances = 2; 2292 adev->gmc.num_umc = 4; 2293 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2294 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2295 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2296 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2297 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2298 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2299 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2300 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2301 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2302 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2303 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2304 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2305 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2306 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2307 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2308 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2309 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2310 break; 2311 case CHIP_RAVEN: 2312 vega10_reg_base_init(adev); 2313 adev->sdma.num_instances = 1; 2314 adev->vcn.num_vcn_inst = 1; 2315 adev->gmc.num_umc = 2; 2316 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2317 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2318 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2319 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2320 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2321 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2322 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2323 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2324 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2325 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2326 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2327 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2328 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2329 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2330 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2331 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2332 } else { 2333 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2334 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2335 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2336 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2337 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2338 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2339 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2340 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2341 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2342 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2343 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2344 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2345 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2346 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2347 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2348 } 2349 break; 2350 case CHIP_VEGA20: 2351 vega20_reg_base_init(adev); 2352 adev->sdma.num_instances = 2; 2353 adev->gmc.num_umc = 8; 2354 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2355 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2356 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2357 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2358 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2359 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2360 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2361 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2362 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2363 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2364 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2365 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2366 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2367 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2368 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2369 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2370 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2371 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2372 break; 2373 case CHIP_ARCTURUS: 2374 arct_reg_base_init(adev); 2375 adev->sdma.num_instances = 8; 2376 adev->vcn.num_vcn_inst = 2; 2377 adev->gmc.num_umc = 8; 2378 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2379 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2380 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2381 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2382 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2383 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2384 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2385 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2386 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2387 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2388 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2389 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2390 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2391 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2392 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2393 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2394 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2395 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2396 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2397 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2398 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2399 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2400 break; 2401 case CHIP_ALDEBARAN: 2402 aldebaran_reg_base_init(adev); 2403 adev->sdma.num_instances = 5; 2404 adev->vcn.num_vcn_inst = 2; 2405 adev->gmc.num_umc = 4; 2406 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2407 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2408 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2409 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2410 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2411 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2412 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2413 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2414 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2415 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2416 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2417 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2418 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2419 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2420 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2421 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2422 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2423 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2424 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2425 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2426 break; 2427 default: 2428 r = amdgpu_discovery_reg_base_init(adev); 2429 if (r) 2430 return -EINVAL; 2431 2432 amdgpu_discovery_harvest_ip(adev); 2433 amdgpu_discovery_get_gfx_info(adev); 2434 amdgpu_discovery_get_mall_info(adev); 2435 amdgpu_discovery_get_vcn_info(adev); 2436 break; 2437 } 2438 2439 amdgpu_discovery_init_soc_config(adev); 2440 amdgpu_discovery_sysfs_init(adev); 2441 2442 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2443 case IP_VERSION(9, 0, 1): 2444 case IP_VERSION(9, 2, 1): 2445 case IP_VERSION(9, 4, 0): 2446 case IP_VERSION(9, 4, 1): 2447 case IP_VERSION(9, 4, 2): 2448 case IP_VERSION(9, 4, 3): 2449 adev->family = AMDGPU_FAMILY_AI; 2450 break; 2451 case IP_VERSION(9, 1, 0): 2452 case IP_VERSION(9, 2, 2): 2453 case IP_VERSION(9, 3, 0): 2454 adev->family = AMDGPU_FAMILY_RV; 2455 break; 2456 case IP_VERSION(10, 1, 10): 2457 case IP_VERSION(10, 1, 1): 2458 case IP_VERSION(10, 1, 2): 2459 case IP_VERSION(10, 1, 3): 2460 case IP_VERSION(10, 1, 4): 2461 case IP_VERSION(10, 3, 0): 2462 case IP_VERSION(10, 3, 2): 2463 case IP_VERSION(10, 3, 4): 2464 case IP_VERSION(10, 3, 5): 2465 adev->family = AMDGPU_FAMILY_NV; 2466 break; 2467 case IP_VERSION(10, 3, 1): 2468 adev->family = AMDGPU_FAMILY_VGH; 2469 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2470 break; 2471 case IP_VERSION(10, 3, 3): 2472 adev->family = AMDGPU_FAMILY_YC; 2473 break; 2474 case IP_VERSION(10, 3, 6): 2475 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2476 break; 2477 case IP_VERSION(10, 3, 7): 2478 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2479 break; 2480 case IP_VERSION(11, 0, 0): 2481 case IP_VERSION(11, 0, 2): 2482 case IP_VERSION(11, 0, 3): 2483 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2484 break; 2485 case IP_VERSION(11, 0, 1): 2486 case IP_VERSION(11, 0, 4): 2487 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2488 break; 2489 case IP_VERSION(11, 5, 0): 2490 case IP_VERSION(11, 5, 1): 2491 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2492 break; 2493 default: 2494 return -EINVAL; 2495 } 2496 2497 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2498 case IP_VERSION(9, 1, 0): 2499 case IP_VERSION(9, 2, 2): 2500 case IP_VERSION(9, 3, 0): 2501 case IP_VERSION(10, 1, 3): 2502 case IP_VERSION(10, 1, 4): 2503 case IP_VERSION(10, 3, 1): 2504 case IP_VERSION(10, 3, 3): 2505 case IP_VERSION(10, 3, 6): 2506 case IP_VERSION(10, 3, 7): 2507 case IP_VERSION(11, 0, 1): 2508 case IP_VERSION(11, 0, 4): 2509 case IP_VERSION(11, 5, 0): 2510 case IP_VERSION(11, 5, 1): 2511 adev->flags |= AMD_IS_APU; 2512 break; 2513 default: 2514 break; 2515 } 2516 2517 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2518 adev->gmc.xgmi.supported = true; 2519 2520 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2521 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2522 2523 /* set NBIO version */ 2524 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2525 case IP_VERSION(6, 1, 0): 2526 case IP_VERSION(6, 2, 0): 2527 adev->nbio.funcs = &nbio_v6_1_funcs; 2528 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2529 break; 2530 case IP_VERSION(7, 0, 0): 2531 case IP_VERSION(7, 0, 1): 2532 case IP_VERSION(2, 5, 0): 2533 adev->nbio.funcs = &nbio_v7_0_funcs; 2534 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2535 break; 2536 case IP_VERSION(7, 4, 0): 2537 case IP_VERSION(7, 4, 1): 2538 case IP_VERSION(7, 4, 4): 2539 adev->nbio.funcs = &nbio_v7_4_funcs; 2540 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2541 break; 2542 case IP_VERSION(7, 9, 0): 2543 adev->nbio.funcs = &nbio_v7_9_funcs; 2544 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2545 break; 2546 case IP_VERSION(7, 11, 0): 2547 case IP_VERSION(7, 11, 1): 2548 adev->nbio.funcs = &nbio_v7_11_funcs; 2549 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2550 break; 2551 case IP_VERSION(7, 2, 0): 2552 case IP_VERSION(7, 2, 1): 2553 case IP_VERSION(7, 3, 0): 2554 case IP_VERSION(7, 5, 0): 2555 case IP_VERSION(7, 5, 1): 2556 adev->nbio.funcs = &nbio_v7_2_funcs; 2557 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2558 break; 2559 case IP_VERSION(2, 1, 1): 2560 case IP_VERSION(2, 3, 0): 2561 case IP_VERSION(2, 3, 1): 2562 case IP_VERSION(2, 3, 2): 2563 case IP_VERSION(3, 3, 0): 2564 case IP_VERSION(3, 3, 1): 2565 case IP_VERSION(3, 3, 2): 2566 case IP_VERSION(3, 3, 3): 2567 adev->nbio.funcs = &nbio_v2_3_funcs; 2568 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2569 break; 2570 case IP_VERSION(4, 3, 0): 2571 case IP_VERSION(4, 3, 1): 2572 if (amdgpu_sriov_vf(adev)) 2573 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2574 else 2575 adev->nbio.funcs = &nbio_v4_3_funcs; 2576 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2577 break; 2578 case IP_VERSION(7, 7, 0): 2579 case IP_VERSION(7, 7, 1): 2580 adev->nbio.funcs = &nbio_v7_7_funcs; 2581 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2582 break; 2583 case IP_VERSION(6, 3, 1): 2584 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2585 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2586 break; 2587 default: 2588 break; 2589 } 2590 2591 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2592 case IP_VERSION(4, 0, 0): 2593 case IP_VERSION(4, 0, 1): 2594 case IP_VERSION(4, 1, 0): 2595 case IP_VERSION(4, 1, 1): 2596 case IP_VERSION(4, 1, 2): 2597 case IP_VERSION(4, 2, 0): 2598 case IP_VERSION(4, 2, 1): 2599 case IP_VERSION(4, 4, 0): 2600 case IP_VERSION(4, 4, 2): 2601 adev->hdp.funcs = &hdp_v4_0_funcs; 2602 break; 2603 case IP_VERSION(5, 0, 0): 2604 case IP_VERSION(5, 0, 1): 2605 case IP_VERSION(5, 0, 2): 2606 case IP_VERSION(5, 0, 3): 2607 case IP_VERSION(5, 0, 4): 2608 case IP_VERSION(5, 2, 0): 2609 adev->hdp.funcs = &hdp_v5_0_funcs; 2610 break; 2611 case IP_VERSION(5, 2, 1): 2612 adev->hdp.funcs = &hdp_v5_2_funcs; 2613 break; 2614 case IP_VERSION(6, 0, 0): 2615 case IP_VERSION(6, 0, 1): 2616 case IP_VERSION(6, 1, 0): 2617 adev->hdp.funcs = &hdp_v6_0_funcs; 2618 break; 2619 case IP_VERSION(7, 0, 0): 2620 adev->hdp.funcs = &hdp_v7_0_funcs; 2621 break; 2622 default: 2623 break; 2624 } 2625 2626 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2627 case IP_VERSION(3, 6, 0): 2628 case IP_VERSION(3, 6, 1): 2629 case IP_VERSION(3, 6, 2): 2630 adev->df.funcs = &df_v3_6_funcs; 2631 break; 2632 case IP_VERSION(2, 1, 0): 2633 case IP_VERSION(2, 1, 1): 2634 case IP_VERSION(2, 5, 0): 2635 case IP_VERSION(3, 5, 1): 2636 case IP_VERSION(3, 5, 2): 2637 adev->df.funcs = &df_v1_7_funcs; 2638 break; 2639 case IP_VERSION(4, 3, 0): 2640 adev->df.funcs = &df_v4_3_funcs; 2641 break; 2642 case IP_VERSION(4, 6, 2): 2643 adev->df.funcs = &df_v4_6_2_funcs; 2644 break; 2645 default: 2646 break; 2647 } 2648 2649 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2650 case IP_VERSION(9, 0, 0): 2651 case IP_VERSION(9, 0, 1): 2652 case IP_VERSION(10, 0, 0): 2653 case IP_VERSION(10, 0, 1): 2654 case IP_VERSION(10, 0, 2): 2655 adev->smuio.funcs = &smuio_v9_0_funcs; 2656 break; 2657 case IP_VERSION(11, 0, 0): 2658 case IP_VERSION(11, 0, 2): 2659 case IP_VERSION(11, 0, 3): 2660 case IP_VERSION(11, 0, 4): 2661 case IP_VERSION(11, 0, 7): 2662 case IP_VERSION(11, 0, 8): 2663 adev->smuio.funcs = &smuio_v11_0_funcs; 2664 break; 2665 case IP_VERSION(11, 0, 6): 2666 case IP_VERSION(11, 0, 10): 2667 case IP_VERSION(11, 0, 11): 2668 case IP_VERSION(11, 5, 0): 2669 case IP_VERSION(13, 0, 1): 2670 case IP_VERSION(13, 0, 9): 2671 case IP_VERSION(13, 0, 10): 2672 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2673 break; 2674 case IP_VERSION(13, 0, 2): 2675 adev->smuio.funcs = &smuio_v13_0_funcs; 2676 break; 2677 case IP_VERSION(13, 0, 3): 2678 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2679 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2680 adev->flags |= AMD_IS_APU; 2681 } 2682 break; 2683 case IP_VERSION(13, 0, 6): 2684 case IP_VERSION(13, 0, 8): 2685 case IP_VERSION(14, 0, 0): 2686 case IP_VERSION(14, 0, 1): 2687 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2688 break; 2689 case IP_VERSION(14, 0, 2): 2690 adev->smuio.funcs = &smuio_v14_0_2_funcs; 2691 break; 2692 default: 2693 break; 2694 } 2695 2696 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2697 case IP_VERSION(6, 0, 0): 2698 case IP_VERSION(6, 0, 1): 2699 case IP_VERSION(6, 0, 2): 2700 case IP_VERSION(6, 0, 3): 2701 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2702 break; 2703 case IP_VERSION(7, 0, 0): 2704 case IP_VERSION(7, 0, 1): 2705 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2706 break; 2707 default: 2708 break; 2709 } 2710 2711 r = amdgpu_discovery_set_common_ip_blocks(adev); 2712 if (r) 2713 return r; 2714 2715 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2716 if (r) 2717 return r; 2718 2719 /* For SR-IOV, PSP needs to be initialized before IH */ 2720 if (amdgpu_sriov_vf(adev)) { 2721 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2722 if (r) 2723 return r; 2724 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2725 if (r) 2726 return r; 2727 } else { 2728 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2729 if (r) 2730 return r; 2731 2732 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2733 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2734 if (r) 2735 return r; 2736 } 2737 } 2738 2739 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2740 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2741 if (r) 2742 return r; 2743 } 2744 2745 r = amdgpu_discovery_set_display_ip_blocks(adev); 2746 if (r) 2747 return r; 2748 2749 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2750 if (r) 2751 return r; 2752 2753 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2754 if (r) 2755 return r; 2756 2757 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2758 !amdgpu_sriov_vf(adev)) || 2759 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2760 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2761 if (r) 2762 return r; 2763 } 2764 2765 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2766 if (r) 2767 return r; 2768 2769 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2770 if (r) 2771 return r; 2772 2773 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 2774 if (r) 2775 return r; 2776 2777 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 2778 if (r) 2779 return r; 2780 2781 return 0; 2782 } 2783 2784