1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <[email protected]> 26 */ 27 #include <linux/list_sort.h> 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 34 u32 ip_instance, u32 ring, 35 struct amdgpu_ring **out_ring) 36 { 37 /* Right now all IPs have only one instance - multiple rings. */ 38 if (ip_instance != 0) { 39 DRM_ERROR("invalid ip instance: %d\n", ip_instance); 40 return -EINVAL; 41 } 42 43 switch (ip_type) { 44 default: 45 DRM_ERROR("unknown ip type: %d\n", ip_type); 46 return -EINVAL; 47 case AMDGPU_HW_IP_GFX: 48 if (ring < adev->gfx.num_gfx_rings) { 49 *out_ring = &adev->gfx.gfx_ring[ring]; 50 } else { 51 DRM_ERROR("only %d gfx rings are supported now\n", 52 adev->gfx.num_gfx_rings); 53 return -EINVAL; 54 } 55 break; 56 case AMDGPU_HW_IP_COMPUTE: 57 if (ring < adev->gfx.num_compute_rings) { 58 *out_ring = &adev->gfx.compute_ring[ring]; 59 } else { 60 DRM_ERROR("only %d compute rings are supported now\n", 61 adev->gfx.num_compute_rings); 62 return -EINVAL; 63 } 64 break; 65 case AMDGPU_HW_IP_DMA: 66 if (ring < adev->sdma.num_instances) { 67 *out_ring = &adev->sdma.instance[ring].ring; 68 } else { 69 DRM_ERROR("only %d SDMA rings are supported\n", 70 adev->sdma.num_instances); 71 return -EINVAL; 72 } 73 break; 74 case AMDGPU_HW_IP_UVD: 75 *out_ring = &adev->uvd.ring; 76 break; 77 case AMDGPU_HW_IP_VCE: 78 if (ring < 2){ 79 *out_ring = &adev->vce.ring[ring]; 80 } else { 81 DRM_ERROR("only two VCE rings are supported\n"); 82 return -EINVAL; 83 } 84 break; 85 } 86 return 0; 87 } 88 89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 90 struct amdgpu_user_fence *uf, 91 struct drm_amdgpu_cs_chunk_fence *fence_data) 92 { 93 struct drm_gem_object *gobj; 94 uint32_t handle; 95 96 handle = fence_data->handle; 97 gobj = drm_gem_object_lookup(p->adev->ddev, p->filp, 98 fence_data->handle); 99 if (gobj == NULL) 100 return -EINVAL; 101 102 uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); 103 uf->offset = fence_data->offset; 104 105 if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) { 106 drm_gem_object_unreference_unlocked(gobj); 107 return -EINVAL; 108 } 109 110 p->uf_entry.robj = amdgpu_bo_ref(uf->bo); 111 p->uf_entry.priority = 0; 112 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; 113 p->uf_entry.tv.shared = true; 114 p->uf_entry.user_pages = NULL; 115 116 drm_gem_object_unreference_unlocked(gobj); 117 return 0; 118 } 119 120 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 121 { 122 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 123 union drm_amdgpu_cs *cs = data; 124 uint64_t *chunk_array_user; 125 uint64_t *chunk_array; 126 struct amdgpu_user_fence uf = {}; 127 unsigned size, num_ibs = 0; 128 int i; 129 int ret; 130 131 if (cs->in.num_chunks == 0) 132 return 0; 133 134 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); 135 if (!chunk_array) 136 return -ENOMEM; 137 138 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); 139 if (!p->ctx) { 140 ret = -EINVAL; 141 goto free_chunk; 142 } 143 144 /* get chunks */ 145 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); 146 if (copy_from_user(chunk_array, chunk_array_user, 147 sizeof(uint64_t)*cs->in.num_chunks)) { 148 ret = -EFAULT; 149 goto put_ctx; 150 } 151 152 p->nchunks = cs->in.num_chunks; 153 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), 154 GFP_KERNEL); 155 if (!p->chunks) { 156 ret = -ENOMEM; 157 goto put_ctx; 158 } 159 160 for (i = 0; i < p->nchunks; i++) { 161 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; 162 struct drm_amdgpu_cs_chunk user_chunk; 163 uint32_t __user *cdata; 164 165 chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; 166 if (copy_from_user(&user_chunk, chunk_ptr, 167 sizeof(struct drm_amdgpu_cs_chunk))) { 168 ret = -EFAULT; 169 i--; 170 goto free_partial_kdata; 171 } 172 p->chunks[i].chunk_id = user_chunk.chunk_id; 173 p->chunks[i].length_dw = user_chunk.length_dw; 174 175 size = p->chunks[i].length_dw; 176 cdata = (void __user *)(unsigned long)user_chunk.chunk_data; 177 178 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); 179 if (p->chunks[i].kdata == NULL) { 180 ret = -ENOMEM; 181 i--; 182 goto free_partial_kdata; 183 } 184 size *= sizeof(uint32_t); 185 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 186 ret = -EFAULT; 187 goto free_partial_kdata; 188 } 189 190 switch (p->chunks[i].chunk_id) { 191 case AMDGPU_CHUNK_ID_IB: 192 ++num_ibs; 193 break; 194 195 case AMDGPU_CHUNK_ID_FENCE: 196 size = sizeof(struct drm_amdgpu_cs_chunk_fence); 197 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { 198 ret = -EINVAL; 199 goto free_partial_kdata; 200 } 201 202 ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata); 203 if (ret) 204 goto free_partial_kdata; 205 206 break; 207 208 case AMDGPU_CHUNK_ID_DEPENDENCIES: 209 break; 210 211 default: 212 ret = -EINVAL; 213 goto free_partial_kdata; 214 } 215 } 216 217 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job); 218 if (ret) 219 goto free_all_kdata; 220 221 p->job->uf = uf; 222 223 kfree(chunk_array); 224 return 0; 225 226 free_all_kdata: 227 i = p->nchunks - 1; 228 free_partial_kdata: 229 for (; i >= 0; i--) 230 drm_free_large(p->chunks[i].kdata); 231 kfree(p->chunks); 232 put_ctx: 233 amdgpu_ctx_put(p->ctx); 234 free_chunk: 235 kfree(chunk_array); 236 237 return ret; 238 } 239 240 /* Returns how many bytes TTM can move per IB. 241 */ 242 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) 243 { 244 u64 real_vram_size = adev->mc.real_vram_size; 245 u64 vram_usage = atomic64_read(&adev->vram_usage); 246 247 /* This function is based on the current VRAM usage. 248 * 249 * - If all of VRAM is free, allow relocating the number of bytes that 250 * is equal to 1/4 of the size of VRAM for this IB. 251 252 * - If more than one half of VRAM is occupied, only allow relocating 253 * 1 MB of data for this IB. 254 * 255 * - From 0 to one half of used VRAM, the threshold decreases 256 * linearly. 257 * __________________ 258 * 1/4 of -|\ | 259 * VRAM | \ | 260 * | \ | 261 * | \ | 262 * | \ | 263 * | \ | 264 * | \ | 265 * | \________|1 MB 266 * |----------------| 267 * VRAM 0 % 100 % 268 * used used 269 * 270 * Note: It's a threshold, not a limit. The threshold must be crossed 271 * for buffer relocations to stop, so any buffer of an arbitrary size 272 * can be moved as long as the threshold isn't crossed before 273 * the relocation takes place. We don't want to disable buffer 274 * relocations completely. 275 * 276 * The idea is that buffers should be placed in VRAM at creation time 277 * and TTM should only do a minimum number of relocations during 278 * command submission. In practice, you need to submit at least 279 * a dozen IBs to move all buffers to VRAM if they are in GTT. 280 * 281 * Also, things can get pretty crazy under memory pressure and actual 282 * VRAM usage can change a lot, so playing safe even at 50% does 283 * consistently increase performance. 284 */ 285 286 u64 half_vram = real_vram_size >> 1; 287 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 288 u64 bytes_moved_threshold = half_free_vram >> 1; 289 return max(bytes_moved_threshold, 1024*1024ull); 290 } 291 292 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 293 struct list_head *validated) 294 { 295 struct amdgpu_bo_list_entry *lobj; 296 u64 initial_bytes_moved; 297 int r; 298 299 list_for_each_entry(lobj, validated, tv.head) { 300 struct amdgpu_bo *bo = lobj->robj; 301 bool binding_userptr = false; 302 struct mm_struct *usermm; 303 uint32_t domain; 304 305 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); 306 if (usermm && usermm != current->mm) 307 return -EPERM; 308 309 /* Check if we have user pages and nobody bound the BO already */ 310 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { 311 size_t size = sizeof(struct page *); 312 313 size *= bo->tbo.ttm->num_pages; 314 memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); 315 binding_userptr = true; 316 } 317 318 if (bo->pin_count) 319 continue; 320 321 /* Avoid moving this one if we have moved too many buffers 322 * for this IB already. 323 * 324 * Note that this allows moving at least one buffer of 325 * any size, because it doesn't take the current "bo" 326 * into account. We don't want to disallow buffer moves 327 * completely. 328 */ 329 if (p->bytes_moved <= p->bytes_moved_threshold) 330 domain = bo->prefered_domains; 331 else 332 domain = bo->allowed_domains; 333 334 retry: 335 amdgpu_ttm_placement_from_domain(bo, domain); 336 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); 337 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 338 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - 339 initial_bytes_moved; 340 341 if (unlikely(r)) { 342 if (r != -ERESTARTSYS && domain != bo->allowed_domains) { 343 domain = bo->allowed_domains; 344 goto retry; 345 } 346 return r; 347 } 348 349 if (binding_userptr) { 350 drm_free_large(lobj->user_pages); 351 lobj->user_pages = NULL; 352 } 353 } 354 return 0; 355 } 356 357 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 358 union drm_amdgpu_cs *cs) 359 { 360 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 361 struct amdgpu_bo_list_entry *e; 362 struct list_head duplicates; 363 bool need_mmap_lock = false; 364 unsigned i, tries = 10; 365 int r; 366 367 INIT_LIST_HEAD(&p->validated); 368 369 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); 370 if (p->bo_list) { 371 need_mmap_lock = p->bo_list->first_userptr != 372 p->bo_list->num_entries; 373 amdgpu_bo_list_get_list(p->bo_list, &p->validated); 374 } 375 376 INIT_LIST_HEAD(&duplicates); 377 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); 378 379 if (p->job->uf.bo) 380 list_add(&p->uf_entry.tv.head, &p->validated); 381 382 if (need_mmap_lock) 383 down_read(¤t->mm->mmap_sem); 384 385 while (1) { 386 struct list_head need_pages; 387 unsigned i; 388 389 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, 390 &duplicates); 391 if (unlikely(r != 0)) 392 goto error_free_pages; 393 394 /* Without a BO list we don't have userptr BOs */ 395 if (!p->bo_list) 396 break; 397 398 INIT_LIST_HEAD(&need_pages); 399 for (i = p->bo_list->first_userptr; 400 i < p->bo_list->num_entries; ++i) { 401 402 e = &p->bo_list->array[i]; 403 404 if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, 405 &e->user_invalidated) && e->user_pages) { 406 407 /* We acquired a page array, but somebody 408 * invalidated it. Free it an try again 409 */ 410 release_pages(e->user_pages, 411 e->robj->tbo.ttm->num_pages, 412 false); 413 drm_free_large(e->user_pages); 414 e->user_pages = NULL; 415 } 416 417 if (e->robj->tbo.ttm->state != tt_bound && 418 !e->user_pages) { 419 list_del(&e->tv.head); 420 list_add(&e->tv.head, &need_pages); 421 422 amdgpu_bo_unreserve(e->robj); 423 } 424 } 425 426 if (list_empty(&need_pages)) 427 break; 428 429 /* Unreserve everything again. */ 430 ttm_eu_backoff_reservation(&p->ticket, &p->validated); 431 432 /* We tried to often, just abort */ 433 if (!--tries) { 434 r = -EDEADLK; 435 goto error_free_pages; 436 } 437 438 /* Fill the page arrays for all useptrs. */ 439 list_for_each_entry(e, &need_pages, tv.head) { 440 struct ttm_tt *ttm = e->robj->tbo.ttm; 441 442 e->user_pages = drm_calloc_large(ttm->num_pages, 443 sizeof(struct page*)); 444 if (!e->user_pages) { 445 r = -ENOMEM; 446 goto error_free_pages; 447 } 448 449 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); 450 if (r) { 451 drm_free_large(e->user_pages); 452 e->user_pages = NULL; 453 goto error_free_pages; 454 } 455 } 456 457 /* And try again. */ 458 list_splice(&need_pages, &p->validated); 459 } 460 461 amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates); 462 463 p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); 464 p->bytes_moved = 0; 465 466 r = amdgpu_cs_list_validate(p, &duplicates); 467 if (r) 468 goto error_validate; 469 470 r = amdgpu_cs_list_validate(p, &p->validated); 471 if (r) 472 goto error_validate; 473 474 if (p->bo_list) { 475 struct amdgpu_vm *vm = &fpriv->vm; 476 unsigned i; 477 478 for (i = 0; i < p->bo_list->num_entries; i++) { 479 struct amdgpu_bo *bo = p->bo_list->array[i].robj; 480 481 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); 482 } 483 } 484 485 error_validate: 486 if (r) { 487 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); 488 ttm_eu_backoff_reservation(&p->ticket, &p->validated); 489 } 490 491 error_free_pages: 492 493 if (need_mmap_lock) 494 up_read(¤t->mm->mmap_sem); 495 496 if (p->bo_list) { 497 for (i = p->bo_list->first_userptr; 498 i < p->bo_list->num_entries; ++i) { 499 e = &p->bo_list->array[i]; 500 501 if (!e->user_pages) 502 continue; 503 504 release_pages(e->user_pages, 505 e->robj->tbo.ttm->num_pages, 506 false); 507 drm_free_large(e->user_pages); 508 } 509 } 510 511 return r; 512 } 513 514 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) 515 { 516 struct amdgpu_bo_list_entry *e; 517 int r; 518 519 list_for_each_entry(e, &p->validated, tv.head) { 520 struct reservation_object *resv = e->robj->tbo.resv; 521 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); 522 523 if (r) 524 return r; 525 } 526 return 0; 527 } 528 529 static int cmp_size_smaller_first(void *priv, struct list_head *a, 530 struct list_head *b) 531 { 532 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); 533 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); 534 535 /* Sort A before B if A is smaller. */ 536 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 537 } 538 539 /** 540 * cs_parser_fini() - clean parser states 541 * @parser: parser structure holding parsing context. 542 * @error: error number 543 * 544 * If error is set than unvalidate buffer, otherwise just free memory 545 * used by parsing context. 546 **/ 547 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 548 { 549 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 550 unsigned i; 551 552 if (!error) { 553 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); 554 555 /* Sort the buffer list from the smallest to largest buffer, 556 * which affects the order of buffers in the LRU list. 557 * This assures that the smallest buffers are added first 558 * to the LRU list, so they are likely to be later evicted 559 * first, instead of large buffers whose eviction is more 560 * expensive. 561 * 562 * This slightly lowers the number of bytes moved by TTM 563 * per frame under memory pressure. 564 */ 565 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 566 567 ttm_eu_fence_buffer_objects(&parser->ticket, 568 &parser->validated, 569 parser->fence); 570 } else if (backoff) { 571 ttm_eu_backoff_reservation(&parser->ticket, 572 &parser->validated); 573 } 574 fence_put(parser->fence); 575 576 if (parser->ctx) 577 amdgpu_ctx_put(parser->ctx); 578 if (parser->bo_list) 579 amdgpu_bo_list_put(parser->bo_list); 580 581 for (i = 0; i < parser->nchunks; i++) 582 drm_free_large(parser->chunks[i].kdata); 583 kfree(parser->chunks); 584 if (parser->job) 585 amdgpu_job_free(parser->job); 586 amdgpu_bo_unref(&parser->uf_entry.robj); 587 } 588 589 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, 590 struct amdgpu_vm *vm) 591 { 592 struct amdgpu_device *adev = p->adev; 593 struct amdgpu_bo_va *bo_va; 594 struct amdgpu_bo *bo; 595 int i, r; 596 597 r = amdgpu_vm_update_page_directory(adev, vm); 598 if (r) 599 return r; 600 601 r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); 602 if (r) 603 return r; 604 605 r = amdgpu_vm_clear_freed(adev, vm); 606 if (r) 607 return r; 608 609 if (p->bo_list) { 610 for (i = 0; i < p->bo_list->num_entries; i++) { 611 struct fence *f; 612 613 /* ignore duplicates */ 614 bo = p->bo_list->array[i].robj; 615 if (!bo) 616 continue; 617 618 bo_va = p->bo_list->array[i].bo_va; 619 if (bo_va == NULL) 620 continue; 621 622 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); 623 if (r) 624 return r; 625 626 f = bo_va->last_pt_update; 627 r = amdgpu_sync_fence(adev, &p->job->sync, f); 628 if (r) 629 return r; 630 } 631 632 } 633 634 r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); 635 636 if (amdgpu_vm_debug && p->bo_list) { 637 /* Invalidate all BOs to test for userspace bugs */ 638 for (i = 0; i < p->bo_list->num_entries; i++) { 639 /* ignore duplicates */ 640 bo = p->bo_list->array[i].robj; 641 if (!bo) 642 continue; 643 644 amdgpu_vm_bo_invalidate(adev, bo); 645 } 646 } 647 648 return r; 649 } 650 651 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 652 struct amdgpu_cs_parser *p) 653 { 654 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 655 struct amdgpu_vm *vm = &fpriv->vm; 656 struct amdgpu_ring *ring = p->job->ring; 657 int i, r; 658 659 /* Only for UVD/VCE VM emulation */ 660 if (ring->funcs->parse_cs) { 661 for (i = 0; i < p->job->num_ibs; i++) { 662 r = amdgpu_ring_parse_cs(ring, p, i); 663 if (r) 664 return r; 665 } 666 } 667 668 r = amdgpu_bo_vm_update_pte(p, vm); 669 if (!r) 670 amdgpu_cs_sync_rings(p); 671 672 return r; 673 } 674 675 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) 676 { 677 if (r == -EDEADLK) { 678 r = amdgpu_gpu_reset(adev); 679 if (!r) 680 r = -EAGAIN; 681 } 682 return r; 683 } 684 685 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 686 struct amdgpu_cs_parser *parser) 687 { 688 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 689 struct amdgpu_vm *vm = &fpriv->vm; 690 int i, j; 691 int r; 692 693 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { 694 struct amdgpu_cs_chunk *chunk; 695 struct amdgpu_ib *ib; 696 struct drm_amdgpu_cs_chunk_ib *chunk_ib; 697 struct amdgpu_ring *ring; 698 699 chunk = &parser->chunks[i]; 700 ib = &parser->job->ibs[j]; 701 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; 702 703 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) 704 continue; 705 706 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, 707 chunk_ib->ip_instance, chunk_ib->ring, 708 &ring); 709 if (r) 710 return r; 711 712 if (parser->job->ring && parser->job->ring != ring) 713 return -EINVAL; 714 715 parser->job->ring = ring; 716 717 if (ring->funcs->parse_cs) { 718 struct amdgpu_bo_va_mapping *m; 719 struct amdgpu_bo *aobj = NULL; 720 uint64_t offset; 721 uint8_t *kptr; 722 723 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, 724 &aobj); 725 if (!aobj) { 726 DRM_ERROR("IB va_start is invalid\n"); 727 return -EINVAL; 728 } 729 730 if ((chunk_ib->va_start + chunk_ib->ib_bytes) > 731 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { 732 DRM_ERROR("IB va_start+ib_bytes is invalid\n"); 733 return -EINVAL; 734 } 735 736 /* the IB should be reserved at this point */ 737 r = amdgpu_bo_kmap(aobj, (void **)&kptr); 738 if (r) { 739 return r; 740 } 741 742 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; 743 kptr += chunk_ib->va_start - offset; 744 745 r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib); 746 if (r) { 747 DRM_ERROR("Failed to get ib !\n"); 748 return r; 749 } 750 751 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); 752 amdgpu_bo_kunmap(aobj); 753 } else { 754 r = amdgpu_ib_get(adev, vm, 0, ib); 755 if (r) { 756 DRM_ERROR("Failed to get ib !\n"); 757 return r; 758 } 759 760 ib->gpu_addr = chunk_ib->va_start; 761 } 762 763 ib->length_dw = chunk_ib->ib_bytes / 4; 764 ib->flags = chunk_ib->flags; 765 ib->ctx = parser->ctx; 766 j++; 767 } 768 769 /* add GDS resources to first IB */ 770 if (parser->bo_list) { 771 struct amdgpu_bo *gds = parser->bo_list->gds_obj; 772 struct amdgpu_bo *gws = parser->bo_list->gws_obj; 773 struct amdgpu_bo *oa = parser->bo_list->oa_obj; 774 struct amdgpu_ib *ib = &parser->job->ibs[0]; 775 776 if (gds) { 777 ib->gds_base = amdgpu_bo_gpu_offset(gds); 778 ib->gds_size = amdgpu_bo_size(gds); 779 } 780 if (gws) { 781 ib->gws_base = amdgpu_bo_gpu_offset(gws); 782 ib->gws_size = amdgpu_bo_size(gws); 783 } 784 if (oa) { 785 ib->oa_base = amdgpu_bo_gpu_offset(oa); 786 ib->oa_size = amdgpu_bo_size(oa); 787 } 788 } 789 /* wrap the last IB with user fence */ 790 if (parser->job->uf.bo) { 791 struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1]; 792 793 /* UVD & VCE fw doesn't support user fences */ 794 if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD || 795 parser->job->ring->type == AMDGPU_RING_TYPE_VCE) 796 return -EINVAL; 797 798 ib->user = &parser->job->uf; 799 } 800 801 return 0; 802 } 803 804 static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 805 struct amdgpu_cs_parser *p) 806 { 807 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 808 int i, j, r; 809 810 for (i = 0; i < p->nchunks; ++i) { 811 struct drm_amdgpu_cs_chunk_dep *deps; 812 struct amdgpu_cs_chunk *chunk; 813 unsigned num_deps; 814 815 chunk = &p->chunks[i]; 816 817 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) 818 continue; 819 820 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; 821 num_deps = chunk->length_dw * 4 / 822 sizeof(struct drm_amdgpu_cs_chunk_dep); 823 824 for (j = 0; j < num_deps; ++j) { 825 struct amdgpu_ring *ring; 826 struct amdgpu_ctx *ctx; 827 struct fence *fence; 828 829 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 830 deps[j].ip_instance, 831 deps[j].ring, &ring); 832 if (r) 833 return r; 834 835 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); 836 if (ctx == NULL) 837 return -EINVAL; 838 839 fence = amdgpu_ctx_get_fence(ctx, ring, 840 deps[j].handle); 841 if (IS_ERR(fence)) { 842 r = PTR_ERR(fence); 843 amdgpu_ctx_put(ctx); 844 return r; 845 846 } else if (fence) { 847 r = amdgpu_sync_fence(adev, &p->job->sync, 848 fence); 849 fence_put(fence); 850 amdgpu_ctx_put(ctx); 851 if (r) 852 return r; 853 } 854 } 855 } 856 857 return 0; 858 } 859 860 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 861 union drm_amdgpu_cs *cs) 862 { 863 struct amdgpu_ring *ring = p->job->ring; 864 struct amd_sched_fence *fence; 865 struct amdgpu_job *job; 866 867 job = p->job; 868 p->job = NULL; 869 870 job->base.sched = &ring->sched; 871 job->base.s_entity = &p->ctx->rings[ring->idx].entity; 872 job->owner = p->filp; 873 874 fence = amd_sched_fence_create(job->base.s_entity, p->filp); 875 if (!fence) { 876 amdgpu_job_free(job); 877 return -ENOMEM; 878 } 879 880 job->base.s_fence = fence; 881 p->fence = fence_get(&fence->base); 882 883 cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, 884 &fence->base); 885 job->ibs[job->num_ibs - 1].sequence = cs->out.handle; 886 887 trace_amdgpu_cs_ioctl(job); 888 amd_sched_entity_push_job(&job->base); 889 890 return 0; 891 } 892 893 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 894 { 895 struct amdgpu_device *adev = dev->dev_private; 896 union drm_amdgpu_cs *cs = data; 897 struct amdgpu_cs_parser parser = {}; 898 bool reserved_buffers = false; 899 int i, r; 900 901 if (!adev->accel_working) 902 return -EBUSY; 903 904 parser.adev = adev; 905 parser.filp = filp; 906 907 r = amdgpu_cs_parser_init(&parser, data); 908 if (r) { 909 DRM_ERROR("Failed to initialize parser !\n"); 910 amdgpu_cs_parser_fini(&parser, r, false); 911 r = amdgpu_cs_handle_lockup(adev, r); 912 return r; 913 } 914 r = amdgpu_cs_parser_bos(&parser, data); 915 if (r == -ENOMEM) 916 DRM_ERROR("Not enough memory for command submission!\n"); 917 else if (r && r != -ERESTARTSYS) 918 DRM_ERROR("Failed to process the buffer list %d!\n", r); 919 else if (!r) { 920 reserved_buffers = true; 921 r = amdgpu_cs_ib_fill(adev, &parser); 922 } 923 924 if (!r) { 925 r = amdgpu_cs_dependencies(adev, &parser); 926 if (r) 927 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 928 } 929 930 if (r) 931 goto out; 932 933 for (i = 0; i < parser.job->num_ibs; i++) 934 trace_amdgpu_cs(&parser, i); 935 936 r = amdgpu_cs_ib_vm_chunk(adev, &parser); 937 if (r) 938 goto out; 939 940 r = amdgpu_cs_submit(&parser, cs); 941 942 out: 943 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 944 r = amdgpu_cs_handle_lockup(adev, r); 945 return r; 946 } 947 948 /** 949 * amdgpu_cs_wait_ioctl - wait for a command submission to finish 950 * 951 * @dev: drm device 952 * @data: data from userspace 953 * @filp: file private 954 * 955 * Wait for the command submission identified by handle to finish. 956 */ 957 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, 958 struct drm_file *filp) 959 { 960 union drm_amdgpu_wait_cs *wait = data; 961 struct amdgpu_device *adev = dev->dev_private; 962 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); 963 struct amdgpu_ring *ring = NULL; 964 struct amdgpu_ctx *ctx; 965 struct fence *fence; 966 long r; 967 968 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 969 wait->in.ring, &ring); 970 if (r) 971 return r; 972 973 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); 974 if (ctx == NULL) 975 return -EINVAL; 976 977 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); 978 if (IS_ERR(fence)) 979 r = PTR_ERR(fence); 980 else if (fence) { 981 r = fence_wait_timeout(fence, true, timeout); 982 fence_put(fence); 983 } else 984 r = 1; 985 986 amdgpu_ctx_put(ctx); 987 if (r < 0) 988 return r; 989 990 memset(wait, 0, sizeof(*wait)); 991 wait->out.status = (r == 0); 992 993 return 0; 994 } 995 996 /** 997 * amdgpu_cs_find_bo_va - find bo_va for VM address 998 * 999 * @parser: command submission parser context 1000 * @addr: VM address 1001 * @bo: resulting BO of the mapping found 1002 * 1003 * Search the buffer objects in the command submission context for a certain 1004 * virtual memory address. Returns allocation structure when found, NULL 1005 * otherwise. 1006 */ 1007 struct amdgpu_bo_va_mapping * 1008 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1009 uint64_t addr, struct amdgpu_bo **bo) 1010 { 1011 struct amdgpu_bo_va_mapping *mapping; 1012 unsigned i; 1013 1014 if (!parser->bo_list) 1015 return NULL; 1016 1017 addr /= AMDGPU_GPU_PAGE_SIZE; 1018 1019 for (i = 0; i < parser->bo_list->num_entries; i++) { 1020 struct amdgpu_bo_list_entry *lobj; 1021 1022 lobj = &parser->bo_list->array[i]; 1023 if (!lobj->bo_va) 1024 continue; 1025 1026 list_for_each_entry(mapping, &lobj->bo_va->valids, list) { 1027 if (mapping->it.start > addr || 1028 addr > mapping->it.last) 1029 continue; 1030 1031 *bo = lobj->bo_va->bo; 1032 return mapping; 1033 } 1034 1035 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { 1036 if (mapping->it.start > addr || 1037 addr > mapping->it.last) 1038 continue; 1039 1040 *bo = lobj->bo_va->bo; 1041 return mapping; 1042 } 1043 } 1044 1045 return NULL; 1046 } 1047