1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __AMDGPU_CPER_H__ 26 #define __AMDGPU_CPER_H__ 27 28 #include "amd_cper.h" 29 #include "amdgpu_aca.h" 30 31 #define CPER_MAX_ALLOWED_COUNT 0x1000 32 #define HDR_LEN (sizeof(struct cper_hdr)) 33 #define SEC_DESC_LEN (sizeof(struct cper_sec_desc)) 34 35 #define BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot)) 36 #define FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal)) 37 #define NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err)) 38 39 #define SEC_DESC_OFFSET(idx) (HDR_LEN + (SEC_DESC_LEN * idx)) 40 41 #define BOOT_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx)) 42 #define FATAL_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx)) 43 #define NONSTD_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx)) 44 45 enum amdgpu_cper_type { 46 AMDGPU_CPER_TYPE_RUNTIME, 47 AMDGPU_CPER_TYPE_FATAL, 48 AMDGPU_CPER_TYPE_BOOT, 49 AMDGPU_CPER_TYPE_BP_THRESHOLD, 50 }; 51 52 struct amdgpu_cper { 53 bool enabled; 54 55 atomic_t unique_id; 56 struct mutex cper_lock; 57 58 /* Lifetime CPERs generated */ 59 uint32_t count; 60 uint32_t max_count; 61 62 uint32_t wptr; 63 64 void *ring[CPER_MAX_ALLOWED_COUNT]; 65 }; 66 67 void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev, 68 struct cper_hdr *hdr, 69 enum amdgpu_cper_type type, 70 enum cper_error_severity sev); 71 int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev, 72 struct cper_hdr *hdr, 73 uint32_t idx, 74 struct cper_sec_crashdump_reg_data reg_data); 75 int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev, 76 struct cper_hdr *hdr, 77 uint32_t idx, 78 enum cper_error_severity sev, 79 uint32_t *reg_dump, 80 uint32_t reg_count); 81 int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev, 82 struct cper_hdr *hdr, 83 uint32_t section_idx); 84 85 struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev, 86 enum amdgpu_cper_type type, 87 uint16_t section_count); 88 /* UE must be encoded into separated cper entries, 1 UE 1 cper */ 89 int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev, 90 struct aca_bank *bank); 91 /* CEs and DEs are combined into 1 cper entry */ 92 int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev, 93 struct aca_banks *banks, 94 uint16_t bank_count); 95 int amdgpu_cper_init(struct amdgpu_device *adev); 96 int amdgpu_cper_fini(struct amdgpu_device *adev); 97 98 #endif 99