1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/amdgpu_drm.h> 25 #include "amdgpu.h" 26 #include "atomfirmware.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "atom.h" 29 #include "atombios.h" 30 #include "soc15_hw_ip.h" 31 32 union firmware_info { 33 struct atom_firmware_info_v3_1 v31; 34 struct atom_firmware_info_v3_2 v32; 35 struct atom_firmware_info_v3_3 v33; 36 struct atom_firmware_info_v3_4 v34; 37 struct atom_firmware_info_v3_5 v35; 38 }; 39 40 /* 41 * Helper function to query firmware capability 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Return firmware_capability in firmwareinfo table on success or 0 if not 46 */ 47 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev) 48 { 49 struct amdgpu_mode_info *mode_info = &adev->mode_info; 50 int index; 51 u16 data_offset, size; 52 union firmware_info *firmware_info; 53 u8 frev, crev; 54 u32 fw_cap = 0; 55 56 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 57 firmwareinfo); 58 59 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 60 index, &size, &frev, &crev, &data_offset)) { 61 /* support firmware_info 3.1 + */ 62 if ((frev == 3 && crev >= 1) || (frev > 3)) { 63 firmware_info = (union firmware_info *) 64 (mode_info->atom_context->bios + data_offset); 65 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); 66 } 67 } 68 69 return fw_cap; 70 } 71 72 /* 73 * Helper function to query gpu virtualizaiton capability 74 * 75 * @adev: amdgpu_device pointer 76 * 77 * Return true if gpu virtualization is supported or false if not 78 */ 79 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev) 80 { 81 u32 fw_cap; 82 83 fw_cap = adev->mode_info.firmware_flags; 84 85 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false; 86 } 87 88 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) 89 { 90 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 91 firmwareinfo); 92 uint16_t data_offset; 93 94 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 95 NULL, NULL, &data_offset)) { 96 struct atom_firmware_info_v3_1 *firmware_info = 97 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 98 data_offset); 99 100 adev->bios_scratch_reg_offset = 101 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); 102 } 103 } 104 105 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev, 106 struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes) 107 { 108 u32 start_addr, fw_size, drv_size; 109 110 start_addr = le32_to_cpu(fw_usage->start_address_in_kb); 111 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); 112 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb); 113 114 DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n", 115 start_addr, 116 fw_size, 117 drv_size); 118 119 if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 120 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 121 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 122 /* Firmware request VRAM reservation for SR-IOV */ 123 adev->mman.fw_vram_usage_start_offset = (start_addr & 124 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 125 adev->mman.fw_vram_usage_size = fw_size << 10; 126 /* Use the default scratch size */ 127 *usage_bytes = 0; 128 } else { 129 *usage_bytes = drv_size << 10; 130 } 131 return 0; 132 } 133 134 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev, 135 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes) 136 { 137 u32 fw_start_addr, fw_size, drv_start_addr, drv_size; 138 139 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb); 140 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); 141 142 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb); 143 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb); 144 145 DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n", 146 fw_start_addr, 147 fw_size, 148 drv_start_addr, 149 drv_size); 150 151 if (amdgpu_sriov_vf(adev) && 152 ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 153 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { 154 /* Firmware request VRAM reservation for SR-IOV */ 155 adev->mman.fw_vram_usage_start_offset = (fw_start_addr & 156 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 157 adev->mman.fw_vram_usage_size = fw_size << 10; 158 } 159 160 if (amdgpu_sriov_vf(adev) && 161 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 162 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { 163 /* driver request VRAM reservation for SR-IOV */ 164 adev->mman.drv_vram_usage_start_offset = (drv_start_addr & 165 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 166 adev->mman.drv_vram_usage_size = drv_size << 10; 167 } 168 169 *usage_bytes = 0; 170 return 0; 171 } 172 173 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) 174 { 175 struct atom_context *ctx = adev->mode_info.atom_context; 176 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 177 vram_usagebyfirmware); 178 struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1; 179 struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2; 180 u16 data_offset; 181 u8 frev, crev; 182 int usage_bytes = 0; 183 184 if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { 185 if (frev == 2 && crev == 1) { 186 fw_usage_v2_1 = 187 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); 188 amdgpu_atomfirmware_allocate_fb_v2_1(adev, 189 fw_usage_v2_1, 190 &usage_bytes); 191 } else if (frev >= 2 && crev >= 2) { 192 fw_usage_v2_2 = 193 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); 194 amdgpu_atomfirmware_allocate_fb_v2_2(adev, 195 fw_usage_v2_2, 196 &usage_bytes); 197 } 198 } 199 200 ctx->scratch_size_bytes = 0; 201 if (usage_bytes == 0) 202 usage_bytes = 20 * 1024; 203 /* allocate some scratch memory */ 204 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 205 if (!ctx->scratch) 206 return -ENOMEM; 207 ctx->scratch_size_bytes = usage_bytes; 208 return 0; 209 } 210 211 union igp_info { 212 struct atom_integrated_system_info_v1_11 v11; 213 struct atom_integrated_system_info_v1_12 v12; 214 struct atom_integrated_system_info_v2_1 v21; 215 }; 216 217 union umc_info { 218 struct atom_umc_info_v3_1 v31; 219 struct atom_umc_info_v3_2 v32; 220 struct atom_umc_info_v3_3 v33; 221 struct atom_umc_info_v4_0 v40; 222 }; 223 224 union vram_info { 225 struct atom_vram_info_header_v2_3 v23; 226 struct atom_vram_info_header_v2_4 v24; 227 struct atom_vram_info_header_v2_5 v25; 228 struct atom_vram_info_header_v2_6 v26; 229 struct atom_vram_info_header_v3_0 v30; 230 }; 231 232 union vram_module { 233 struct atom_vram_module_v9 v9; 234 struct atom_vram_module_v10 v10; 235 struct atom_vram_module_v11 v11; 236 struct atom_vram_module_v3_0 v30; 237 }; 238 239 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, 240 int atom_mem_type) 241 { 242 int vram_type; 243 244 if (adev->flags & AMD_IS_APU) { 245 switch (atom_mem_type) { 246 case Ddr2MemType: 247 case LpDdr2MemType: 248 vram_type = AMDGPU_VRAM_TYPE_DDR2; 249 break; 250 case Ddr3MemType: 251 case LpDdr3MemType: 252 vram_type = AMDGPU_VRAM_TYPE_DDR3; 253 break; 254 case Ddr4MemType: 255 vram_type = AMDGPU_VRAM_TYPE_DDR4; 256 break; 257 case LpDdr4MemType: 258 vram_type = AMDGPU_VRAM_TYPE_LPDDR4; 259 break; 260 case Ddr5MemType: 261 vram_type = AMDGPU_VRAM_TYPE_DDR5; 262 break; 263 case LpDdr5MemType: 264 vram_type = AMDGPU_VRAM_TYPE_LPDDR5; 265 break; 266 default: 267 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 268 break; 269 } 270 } else { 271 switch (atom_mem_type) { 272 case ATOM_DGPU_VRAM_TYPE_GDDR5: 273 vram_type = AMDGPU_VRAM_TYPE_GDDR5; 274 break; 275 case ATOM_DGPU_VRAM_TYPE_HBM2: 276 case ATOM_DGPU_VRAM_TYPE_HBM2E: 277 case ATOM_DGPU_VRAM_TYPE_HBM3: 278 vram_type = AMDGPU_VRAM_TYPE_HBM; 279 break; 280 case ATOM_DGPU_VRAM_TYPE_GDDR6: 281 vram_type = AMDGPU_VRAM_TYPE_GDDR6; 282 break; 283 default: 284 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 285 break; 286 } 287 } 288 289 return vram_type; 290 } 291 292 int 293 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 294 int *vram_width, int *vram_type, 295 int *vram_vendor) 296 { 297 struct amdgpu_mode_info *mode_info = &adev->mode_info; 298 int index, i = 0; 299 u16 data_offset, size; 300 union igp_info *igp_info; 301 union vram_info *vram_info; 302 union umc_info *umc_info; 303 union vram_module *vram_module; 304 u8 frev, crev; 305 u8 mem_type; 306 u8 mem_vendor; 307 u32 mem_channel_number; 308 u32 mem_channel_width; 309 u32 module_id; 310 311 if (adev->flags & AMD_IS_APU) 312 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 313 integratedsysteminfo); 314 else { 315 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 316 case IP_VERSION(12, 0, 0): 317 case IP_VERSION(12, 0, 1): 318 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); 319 break; 320 default: 321 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info); 322 } 323 } 324 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 325 index, &size, 326 &frev, &crev, &data_offset)) { 327 if (adev->flags & AMD_IS_APU) { 328 igp_info = (union igp_info *) 329 (mode_info->atom_context->bios + data_offset); 330 switch (frev) { 331 case 1: 332 switch (crev) { 333 case 11: 334 case 12: 335 mem_channel_number = igp_info->v11.umachannelnumber; 336 if (!mem_channel_number) 337 mem_channel_number = 1; 338 mem_type = igp_info->v11.memorytype; 339 if (mem_type == LpDdr5MemType) 340 mem_channel_width = 32; 341 else 342 mem_channel_width = 64; 343 if (vram_width) 344 *vram_width = mem_channel_number * mem_channel_width; 345 if (vram_type) 346 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 347 break; 348 default: 349 return -EINVAL; 350 } 351 break; 352 case 2: 353 switch (crev) { 354 case 1: 355 case 2: 356 mem_channel_number = igp_info->v21.umachannelnumber; 357 if (!mem_channel_number) 358 mem_channel_number = 1; 359 mem_type = igp_info->v21.memorytype; 360 if (mem_type == LpDdr5MemType) 361 mem_channel_width = 32; 362 else 363 mem_channel_width = 64; 364 if (vram_width) 365 *vram_width = mem_channel_number * mem_channel_width; 366 if (vram_type) 367 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 368 break; 369 default: 370 return -EINVAL; 371 } 372 break; 373 default: 374 return -EINVAL; 375 } 376 } else { 377 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 378 case IP_VERSION(12, 0, 0): 379 case IP_VERSION(12, 0, 1): 380 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); 381 382 if (frev == 4) { 383 switch (crev) { 384 case 0: 385 mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); 386 mem_type = le32_to_cpu(umc_info->v40.vram_type); 387 mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); 388 mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; 389 if (vram_vendor) 390 *vram_vendor = mem_vendor; 391 if (vram_type) 392 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 393 if (vram_width) 394 *vram_width = mem_channel_number * (1 << mem_channel_width); 395 break; 396 default: 397 return -EINVAL; 398 } 399 } else 400 return -EINVAL; 401 break; 402 default: 403 vram_info = (union vram_info *) 404 (mode_info->atom_context->bios + data_offset); 405 406 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; 407 if (frev == 3) { 408 switch (crev) { 409 /* v30 */ 410 case 0: 411 vram_module = (union vram_module *)vram_info->v30.vram_module; 412 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; 413 if (vram_vendor) 414 *vram_vendor = mem_vendor; 415 mem_type = vram_info->v30.memory_type; 416 if (vram_type) 417 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 418 mem_channel_number = vram_info->v30.channel_num; 419 mem_channel_width = vram_info->v30.channel_width; 420 if (vram_width) 421 *vram_width = mem_channel_number * (1 << mem_channel_width); 422 break; 423 default: 424 return -EINVAL; 425 } 426 } else if (frev == 2) { 427 switch (crev) { 428 /* v23 */ 429 case 3: 430 if (module_id > vram_info->v23.vram_module_num) 431 module_id = 0; 432 vram_module = (union vram_module *)vram_info->v23.vram_module; 433 while (i < module_id) { 434 vram_module = (union vram_module *) 435 ((u8 *)vram_module + vram_module->v9.vram_module_size); 436 i++; 437 } 438 mem_type = vram_module->v9.memory_type; 439 if (vram_type) 440 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 441 mem_channel_number = vram_module->v9.channel_num; 442 mem_channel_width = vram_module->v9.channel_width; 443 if (vram_width) 444 *vram_width = mem_channel_number * (1 << mem_channel_width); 445 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 446 if (vram_vendor) 447 *vram_vendor = mem_vendor; 448 break; 449 /* v24 */ 450 case 4: 451 if (module_id > vram_info->v24.vram_module_num) 452 module_id = 0; 453 vram_module = (union vram_module *)vram_info->v24.vram_module; 454 while (i < module_id) { 455 vram_module = (union vram_module *) 456 ((u8 *)vram_module + vram_module->v10.vram_module_size); 457 i++; 458 } 459 mem_type = vram_module->v10.memory_type; 460 if (vram_type) 461 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 462 mem_channel_number = vram_module->v10.channel_num; 463 mem_channel_width = vram_module->v10.channel_width; 464 if (vram_width) 465 *vram_width = mem_channel_number * (1 << mem_channel_width); 466 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; 467 if (vram_vendor) 468 *vram_vendor = mem_vendor; 469 break; 470 /* v25 */ 471 case 5: 472 if (module_id > vram_info->v25.vram_module_num) 473 module_id = 0; 474 vram_module = (union vram_module *)vram_info->v25.vram_module; 475 while (i < module_id) { 476 vram_module = (union vram_module *) 477 ((u8 *)vram_module + vram_module->v11.vram_module_size); 478 i++; 479 } 480 mem_type = vram_module->v11.memory_type; 481 if (vram_type) 482 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 483 mem_channel_number = vram_module->v11.channel_num; 484 mem_channel_width = vram_module->v11.channel_width; 485 if (vram_width) 486 *vram_width = mem_channel_number * (1 << mem_channel_width); 487 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; 488 if (vram_vendor) 489 *vram_vendor = mem_vendor; 490 break; 491 /* v26 */ 492 case 6: 493 if (module_id > vram_info->v26.vram_module_num) 494 module_id = 0; 495 vram_module = (union vram_module *)vram_info->v26.vram_module; 496 while (i < module_id) { 497 vram_module = (union vram_module *) 498 ((u8 *)vram_module + vram_module->v9.vram_module_size); 499 i++; 500 } 501 mem_type = vram_module->v9.memory_type; 502 if (vram_type) 503 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 504 mem_channel_number = vram_module->v9.channel_num; 505 mem_channel_width = vram_module->v9.channel_width; 506 if (vram_width) 507 *vram_width = mem_channel_number * (1 << mem_channel_width); 508 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 509 if (vram_vendor) 510 *vram_vendor = mem_vendor; 511 break; 512 default: 513 return -EINVAL; 514 } 515 } else { 516 /* invalid frev */ 517 return -EINVAL; 518 } 519 } 520 } 521 } 522 523 return 0; 524 } 525 526 /* 527 * Return true if vbios enabled ecc by default, if umc info table is available 528 * or false if ecc is not enabled or umc info table is not available 529 */ 530 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 531 { 532 struct amdgpu_mode_info *mode_info = &adev->mode_info; 533 int index; 534 u16 data_offset, size; 535 union umc_info *umc_info; 536 u8 frev, crev; 537 bool ecc_default_enabled = false; 538 u8 umc_config; 539 u32 umc_config1; 540 541 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 542 umc_info); 543 544 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 545 index, &size, &frev, &crev, &data_offset)) { 546 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); 547 if (frev == 3) { 548 switch (crev) { 549 case 1: 550 umc_config = le32_to_cpu(umc_info->v31.umc_config); 551 ecc_default_enabled = 552 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 553 break; 554 case 2: 555 umc_config = le32_to_cpu(umc_info->v32.umc_config); 556 ecc_default_enabled = 557 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 558 break; 559 case 3: 560 umc_config = le32_to_cpu(umc_info->v33.umc_config); 561 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1); 562 ecc_default_enabled = 563 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) || 564 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false; 565 break; 566 default: 567 /* unsupported crev */ 568 return false; 569 } 570 } else if (frev == 4) { 571 switch (crev) { 572 case 0: 573 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1); 574 ecc_default_enabled = 575 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false; 576 break; 577 default: 578 /* unsupported crev */ 579 return false; 580 } 581 } else { 582 /* unsupported frev */ 583 return false; 584 } 585 } 586 587 return ecc_default_enabled; 588 } 589 590 /* 591 * Helper function to query sram ecc capablity 592 * 593 * @adev: amdgpu_device pointer 594 * 595 * Return true if vbios supports sram ecc or false if not 596 */ 597 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev) 598 { 599 u32 fw_cap; 600 601 fw_cap = adev->mode_info.firmware_flags; 602 603 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; 604 } 605 606 /* 607 * Helper function to query dynamic boot config capability 608 * 609 * @adev: amdgpu_device pointer 610 * 611 * Return true if vbios supports dynamic boot config or false if not 612 */ 613 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev) 614 { 615 u32 fw_cap; 616 617 fw_cap = adev->mode_info.firmware_flags; 618 619 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false; 620 } 621 622 /** 623 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS 624 * @adev: amdgpu_device pointer 625 * @i2c_address: pointer to u8; if not NULL, will contain 626 * the RAS EEPROM address if the function returns true 627 * 628 * Return true if VBIOS supports RAS EEPROM address reporting, 629 * else return false. If true and @i2c_address is not NULL, 630 * will contain the RAS ROM address. 631 */ 632 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, 633 u8 *i2c_address) 634 { 635 struct amdgpu_mode_info *mode_info = &adev->mode_info; 636 int index; 637 u16 data_offset, size; 638 union firmware_info *firmware_info; 639 u8 frev, crev; 640 641 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 642 firmwareinfo); 643 644 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 645 index, &size, &frev, &crev, 646 &data_offset)) { 647 /* support firmware_info 3.4 + */ 648 if ((frev == 3 && crev >= 4) || (frev > 3)) { 649 firmware_info = (union firmware_info *) 650 (mode_info->atom_context->bios + data_offset); 651 /* The ras_rom_i2c_slave_addr should ideally 652 * be a 19-bit EEPROM address, which would be 653 * used as is by the driver; see top of 654 * amdgpu_eeprom.c. 655 * 656 * When this is the case, 0 is of course a 657 * valid RAS EEPROM address, in which case, 658 * we'll drop the first "if (firm...)" and only 659 * leave the check for the pointer. 660 * 661 * The reason this works right now is because 662 * ras_rom_i2c_slave_addr contains the EEPROM 663 * device type qualifier 1010b in the top 4 664 * bits. 665 */ 666 if (firmware_info->v34.ras_rom_i2c_slave_addr) { 667 if (i2c_address) 668 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr; 669 return true; 670 } 671 } 672 } 673 674 return false; 675 } 676 677 678 union smu_info { 679 struct atom_smu_info_v3_1 v31; 680 struct atom_smu_info_v4_0 v40; 681 }; 682 683 union gfx_info { 684 struct atom_gfx_info_v2_2 v22; 685 struct atom_gfx_info_v2_4 v24; 686 struct atom_gfx_info_v2_7 v27; 687 struct atom_gfx_info_v3_0 v30; 688 }; 689 690 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) 691 { 692 struct amdgpu_mode_info *mode_info = &adev->mode_info; 693 struct amdgpu_pll *spll = &adev->clock.spll; 694 struct amdgpu_pll *mpll = &adev->clock.mpll; 695 uint8_t frev, crev; 696 uint16_t data_offset; 697 int ret = -EINVAL, index; 698 699 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 700 firmwareinfo); 701 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 702 &frev, &crev, &data_offset)) { 703 union firmware_info *firmware_info = 704 (union firmware_info *)(mode_info->atom_context->bios + 705 data_offset); 706 707 adev->clock.default_sclk = 708 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 709 adev->clock.default_mclk = 710 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 711 712 adev->pm.current_sclk = adev->clock.default_sclk; 713 adev->pm.current_mclk = adev->clock.default_mclk; 714 715 ret = 0; 716 } 717 718 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 719 smu_info); 720 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 721 &frev, &crev, &data_offset)) { 722 union smu_info *smu_info = 723 (union smu_info *)(mode_info->atom_context->bios + 724 data_offset); 725 726 /* system clock */ 727 if (frev == 3) 728 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); 729 else if (frev == 4) 730 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz); 731 732 spll->reference_div = 0; 733 spll->min_post_div = 1; 734 spll->max_post_div = 1; 735 spll->min_ref_div = 2; 736 spll->max_ref_div = 0xff; 737 spll->min_feedback_div = 4; 738 spll->max_feedback_div = 0xff; 739 spll->best_vco = 0; 740 741 ret = 0; 742 } 743 744 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 745 umc_info); 746 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 747 &frev, &crev, &data_offset)) { 748 union umc_info *umc_info = 749 (union umc_info *)(mode_info->atom_context->bios + 750 data_offset); 751 752 /* memory clock */ 753 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); 754 755 mpll->reference_div = 0; 756 mpll->min_post_div = 1; 757 mpll->max_post_div = 1; 758 mpll->min_ref_div = 2; 759 mpll->max_ref_div = 0xff; 760 mpll->min_feedback_div = 4; 761 mpll->max_feedback_div = 0xff; 762 mpll->best_vco = 0; 763 764 ret = 0; 765 } 766 767 /* if asic is Navi+, the rlc reference clock is used for system clock 768 * from vbios gfx_info table */ 769 if (adev->asic_type >= CHIP_NAVI10) { 770 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 771 gfx_info); 772 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 773 &frev, &crev, &data_offset)) { 774 union gfx_info *gfx_info = (union gfx_info *) 775 (mode_info->atom_context->bios + data_offset); 776 if ((frev == 3) || 777 (frev == 2 && crev == 6)) { 778 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk); 779 ret = 0; 780 } else if ((frev == 2) && 781 (crev >= 2) && 782 (crev != 6)) { 783 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk); 784 ret = 0; 785 } else { 786 BUG(); 787 } 788 } 789 } 790 791 return ret; 792 } 793 794 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 795 { 796 struct amdgpu_mode_info *mode_info = &adev->mode_info; 797 int index; 798 uint8_t frev, crev; 799 uint16_t data_offset; 800 801 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 802 gfx_info); 803 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 804 &frev, &crev, &data_offset)) { 805 union gfx_info *gfx_info = (union gfx_info *) 806 (mode_info->atom_context->bios + data_offset); 807 if (frev == 2) { 808 switch (crev) { 809 case 4: 810 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; 811 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; 812 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; 813 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; 814 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; 815 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); 816 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; 817 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; 818 adev->gfx.config.gs_prim_buffer_depth = 819 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth); 820 adev->gfx.config.double_offchip_lds_buf = 821 gfx_info->v24.gc_double_offchip_lds_buffer; 822 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size); 823 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd); 824 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; 825 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); 826 return 0; 827 case 7: 828 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines; 829 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; 830 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; 831 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; 832 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches; 833 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); 834 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds; 835 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth; 836 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth); 837 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer; 838 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size); 839 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd); 840 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu; 841 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size); 842 return 0; 843 default: 844 return -EINVAL; 845 } 846 } else if (frev == 3) { 847 switch (crev) { 848 case 0: 849 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines; 850 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh; 851 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; 852 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se; 853 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches; 854 return 0; 855 default: 856 return -EINVAL; 857 } 858 } else { 859 return -EINVAL; 860 } 861 862 } 863 return -EINVAL; 864 } 865 866 /* 867 * Helper function to query two stage mem training capability 868 * 869 * @adev: amdgpu_device pointer 870 * 871 * Return true if two stage mem training is supported or false if not 872 */ 873 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev) 874 { 875 u32 fw_cap; 876 877 fw_cap = adev->mode_info.firmware_flags; 878 879 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false; 880 } 881 882 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) 883 { 884 struct atom_context *ctx = adev->mode_info.atom_context; 885 union firmware_info *firmware_info; 886 int index; 887 u16 data_offset, size; 888 u8 frev, crev; 889 int fw_reserved_fb_size; 890 891 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 892 firmwareinfo); 893 894 if (!amdgpu_atom_parse_data_header(ctx, index, &size, 895 &frev, &crev, &data_offset)) 896 /* fail to parse data_header */ 897 return 0; 898 899 firmware_info = (union firmware_info *)(ctx->bios + data_offset); 900 901 if (frev != 3) 902 return -EINVAL; 903 904 switch (crev) { 905 case 4: 906 fw_reserved_fb_size = 907 (firmware_info->v34.fw_reserved_size_in_kb << 10); 908 break; 909 case 5: 910 fw_reserved_fb_size = 911 (firmware_info->v35.fw_reserved_size_in_kb << 10); 912 break; 913 default: 914 fw_reserved_fb_size = 0; 915 break; 916 } 917 918 return fw_reserved_fb_size; 919 } 920 921 /* 922 * Helper function to execute asic_init table 923 * 924 * @adev: amdgpu_device pointer 925 * @fb_reset: flag to indicate whether fb is reset or not 926 * 927 * Return 0 if succeed, otherwise failed 928 */ 929 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset) 930 { 931 struct amdgpu_mode_info *mode_info = &adev->mode_info; 932 struct atom_context *ctx; 933 uint8_t frev, crev; 934 uint16_t data_offset; 935 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz; 936 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1; 937 int index; 938 939 if (!mode_info) 940 return -EINVAL; 941 942 ctx = mode_info->atom_context; 943 if (!ctx) 944 return -EINVAL; 945 946 /* query bootup sclk/mclk from firmware_info table */ 947 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 948 firmwareinfo); 949 if (amdgpu_atom_parse_data_header(ctx, index, NULL, 950 &frev, &crev, &data_offset)) { 951 union firmware_info *firmware_info = 952 (union firmware_info *)(ctx->bios + 953 data_offset); 954 955 bootup_sclk_in10khz = 956 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 957 bootup_mclk_in10khz = 958 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 959 } else { 960 return -EINVAL; 961 } 962 963 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 964 asic_init); 965 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) { 966 if (frev == 2 && crev >= 1) { 967 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1)); 968 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz; 969 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz; 970 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT; 971 if (!fb_reset) 972 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT; 973 else 974 asic_init_ps_v2_1.param.memparam.memflag = 0; 975 } else { 976 return -EINVAL; 977 } 978 } else { 979 return -EINVAL; 980 } 981 982 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1, 983 sizeof(asic_init_ps_v2_1)); 984 } 985