1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/amdgpu_drm.h> 25 #include "amdgpu.h" 26 #include "atomfirmware.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "atom.h" 29 #include "atombios.h" 30 #include "soc15_hw_ip.h" 31 32 union firmware_info { 33 struct atom_firmware_info_v3_1 v31; 34 struct atom_firmware_info_v3_2 v32; 35 struct atom_firmware_info_v3_3 v33; 36 struct atom_firmware_info_v3_4 v34; 37 }; 38 39 /* 40 * Helper function to query firmware capability 41 * 42 * @adev: amdgpu_device pointer 43 * 44 * Return firmware_capability in firmwareinfo table on success or 0 if not 45 */ 46 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev) 47 { 48 struct amdgpu_mode_info *mode_info = &adev->mode_info; 49 int index; 50 u16 data_offset, size; 51 union firmware_info *firmware_info; 52 u8 frev, crev; 53 u32 fw_cap = 0; 54 55 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 56 firmwareinfo); 57 58 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 59 index, &size, &frev, &crev, &data_offset)) { 60 /* support firmware_info 3.1 + */ 61 if ((frev == 3 && crev >=1) || (frev > 3)) { 62 firmware_info = (union firmware_info *) 63 (mode_info->atom_context->bios + data_offset); 64 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); 65 } 66 } 67 68 return fw_cap; 69 } 70 71 /* 72 * Helper function to query gpu virtualizaiton capability 73 * 74 * @adev: amdgpu_device pointer 75 * 76 * Return true if gpu virtualization is supported or false if not 77 */ 78 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev) 79 { 80 u32 fw_cap; 81 82 fw_cap = adev->mode_info.firmware_flags; 83 84 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false; 85 } 86 87 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) 88 { 89 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 90 firmwareinfo); 91 uint16_t data_offset; 92 93 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 94 NULL, NULL, &data_offset)) { 95 struct atom_firmware_info_v3_1 *firmware_info = 96 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 97 data_offset); 98 99 adev->bios_scratch_reg_offset = 100 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); 101 } 102 } 103 104 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev, 105 struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes) 106 { 107 u32 start_addr, fw_size, drv_size; 108 109 start_addr = le32_to_cpu(fw_usage->start_address_in_kb); 110 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); 111 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb); 112 113 DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n", 114 start_addr, 115 fw_size, 116 drv_size); 117 118 if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 119 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 120 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 121 /* Firmware request VRAM reservation for SR-IOV */ 122 adev->mman.fw_vram_usage_start_offset = (start_addr & 123 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 124 adev->mman.fw_vram_usage_size = fw_size << 10; 125 /* Use the default scratch size */ 126 *usage_bytes = 0; 127 } else { 128 *usage_bytes = drv_size << 10; 129 } 130 return 0; 131 } 132 133 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev, 134 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes) 135 { 136 u32 fw_start_addr, fw_size, drv_start_addr, drv_size; 137 138 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb); 139 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); 140 141 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb); 142 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb); 143 144 DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n", 145 fw_start_addr, 146 fw_size, 147 drv_start_addr, 148 drv_size); 149 150 if ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 151 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0) { 152 /* Firmware request VRAM reservation for SR-IOV */ 153 adev->mman.fw_vram_usage_start_offset = (fw_start_addr & 154 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 155 adev->mman.fw_vram_usage_size = fw_size << 10; 156 } 157 158 if ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 159 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0) { 160 /* driver request VRAM reservation for SR-IOV */ 161 adev->mman.drv_vram_usage_start_offset = (drv_start_addr & 162 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 163 adev->mman.drv_vram_usage_size = drv_size << 10; 164 } 165 166 *usage_bytes = 0; 167 return 0; 168 } 169 170 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) 171 { 172 struct atom_context *ctx = adev->mode_info.atom_context; 173 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 174 vram_usagebyfirmware); 175 struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1; 176 struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2; 177 u16 data_offset; 178 u8 frev, crev; 179 int usage_bytes = 0; 180 181 if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { 182 if (frev == 2 && crev == 1) { 183 fw_usage_v2_1 = 184 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); 185 amdgpu_atomfirmware_allocate_fb_v2_1(adev, 186 fw_usage_v2_1, 187 &usage_bytes); 188 } else if (frev >= 2 && crev >= 2) { 189 fw_usage_v2_2 = 190 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); 191 amdgpu_atomfirmware_allocate_fb_v2_2(adev, 192 fw_usage_v2_2, 193 &usage_bytes); 194 } 195 } 196 197 ctx->scratch_size_bytes = 0; 198 if (usage_bytes == 0) 199 usage_bytes = 20 * 1024; 200 /* allocate some scratch memory */ 201 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 202 if (!ctx->scratch) 203 return -ENOMEM; 204 ctx->scratch_size_bytes = usage_bytes; 205 return 0; 206 } 207 208 union igp_info { 209 struct atom_integrated_system_info_v1_11 v11; 210 struct atom_integrated_system_info_v1_12 v12; 211 struct atom_integrated_system_info_v2_1 v21; 212 }; 213 214 union umc_info { 215 struct atom_umc_info_v3_1 v31; 216 struct atom_umc_info_v3_2 v32; 217 struct atom_umc_info_v3_3 v33; 218 }; 219 220 union vram_info { 221 struct atom_vram_info_header_v2_3 v23; 222 struct atom_vram_info_header_v2_4 v24; 223 struct atom_vram_info_header_v2_5 v25; 224 struct atom_vram_info_header_v2_6 v26; 225 struct atom_vram_info_header_v3_0 v30; 226 }; 227 228 union vram_module { 229 struct atom_vram_module_v9 v9; 230 struct atom_vram_module_v10 v10; 231 struct atom_vram_module_v11 v11; 232 struct atom_vram_module_v3_0 v30; 233 }; 234 235 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, 236 int atom_mem_type) 237 { 238 int vram_type; 239 240 if (adev->flags & AMD_IS_APU) { 241 switch (atom_mem_type) { 242 case Ddr2MemType: 243 case LpDdr2MemType: 244 vram_type = AMDGPU_VRAM_TYPE_DDR2; 245 break; 246 case Ddr3MemType: 247 case LpDdr3MemType: 248 vram_type = AMDGPU_VRAM_TYPE_DDR3; 249 break; 250 case Ddr4MemType: 251 vram_type = AMDGPU_VRAM_TYPE_DDR4; 252 break; 253 case LpDdr4MemType: 254 vram_type = AMDGPU_VRAM_TYPE_LPDDR4; 255 break; 256 case Ddr5MemType: 257 vram_type = AMDGPU_VRAM_TYPE_DDR5; 258 break; 259 case LpDdr5MemType: 260 vram_type = AMDGPU_VRAM_TYPE_LPDDR5; 261 break; 262 default: 263 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 264 break; 265 } 266 } else { 267 switch (atom_mem_type) { 268 case ATOM_DGPU_VRAM_TYPE_GDDR5: 269 vram_type = AMDGPU_VRAM_TYPE_GDDR5; 270 break; 271 case ATOM_DGPU_VRAM_TYPE_HBM2: 272 case ATOM_DGPU_VRAM_TYPE_HBM2E: 273 vram_type = AMDGPU_VRAM_TYPE_HBM; 274 break; 275 case ATOM_DGPU_VRAM_TYPE_GDDR6: 276 vram_type = AMDGPU_VRAM_TYPE_GDDR6; 277 break; 278 default: 279 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 280 break; 281 } 282 } 283 284 return vram_type; 285 } 286 287 288 int 289 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 290 int *vram_width, int *vram_type, 291 int *vram_vendor) 292 { 293 struct amdgpu_mode_info *mode_info = &adev->mode_info; 294 int index, i = 0; 295 u16 data_offset, size; 296 union igp_info *igp_info; 297 union vram_info *vram_info; 298 union vram_module *vram_module; 299 u8 frev, crev; 300 u8 mem_type; 301 u8 mem_vendor; 302 u32 mem_channel_number; 303 u32 mem_channel_width; 304 u32 module_id; 305 306 if (adev->flags & AMD_IS_APU) 307 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 308 integratedsysteminfo); 309 else 310 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 311 vram_info); 312 313 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 314 index, &size, 315 &frev, &crev, &data_offset)) { 316 if (adev->flags & AMD_IS_APU) { 317 igp_info = (union igp_info *) 318 (mode_info->atom_context->bios + data_offset); 319 switch (frev) { 320 case 1: 321 switch (crev) { 322 case 11: 323 case 12: 324 mem_channel_number = igp_info->v11.umachannelnumber; 325 if (!mem_channel_number) 326 mem_channel_number = 1; 327 /* channel width is 64 */ 328 if (vram_width) 329 *vram_width = mem_channel_number * 64; 330 mem_type = igp_info->v11.memorytype; 331 if (vram_type) 332 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 333 break; 334 default: 335 return -EINVAL; 336 } 337 break; 338 case 2: 339 switch (crev) { 340 case 1: 341 case 2: 342 mem_channel_number = igp_info->v21.umachannelnumber; 343 if (!mem_channel_number) 344 mem_channel_number = 1; 345 /* channel width is 64 */ 346 if (vram_width) 347 *vram_width = mem_channel_number * 64; 348 mem_type = igp_info->v21.memorytype; 349 if (vram_type) 350 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 351 break; 352 default: 353 return -EINVAL; 354 } 355 break; 356 default: 357 return -EINVAL; 358 } 359 } else { 360 vram_info = (union vram_info *) 361 (mode_info->atom_context->bios + data_offset); 362 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; 363 if (frev == 3) { 364 switch (crev) { 365 /* v30 */ 366 case 0: 367 vram_module = (union vram_module *)vram_info->v30.vram_module; 368 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; 369 if (vram_vendor) 370 *vram_vendor = mem_vendor; 371 mem_type = vram_info->v30.memory_type; 372 if (vram_type) 373 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 374 mem_channel_number = vram_info->v30.channel_num; 375 mem_channel_width = vram_info->v30.channel_width; 376 if (vram_width) 377 *vram_width = mem_channel_number * (1 << mem_channel_width); 378 break; 379 default: 380 return -EINVAL; 381 } 382 } else if (frev == 2) { 383 switch (crev) { 384 /* v23 */ 385 case 3: 386 if (module_id > vram_info->v23.vram_module_num) 387 module_id = 0; 388 vram_module = (union vram_module *)vram_info->v23.vram_module; 389 while (i < module_id) { 390 vram_module = (union vram_module *) 391 ((u8 *)vram_module + vram_module->v9.vram_module_size); 392 i++; 393 } 394 mem_type = vram_module->v9.memory_type; 395 if (vram_type) 396 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 397 mem_channel_number = vram_module->v9.channel_num; 398 mem_channel_width = vram_module->v9.channel_width; 399 if (vram_width) 400 *vram_width = mem_channel_number * (1 << mem_channel_width); 401 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 402 if (vram_vendor) 403 *vram_vendor = mem_vendor; 404 break; 405 /* v24 */ 406 case 4: 407 if (module_id > vram_info->v24.vram_module_num) 408 module_id = 0; 409 vram_module = (union vram_module *)vram_info->v24.vram_module; 410 while (i < module_id) { 411 vram_module = (union vram_module *) 412 ((u8 *)vram_module + vram_module->v10.vram_module_size); 413 i++; 414 } 415 mem_type = vram_module->v10.memory_type; 416 if (vram_type) 417 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 418 mem_channel_number = vram_module->v10.channel_num; 419 mem_channel_width = vram_module->v10.channel_width; 420 if (vram_width) 421 *vram_width = mem_channel_number * (1 << mem_channel_width); 422 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; 423 if (vram_vendor) 424 *vram_vendor = mem_vendor; 425 break; 426 /* v25 */ 427 case 5: 428 if (module_id > vram_info->v25.vram_module_num) 429 module_id = 0; 430 vram_module = (union vram_module *)vram_info->v25.vram_module; 431 while (i < module_id) { 432 vram_module = (union vram_module *) 433 ((u8 *)vram_module + vram_module->v11.vram_module_size); 434 i++; 435 } 436 mem_type = vram_module->v11.memory_type; 437 if (vram_type) 438 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 439 mem_channel_number = vram_module->v11.channel_num; 440 mem_channel_width = vram_module->v11.channel_width; 441 if (vram_width) 442 *vram_width = mem_channel_number * (1 << mem_channel_width); 443 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; 444 if (vram_vendor) 445 *vram_vendor = mem_vendor; 446 break; 447 /* v26 */ 448 case 6: 449 if (module_id > vram_info->v26.vram_module_num) 450 module_id = 0; 451 vram_module = (union vram_module *)vram_info->v26.vram_module; 452 while (i < module_id) { 453 vram_module = (union vram_module *) 454 ((u8 *)vram_module + vram_module->v9.vram_module_size); 455 i++; 456 } 457 mem_type = vram_module->v9.memory_type; 458 if (vram_type) 459 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 460 mem_channel_number = vram_module->v9.channel_num; 461 mem_channel_width = vram_module->v9.channel_width; 462 if (vram_width) 463 *vram_width = mem_channel_number * (1 << mem_channel_width); 464 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 465 if (vram_vendor) 466 *vram_vendor = mem_vendor; 467 break; 468 default: 469 return -EINVAL; 470 } 471 } else { 472 /* invalid frev */ 473 return -EINVAL; 474 } 475 } 476 477 } 478 479 return 0; 480 } 481 482 /* 483 * Return true if vbios enabled ecc by default, if umc info table is available 484 * or false if ecc is not enabled or umc info table is not available 485 */ 486 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 487 { 488 struct amdgpu_mode_info *mode_info = &adev->mode_info; 489 int index; 490 u16 data_offset, size; 491 union umc_info *umc_info; 492 u8 frev, crev; 493 bool ecc_default_enabled = false; 494 u8 umc_config; 495 u32 umc_config1; 496 497 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 498 umc_info); 499 500 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 501 index, &size, &frev, &crev, &data_offset)) { 502 if (frev == 3) { 503 umc_info = (union umc_info *) 504 (mode_info->atom_context->bios + data_offset); 505 switch (crev) { 506 case 1: 507 umc_config = le32_to_cpu(umc_info->v31.umc_config); 508 ecc_default_enabled = 509 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 510 break; 511 case 2: 512 umc_config = le32_to_cpu(umc_info->v32.umc_config); 513 ecc_default_enabled = 514 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 515 break; 516 case 3: 517 umc_config = le32_to_cpu(umc_info->v33.umc_config); 518 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1); 519 ecc_default_enabled = 520 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) || 521 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false; 522 break; 523 default: 524 /* unsupported crev */ 525 return false; 526 } 527 } 528 } 529 530 return ecc_default_enabled; 531 } 532 533 /* 534 * Helper function to query sram ecc capablity 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Return true if vbios supports sram ecc or false if not 539 */ 540 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev) 541 { 542 u32 fw_cap; 543 544 fw_cap = adev->mode_info.firmware_flags; 545 546 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; 547 } 548 549 /* 550 * Helper function to query dynamic boot config capability 551 * 552 * @adev: amdgpu_device pointer 553 * 554 * Return true if vbios supports dynamic boot config or false if not 555 */ 556 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev) 557 { 558 u32 fw_cap; 559 560 fw_cap = adev->mode_info.firmware_flags; 561 562 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false; 563 } 564 565 /** 566 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS 567 * @adev: amdgpu_device pointer 568 * @i2c_address: pointer to u8; if not NULL, will contain 569 * the RAS EEPROM address if the function returns true 570 * 571 * Return true if VBIOS supports RAS EEPROM address reporting, 572 * else return false. If true and @i2c_address is not NULL, 573 * will contain the RAS ROM address. 574 */ 575 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, 576 u8 *i2c_address) 577 { 578 struct amdgpu_mode_info *mode_info = &adev->mode_info; 579 int index; 580 u16 data_offset, size; 581 union firmware_info *firmware_info; 582 u8 frev, crev; 583 584 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 585 firmwareinfo); 586 587 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 588 index, &size, &frev, &crev, 589 &data_offset)) { 590 /* support firmware_info 3.4 + */ 591 if ((frev == 3 && crev >=4) || (frev > 3)) { 592 firmware_info = (union firmware_info *) 593 (mode_info->atom_context->bios + data_offset); 594 /* The ras_rom_i2c_slave_addr should ideally 595 * be a 19-bit EEPROM address, which would be 596 * used as is by the driver; see top of 597 * amdgpu_eeprom.c. 598 * 599 * When this is the case, 0 is of course a 600 * valid RAS EEPROM address, in which case, 601 * we'll drop the first "if (firm...)" and only 602 * leave the check for the pointer. 603 * 604 * The reason this works right now is because 605 * ras_rom_i2c_slave_addr contains the EEPROM 606 * device type qualifier 1010b in the top 4 607 * bits. 608 */ 609 if (firmware_info->v34.ras_rom_i2c_slave_addr) { 610 if (i2c_address) 611 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr; 612 return true; 613 } 614 } 615 } 616 617 return false; 618 } 619 620 621 union smu_info { 622 struct atom_smu_info_v3_1 v31; 623 struct atom_smu_info_v4_0 v40; 624 }; 625 626 union gfx_info { 627 struct atom_gfx_info_v2_2 v22; 628 struct atom_gfx_info_v2_4 v24; 629 struct atom_gfx_info_v2_7 v27; 630 struct atom_gfx_info_v3_0 v30; 631 }; 632 633 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) 634 { 635 struct amdgpu_mode_info *mode_info = &adev->mode_info; 636 struct amdgpu_pll *spll = &adev->clock.spll; 637 struct amdgpu_pll *mpll = &adev->clock.mpll; 638 uint8_t frev, crev; 639 uint16_t data_offset; 640 int ret = -EINVAL, index; 641 642 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 643 firmwareinfo); 644 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 645 &frev, &crev, &data_offset)) { 646 union firmware_info *firmware_info = 647 (union firmware_info *)(mode_info->atom_context->bios + 648 data_offset); 649 650 adev->clock.default_sclk = 651 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 652 adev->clock.default_mclk = 653 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 654 655 adev->pm.current_sclk = adev->clock.default_sclk; 656 adev->pm.current_mclk = adev->clock.default_mclk; 657 658 ret = 0; 659 } 660 661 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 662 smu_info); 663 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 664 &frev, &crev, &data_offset)) { 665 union smu_info *smu_info = 666 (union smu_info *)(mode_info->atom_context->bios + 667 data_offset); 668 669 /* system clock */ 670 if (frev == 3) 671 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); 672 else if (frev == 4) 673 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz); 674 675 spll->reference_div = 0; 676 spll->min_post_div = 1; 677 spll->max_post_div = 1; 678 spll->min_ref_div = 2; 679 spll->max_ref_div = 0xff; 680 spll->min_feedback_div = 4; 681 spll->max_feedback_div = 0xff; 682 spll->best_vco = 0; 683 684 ret = 0; 685 } 686 687 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 688 umc_info); 689 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 690 &frev, &crev, &data_offset)) { 691 union umc_info *umc_info = 692 (union umc_info *)(mode_info->atom_context->bios + 693 data_offset); 694 695 /* memory clock */ 696 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); 697 698 mpll->reference_div = 0; 699 mpll->min_post_div = 1; 700 mpll->max_post_div = 1; 701 mpll->min_ref_div = 2; 702 mpll->max_ref_div = 0xff; 703 mpll->min_feedback_div = 4; 704 mpll->max_feedback_div = 0xff; 705 mpll->best_vco = 0; 706 707 ret = 0; 708 } 709 710 /* if asic is Navi+, the rlc reference clock is used for system clock 711 * from vbios gfx_info table */ 712 if (adev->asic_type >= CHIP_NAVI10) { 713 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 714 gfx_info); 715 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 716 &frev, &crev, &data_offset)) { 717 union gfx_info *gfx_info = (union gfx_info *) 718 (mode_info->atom_context->bios + data_offset); 719 if ((frev == 3) || 720 (frev == 2 && crev == 6)) { 721 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk); 722 ret = 0; 723 } else if ((frev == 2) && 724 (crev >= 2) && 725 (crev != 6)) { 726 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk); 727 ret = 0; 728 } else { 729 BUG(); 730 } 731 } 732 } 733 734 return ret; 735 } 736 737 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 738 { 739 struct amdgpu_mode_info *mode_info = &adev->mode_info; 740 int index; 741 uint8_t frev, crev; 742 uint16_t data_offset; 743 744 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 745 gfx_info); 746 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 747 &frev, &crev, &data_offset)) { 748 union gfx_info *gfx_info = (union gfx_info *) 749 (mode_info->atom_context->bios + data_offset); 750 if (frev == 2) { 751 switch (crev) { 752 case 4: 753 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; 754 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; 755 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; 756 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; 757 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; 758 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); 759 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; 760 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; 761 adev->gfx.config.gs_prim_buffer_depth = 762 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth); 763 adev->gfx.config.double_offchip_lds_buf = 764 gfx_info->v24.gc_double_offchip_lds_buffer; 765 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size); 766 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd); 767 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; 768 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); 769 return 0; 770 case 7: 771 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines; 772 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; 773 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; 774 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; 775 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches; 776 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); 777 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds; 778 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth; 779 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth); 780 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer; 781 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size); 782 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd); 783 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu; 784 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size); 785 return 0; 786 default: 787 return -EINVAL; 788 } 789 } else if (frev == 3) { 790 switch (crev) { 791 case 0: 792 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines; 793 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh; 794 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; 795 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se; 796 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches; 797 return 0; 798 default: 799 return -EINVAL; 800 } 801 } else { 802 return -EINVAL; 803 } 804 805 } 806 return -EINVAL; 807 } 808 809 /* 810 * Helper function to query two stage mem training capability 811 * 812 * @adev: amdgpu_device pointer 813 * 814 * Return true if two stage mem training is supported or false if not 815 */ 816 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev) 817 { 818 u32 fw_cap; 819 820 fw_cap = adev->mode_info.firmware_flags; 821 822 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false; 823 } 824 825 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) 826 { 827 struct atom_context *ctx = adev->mode_info.atom_context; 828 union firmware_info *firmware_info; 829 int index; 830 u16 data_offset, size; 831 u8 frev, crev; 832 int fw_reserved_fb_size; 833 834 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 835 firmwareinfo); 836 837 if (!amdgpu_atom_parse_data_header(ctx, index, &size, 838 &frev, &crev, &data_offset)) 839 /* fail to parse data_header */ 840 return 0; 841 842 firmware_info = (union firmware_info *)(ctx->bios + data_offset); 843 844 if (frev !=3) 845 return -EINVAL; 846 847 switch (crev) { 848 case 4: 849 fw_reserved_fb_size = 850 (firmware_info->v34.fw_reserved_size_in_kb << 10); 851 break; 852 default: 853 fw_reserved_fb_size = 0; 854 break; 855 } 856 857 return fw_reserved_fb_size; 858 } 859 860 /* 861 * Helper function to execute asic_init table 862 * 863 * @adev: amdgpu_device pointer 864 * @fb_reset: flag to indicate whether fb is reset or not 865 * 866 * Return 0 if succeed, otherwise failed 867 */ 868 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset) 869 { 870 struct amdgpu_mode_info *mode_info = &adev->mode_info; 871 struct atom_context *ctx; 872 uint8_t frev, crev; 873 uint16_t data_offset; 874 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz; 875 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1; 876 int index; 877 878 if (!mode_info) 879 return -EINVAL; 880 881 ctx = mode_info->atom_context; 882 if (!ctx) 883 return -EINVAL; 884 885 /* query bootup sclk/mclk from firmware_info table */ 886 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 887 firmwareinfo); 888 if (amdgpu_atom_parse_data_header(ctx, index, NULL, 889 &frev, &crev, &data_offset)) { 890 union firmware_info *firmware_info = 891 (union firmware_info *)(ctx->bios + 892 data_offset); 893 894 bootup_sclk_in10khz = 895 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 896 bootup_mclk_in10khz = 897 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 898 } else { 899 return -EINVAL; 900 } 901 902 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 903 asic_init); 904 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) { 905 if (frev == 2 && crev >= 1) { 906 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1)); 907 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz; 908 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz; 909 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT; 910 if (!fb_reset) 911 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT; 912 else 913 asic_init_ps_v2_1.param.memparam.memflag = 0; 914 } else { 915 return -EINVAL; 916 } 917 } else { 918 return -EINVAL; 919 } 920 921 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1); 922 } 923