1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 extern unsigned amdgpu_pcie_gen_cap; 89 extern unsigned amdgpu_pcie_lane_cap; 90 91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 95 #define AMDGPU_IB_POOL_SIZE 16 96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 97 #define AMDGPUFB_CONN_LIMIT 4 98 #define AMDGPU_BIOS_NUM_SCRATCH 8 99 100 /* max number of rings */ 101 #define AMDGPU_MAX_RINGS 16 102 #define AMDGPU_MAX_GFX_RINGS 1 103 #define AMDGPU_MAX_COMPUTE_RINGS 8 104 #define AMDGPU_MAX_VCE_RINGS 2 105 106 /* max number of IP instances */ 107 #define AMDGPU_MAX_SDMA_INSTANCES 2 108 109 /* hardcode that limit for now */ 110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 111 112 /* hard reset data */ 113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 114 115 /* reset flags */ 116 #define AMDGPU_RESET_GFX (1 << 0) 117 #define AMDGPU_RESET_COMPUTE (1 << 1) 118 #define AMDGPU_RESET_DMA (1 << 2) 119 #define AMDGPU_RESET_CP (1 << 3) 120 #define AMDGPU_RESET_GRBM (1 << 4) 121 #define AMDGPU_RESET_DMA1 (1 << 5) 122 #define AMDGPU_RESET_RLC (1 << 6) 123 #define AMDGPU_RESET_SEM (1 << 7) 124 #define AMDGPU_RESET_IH (1 << 8) 125 #define AMDGPU_RESET_VMC (1 << 9) 126 #define AMDGPU_RESET_MC (1 << 10) 127 #define AMDGPU_RESET_DISPLAY (1 << 11) 128 #define AMDGPU_RESET_UVD (1 << 12) 129 #define AMDGPU_RESET_VCE (1 << 13) 130 #define AMDGPU_RESET_VCE1 (1 << 14) 131 132 /* GFX current status */ 133 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 134 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 135 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 136 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 137 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 138 139 /* max cursor sizes (in pixels) */ 140 #define CIK_CURSOR_WIDTH 128 141 #define CIK_CURSOR_HEIGHT 128 142 143 struct amdgpu_device; 144 struct amdgpu_ib; 145 struct amdgpu_vm; 146 struct amdgpu_ring; 147 struct amdgpu_cs_parser; 148 struct amdgpu_job; 149 struct amdgpu_irq_src; 150 struct amdgpu_fpriv; 151 152 enum amdgpu_cp_irq { 153 AMDGPU_CP_IRQ_GFX_EOP = 0, 154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 162 163 AMDGPU_CP_IRQ_LAST 164 }; 165 166 enum amdgpu_sdma_irq { 167 AMDGPU_SDMA_IRQ_TRAP0 = 0, 168 AMDGPU_SDMA_IRQ_TRAP1, 169 170 AMDGPU_SDMA_IRQ_LAST 171 }; 172 173 enum amdgpu_thermal_irq { 174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 176 177 AMDGPU_THERMAL_IRQ_LAST 178 }; 179 180 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 181 enum amd_ip_block_type block_type, 182 enum amd_clockgating_state state); 183 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 184 enum amd_ip_block_type block_type, 185 enum amd_powergating_state state); 186 187 struct amdgpu_ip_block_version { 188 enum amd_ip_block_type type; 189 u32 major; 190 u32 minor; 191 u32 rev; 192 const struct amd_ip_funcs *funcs; 193 }; 194 195 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 196 enum amd_ip_block_type type, 197 u32 major, u32 minor); 198 199 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 200 struct amdgpu_device *adev, 201 enum amd_ip_block_type type); 202 203 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 204 struct amdgpu_buffer_funcs { 205 /* maximum bytes in a single operation */ 206 uint32_t copy_max_bytes; 207 208 /* number of dw to reserve per operation */ 209 unsigned copy_num_dw; 210 211 /* used for buffer migration */ 212 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 213 /* src addr in bytes */ 214 uint64_t src_offset, 215 /* dst addr in bytes */ 216 uint64_t dst_offset, 217 /* number of byte to transfer */ 218 uint32_t byte_count); 219 220 /* maximum bytes in a single operation */ 221 uint32_t fill_max_bytes; 222 223 /* number of dw to reserve per operation */ 224 unsigned fill_num_dw; 225 226 /* used for buffer clearing */ 227 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 228 /* value to write to memory */ 229 uint32_t src_data, 230 /* dst addr in bytes */ 231 uint64_t dst_offset, 232 /* number of byte to fill */ 233 uint32_t byte_count); 234 }; 235 236 /* provided by hw blocks that can write ptes, e.g., sdma */ 237 struct amdgpu_vm_pte_funcs { 238 /* copy pte entries from GART */ 239 void (*copy_pte)(struct amdgpu_ib *ib, 240 uint64_t pe, uint64_t src, 241 unsigned count); 242 /* write pte one entry at a time with addr mapping */ 243 void (*write_pte)(struct amdgpu_ib *ib, 244 const dma_addr_t *pages_addr, uint64_t pe, 245 uint64_t addr, unsigned count, 246 uint32_t incr, uint32_t flags); 247 /* for linear pte/pde updates without addr mapping */ 248 void (*set_pte_pde)(struct amdgpu_ib *ib, 249 uint64_t pe, 250 uint64_t addr, unsigned count, 251 uint32_t incr, uint32_t flags); 252 }; 253 254 /* provided by the gmc block */ 255 struct amdgpu_gart_funcs { 256 /* flush the vm tlb via mmio */ 257 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 258 uint32_t vmid); 259 /* write pte/pde updates using the cpu */ 260 int (*set_pte_pde)(struct amdgpu_device *adev, 261 void *cpu_pt_addr, /* cpu addr of page table */ 262 uint32_t gpu_page_idx, /* pte/pde to update */ 263 uint64_t addr, /* addr to write into pte/pde */ 264 uint32_t flags); /* access flags */ 265 }; 266 267 /* provided by the ih block */ 268 struct amdgpu_ih_funcs { 269 /* ring read/write ptr handling, called from interrupt context */ 270 u32 (*get_wptr)(struct amdgpu_device *adev); 271 void (*decode_iv)(struct amdgpu_device *adev, 272 struct amdgpu_iv_entry *entry); 273 void (*set_rptr)(struct amdgpu_device *adev); 274 }; 275 276 /* provided by hw blocks that expose a ring buffer for commands */ 277 struct amdgpu_ring_funcs { 278 /* ring read/write ptr handling */ 279 u32 (*get_rptr)(struct amdgpu_ring *ring); 280 u32 (*get_wptr)(struct amdgpu_ring *ring); 281 void (*set_wptr)(struct amdgpu_ring *ring); 282 /* validating and patching of IBs */ 283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 284 /* command emit functions */ 285 void (*emit_ib)(struct amdgpu_ring *ring, 286 struct amdgpu_ib *ib, 287 unsigned vm_id, bool ctx_switch); 288 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 289 uint64_t seq, unsigned flags); 290 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 291 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 292 uint64_t pd_addr); 293 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 294 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 295 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 296 uint32_t gds_base, uint32_t gds_size, 297 uint32_t gws_base, uint32_t gws_size, 298 uint32_t oa_base, uint32_t oa_size); 299 /* testing functions */ 300 int (*test_ring)(struct amdgpu_ring *ring); 301 int (*test_ib)(struct amdgpu_ring *ring); 302 /* insert NOP packets */ 303 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 304 /* pad the indirect buffer to the necessary number of dw */ 305 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 306 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 307 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 308 }; 309 310 /* 311 * BIOS. 312 */ 313 bool amdgpu_get_bios(struct amdgpu_device *adev); 314 bool amdgpu_read_bios(struct amdgpu_device *adev); 315 316 /* 317 * Dummy page 318 */ 319 struct amdgpu_dummy_page { 320 struct page *page; 321 dma_addr_t addr; 322 }; 323 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 324 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 325 326 327 /* 328 * Clocks 329 */ 330 331 #define AMDGPU_MAX_PPLL 3 332 333 struct amdgpu_clock { 334 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 335 struct amdgpu_pll spll; 336 struct amdgpu_pll mpll; 337 /* 10 Khz units */ 338 uint32_t default_mclk; 339 uint32_t default_sclk; 340 uint32_t default_dispclk; 341 uint32_t current_dispclk; 342 uint32_t dp_extclk; 343 uint32_t max_pixel_clock; 344 }; 345 346 /* 347 * Fences. 348 */ 349 struct amdgpu_fence_driver { 350 uint64_t gpu_addr; 351 volatile uint32_t *cpu_addr; 352 /* sync_seq is protected by ring emission lock */ 353 uint32_t sync_seq; 354 atomic_t last_seq; 355 bool initialized; 356 struct amdgpu_irq_src *irq_src; 357 unsigned irq_type; 358 struct timer_list fallback_timer; 359 unsigned num_fences_mask; 360 spinlock_t lock; 361 struct fence **fences; 362 }; 363 364 /* some special values for the owner field */ 365 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 366 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 367 368 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 369 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 370 371 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 372 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 373 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 374 375 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 376 unsigned num_hw_submission); 377 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 378 struct amdgpu_irq_src *irq_src, 379 unsigned irq_type); 380 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 381 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 382 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 383 void amdgpu_fence_process(struct amdgpu_ring *ring); 384 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 385 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 386 387 /* 388 * TTM. 389 */ 390 391 #define AMDGPU_TTM_LRU_SIZE 20 392 393 struct amdgpu_mman_lru { 394 struct list_head *lru[TTM_NUM_MEM_TYPES]; 395 struct list_head *swap_lru; 396 }; 397 398 struct amdgpu_mman { 399 struct ttm_bo_global_ref bo_global_ref; 400 struct drm_global_reference mem_global_ref; 401 struct ttm_bo_device bdev; 402 bool mem_global_referenced; 403 bool initialized; 404 405 #if defined(CONFIG_DEBUG_FS) 406 struct dentry *vram; 407 struct dentry *gtt; 408 #endif 409 410 /* buffer handling */ 411 const struct amdgpu_buffer_funcs *buffer_funcs; 412 struct amdgpu_ring *buffer_funcs_ring; 413 /* Scheduler entity for buffer moves */ 414 struct amd_sched_entity entity; 415 416 /* custom LRU management */ 417 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; 418 }; 419 420 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 421 uint64_t src_offset, 422 uint64_t dst_offset, 423 uint32_t byte_count, 424 struct reservation_object *resv, 425 struct fence **fence); 426 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 427 428 struct amdgpu_bo_list_entry { 429 struct amdgpu_bo *robj; 430 struct ttm_validate_buffer tv; 431 struct amdgpu_bo_va *bo_va; 432 uint32_t priority; 433 struct page **user_pages; 434 int user_invalidated; 435 }; 436 437 struct amdgpu_bo_va_mapping { 438 struct list_head list; 439 struct interval_tree_node it; 440 uint64_t offset; 441 uint32_t flags; 442 }; 443 444 /* bo virtual addresses in a specific vm */ 445 struct amdgpu_bo_va { 446 /* protected by bo being reserved */ 447 struct list_head bo_list; 448 struct fence *last_pt_update; 449 unsigned ref_count; 450 451 /* protected by vm mutex and spinlock */ 452 struct list_head vm_status; 453 454 /* mappings for this bo_va */ 455 struct list_head invalids; 456 struct list_head valids; 457 458 /* constant after initialization */ 459 struct amdgpu_vm *vm; 460 struct amdgpu_bo *bo; 461 }; 462 463 #define AMDGPU_GEM_DOMAIN_MAX 0x3 464 465 struct amdgpu_bo { 466 /* Protected by gem.mutex */ 467 struct list_head list; 468 /* Protected by tbo.reserved */ 469 u32 prefered_domains; 470 u32 allowed_domains; 471 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 472 struct ttm_placement placement; 473 struct ttm_buffer_object tbo; 474 struct ttm_bo_kmap_obj kmap; 475 u64 flags; 476 unsigned pin_count; 477 void *kptr; 478 u64 tiling_flags; 479 u64 metadata_flags; 480 void *metadata; 481 u32 metadata_size; 482 /* list of all virtual address to which this bo 483 * is associated to 484 */ 485 struct list_head va; 486 /* Constant after initialization */ 487 struct amdgpu_device *adev; 488 struct drm_gem_object gem_base; 489 struct amdgpu_bo *parent; 490 491 struct ttm_bo_kmap_obj dma_buf_vmap; 492 struct amdgpu_mn *mn; 493 struct list_head mn_list; 494 }; 495 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 496 497 void amdgpu_gem_object_free(struct drm_gem_object *obj); 498 int amdgpu_gem_object_open(struct drm_gem_object *obj, 499 struct drm_file *file_priv); 500 void amdgpu_gem_object_close(struct drm_gem_object *obj, 501 struct drm_file *file_priv); 502 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 503 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 504 struct drm_gem_object * 505 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 506 struct dma_buf_attachment *attach, 507 struct sg_table *sg); 508 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 509 struct drm_gem_object *gobj, 510 int flags); 511 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 512 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 513 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 514 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 515 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 516 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 517 518 /* sub-allocation manager, it has to be protected by another lock. 519 * By conception this is an helper for other part of the driver 520 * like the indirect buffer or semaphore, which both have their 521 * locking. 522 * 523 * Principe is simple, we keep a list of sub allocation in offset 524 * order (first entry has offset == 0, last entry has the highest 525 * offset). 526 * 527 * When allocating new object we first check if there is room at 528 * the end total_size - (last_object_offset + last_object_size) >= 529 * alloc_size. If so we allocate new object there. 530 * 531 * When there is not enough room at the end, we start waiting for 532 * each sub object until we reach object_offset+object_size >= 533 * alloc_size, this object then become the sub object we return. 534 * 535 * Alignment can't be bigger than page size. 536 * 537 * Hole are not considered for allocation to keep things simple. 538 * Assumption is that there won't be hole (all object on same 539 * alignment). 540 */ 541 542 #define AMDGPU_SA_NUM_FENCE_LISTS 32 543 544 struct amdgpu_sa_manager { 545 wait_queue_head_t wq; 546 struct amdgpu_bo *bo; 547 struct list_head *hole; 548 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 549 struct list_head olist; 550 unsigned size; 551 uint64_t gpu_addr; 552 void *cpu_ptr; 553 uint32_t domain; 554 uint32_t align; 555 }; 556 557 /* sub-allocation buffer */ 558 struct amdgpu_sa_bo { 559 struct list_head olist; 560 struct list_head flist; 561 struct amdgpu_sa_manager *manager; 562 unsigned soffset; 563 unsigned eoffset; 564 struct fence *fence; 565 }; 566 567 /* 568 * GEM objects. 569 */ 570 void amdgpu_gem_force_release(struct amdgpu_device *adev); 571 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 572 int alignment, u32 initial_domain, 573 u64 flags, bool kernel, 574 struct drm_gem_object **obj); 575 576 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 577 struct drm_device *dev, 578 struct drm_mode_create_dumb *args); 579 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 580 struct drm_device *dev, 581 uint32_t handle, uint64_t *offset_p); 582 /* 583 * Synchronization 584 */ 585 struct amdgpu_sync { 586 DECLARE_HASHTABLE(fences, 4); 587 struct fence *last_vm_update; 588 }; 589 590 void amdgpu_sync_create(struct amdgpu_sync *sync); 591 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 592 struct fence *f); 593 int amdgpu_sync_resv(struct amdgpu_device *adev, 594 struct amdgpu_sync *sync, 595 struct reservation_object *resv, 596 void *owner); 597 bool amdgpu_sync_is_idle(struct amdgpu_sync *sync); 598 int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, 599 struct fence *fence); 600 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 601 int amdgpu_sync_wait(struct amdgpu_sync *sync); 602 void amdgpu_sync_free(struct amdgpu_sync *sync); 603 int amdgpu_sync_init(void); 604 void amdgpu_sync_fini(void); 605 606 /* 607 * GART structures, functions & helpers 608 */ 609 struct amdgpu_mc; 610 611 #define AMDGPU_GPU_PAGE_SIZE 4096 612 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 613 #define AMDGPU_GPU_PAGE_SHIFT 12 614 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 615 616 struct amdgpu_gart { 617 dma_addr_t table_addr; 618 struct amdgpu_bo *robj; 619 void *ptr; 620 unsigned num_gpu_pages; 621 unsigned num_cpu_pages; 622 unsigned table_size; 623 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 624 struct page **pages; 625 #endif 626 bool ready; 627 const struct amdgpu_gart_funcs *gart_funcs; 628 }; 629 630 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 631 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 632 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 633 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 634 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 635 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 636 int amdgpu_gart_init(struct amdgpu_device *adev); 637 void amdgpu_gart_fini(struct amdgpu_device *adev); 638 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 639 int pages); 640 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 641 int pages, struct page **pagelist, 642 dma_addr_t *dma_addr, uint32_t flags); 643 644 /* 645 * GPU MC structures, functions & helpers 646 */ 647 struct amdgpu_mc { 648 resource_size_t aper_size; 649 resource_size_t aper_base; 650 resource_size_t agp_base; 651 /* for some chips with <= 32MB we need to lie 652 * about vram size near mc fb location */ 653 u64 mc_vram_size; 654 u64 visible_vram_size; 655 u64 gtt_size; 656 u64 gtt_start; 657 u64 gtt_end; 658 u64 vram_start; 659 u64 vram_end; 660 unsigned vram_width; 661 u64 real_vram_size; 662 int vram_mtrr; 663 u64 gtt_base_align; 664 u64 mc_mask; 665 const struct firmware *fw; /* MC firmware */ 666 uint32_t fw_version; 667 struct amdgpu_irq_src vm_fault; 668 uint32_t vram_type; 669 }; 670 671 /* 672 * GPU doorbell structures, functions & helpers 673 */ 674 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 675 { 676 AMDGPU_DOORBELL_KIQ = 0x000, 677 AMDGPU_DOORBELL_HIQ = 0x001, 678 AMDGPU_DOORBELL_DIQ = 0x002, 679 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 680 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 681 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 682 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 683 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 684 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 685 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 686 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 687 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 688 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 689 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 690 AMDGPU_DOORBELL_IH = 0x1E8, 691 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 692 AMDGPU_DOORBELL_INVALID = 0xFFFF 693 } AMDGPU_DOORBELL_ASSIGNMENT; 694 695 struct amdgpu_doorbell { 696 /* doorbell mmio */ 697 resource_size_t base; 698 resource_size_t size; 699 u32 __iomem *ptr; 700 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 701 }; 702 703 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 704 phys_addr_t *aperture_base, 705 size_t *aperture_size, 706 size_t *start_offset); 707 708 /* 709 * IRQS. 710 */ 711 712 struct amdgpu_flip_work { 713 struct work_struct flip_work; 714 struct work_struct unpin_work; 715 struct amdgpu_device *adev; 716 int crtc_id; 717 uint64_t base; 718 struct drm_pending_vblank_event *event; 719 struct amdgpu_bo *old_rbo; 720 struct fence *excl; 721 unsigned shared_count; 722 struct fence **shared; 723 struct fence_cb cb; 724 bool async; 725 }; 726 727 728 /* 729 * CP & rings. 730 */ 731 732 struct amdgpu_ib { 733 struct amdgpu_sa_bo *sa_bo; 734 uint32_t length_dw; 735 uint64_t gpu_addr; 736 uint32_t *ptr; 737 uint32_t flags; 738 }; 739 740 enum amdgpu_ring_type { 741 AMDGPU_RING_TYPE_GFX, 742 AMDGPU_RING_TYPE_COMPUTE, 743 AMDGPU_RING_TYPE_SDMA, 744 AMDGPU_RING_TYPE_UVD, 745 AMDGPU_RING_TYPE_VCE 746 }; 747 748 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 749 750 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 751 struct amdgpu_job **job, struct amdgpu_vm *vm); 752 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 753 struct amdgpu_job **job); 754 755 void amdgpu_job_free(struct amdgpu_job *job); 756 void amdgpu_job_free_func(struct kref *refcount); 757 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 758 struct amd_sched_entity *entity, void *owner, 759 struct fence **f); 760 void amdgpu_job_timeout_func(struct work_struct *work); 761 762 struct amdgpu_ring { 763 struct amdgpu_device *adev; 764 const struct amdgpu_ring_funcs *funcs; 765 struct amdgpu_fence_driver fence_drv; 766 struct amd_gpu_scheduler sched; 767 768 spinlock_t fence_lock; 769 struct amdgpu_bo *ring_obj; 770 volatile uint32_t *ring; 771 unsigned rptr_offs; 772 u64 next_rptr_gpu_addr; 773 volatile u32 *next_rptr_cpu_addr; 774 unsigned wptr; 775 unsigned wptr_old; 776 unsigned ring_size; 777 unsigned max_dw; 778 int count_dw; 779 uint64_t gpu_addr; 780 uint32_t align_mask; 781 uint32_t ptr_mask; 782 bool ready; 783 u32 nop; 784 u32 idx; 785 u32 me; 786 u32 pipe; 787 u32 queue; 788 struct amdgpu_bo *mqd_obj; 789 u32 doorbell_index; 790 bool use_doorbell; 791 unsigned wptr_offs; 792 unsigned next_rptr_offs; 793 unsigned fence_offs; 794 uint64_t current_ctx; 795 enum amdgpu_ring_type type; 796 char name[16]; 797 unsigned cond_exe_offs; 798 u64 cond_exe_gpu_addr; 799 volatile u32 *cond_exe_cpu_addr; 800 }; 801 802 /* 803 * VM 804 */ 805 806 /* maximum number of VMIDs */ 807 #define AMDGPU_NUM_VM 16 808 809 /* number of entries in page table */ 810 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 811 812 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 813 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 814 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 815 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 816 817 #define AMDGPU_PTE_VALID (1 << 0) 818 #define AMDGPU_PTE_SYSTEM (1 << 1) 819 #define AMDGPU_PTE_SNOOPED (1 << 2) 820 821 /* VI only */ 822 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 823 824 #define AMDGPU_PTE_READABLE (1 << 5) 825 #define AMDGPU_PTE_WRITEABLE (1 << 6) 826 827 /* PTE (Page Table Entry) fragment field for different page sizes */ 828 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 829 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 830 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 831 832 /* How to programm VM fault handling */ 833 #define AMDGPU_VM_FAULT_STOP_NEVER 0 834 #define AMDGPU_VM_FAULT_STOP_FIRST 1 835 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 836 837 struct amdgpu_vm_pt { 838 struct amdgpu_bo_list_entry entry; 839 uint64_t addr; 840 }; 841 842 struct amdgpu_vm { 843 /* tree of virtual addresses mapped */ 844 struct rb_root va; 845 846 /* protecting invalidated */ 847 spinlock_t status_lock; 848 849 /* BOs moved, but not yet updated in the PT */ 850 struct list_head invalidated; 851 852 /* BOs cleared in the PT because of a move */ 853 struct list_head cleared; 854 855 /* BO mappings freed, but not yet updated in the PT */ 856 struct list_head freed; 857 858 /* contains the page directory */ 859 struct amdgpu_bo *page_directory; 860 unsigned max_pde_used; 861 struct fence *page_directory_fence; 862 863 /* array of page tables, one for each page directory entry */ 864 struct amdgpu_vm_pt *page_tables; 865 866 /* for id and flush management per ring */ 867 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 868 869 /* protecting freed */ 870 spinlock_t freed_lock; 871 872 /* Scheduler entity for page table updates */ 873 struct amd_sched_entity entity; 874 875 /* client id */ 876 u64 client_id; 877 }; 878 879 struct amdgpu_vm_id { 880 struct list_head list; 881 struct fence *first; 882 struct amdgpu_sync active; 883 struct fence *last_flush; 884 struct amdgpu_ring *last_user; 885 atomic64_t owner; 886 887 uint64_t pd_gpu_addr; 888 /* last flushed PD/PT update */ 889 struct fence *flushed_updates; 890 891 uint32_t gds_base; 892 uint32_t gds_size; 893 uint32_t gws_base; 894 uint32_t gws_size; 895 uint32_t oa_base; 896 uint32_t oa_size; 897 }; 898 899 struct amdgpu_vm_manager { 900 /* Handling of VMIDs */ 901 struct mutex lock; 902 unsigned num_ids; 903 struct list_head ids_lru; 904 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 905 906 uint32_t max_pfn; 907 /* vram base address for page table entry */ 908 u64 vram_base_offset; 909 /* is vm enabled? */ 910 bool enabled; 911 /* vm pte handling */ 912 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 913 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 914 unsigned vm_pte_num_rings; 915 atomic_t vm_pte_next_ring; 916 /* client id counter */ 917 atomic64_t client_counter; 918 }; 919 920 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 921 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 922 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 923 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 924 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 925 struct list_head *validated, 926 struct amdgpu_bo_list_entry *entry); 927 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 928 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 929 struct amdgpu_vm *vm); 930 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 931 struct amdgpu_sync *sync, struct fence *fence, 932 unsigned *vm_id, uint64_t *vm_pd_addr); 933 int amdgpu_vm_flush(struct amdgpu_ring *ring, 934 unsigned vm_id, uint64_t pd_addr, 935 uint32_t gds_base, uint32_t gds_size, 936 uint32_t gws_base, uint32_t gws_size, 937 uint32_t oa_base, uint32_t oa_size); 938 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 939 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 940 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 941 struct amdgpu_vm *vm); 942 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 943 struct amdgpu_vm *vm); 944 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 945 struct amdgpu_sync *sync); 946 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 947 struct amdgpu_bo_va *bo_va, 948 struct ttm_mem_reg *mem); 949 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 950 struct amdgpu_bo *bo); 951 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 952 struct amdgpu_bo *bo); 953 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 954 struct amdgpu_vm *vm, 955 struct amdgpu_bo *bo); 956 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 957 struct amdgpu_bo_va *bo_va, 958 uint64_t addr, uint64_t offset, 959 uint64_t size, uint32_t flags); 960 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 961 struct amdgpu_bo_va *bo_va, 962 uint64_t addr); 963 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 964 struct amdgpu_bo_va *bo_va); 965 966 /* 967 * context related structures 968 */ 969 970 struct amdgpu_ctx_ring { 971 uint64_t sequence; 972 struct fence **fences; 973 struct amd_sched_entity entity; 974 }; 975 976 struct amdgpu_ctx { 977 struct kref refcount; 978 struct amdgpu_device *adev; 979 unsigned reset_counter; 980 spinlock_t ring_lock; 981 struct fence **fences; 982 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 983 }; 984 985 struct amdgpu_ctx_mgr { 986 struct amdgpu_device *adev; 987 struct mutex lock; 988 /* protected by lock */ 989 struct idr ctx_handles; 990 }; 991 992 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 993 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 994 995 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 996 struct fence *fence); 997 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 998 struct amdgpu_ring *ring, uint64_t seq); 999 1000 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1001 struct drm_file *filp); 1002 1003 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1004 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1005 1006 /* 1007 * file private structure 1008 */ 1009 1010 struct amdgpu_fpriv { 1011 struct amdgpu_vm vm; 1012 struct mutex bo_list_lock; 1013 struct idr bo_list_handles; 1014 struct amdgpu_ctx_mgr ctx_mgr; 1015 }; 1016 1017 /* 1018 * residency list 1019 */ 1020 1021 struct amdgpu_bo_list { 1022 struct mutex lock; 1023 struct amdgpu_bo *gds_obj; 1024 struct amdgpu_bo *gws_obj; 1025 struct amdgpu_bo *oa_obj; 1026 unsigned first_userptr; 1027 unsigned num_entries; 1028 struct amdgpu_bo_list_entry *array; 1029 }; 1030 1031 struct amdgpu_bo_list * 1032 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1033 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1034 struct list_head *validated); 1035 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1036 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1037 1038 /* 1039 * GFX stuff 1040 */ 1041 #include "clearstate_defs.h" 1042 1043 struct amdgpu_rlc_funcs { 1044 void (*enter_safe_mode)(struct amdgpu_device *adev); 1045 void (*exit_safe_mode)(struct amdgpu_device *adev); 1046 }; 1047 1048 struct amdgpu_rlc { 1049 /* for power gating */ 1050 struct amdgpu_bo *save_restore_obj; 1051 uint64_t save_restore_gpu_addr; 1052 volatile uint32_t *sr_ptr; 1053 const u32 *reg_list; 1054 u32 reg_list_size; 1055 /* for clear state */ 1056 struct amdgpu_bo *clear_state_obj; 1057 uint64_t clear_state_gpu_addr; 1058 volatile uint32_t *cs_ptr; 1059 const struct cs_section_def *cs_data; 1060 u32 clear_state_size; 1061 /* for cp tables */ 1062 struct amdgpu_bo *cp_table_obj; 1063 uint64_t cp_table_gpu_addr; 1064 volatile uint32_t *cp_table_ptr; 1065 u32 cp_table_size; 1066 1067 /* safe mode for updating CG/PG state */ 1068 bool in_safe_mode; 1069 const struct amdgpu_rlc_funcs *funcs; 1070 1071 /* for firmware data */ 1072 u32 save_and_restore_offset; 1073 u32 clear_state_descriptor_offset; 1074 u32 avail_scratch_ram_locations; 1075 u32 reg_restore_list_size; 1076 u32 reg_list_format_start; 1077 u32 reg_list_format_separate_start; 1078 u32 starting_offsets_start; 1079 u32 reg_list_format_size_bytes; 1080 u32 reg_list_size_bytes; 1081 1082 u32 *register_list_format; 1083 u32 *register_restore; 1084 }; 1085 1086 struct amdgpu_mec { 1087 struct amdgpu_bo *hpd_eop_obj; 1088 u64 hpd_eop_gpu_addr; 1089 u32 num_pipe; 1090 u32 num_mec; 1091 u32 num_queue; 1092 }; 1093 1094 /* 1095 * GPU scratch registers structures, functions & helpers 1096 */ 1097 struct amdgpu_scratch { 1098 unsigned num_reg; 1099 uint32_t reg_base; 1100 bool free[32]; 1101 uint32_t reg[32]; 1102 }; 1103 1104 /* 1105 * GFX configurations 1106 */ 1107 struct amdgpu_gca_config { 1108 unsigned max_shader_engines; 1109 unsigned max_tile_pipes; 1110 unsigned max_cu_per_sh; 1111 unsigned max_sh_per_se; 1112 unsigned max_backends_per_se; 1113 unsigned max_texture_channel_caches; 1114 unsigned max_gprs; 1115 unsigned max_gs_threads; 1116 unsigned max_hw_contexts; 1117 unsigned sc_prim_fifo_size_frontend; 1118 unsigned sc_prim_fifo_size_backend; 1119 unsigned sc_hiz_tile_fifo_size; 1120 unsigned sc_earlyz_tile_fifo_size; 1121 1122 unsigned num_tile_pipes; 1123 unsigned backend_enable_mask; 1124 unsigned mem_max_burst_length_bytes; 1125 unsigned mem_row_size_in_kb; 1126 unsigned shader_engine_tile_size; 1127 unsigned num_gpus; 1128 unsigned multi_gpu_tile_size; 1129 unsigned mc_arb_ramcfg; 1130 unsigned gb_addr_config; 1131 unsigned num_rbs; 1132 1133 uint32_t tile_mode_array[32]; 1134 uint32_t macrotile_mode_array[16]; 1135 }; 1136 1137 struct amdgpu_cu_info { 1138 uint32_t number; /* total active CU number */ 1139 uint32_t ao_cu_mask; 1140 uint32_t bitmap[4][4]; 1141 }; 1142 1143 struct amdgpu_gfx { 1144 struct mutex gpu_clock_mutex; 1145 struct amdgpu_gca_config config; 1146 struct amdgpu_rlc rlc; 1147 struct amdgpu_mec mec; 1148 struct amdgpu_scratch scratch; 1149 const struct firmware *me_fw; /* ME firmware */ 1150 uint32_t me_fw_version; 1151 const struct firmware *pfp_fw; /* PFP firmware */ 1152 uint32_t pfp_fw_version; 1153 const struct firmware *ce_fw; /* CE firmware */ 1154 uint32_t ce_fw_version; 1155 const struct firmware *rlc_fw; /* RLC firmware */ 1156 uint32_t rlc_fw_version; 1157 const struct firmware *mec_fw; /* MEC firmware */ 1158 uint32_t mec_fw_version; 1159 const struct firmware *mec2_fw; /* MEC2 firmware */ 1160 uint32_t mec2_fw_version; 1161 uint32_t me_feature_version; 1162 uint32_t ce_feature_version; 1163 uint32_t pfp_feature_version; 1164 uint32_t rlc_feature_version; 1165 uint32_t mec_feature_version; 1166 uint32_t mec2_feature_version; 1167 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1168 unsigned num_gfx_rings; 1169 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1170 unsigned num_compute_rings; 1171 struct amdgpu_irq_src eop_irq; 1172 struct amdgpu_irq_src priv_reg_irq; 1173 struct amdgpu_irq_src priv_inst_irq; 1174 /* gfx status */ 1175 uint32_t gfx_current_status; 1176 /* ce ram size*/ 1177 unsigned ce_ram_size; 1178 struct amdgpu_cu_info cu_info; 1179 }; 1180 1181 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1182 unsigned size, struct amdgpu_ib *ib); 1183 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1184 struct fence *f); 1185 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1186 struct amdgpu_ib *ib, struct fence *last_vm_update, 1187 struct amdgpu_job *job, struct fence **f); 1188 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1189 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1190 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1191 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1192 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1193 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 1194 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1195 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1196 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1197 uint32_t **data); 1198 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1199 unsigned size, uint32_t *data); 1200 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1201 unsigned ring_size, u32 nop, u32 align_mask, 1202 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1203 enum amdgpu_ring_type ring_type); 1204 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1205 1206 /* 1207 * CS. 1208 */ 1209 struct amdgpu_cs_chunk { 1210 uint32_t chunk_id; 1211 uint32_t length_dw; 1212 void *kdata; 1213 }; 1214 1215 struct amdgpu_cs_parser { 1216 struct amdgpu_device *adev; 1217 struct drm_file *filp; 1218 struct amdgpu_ctx *ctx; 1219 1220 /* chunks */ 1221 unsigned nchunks; 1222 struct amdgpu_cs_chunk *chunks; 1223 1224 /* scheduler job object */ 1225 struct amdgpu_job *job; 1226 1227 /* buffer objects */ 1228 struct ww_acquire_ctx ticket; 1229 struct amdgpu_bo_list *bo_list; 1230 struct amdgpu_bo_list_entry vm_pd; 1231 struct list_head validated; 1232 struct fence *fence; 1233 uint64_t bytes_moved_threshold; 1234 uint64_t bytes_moved; 1235 1236 /* user fence */ 1237 struct amdgpu_bo_list_entry uf_entry; 1238 }; 1239 1240 struct amdgpu_job { 1241 struct amd_sched_job base; 1242 struct amdgpu_device *adev; 1243 struct amdgpu_vm *vm; 1244 struct amdgpu_ring *ring; 1245 struct amdgpu_sync sync; 1246 struct amdgpu_ib *ibs; 1247 struct fence *fence; /* the hw fence */ 1248 uint32_t num_ibs; 1249 void *owner; 1250 uint64_t ctx; 1251 unsigned vm_id; 1252 uint64_t vm_pd_addr; 1253 uint32_t gds_base, gds_size; 1254 uint32_t gws_base, gws_size; 1255 uint32_t oa_base, oa_size; 1256 1257 /* user fence handling */ 1258 struct amdgpu_bo *uf_bo; 1259 uint32_t uf_offset; 1260 uint64_t uf_sequence; 1261 1262 }; 1263 #define to_amdgpu_job(sched_job) \ 1264 container_of((sched_job), struct amdgpu_job, base) 1265 1266 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1267 uint32_t ib_idx, int idx) 1268 { 1269 return p->job->ibs[ib_idx].ptr[idx]; 1270 } 1271 1272 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1273 uint32_t ib_idx, int idx, 1274 uint32_t value) 1275 { 1276 p->job->ibs[ib_idx].ptr[idx] = value; 1277 } 1278 1279 /* 1280 * Writeback 1281 */ 1282 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1283 1284 struct amdgpu_wb { 1285 struct amdgpu_bo *wb_obj; 1286 volatile uint32_t *wb; 1287 uint64_t gpu_addr; 1288 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1289 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1290 }; 1291 1292 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1293 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1294 1295 1296 1297 enum amdgpu_int_thermal_type { 1298 THERMAL_TYPE_NONE, 1299 THERMAL_TYPE_EXTERNAL, 1300 THERMAL_TYPE_EXTERNAL_GPIO, 1301 THERMAL_TYPE_RV6XX, 1302 THERMAL_TYPE_RV770, 1303 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1304 THERMAL_TYPE_EVERGREEN, 1305 THERMAL_TYPE_SUMO, 1306 THERMAL_TYPE_NI, 1307 THERMAL_TYPE_SI, 1308 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1309 THERMAL_TYPE_CI, 1310 THERMAL_TYPE_KV, 1311 }; 1312 1313 enum amdgpu_dpm_auto_throttle_src { 1314 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1315 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1316 }; 1317 1318 enum amdgpu_dpm_event_src { 1319 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1320 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1321 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1322 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1323 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1324 }; 1325 1326 #define AMDGPU_MAX_VCE_LEVELS 6 1327 1328 enum amdgpu_vce_level { 1329 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1330 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1331 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1332 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1333 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1334 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1335 }; 1336 1337 struct amdgpu_ps { 1338 u32 caps; /* vbios flags */ 1339 u32 class; /* vbios flags */ 1340 u32 class2; /* vbios flags */ 1341 /* UVD clocks */ 1342 u32 vclk; 1343 u32 dclk; 1344 /* VCE clocks */ 1345 u32 evclk; 1346 u32 ecclk; 1347 bool vce_active; 1348 enum amdgpu_vce_level vce_level; 1349 /* asic priv */ 1350 void *ps_priv; 1351 }; 1352 1353 struct amdgpu_dpm_thermal { 1354 /* thermal interrupt work */ 1355 struct work_struct work; 1356 /* low temperature threshold */ 1357 int min_temp; 1358 /* high temperature threshold */ 1359 int max_temp; 1360 /* was last interrupt low to high or high to low */ 1361 bool high_to_low; 1362 /* interrupt source */ 1363 struct amdgpu_irq_src irq; 1364 }; 1365 1366 enum amdgpu_clk_action 1367 { 1368 AMDGPU_SCLK_UP = 1, 1369 AMDGPU_SCLK_DOWN 1370 }; 1371 1372 struct amdgpu_blacklist_clocks 1373 { 1374 u32 sclk; 1375 u32 mclk; 1376 enum amdgpu_clk_action action; 1377 }; 1378 1379 struct amdgpu_clock_and_voltage_limits { 1380 u32 sclk; 1381 u32 mclk; 1382 u16 vddc; 1383 u16 vddci; 1384 }; 1385 1386 struct amdgpu_clock_array { 1387 u32 count; 1388 u32 *values; 1389 }; 1390 1391 struct amdgpu_clock_voltage_dependency_entry { 1392 u32 clk; 1393 u16 v; 1394 }; 1395 1396 struct amdgpu_clock_voltage_dependency_table { 1397 u32 count; 1398 struct amdgpu_clock_voltage_dependency_entry *entries; 1399 }; 1400 1401 union amdgpu_cac_leakage_entry { 1402 struct { 1403 u16 vddc; 1404 u32 leakage; 1405 }; 1406 struct { 1407 u16 vddc1; 1408 u16 vddc2; 1409 u16 vddc3; 1410 }; 1411 }; 1412 1413 struct amdgpu_cac_leakage_table { 1414 u32 count; 1415 union amdgpu_cac_leakage_entry *entries; 1416 }; 1417 1418 struct amdgpu_phase_shedding_limits_entry { 1419 u16 voltage; 1420 u32 sclk; 1421 u32 mclk; 1422 }; 1423 1424 struct amdgpu_phase_shedding_limits_table { 1425 u32 count; 1426 struct amdgpu_phase_shedding_limits_entry *entries; 1427 }; 1428 1429 struct amdgpu_uvd_clock_voltage_dependency_entry { 1430 u32 vclk; 1431 u32 dclk; 1432 u16 v; 1433 }; 1434 1435 struct amdgpu_uvd_clock_voltage_dependency_table { 1436 u8 count; 1437 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1438 }; 1439 1440 struct amdgpu_vce_clock_voltage_dependency_entry { 1441 u32 ecclk; 1442 u32 evclk; 1443 u16 v; 1444 }; 1445 1446 struct amdgpu_vce_clock_voltage_dependency_table { 1447 u8 count; 1448 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1449 }; 1450 1451 struct amdgpu_ppm_table { 1452 u8 ppm_design; 1453 u16 cpu_core_number; 1454 u32 platform_tdp; 1455 u32 small_ac_platform_tdp; 1456 u32 platform_tdc; 1457 u32 small_ac_platform_tdc; 1458 u32 apu_tdp; 1459 u32 dgpu_tdp; 1460 u32 dgpu_ulv_power; 1461 u32 tj_max; 1462 }; 1463 1464 struct amdgpu_cac_tdp_table { 1465 u16 tdp; 1466 u16 configurable_tdp; 1467 u16 tdc; 1468 u16 battery_power_limit; 1469 u16 small_power_limit; 1470 u16 low_cac_leakage; 1471 u16 high_cac_leakage; 1472 u16 maximum_power_delivery_limit; 1473 }; 1474 1475 struct amdgpu_dpm_dynamic_state { 1476 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1477 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1478 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1479 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1480 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1481 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1482 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1483 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1484 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1485 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1486 struct amdgpu_clock_array valid_sclk_values; 1487 struct amdgpu_clock_array valid_mclk_values; 1488 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1489 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1490 u32 mclk_sclk_ratio; 1491 u32 sclk_mclk_delta; 1492 u16 vddc_vddci_delta; 1493 u16 min_vddc_for_pcie_gen2; 1494 struct amdgpu_cac_leakage_table cac_leakage_table; 1495 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1496 struct amdgpu_ppm_table *ppm_table; 1497 struct amdgpu_cac_tdp_table *cac_tdp_table; 1498 }; 1499 1500 struct amdgpu_dpm_fan { 1501 u16 t_min; 1502 u16 t_med; 1503 u16 t_high; 1504 u16 pwm_min; 1505 u16 pwm_med; 1506 u16 pwm_high; 1507 u8 t_hyst; 1508 u32 cycle_delay; 1509 u16 t_max; 1510 u8 control_mode; 1511 u16 default_max_fan_pwm; 1512 u16 default_fan_output_sensitivity; 1513 u16 fan_output_sensitivity; 1514 bool ucode_fan_control; 1515 }; 1516 1517 enum amdgpu_pcie_gen { 1518 AMDGPU_PCIE_GEN1 = 0, 1519 AMDGPU_PCIE_GEN2 = 1, 1520 AMDGPU_PCIE_GEN3 = 2, 1521 AMDGPU_PCIE_GEN_INVALID = 0xffff 1522 }; 1523 1524 enum amdgpu_dpm_forced_level { 1525 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1526 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1527 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1528 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1529 }; 1530 1531 struct amdgpu_vce_state { 1532 /* vce clocks */ 1533 u32 evclk; 1534 u32 ecclk; 1535 /* gpu clocks */ 1536 u32 sclk; 1537 u32 mclk; 1538 u8 clk_idx; 1539 u8 pstate; 1540 }; 1541 1542 struct amdgpu_dpm_funcs { 1543 int (*get_temperature)(struct amdgpu_device *adev); 1544 int (*pre_set_power_state)(struct amdgpu_device *adev); 1545 int (*set_power_state)(struct amdgpu_device *adev); 1546 void (*post_set_power_state)(struct amdgpu_device *adev); 1547 void (*display_configuration_changed)(struct amdgpu_device *adev); 1548 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1549 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1550 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1551 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1552 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1553 bool (*vblank_too_short)(struct amdgpu_device *adev); 1554 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1555 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1556 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1557 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1558 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1559 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1560 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1561 }; 1562 1563 struct amdgpu_dpm { 1564 struct amdgpu_ps *ps; 1565 /* number of valid power states */ 1566 int num_ps; 1567 /* current power state that is active */ 1568 struct amdgpu_ps *current_ps; 1569 /* requested power state */ 1570 struct amdgpu_ps *requested_ps; 1571 /* boot up power state */ 1572 struct amdgpu_ps *boot_ps; 1573 /* default uvd power state */ 1574 struct amdgpu_ps *uvd_ps; 1575 /* vce requirements */ 1576 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1577 enum amdgpu_vce_level vce_level; 1578 enum amd_pm_state_type state; 1579 enum amd_pm_state_type user_state; 1580 u32 platform_caps; 1581 u32 voltage_response_time; 1582 u32 backbias_response_time; 1583 void *priv; 1584 u32 new_active_crtcs; 1585 int new_active_crtc_count; 1586 u32 current_active_crtcs; 1587 int current_active_crtc_count; 1588 struct amdgpu_dpm_dynamic_state dyn_state; 1589 struct amdgpu_dpm_fan fan; 1590 u32 tdp_limit; 1591 u32 near_tdp_limit; 1592 u32 near_tdp_limit_adjusted; 1593 u32 sq_ramping_threshold; 1594 u32 cac_leakage; 1595 u16 tdp_od_limit; 1596 u32 tdp_adjustment; 1597 u16 load_line_slope; 1598 bool power_control; 1599 bool ac_power; 1600 /* special states active */ 1601 bool thermal_active; 1602 bool uvd_active; 1603 bool vce_active; 1604 /* thermal handling */ 1605 struct amdgpu_dpm_thermal thermal; 1606 /* forced levels */ 1607 enum amdgpu_dpm_forced_level forced_level; 1608 }; 1609 1610 struct amdgpu_pm { 1611 struct mutex mutex; 1612 u32 current_sclk; 1613 u32 current_mclk; 1614 u32 default_sclk; 1615 u32 default_mclk; 1616 struct amdgpu_i2c_chan *i2c_bus; 1617 /* internal thermal controller on rv6xx+ */ 1618 enum amdgpu_int_thermal_type int_thermal_type; 1619 struct device *int_hwmon_dev; 1620 /* fan control parameters */ 1621 bool no_fan; 1622 u8 fan_pulses_per_revolution; 1623 u8 fan_min_rpm; 1624 u8 fan_max_rpm; 1625 /* dpm */ 1626 bool dpm_enabled; 1627 bool sysfs_initialized; 1628 struct amdgpu_dpm dpm; 1629 const struct firmware *fw; /* SMC firmware */ 1630 uint32_t fw_version; 1631 const struct amdgpu_dpm_funcs *funcs; 1632 uint32_t pcie_gen_mask; 1633 uint32_t pcie_mlw_mask; 1634 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1635 }; 1636 1637 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1638 1639 /* 1640 * UVD 1641 */ 1642 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1643 #define AMDGPU_MAX_UVD_HANDLES 40 1644 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1645 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1646 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1647 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1648 1649 struct amdgpu_uvd { 1650 struct amdgpu_bo *vcpu_bo; 1651 void *cpu_addr; 1652 uint64_t gpu_addr; 1653 unsigned fw_version; 1654 void *saved_bo; 1655 unsigned max_handles; 1656 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1657 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1658 struct delayed_work idle_work; 1659 const struct firmware *fw; /* UVD firmware */ 1660 struct amdgpu_ring ring; 1661 struct amdgpu_irq_src irq; 1662 bool address_64_bit; 1663 struct amd_sched_entity entity; 1664 }; 1665 1666 /* 1667 * VCE 1668 */ 1669 #define AMDGPU_MAX_VCE_HANDLES 16 1670 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1671 1672 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1673 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1674 1675 struct amdgpu_vce { 1676 struct amdgpu_bo *vcpu_bo; 1677 uint64_t gpu_addr; 1678 unsigned fw_version; 1679 unsigned fb_version; 1680 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1681 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1682 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1683 struct delayed_work idle_work; 1684 const struct firmware *fw; /* VCE firmware */ 1685 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1686 struct amdgpu_irq_src irq; 1687 unsigned harvest_config; 1688 struct amd_sched_entity entity; 1689 }; 1690 1691 /* 1692 * SDMA 1693 */ 1694 struct amdgpu_sdma_instance { 1695 /* SDMA firmware */ 1696 const struct firmware *fw; 1697 uint32_t fw_version; 1698 uint32_t feature_version; 1699 1700 struct amdgpu_ring ring; 1701 bool burst_nop; 1702 }; 1703 1704 struct amdgpu_sdma { 1705 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1706 struct amdgpu_irq_src trap_irq; 1707 struct amdgpu_irq_src illegal_inst_irq; 1708 int num_instances; 1709 }; 1710 1711 /* 1712 * Firmware 1713 */ 1714 struct amdgpu_firmware { 1715 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1716 bool smu_load; 1717 struct amdgpu_bo *fw_buf; 1718 unsigned int fw_size; 1719 }; 1720 1721 /* 1722 * Benchmarking 1723 */ 1724 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1725 1726 1727 /* 1728 * Testing 1729 */ 1730 void amdgpu_test_moves(struct amdgpu_device *adev); 1731 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1732 struct amdgpu_ring *cpA, 1733 struct amdgpu_ring *cpB); 1734 void amdgpu_test_syncing(struct amdgpu_device *adev); 1735 1736 /* 1737 * MMU Notifier 1738 */ 1739 #if defined(CONFIG_MMU_NOTIFIER) 1740 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1741 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1742 #else 1743 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1744 { 1745 return -ENODEV; 1746 } 1747 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1748 #endif 1749 1750 /* 1751 * Debugfs 1752 */ 1753 struct amdgpu_debugfs { 1754 const struct drm_info_list *files; 1755 unsigned num_files; 1756 }; 1757 1758 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1759 const struct drm_info_list *files, 1760 unsigned nfiles); 1761 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1762 1763 #if defined(CONFIG_DEBUG_FS) 1764 int amdgpu_debugfs_init(struct drm_minor *minor); 1765 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1766 #endif 1767 1768 /* 1769 * amdgpu smumgr functions 1770 */ 1771 struct amdgpu_smumgr_funcs { 1772 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1773 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1774 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1775 }; 1776 1777 /* 1778 * amdgpu smumgr 1779 */ 1780 struct amdgpu_smumgr { 1781 struct amdgpu_bo *toc_buf; 1782 struct amdgpu_bo *smu_buf; 1783 /* asic priv smu data */ 1784 void *priv; 1785 spinlock_t smu_lock; 1786 /* smumgr functions */ 1787 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1788 /* ucode loading complete flag */ 1789 uint32_t fw_flags; 1790 }; 1791 1792 /* 1793 * ASIC specific register table accessible by UMD 1794 */ 1795 struct amdgpu_allowed_register_entry { 1796 uint32_t reg_offset; 1797 bool untouched; 1798 bool grbm_indexed; 1799 }; 1800 1801 /* 1802 * ASIC specific functions. 1803 */ 1804 struct amdgpu_asic_funcs { 1805 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1806 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1807 u8 *bios, u32 length_bytes); 1808 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1809 u32 sh_num, u32 reg_offset, u32 *value); 1810 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1811 int (*reset)(struct amdgpu_device *adev); 1812 /* wait for mc_idle */ 1813 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1814 /* get the reference clock */ 1815 u32 (*get_xclk)(struct amdgpu_device *adev); 1816 /* get the gpu clock counter */ 1817 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1818 /* MM block clocks */ 1819 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1820 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1821 }; 1822 1823 /* 1824 * IOCTL. 1825 */ 1826 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1827 struct drm_file *filp); 1828 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1829 struct drm_file *filp); 1830 1831 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1832 struct drm_file *filp); 1833 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1834 struct drm_file *filp); 1835 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1836 struct drm_file *filp); 1837 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1838 struct drm_file *filp); 1839 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1840 struct drm_file *filp); 1841 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1842 struct drm_file *filp); 1843 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1844 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1845 1846 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1847 struct drm_file *filp); 1848 1849 /* VRAM scratch page for HDP bug, default vram page */ 1850 struct amdgpu_vram_scratch { 1851 struct amdgpu_bo *robj; 1852 volatile uint32_t *ptr; 1853 u64 gpu_addr; 1854 }; 1855 1856 /* 1857 * ACPI 1858 */ 1859 struct amdgpu_atif_notification_cfg { 1860 bool enabled; 1861 int command_code; 1862 }; 1863 1864 struct amdgpu_atif_notifications { 1865 bool display_switch; 1866 bool expansion_mode_change; 1867 bool thermal_state; 1868 bool forced_power_state; 1869 bool system_power_state; 1870 bool display_conf_change; 1871 bool px_gfx_switch; 1872 bool brightness_change; 1873 bool dgpu_display_event; 1874 }; 1875 1876 struct amdgpu_atif_functions { 1877 bool system_params; 1878 bool sbios_requests; 1879 bool select_active_disp; 1880 bool lid_state; 1881 bool get_tv_standard; 1882 bool set_tv_standard; 1883 bool get_panel_expansion_mode; 1884 bool set_panel_expansion_mode; 1885 bool temperature_change; 1886 bool graphics_device_types; 1887 }; 1888 1889 struct amdgpu_atif { 1890 struct amdgpu_atif_notifications notifications; 1891 struct amdgpu_atif_functions functions; 1892 struct amdgpu_atif_notification_cfg notification_cfg; 1893 struct amdgpu_encoder *encoder_for_bl; 1894 }; 1895 1896 struct amdgpu_atcs_functions { 1897 bool get_ext_state; 1898 bool pcie_perf_req; 1899 bool pcie_dev_rdy; 1900 bool pcie_bus_width; 1901 }; 1902 1903 struct amdgpu_atcs { 1904 struct amdgpu_atcs_functions functions; 1905 }; 1906 1907 /* 1908 * CGS 1909 */ 1910 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1911 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1912 1913 1914 /* GPU virtualization */ 1915 struct amdgpu_virtualization { 1916 bool supports_sr_iov; 1917 }; 1918 1919 /* 1920 * Core structure, functions and helpers. 1921 */ 1922 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1923 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1924 1925 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1926 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1927 1928 struct amdgpu_ip_block_status { 1929 bool valid; 1930 bool sw; 1931 bool hw; 1932 }; 1933 1934 struct amdgpu_device { 1935 struct device *dev; 1936 struct drm_device *ddev; 1937 struct pci_dev *pdev; 1938 1939 #ifdef CONFIG_DRM_AMD_ACP 1940 struct amdgpu_acp acp; 1941 #endif 1942 1943 /* ASIC */ 1944 enum amd_asic_type asic_type; 1945 uint32_t family; 1946 uint32_t rev_id; 1947 uint32_t external_rev_id; 1948 unsigned long flags; 1949 int usec_timeout; 1950 const struct amdgpu_asic_funcs *asic_funcs; 1951 bool shutdown; 1952 bool need_dma32; 1953 bool accel_working; 1954 struct work_struct reset_work; 1955 struct notifier_block acpi_nb; 1956 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1957 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1958 unsigned debugfs_count; 1959 #if defined(CONFIG_DEBUG_FS) 1960 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1961 #endif 1962 struct amdgpu_atif atif; 1963 struct amdgpu_atcs atcs; 1964 struct mutex srbm_mutex; 1965 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1966 struct mutex grbm_idx_mutex; 1967 struct dev_pm_domain vga_pm_domain; 1968 bool have_disp_power_ref; 1969 1970 /* BIOS */ 1971 uint8_t *bios; 1972 bool is_atom_bios; 1973 struct amdgpu_bo *stollen_vga_memory; 1974 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1975 1976 /* Register/doorbell mmio */ 1977 resource_size_t rmmio_base; 1978 resource_size_t rmmio_size; 1979 void __iomem *rmmio; 1980 /* protects concurrent MM_INDEX/DATA based register access */ 1981 spinlock_t mmio_idx_lock; 1982 /* protects concurrent SMC based register access */ 1983 spinlock_t smc_idx_lock; 1984 amdgpu_rreg_t smc_rreg; 1985 amdgpu_wreg_t smc_wreg; 1986 /* protects concurrent PCIE register access */ 1987 spinlock_t pcie_idx_lock; 1988 amdgpu_rreg_t pcie_rreg; 1989 amdgpu_wreg_t pcie_wreg; 1990 /* protects concurrent UVD register access */ 1991 spinlock_t uvd_ctx_idx_lock; 1992 amdgpu_rreg_t uvd_ctx_rreg; 1993 amdgpu_wreg_t uvd_ctx_wreg; 1994 /* protects concurrent DIDT register access */ 1995 spinlock_t didt_idx_lock; 1996 amdgpu_rreg_t didt_rreg; 1997 amdgpu_wreg_t didt_wreg; 1998 /* protects concurrent ENDPOINT (audio) register access */ 1999 spinlock_t audio_endpt_idx_lock; 2000 amdgpu_block_rreg_t audio_endpt_rreg; 2001 amdgpu_block_wreg_t audio_endpt_wreg; 2002 void __iomem *rio_mem; 2003 resource_size_t rio_mem_size; 2004 struct amdgpu_doorbell doorbell; 2005 2006 /* clock/pll info */ 2007 struct amdgpu_clock clock; 2008 2009 /* MC */ 2010 struct amdgpu_mc mc; 2011 struct amdgpu_gart gart; 2012 struct amdgpu_dummy_page dummy_page; 2013 struct amdgpu_vm_manager vm_manager; 2014 2015 /* memory management */ 2016 struct amdgpu_mman mman; 2017 struct amdgpu_vram_scratch vram_scratch; 2018 struct amdgpu_wb wb; 2019 atomic64_t vram_usage; 2020 atomic64_t vram_vis_usage; 2021 atomic64_t gtt_usage; 2022 atomic64_t num_bytes_moved; 2023 atomic_t gpu_reset_counter; 2024 2025 /* display */ 2026 struct amdgpu_mode_info mode_info; 2027 struct work_struct hotplug_work; 2028 struct amdgpu_irq_src crtc_irq; 2029 struct amdgpu_irq_src pageflip_irq; 2030 struct amdgpu_irq_src hpd_irq; 2031 2032 /* rings */ 2033 unsigned fence_context; 2034 unsigned num_rings; 2035 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2036 bool ib_pool_ready; 2037 struct amdgpu_sa_manager ring_tmp_bo; 2038 2039 /* interrupts */ 2040 struct amdgpu_irq irq; 2041 2042 /* powerplay */ 2043 struct amd_powerplay powerplay; 2044 bool pp_enabled; 2045 bool pp_force_state_enabled; 2046 2047 /* dpm */ 2048 struct amdgpu_pm pm; 2049 u32 cg_flags; 2050 u32 pg_flags; 2051 2052 /* amdgpu smumgr */ 2053 struct amdgpu_smumgr smu; 2054 2055 /* gfx */ 2056 struct amdgpu_gfx gfx; 2057 2058 /* sdma */ 2059 struct amdgpu_sdma sdma; 2060 2061 /* uvd */ 2062 struct amdgpu_uvd uvd; 2063 2064 /* vce */ 2065 struct amdgpu_vce vce; 2066 2067 /* firmwares */ 2068 struct amdgpu_firmware firmware; 2069 2070 /* GDS */ 2071 struct amdgpu_gds gds; 2072 2073 const struct amdgpu_ip_block_version *ip_blocks; 2074 int num_ip_blocks; 2075 struct amdgpu_ip_block_status *ip_block_status; 2076 struct mutex mn_lock; 2077 DECLARE_HASHTABLE(mn_hash, 7); 2078 2079 /* tracking pinned memory */ 2080 u64 vram_pin_size; 2081 u64 invisible_pin_size; 2082 u64 gart_pin_size; 2083 2084 /* amdkfd interface */ 2085 struct kfd_dev *kfd; 2086 2087 struct amdgpu_virtualization virtualization; 2088 }; 2089 2090 bool amdgpu_device_is_px(struct drm_device *dev); 2091 int amdgpu_device_init(struct amdgpu_device *adev, 2092 struct drm_device *ddev, 2093 struct pci_dev *pdev, 2094 uint32_t flags); 2095 void amdgpu_device_fini(struct amdgpu_device *adev); 2096 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2097 2098 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2099 bool always_indirect); 2100 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2101 bool always_indirect); 2102 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2103 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2104 2105 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2106 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2107 2108 /* 2109 * Registers read & write functions. 2110 */ 2111 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2112 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2113 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2114 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2115 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2116 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2117 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2118 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2119 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2120 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2121 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2122 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2123 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2124 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2125 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2126 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2127 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2128 #define WREG32_P(reg, val, mask) \ 2129 do { \ 2130 uint32_t tmp_ = RREG32(reg); \ 2131 tmp_ &= (mask); \ 2132 tmp_ |= ((val) & ~(mask)); \ 2133 WREG32(reg, tmp_); \ 2134 } while (0) 2135 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2136 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2137 #define WREG32_PLL_P(reg, val, mask) \ 2138 do { \ 2139 uint32_t tmp_ = RREG32_PLL(reg); \ 2140 tmp_ &= (mask); \ 2141 tmp_ |= ((val) & ~(mask)); \ 2142 WREG32_PLL(reg, tmp_); \ 2143 } while (0) 2144 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2145 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2146 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2147 2148 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2149 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2150 2151 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2152 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2153 2154 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2155 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2156 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2157 2158 #define REG_GET_FIELD(value, reg, field) \ 2159 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2160 2161 /* 2162 * BIOS helpers. 2163 */ 2164 #define RBIOS8(i) (adev->bios[i]) 2165 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2166 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2167 2168 /* 2169 * RING helpers. 2170 */ 2171 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2172 { 2173 if (ring->count_dw <= 0) 2174 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2175 ring->ring[ring->wptr++] = v; 2176 ring->wptr &= ring->ptr_mask; 2177 ring->count_dw--; 2178 } 2179 2180 static inline struct amdgpu_sdma_instance * 2181 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2182 { 2183 struct amdgpu_device *adev = ring->adev; 2184 int i; 2185 2186 for (i = 0; i < adev->sdma.num_instances; i++) 2187 if (&adev->sdma.instance[i].ring == ring) 2188 break; 2189 2190 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2191 return &adev->sdma.instance[i]; 2192 else 2193 return NULL; 2194 } 2195 2196 /* 2197 * ASICs macro. 2198 */ 2199 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2200 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2201 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2202 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2203 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2204 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2205 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2206 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2207 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2208 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2209 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2210 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2211 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2212 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2213 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2214 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2215 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2216 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2217 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2218 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2219 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2220 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 2221 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 2222 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2223 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2224 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2225 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2226 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 2227 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 2228 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 2229 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 2230 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2231 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2232 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2233 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2234 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2235 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2236 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2237 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2238 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2239 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2240 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2241 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2242 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2243 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 2244 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2245 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2246 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2247 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2248 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2249 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2250 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2251 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2252 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2253 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2254 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2255 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2256 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2257 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2258 2259 #define amdgpu_dpm_get_temperature(adev) \ 2260 ((adev)->pp_enabled ? \ 2261 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2262 (adev)->pm.funcs->get_temperature((adev))) 2263 2264 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2265 ((adev)->pp_enabled ? \ 2266 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2267 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2268 2269 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2270 ((adev)->pp_enabled ? \ 2271 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2272 (adev)->pm.funcs->get_fan_control_mode((adev))) 2273 2274 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2275 ((adev)->pp_enabled ? \ 2276 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2277 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2278 2279 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2280 ((adev)->pp_enabled ? \ 2281 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2282 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2283 2284 #define amdgpu_dpm_get_sclk(adev, l) \ 2285 ((adev)->pp_enabled ? \ 2286 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2287 (adev)->pm.funcs->get_sclk((adev), (l))) 2288 2289 #define amdgpu_dpm_get_mclk(adev, l) \ 2290 ((adev)->pp_enabled ? \ 2291 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2292 (adev)->pm.funcs->get_mclk((adev), (l))) 2293 2294 2295 #define amdgpu_dpm_force_performance_level(adev, l) \ 2296 ((adev)->pp_enabled ? \ 2297 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2298 (adev)->pm.funcs->force_performance_level((adev), (l))) 2299 2300 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2301 ((adev)->pp_enabled ? \ 2302 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2303 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2304 2305 #define amdgpu_dpm_powergate_vce(adev, g) \ 2306 ((adev)->pp_enabled ? \ 2307 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2308 (adev)->pm.funcs->powergate_vce((adev), (g))) 2309 2310 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2311 ((adev)->pp_enabled ? \ 2312 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2313 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2314 2315 #define amdgpu_dpm_get_current_power_state(adev) \ 2316 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2317 2318 #define amdgpu_dpm_get_performance_level(adev) \ 2319 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2320 2321 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2322 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2323 2324 #define amdgpu_dpm_get_pp_table(adev, table) \ 2325 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2326 2327 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2328 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2329 2330 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2331 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2332 2333 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2334 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2335 2336 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2337 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2338 2339 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2340 2341 /* Common functions */ 2342 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2343 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2344 bool amdgpu_card_posted(struct amdgpu_device *adev); 2345 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2346 2347 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2348 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2349 u32 ip_instance, u32 ring, 2350 struct amdgpu_ring **out_ring); 2351 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2352 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2353 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 2354 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2355 uint32_t flags); 2356 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2357 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2358 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2359 unsigned long end); 2360 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 2361 int *last_invalidated); 2362 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2363 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2364 struct ttm_mem_reg *mem); 2365 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2366 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2367 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2368 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2369 const u32 *registers, 2370 const u32 array_size); 2371 2372 bool amdgpu_device_is_px(struct drm_device *dev); 2373 /* atpx handler */ 2374 #if defined(CONFIG_VGA_SWITCHEROO) 2375 void amdgpu_register_atpx_handler(void); 2376 void amdgpu_unregister_atpx_handler(void); 2377 #else 2378 static inline void amdgpu_register_atpx_handler(void) {} 2379 static inline void amdgpu_unregister_atpx_handler(void) {} 2380 #endif 2381 2382 /* 2383 * KMS 2384 */ 2385 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2386 extern const int amdgpu_max_kms_ioctl; 2387 2388 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2389 int amdgpu_driver_unload_kms(struct drm_device *dev); 2390 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2391 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2392 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2393 struct drm_file *file_priv); 2394 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2395 struct drm_file *file_priv); 2396 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2397 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2398 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2399 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2400 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2401 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2402 int *max_error, 2403 struct timeval *vblank_time, 2404 unsigned flags); 2405 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2406 unsigned long arg); 2407 2408 /* 2409 * functions used by amdgpu_encoder.c 2410 */ 2411 struct amdgpu_afmt_acr { 2412 u32 clock; 2413 2414 int n_32khz; 2415 int cts_32khz; 2416 2417 int n_44_1khz; 2418 int cts_44_1khz; 2419 2420 int n_48khz; 2421 int cts_48khz; 2422 2423 }; 2424 2425 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2426 2427 /* amdgpu_acpi.c */ 2428 #if defined(CONFIG_ACPI) 2429 int amdgpu_acpi_init(struct amdgpu_device *adev); 2430 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2431 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2432 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2433 u8 perf_req, bool advertise); 2434 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2435 #else 2436 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2437 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2438 #endif 2439 2440 struct amdgpu_bo_va_mapping * 2441 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2442 uint64_t addr, struct amdgpu_bo **bo); 2443 2444 #include "amdgpu_object.h" 2445 #endif 2446