1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 extern unsigned amdgpu_pcie_gen_cap; 89 extern unsigned amdgpu_pcie_lane_cap; 90 91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 95 #define AMDGPU_IB_POOL_SIZE 16 96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 97 #define AMDGPUFB_CONN_LIMIT 4 98 #define AMDGPU_BIOS_NUM_SCRATCH 8 99 100 /* max number of rings */ 101 #define AMDGPU_MAX_RINGS 16 102 #define AMDGPU_MAX_GFX_RINGS 1 103 #define AMDGPU_MAX_COMPUTE_RINGS 8 104 #define AMDGPU_MAX_VCE_RINGS 2 105 106 /* max number of IP instances */ 107 #define AMDGPU_MAX_SDMA_INSTANCES 2 108 109 /* hardcode that limit for now */ 110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 111 112 /* hard reset data */ 113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 114 115 /* reset flags */ 116 #define AMDGPU_RESET_GFX (1 << 0) 117 #define AMDGPU_RESET_COMPUTE (1 << 1) 118 #define AMDGPU_RESET_DMA (1 << 2) 119 #define AMDGPU_RESET_CP (1 << 3) 120 #define AMDGPU_RESET_GRBM (1 << 4) 121 #define AMDGPU_RESET_DMA1 (1 << 5) 122 #define AMDGPU_RESET_RLC (1 << 6) 123 #define AMDGPU_RESET_SEM (1 << 7) 124 #define AMDGPU_RESET_IH (1 << 8) 125 #define AMDGPU_RESET_VMC (1 << 9) 126 #define AMDGPU_RESET_MC (1 << 10) 127 #define AMDGPU_RESET_DISPLAY (1 << 11) 128 #define AMDGPU_RESET_UVD (1 << 12) 129 #define AMDGPU_RESET_VCE (1 << 13) 130 #define AMDGPU_RESET_VCE1 (1 << 14) 131 132 /* GFX current status */ 133 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 134 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 135 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 136 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 137 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 138 139 /* max cursor sizes (in pixels) */ 140 #define CIK_CURSOR_WIDTH 128 141 #define CIK_CURSOR_HEIGHT 128 142 143 struct amdgpu_device; 144 struct amdgpu_ib; 145 struct amdgpu_vm; 146 struct amdgpu_ring; 147 struct amdgpu_cs_parser; 148 struct amdgpu_job; 149 struct amdgpu_irq_src; 150 struct amdgpu_fpriv; 151 152 enum amdgpu_cp_irq { 153 AMDGPU_CP_IRQ_GFX_EOP = 0, 154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 162 163 AMDGPU_CP_IRQ_LAST 164 }; 165 166 enum amdgpu_sdma_irq { 167 AMDGPU_SDMA_IRQ_TRAP0 = 0, 168 AMDGPU_SDMA_IRQ_TRAP1, 169 170 AMDGPU_SDMA_IRQ_LAST 171 }; 172 173 enum amdgpu_thermal_irq { 174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 176 177 AMDGPU_THERMAL_IRQ_LAST 178 }; 179 180 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 181 enum amd_ip_block_type block_type, 182 enum amd_clockgating_state state); 183 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 184 enum amd_ip_block_type block_type, 185 enum amd_powergating_state state); 186 187 struct amdgpu_ip_block_version { 188 enum amd_ip_block_type type; 189 u32 major; 190 u32 minor; 191 u32 rev; 192 const struct amd_ip_funcs *funcs; 193 }; 194 195 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 196 enum amd_ip_block_type type, 197 u32 major, u32 minor); 198 199 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 200 struct amdgpu_device *adev, 201 enum amd_ip_block_type type); 202 203 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 204 struct amdgpu_buffer_funcs { 205 /* maximum bytes in a single operation */ 206 uint32_t copy_max_bytes; 207 208 /* number of dw to reserve per operation */ 209 unsigned copy_num_dw; 210 211 /* used for buffer migration */ 212 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 213 /* src addr in bytes */ 214 uint64_t src_offset, 215 /* dst addr in bytes */ 216 uint64_t dst_offset, 217 /* number of byte to transfer */ 218 uint32_t byte_count); 219 220 /* maximum bytes in a single operation */ 221 uint32_t fill_max_bytes; 222 223 /* number of dw to reserve per operation */ 224 unsigned fill_num_dw; 225 226 /* used for buffer clearing */ 227 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 228 /* value to write to memory */ 229 uint32_t src_data, 230 /* dst addr in bytes */ 231 uint64_t dst_offset, 232 /* number of byte to fill */ 233 uint32_t byte_count); 234 }; 235 236 /* provided by hw blocks that can write ptes, e.g., sdma */ 237 struct amdgpu_vm_pte_funcs { 238 /* copy pte entries from GART */ 239 void (*copy_pte)(struct amdgpu_ib *ib, 240 uint64_t pe, uint64_t src, 241 unsigned count); 242 /* write pte one entry at a time with addr mapping */ 243 void (*write_pte)(struct amdgpu_ib *ib, 244 const dma_addr_t *pages_addr, uint64_t pe, 245 uint64_t addr, unsigned count, 246 uint32_t incr, uint32_t flags); 247 /* for linear pte/pde updates without addr mapping */ 248 void (*set_pte_pde)(struct amdgpu_ib *ib, 249 uint64_t pe, 250 uint64_t addr, unsigned count, 251 uint32_t incr, uint32_t flags); 252 }; 253 254 /* provided by the gmc block */ 255 struct amdgpu_gart_funcs { 256 /* flush the vm tlb via mmio */ 257 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 258 uint32_t vmid); 259 /* write pte/pde updates using the cpu */ 260 int (*set_pte_pde)(struct amdgpu_device *adev, 261 void *cpu_pt_addr, /* cpu addr of page table */ 262 uint32_t gpu_page_idx, /* pte/pde to update */ 263 uint64_t addr, /* addr to write into pte/pde */ 264 uint32_t flags); /* access flags */ 265 }; 266 267 /* provided by the ih block */ 268 struct amdgpu_ih_funcs { 269 /* ring read/write ptr handling, called from interrupt context */ 270 u32 (*get_wptr)(struct amdgpu_device *adev); 271 void (*decode_iv)(struct amdgpu_device *adev, 272 struct amdgpu_iv_entry *entry); 273 void (*set_rptr)(struct amdgpu_device *adev); 274 }; 275 276 /* provided by hw blocks that expose a ring buffer for commands */ 277 struct amdgpu_ring_funcs { 278 /* ring read/write ptr handling */ 279 u32 (*get_rptr)(struct amdgpu_ring *ring); 280 u32 (*get_wptr)(struct amdgpu_ring *ring); 281 void (*set_wptr)(struct amdgpu_ring *ring); 282 /* validating and patching of IBs */ 283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 284 /* command emit functions */ 285 void (*emit_ib)(struct amdgpu_ring *ring, 286 struct amdgpu_ib *ib); 287 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 288 uint64_t seq, unsigned flags); 289 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 291 uint64_t pd_addr); 292 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 293 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 294 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 295 uint32_t gds_base, uint32_t gds_size, 296 uint32_t gws_base, uint32_t gws_size, 297 uint32_t oa_base, uint32_t oa_size); 298 /* testing functions */ 299 int (*test_ring)(struct amdgpu_ring *ring); 300 int (*test_ib)(struct amdgpu_ring *ring); 301 /* insert NOP packets */ 302 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 303 /* pad the indirect buffer to the necessary number of dw */ 304 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 305 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 306 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 307 }; 308 309 /* 310 * BIOS. 311 */ 312 bool amdgpu_get_bios(struct amdgpu_device *adev); 313 bool amdgpu_read_bios(struct amdgpu_device *adev); 314 315 /* 316 * Dummy page 317 */ 318 struct amdgpu_dummy_page { 319 struct page *page; 320 dma_addr_t addr; 321 }; 322 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 323 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 324 325 326 /* 327 * Clocks 328 */ 329 330 #define AMDGPU_MAX_PPLL 3 331 332 struct amdgpu_clock { 333 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 334 struct amdgpu_pll spll; 335 struct amdgpu_pll mpll; 336 /* 10 Khz units */ 337 uint32_t default_mclk; 338 uint32_t default_sclk; 339 uint32_t default_dispclk; 340 uint32_t current_dispclk; 341 uint32_t dp_extclk; 342 uint32_t max_pixel_clock; 343 }; 344 345 /* 346 * Fences. 347 */ 348 struct amdgpu_fence_driver { 349 uint64_t gpu_addr; 350 volatile uint32_t *cpu_addr; 351 /* sync_seq is protected by ring emission lock */ 352 uint32_t sync_seq; 353 atomic_t last_seq; 354 bool initialized; 355 struct amdgpu_irq_src *irq_src; 356 unsigned irq_type; 357 struct timer_list fallback_timer; 358 unsigned num_fences_mask; 359 spinlock_t lock; 360 struct fence **fences; 361 }; 362 363 /* some special values for the owner field */ 364 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 365 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 366 367 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 368 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 369 370 struct amdgpu_user_fence { 371 /* write-back bo */ 372 struct amdgpu_bo *bo; 373 /* write-back address offset to bo start */ 374 uint32_t offset; 375 }; 376 377 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 378 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 379 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 380 381 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 382 unsigned num_hw_submission); 383 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 384 struct amdgpu_irq_src *irq_src, 385 unsigned irq_type); 386 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 387 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 388 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 389 void amdgpu_fence_process(struct amdgpu_ring *ring); 390 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 391 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 392 393 /* 394 * TTM. 395 */ 396 397 #define AMDGPU_TTM_LRU_SIZE 20 398 399 struct amdgpu_mman_lru { 400 struct list_head *lru[TTM_NUM_MEM_TYPES]; 401 struct list_head *swap_lru; 402 }; 403 404 struct amdgpu_mman { 405 struct ttm_bo_global_ref bo_global_ref; 406 struct drm_global_reference mem_global_ref; 407 struct ttm_bo_device bdev; 408 bool mem_global_referenced; 409 bool initialized; 410 411 #if defined(CONFIG_DEBUG_FS) 412 struct dentry *vram; 413 struct dentry *gtt; 414 #endif 415 416 /* buffer handling */ 417 const struct amdgpu_buffer_funcs *buffer_funcs; 418 struct amdgpu_ring *buffer_funcs_ring; 419 /* Scheduler entity for buffer moves */ 420 struct amd_sched_entity entity; 421 422 /* custom LRU management */ 423 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; 424 }; 425 426 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 427 uint64_t src_offset, 428 uint64_t dst_offset, 429 uint32_t byte_count, 430 struct reservation_object *resv, 431 struct fence **fence); 432 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 433 434 struct amdgpu_bo_list_entry { 435 struct amdgpu_bo *robj; 436 struct ttm_validate_buffer tv; 437 struct amdgpu_bo_va *bo_va; 438 uint32_t priority; 439 struct page **user_pages; 440 int user_invalidated; 441 }; 442 443 struct amdgpu_bo_va_mapping { 444 struct list_head list; 445 struct interval_tree_node it; 446 uint64_t offset; 447 uint32_t flags; 448 }; 449 450 /* bo virtual addresses in a specific vm */ 451 struct amdgpu_bo_va { 452 /* protected by bo being reserved */ 453 struct list_head bo_list; 454 struct fence *last_pt_update; 455 unsigned ref_count; 456 457 /* protected by vm mutex and spinlock */ 458 struct list_head vm_status; 459 460 /* mappings for this bo_va */ 461 struct list_head invalids; 462 struct list_head valids; 463 464 /* constant after initialization */ 465 struct amdgpu_vm *vm; 466 struct amdgpu_bo *bo; 467 }; 468 469 #define AMDGPU_GEM_DOMAIN_MAX 0x3 470 471 struct amdgpu_bo { 472 /* Protected by gem.mutex */ 473 struct list_head list; 474 /* Protected by tbo.reserved */ 475 u32 prefered_domains; 476 u32 allowed_domains; 477 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 478 struct ttm_placement placement; 479 struct ttm_buffer_object tbo; 480 struct ttm_bo_kmap_obj kmap; 481 u64 flags; 482 unsigned pin_count; 483 void *kptr; 484 u64 tiling_flags; 485 u64 metadata_flags; 486 void *metadata; 487 u32 metadata_size; 488 /* list of all virtual address to which this bo 489 * is associated to 490 */ 491 struct list_head va; 492 /* Constant after initialization */ 493 struct amdgpu_device *adev; 494 struct drm_gem_object gem_base; 495 struct amdgpu_bo *parent; 496 497 struct ttm_bo_kmap_obj dma_buf_vmap; 498 struct amdgpu_mn *mn; 499 struct list_head mn_list; 500 }; 501 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 502 503 void amdgpu_gem_object_free(struct drm_gem_object *obj); 504 int amdgpu_gem_object_open(struct drm_gem_object *obj, 505 struct drm_file *file_priv); 506 void amdgpu_gem_object_close(struct drm_gem_object *obj, 507 struct drm_file *file_priv); 508 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 509 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 510 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 511 struct dma_buf_attachment *attach, 512 struct sg_table *sg); 513 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 514 struct drm_gem_object *gobj, 515 int flags); 516 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 517 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 518 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 519 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 520 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 521 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 522 523 /* sub-allocation manager, it has to be protected by another lock. 524 * By conception this is an helper for other part of the driver 525 * like the indirect buffer or semaphore, which both have their 526 * locking. 527 * 528 * Principe is simple, we keep a list of sub allocation in offset 529 * order (first entry has offset == 0, last entry has the highest 530 * offset). 531 * 532 * When allocating new object we first check if there is room at 533 * the end total_size - (last_object_offset + last_object_size) >= 534 * alloc_size. If so we allocate new object there. 535 * 536 * When there is not enough room at the end, we start waiting for 537 * each sub object until we reach object_offset+object_size >= 538 * alloc_size, this object then become the sub object we return. 539 * 540 * Alignment can't be bigger than page size. 541 * 542 * Hole are not considered for allocation to keep things simple. 543 * Assumption is that there won't be hole (all object on same 544 * alignment). 545 */ 546 547 #define AMDGPU_SA_NUM_FENCE_LISTS 32 548 549 struct amdgpu_sa_manager { 550 wait_queue_head_t wq; 551 struct amdgpu_bo *bo; 552 struct list_head *hole; 553 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 554 struct list_head olist; 555 unsigned size; 556 uint64_t gpu_addr; 557 void *cpu_ptr; 558 uint32_t domain; 559 uint32_t align; 560 }; 561 562 /* sub-allocation buffer */ 563 struct amdgpu_sa_bo { 564 struct list_head olist; 565 struct list_head flist; 566 struct amdgpu_sa_manager *manager; 567 unsigned soffset; 568 unsigned eoffset; 569 struct fence *fence; 570 }; 571 572 /* 573 * GEM objects. 574 */ 575 void amdgpu_gem_force_release(struct amdgpu_device *adev); 576 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 577 int alignment, u32 initial_domain, 578 u64 flags, bool kernel, 579 struct drm_gem_object **obj); 580 581 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 582 struct drm_device *dev, 583 struct drm_mode_create_dumb *args); 584 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 585 struct drm_device *dev, 586 uint32_t handle, uint64_t *offset_p); 587 /* 588 * Synchronization 589 */ 590 struct amdgpu_sync { 591 DECLARE_HASHTABLE(fences, 4); 592 struct fence *last_vm_update; 593 }; 594 595 void amdgpu_sync_create(struct amdgpu_sync *sync); 596 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 597 struct fence *f); 598 int amdgpu_sync_resv(struct amdgpu_device *adev, 599 struct amdgpu_sync *sync, 600 struct reservation_object *resv, 601 void *owner); 602 bool amdgpu_sync_is_idle(struct amdgpu_sync *sync); 603 int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, 604 struct fence *fence); 605 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 606 int amdgpu_sync_wait(struct amdgpu_sync *sync); 607 void amdgpu_sync_free(struct amdgpu_sync *sync); 608 int amdgpu_sync_init(void); 609 void amdgpu_sync_fini(void); 610 611 /* 612 * GART structures, functions & helpers 613 */ 614 struct amdgpu_mc; 615 616 #define AMDGPU_GPU_PAGE_SIZE 4096 617 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 618 #define AMDGPU_GPU_PAGE_SHIFT 12 619 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 620 621 struct amdgpu_gart { 622 dma_addr_t table_addr; 623 struct amdgpu_bo *robj; 624 void *ptr; 625 unsigned num_gpu_pages; 626 unsigned num_cpu_pages; 627 unsigned table_size; 628 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 629 struct page **pages; 630 #endif 631 bool ready; 632 const struct amdgpu_gart_funcs *gart_funcs; 633 }; 634 635 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 636 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 637 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 638 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 639 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 640 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 641 int amdgpu_gart_init(struct amdgpu_device *adev); 642 void amdgpu_gart_fini(struct amdgpu_device *adev); 643 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 644 int pages); 645 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 646 int pages, struct page **pagelist, 647 dma_addr_t *dma_addr, uint32_t flags); 648 649 /* 650 * GPU MC structures, functions & helpers 651 */ 652 struct amdgpu_mc { 653 resource_size_t aper_size; 654 resource_size_t aper_base; 655 resource_size_t agp_base; 656 /* for some chips with <= 32MB we need to lie 657 * about vram size near mc fb location */ 658 u64 mc_vram_size; 659 u64 visible_vram_size; 660 u64 gtt_size; 661 u64 gtt_start; 662 u64 gtt_end; 663 u64 vram_start; 664 u64 vram_end; 665 unsigned vram_width; 666 u64 real_vram_size; 667 int vram_mtrr; 668 u64 gtt_base_align; 669 u64 mc_mask; 670 const struct firmware *fw; /* MC firmware */ 671 uint32_t fw_version; 672 struct amdgpu_irq_src vm_fault; 673 uint32_t vram_type; 674 }; 675 676 /* 677 * GPU doorbell structures, functions & helpers 678 */ 679 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 680 { 681 AMDGPU_DOORBELL_KIQ = 0x000, 682 AMDGPU_DOORBELL_HIQ = 0x001, 683 AMDGPU_DOORBELL_DIQ = 0x002, 684 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 685 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 686 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 687 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 688 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 689 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 690 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 691 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 692 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 693 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 694 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 695 AMDGPU_DOORBELL_IH = 0x1E8, 696 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 697 AMDGPU_DOORBELL_INVALID = 0xFFFF 698 } AMDGPU_DOORBELL_ASSIGNMENT; 699 700 struct amdgpu_doorbell { 701 /* doorbell mmio */ 702 resource_size_t base; 703 resource_size_t size; 704 u32 __iomem *ptr; 705 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 706 }; 707 708 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 709 phys_addr_t *aperture_base, 710 size_t *aperture_size, 711 size_t *start_offset); 712 713 /* 714 * IRQS. 715 */ 716 717 struct amdgpu_flip_work { 718 struct work_struct flip_work; 719 struct work_struct unpin_work; 720 struct amdgpu_device *adev; 721 int crtc_id; 722 uint64_t base; 723 struct drm_pending_vblank_event *event; 724 struct amdgpu_bo *old_rbo; 725 struct fence *excl; 726 unsigned shared_count; 727 struct fence **shared; 728 struct fence_cb cb; 729 }; 730 731 732 /* 733 * CP & rings. 734 */ 735 736 struct amdgpu_ib { 737 struct amdgpu_sa_bo *sa_bo; 738 uint32_t length_dw; 739 uint64_t gpu_addr; 740 uint32_t *ptr; 741 struct amdgpu_user_fence *user; 742 struct amdgpu_vm *vm; 743 unsigned vm_id; 744 uint64_t vm_pd_addr; 745 struct amdgpu_ctx *ctx; 746 uint32_t gds_base, gds_size; 747 uint32_t gws_base, gws_size; 748 uint32_t oa_base, oa_size; 749 uint32_t flags; 750 /* resulting sequence number */ 751 uint64_t sequence; 752 }; 753 754 enum amdgpu_ring_type { 755 AMDGPU_RING_TYPE_GFX, 756 AMDGPU_RING_TYPE_COMPUTE, 757 AMDGPU_RING_TYPE_SDMA, 758 AMDGPU_RING_TYPE_UVD, 759 AMDGPU_RING_TYPE_VCE 760 }; 761 762 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 763 764 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 765 struct amdgpu_job **job); 766 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 767 struct amdgpu_job **job); 768 769 void amdgpu_job_free(struct amdgpu_job *job); 770 void amdgpu_job_free_func(struct kref *refcount); 771 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 772 struct amd_sched_entity *entity, void *owner, 773 struct fence **f); 774 void amdgpu_job_timeout_func(struct work_struct *work); 775 776 struct amdgpu_ring { 777 struct amdgpu_device *adev; 778 const struct amdgpu_ring_funcs *funcs; 779 struct amdgpu_fence_driver fence_drv; 780 struct amd_gpu_scheduler sched; 781 782 spinlock_t fence_lock; 783 struct amdgpu_bo *ring_obj; 784 volatile uint32_t *ring; 785 unsigned rptr_offs; 786 u64 next_rptr_gpu_addr; 787 volatile u32 *next_rptr_cpu_addr; 788 unsigned wptr; 789 unsigned wptr_old; 790 unsigned ring_size; 791 unsigned max_dw; 792 int count_dw; 793 uint64_t gpu_addr; 794 uint32_t align_mask; 795 uint32_t ptr_mask; 796 bool ready; 797 u32 nop; 798 u32 idx; 799 u32 me; 800 u32 pipe; 801 u32 queue; 802 struct amdgpu_bo *mqd_obj; 803 u32 doorbell_index; 804 bool use_doorbell; 805 unsigned wptr_offs; 806 unsigned next_rptr_offs; 807 unsigned fence_offs; 808 struct amdgpu_ctx *current_ctx; 809 enum amdgpu_ring_type type; 810 char name[16]; 811 unsigned cond_exe_offs; 812 u64 cond_exe_gpu_addr; 813 volatile u32 *cond_exe_cpu_addr; 814 }; 815 816 /* 817 * VM 818 */ 819 820 /* maximum number of VMIDs */ 821 #define AMDGPU_NUM_VM 16 822 823 /* number of entries in page table */ 824 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 825 826 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 827 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 828 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 829 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 830 831 #define AMDGPU_PTE_VALID (1 << 0) 832 #define AMDGPU_PTE_SYSTEM (1 << 1) 833 #define AMDGPU_PTE_SNOOPED (1 << 2) 834 835 /* VI only */ 836 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 837 838 #define AMDGPU_PTE_READABLE (1 << 5) 839 #define AMDGPU_PTE_WRITEABLE (1 << 6) 840 841 /* PTE (Page Table Entry) fragment field for different page sizes */ 842 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 843 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 844 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 845 846 /* How to programm VM fault handling */ 847 #define AMDGPU_VM_FAULT_STOP_NEVER 0 848 #define AMDGPU_VM_FAULT_STOP_FIRST 1 849 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 850 851 struct amdgpu_vm_pt { 852 struct amdgpu_bo_list_entry entry; 853 uint64_t addr; 854 }; 855 856 struct amdgpu_vm { 857 /* tree of virtual addresses mapped */ 858 struct rb_root va; 859 860 /* protecting invalidated */ 861 spinlock_t status_lock; 862 863 /* BOs moved, but not yet updated in the PT */ 864 struct list_head invalidated; 865 866 /* BOs cleared in the PT because of a move */ 867 struct list_head cleared; 868 869 /* BO mappings freed, but not yet updated in the PT */ 870 struct list_head freed; 871 872 /* contains the page directory */ 873 struct amdgpu_bo *page_directory; 874 unsigned max_pde_used; 875 struct fence *page_directory_fence; 876 877 /* array of page tables, one for each page directory entry */ 878 struct amdgpu_vm_pt *page_tables; 879 880 /* for id and flush management per ring */ 881 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 882 883 /* protecting freed */ 884 spinlock_t freed_lock; 885 886 /* Scheduler entity for page table updates */ 887 struct amd_sched_entity entity; 888 }; 889 890 struct amdgpu_vm_id { 891 struct list_head list; 892 struct fence *first; 893 struct amdgpu_sync active; 894 struct fence *last_flush; 895 struct amdgpu_ring *last_user; 896 atomic_long_t owner; 897 898 uint64_t pd_gpu_addr; 899 /* last flushed PD/PT update */ 900 struct fence *flushed_updates; 901 902 uint32_t gds_base; 903 uint32_t gds_size; 904 uint32_t gws_base; 905 uint32_t gws_size; 906 uint32_t oa_base; 907 uint32_t oa_size; 908 }; 909 910 struct amdgpu_vm_manager { 911 /* Handling of VMIDs */ 912 struct mutex lock; 913 unsigned num_ids; 914 struct list_head ids_lru; 915 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 916 917 uint32_t max_pfn; 918 /* vram base address for page table entry */ 919 u64 vram_base_offset; 920 /* is vm enabled? */ 921 bool enabled; 922 /* vm pte handling */ 923 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 924 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 925 unsigned vm_pte_num_rings; 926 atomic_t vm_pte_next_ring; 927 }; 928 929 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 930 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 931 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 932 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 933 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 934 struct list_head *validated, 935 struct amdgpu_bo_list_entry *entry); 936 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 937 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 938 struct amdgpu_vm *vm); 939 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 940 struct amdgpu_sync *sync, struct fence *fence, 941 unsigned *vm_id, uint64_t *vm_pd_addr); 942 int amdgpu_vm_flush(struct amdgpu_ring *ring, 943 unsigned vm_id, uint64_t pd_addr, 944 uint32_t gds_base, uint32_t gds_size, 945 uint32_t gws_base, uint32_t gws_size, 946 uint32_t oa_base, uint32_t oa_size); 947 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 948 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 949 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 950 struct amdgpu_vm *vm); 951 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 952 struct amdgpu_vm *vm); 953 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 954 struct amdgpu_sync *sync); 955 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 956 struct amdgpu_bo_va *bo_va, 957 struct ttm_mem_reg *mem); 958 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 959 struct amdgpu_bo *bo); 960 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 961 struct amdgpu_bo *bo); 962 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 963 struct amdgpu_vm *vm, 964 struct amdgpu_bo *bo); 965 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 966 struct amdgpu_bo_va *bo_va, 967 uint64_t addr, uint64_t offset, 968 uint64_t size, uint32_t flags); 969 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 970 struct amdgpu_bo_va *bo_va, 971 uint64_t addr); 972 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 973 struct amdgpu_bo_va *bo_va); 974 975 /* 976 * context related structures 977 */ 978 979 struct amdgpu_ctx_ring { 980 uint64_t sequence; 981 struct fence **fences; 982 struct amd_sched_entity entity; 983 }; 984 985 struct amdgpu_ctx { 986 struct kref refcount; 987 struct amdgpu_device *adev; 988 unsigned reset_counter; 989 spinlock_t ring_lock; 990 struct fence **fences; 991 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 992 }; 993 994 struct amdgpu_ctx_mgr { 995 struct amdgpu_device *adev; 996 struct mutex lock; 997 /* protected by lock */ 998 struct idr ctx_handles; 999 }; 1000 1001 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1002 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1003 1004 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1005 struct fence *fence); 1006 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1007 struct amdgpu_ring *ring, uint64_t seq); 1008 1009 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1010 struct drm_file *filp); 1011 1012 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1013 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1014 1015 /* 1016 * file private structure 1017 */ 1018 1019 struct amdgpu_fpriv { 1020 struct amdgpu_vm vm; 1021 struct mutex bo_list_lock; 1022 struct idr bo_list_handles; 1023 struct amdgpu_ctx_mgr ctx_mgr; 1024 }; 1025 1026 /* 1027 * residency list 1028 */ 1029 1030 struct amdgpu_bo_list { 1031 struct mutex lock; 1032 struct amdgpu_bo *gds_obj; 1033 struct amdgpu_bo *gws_obj; 1034 struct amdgpu_bo *oa_obj; 1035 unsigned first_userptr; 1036 unsigned num_entries; 1037 struct amdgpu_bo_list_entry *array; 1038 }; 1039 1040 struct amdgpu_bo_list * 1041 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1042 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1043 struct list_head *validated); 1044 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1045 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1046 1047 /* 1048 * GFX stuff 1049 */ 1050 #include "clearstate_defs.h" 1051 1052 struct amdgpu_rlc_funcs { 1053 void (*enter_safe_mode)(struct amdgpu_device *adev); 1054 void (*exit_safe_mode)(struct amdgpu_device *adev); 1055 }; 1056 1057 struct amdgpu_rlc { 1058 /* for power gating */ 1059 struct amdgpu_bo *save_restore_obj; 1060 uint64_t save_restore_gpu_addr; 1061 volatile uint32_t *sr_ptr; 1062 const u32 *reg_list; 1063 u32 reg_list_size; 1064 /* for clear state */ 1065 struct amdgpu_bo *clear_state_obj; 1066 uint64_t clear_state_gpu_addr; 1067 volatile uint32_t *cs_ptr; 1068 const struct cs_section_def *cs_data; 1069 u32 clear_state_size; 1070 /* for cp tables */ 1071 struct amdgpu_bo *cp_table_obj; 1072 uint64_t cp_table_gpu_addr; 1073 volatile uint32_t *cp_table_ptr; 1074 u32 cp_table_size; 1075 1076 /* safe mode for updating CG/PG state */ 1077 bool in_safe_mode; 1078 const struct amdgpu_rlc_funcs *funcs; 1079 }; 1080 1081 struct amdgpu_mec { 1082 struct amdgpu_bo *hpd_eop_obj; 1083 u64 hpd_eop_gpu_addr; 1084 u32 num_pipe; 1085 u32 num_mec; 1086 u32 num_queue; 1087 }; 1088 1089 /* 1090 * GPU scratch registers structures, functions & helpers 1091 */ 1092 struct amdgpu_scratch { 1093 unsigned num_reg; 1094 uint32_t reg_base; 1095 bool free[32]; 1096 uint32_t reg[32]; 1097 }; 1098 1099 /* 1100 * GFX configurations 1101 */ 1102 struct amdgpu_gca_config { 1103 unsigned max_shader_engines; 1104 unsigned max_tile_pipes; 1105 unsigned max_cu_per_sh; 1106 unsigned max_sh_per_se; 1107 unsigned max_backends_per_se; 1108 unsigned max_texture_channel_caches; 1109 unsigned max_gprs; 1110 unsigned max_gs_threads; 1111 unsigned max_hw_contexts; 1112 unsigned sc_prim_fifo_size_frontend; 1113 unsigned sc_prim_fifo_size_backend; 1114 unsigned sc_hiz_tile_fifo_size; 1115 unsigned sc_earlyz_tile_fifo_size; 1116 1117 unsigned num_tile_pipes; 1118 unsigned backend_enable_mask; 1119 unsigned mem_max_burst_length_bytes; 1120 unsigned mem_row_size_in_kb; 1121 unsigned shader_engine_tile_size; 1122 unsigned num_gpus; 1123 unsigned multi_gpu_tile_size; 1124 unsigned mc_arb_ramcfg; 1125 unsigned gb_addr_config; 1126 unsigned num_rbs; 1127 1128 uint32_t tile_mode_array[32]; 1129 uint32_t macrotile_mode_array[16]; 1130 }; 1131 1132 struct amdgpu_gfx { 1133 struct mutex gpu_clock_mutex; 1134 struct amdgpu_gca_config config; 1135 struct amdgpu_rlc rlc; 1136 struct amdgpu_mec mec; 1137 struct amdgpu_scratch scratch; 1138 const struct firmware *me_fw; /* ME firmware */ 1139 uint32_t me_fw_version; 1140 const struct firmware *pfp_fw; /* PFP firmware */ 1141 uint32_t pfp_fw_version; 1142 const struct firmware *ce_fw; /* CE firmware */ 1143 uint32_t ce_fw_version; 1144 const struct firmware *rlc_fw; /* RLC firmware */ 1145 uint32_t rlc_fw_version; 1146 const struct firmware *mec_fw; /* MEC firmware */ 1147 uint32_t mec_fw_version; 1148 const struct firmware *mec2_fw; /* MEC2 firmware */ 1149 uint32_t mec2_fw_version; 1150 uint32_t me_feature_version; 1151 uint32_t ce_feature_version; 1152 uint32_t pfp_feature_version; 1153 uint32_t rlc_feature_version; 1154 uint32_t mec_feature_version; 1155 uint32_t mec2_feature_version; 1156 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1157 unsigned num_gfx_rings; 1158 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1159 unsigned num_compute_rings; 1160 struct amdgpu_irq_src eop_irq; 1161 struct amdgpu_irq_src priv_reg_irq; 1162 struct amdgpu_irq_src priv_inst_irq; 1163 /* gfx status */ 1164 uint32_t gfx_current_status; 1165 /* ce ram size*/ 1166 unsigned ce_ram_size; 1167 }; 1168 1169 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1170 unsigned size, struct amdgpu_ib *ib); 1171 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f); 1172 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1173 struct amdgpu_ib *ib, struct fence *last_vm_update, 1174 struct fence **f); 1175 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1176 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1177 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1178 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1179 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1180 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 1181 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1182 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1183 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1184 uint32_t **data); 1185 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1186 unsigned size, uint32_t *data); 1187 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1188 unsigned ring_size, u32 nop, u32 align_mask, 1189 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1190 enum amdgpu_ring_type ring_type); 1191 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1192 1193 /* 1194 * CS. 1195 */ 1196 struct amdgpu_cs_chunk { 1197 uint32_t chunk_id; 1198 uint32_t length_dw; 1199 uint32_t *kdata; 1200 }; 1201 1202 struct amdgpu_cs_parser { 1203 struct amdgpu_device *adev; 1204 struct drm_file *filp; 1205 struct amdgpu_ctx *ctx; 1206 1207 /* chunks */ 1208 unsigned nchunks; 1209 struct amdgpu_cs_chunk *chunks; 1210 1211 /* scheduler job object */ 1212 struct amdgpu_job *job; 1213 1214 /* buffer objects */ 1215 struct ww_acquire_ctx ticket; 1216 struct amdgpu_bo_list *bo_list; 1217 struct amdgpu_bo_list_entry vm_pd; 1218 struct list_head validated; 1219 struct fence *fence; 1220 uint64_t bytes_moved_threshold; 1221 uint64_t bytes_moved; 1222 1223 /* user fence */ 1224 struct amdgpu_bo_list_entry uf_entry; 1225 }; 1226 1227 struct amdgpu_job { 1228 struct amd_sched_job base; 1229 struct amdgpu_device *adev; 1230 struct amdgpu_ring *ring; 1231 struct amdgpu_sync sync; 1232 struct amdgpu_ib *ibs; 1233 struct fence *fence; /* the hw fence */ 1234 uint32_t num_ibs; 1235 void *owner; 1236 struct amdgpu_user_fence uf; 1237 }; 1238 #define to_amdgpu_job(sched_job) \ 1239 container_of((sched_job), struct amdgpu_job, base) 1240 1241 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1242 uint32_t ib_idx, int idx) 1243 { 1244 return p->job->ibs[ib_idx].ptr[idx]; 1245 } 1246 1247 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1248 uint32_t ib_idx, int idx, 1249 uint32_t value) 1250 { 1251 p->job->ibs[ib_idx].ptr[idx] = value; 1252 } 1253 1254 /* 1255 * Writeback 1256 */ 1257 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1258 1259 struct amdgpu_wb { 1260 struct amdgpu_bo *wb_obj; 1261 volatile uint32_t *wb; 1262 uint64_t gpu_addr; 1263 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1264 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1265 }; 1266 1267 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1268 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1269 1270 1271 1272 enum amdgpu_int_thermal_type { 1273 THERMAL_TYPE_NONE, 1274 THERMAL_TYPE_EXTERNAL, 1275 THERMAL_TYPE_EXTERNAL_GPIO, 1276 THERMAL_TYPE_RV6XX, 1277 THERMAL_TYPE_RV770, 1278 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1279 THERMAL_TYPE_EVERGREEN, 1280 THERMAL_TYPE_SUMO, 1281 THERMAL_TYPE_NI, 1282 THERMAL_TYPE_SI, 1283 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1284 THERMAL_TYPE_CI, 1285 THERMAL_TYPE_KV, 1286 }; 1287 1288 enum amdgpu_dpm_auto_throttle_src { 1289 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1290 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1291 }; 1292 1293 enum amdgpu_dpm_event_src { 1294 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1295 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1296 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1297 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1298 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1299 }; 1300 1301 #define AMDGPU_MAX_VCE_LEVELS 6 1302 1303 enum amdgpu_vce_level { 1304 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1305 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1306 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1307 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1308 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1309 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1310 }; 1311 1312 struct amdgpu_ps { 1313 u32 caps; /* vbios flags */ 1314 u32 class; /* vbios flags */ 1315 u32 class2; /* vbios flags */ 1316 /* UVD clocks */ 1317 u32 vclk; 1318 u32 dclk; 1319 /* VCE clocks */ 1320 u32 evclk; 1321 u32 ecclk; 1322 bool vce_active; 1323 enum amdgpu_vce_level vce_level; 1324 /* asic priv */ 1325 void *ps_priv; 1326 }; 1327 1328 struct amdgpu_dpm_thermal { 1329 /* thermal interrupt work */ 1330 struct work_struct work; 1331 /* low temperature threshold */ 1332 int min_temp; 1333 /* high temperature threshold */ 1334 int max_temp; 1335 /* was last interrupt low to high or high to low */ 1336 bool high_to_low; 1337 /* interrupt source */ 1338 struct amdgpu_irq_src irq; 1339 }; 1340 1341 enum amdgpu_clk_action 1342 { 1343 AMDGPU_SCLK_UP = 1, 1344 AMDGPU_SCLK_DOWN 1345 }; 1346 1347 struct amdgpu_blacklist_clocks 1348 { 1349 u32 sclk; 1350 u32 mclk; 1351 enum amdgpu_clk_action action; 1352 }; 1353 1354 struct amdgpu_clock_and_voltage_limits { 1355 u32 sclk; 1356 u32 mclk; 1357 u16 vddc; 1358 u16 vddci; 1359 }; 1360 1361 struct amdgpu_clock_array { 1362 u32 count; 1363 u32 *values; 1364 }; 1365 1366 struct amdgpu_clock_voltage_dependency_entry { 1367 u32 clk; 1368 u16 v; 1369 }; 1370 1371 struct amdgpu_clock_voltage_dependency_table { 1372 u32 count; 1373 struct amdgpu_clock_voltage_dependency_entry *entries; 1374 }; 1375 1376 union amdgpu_cac_leakage_entry { 1377 struct { 1378 u16 vddc; 1379 u32 leakage; 1380 }; 1381 struct { 1382 u16 vddc1; 1383 u16 vddc2; 1384 u16 vddc3; 1385 }; 1386 }; 1387 1388 struct amdgpu_cac_leakage_table { 1389 u32 count; 1390 union amdgpu_cac_leakage_entry *entries; 1391 }; 1392 1393 struct amdgpu_phase_shedding_limits_entry { 1394 u16 voltage; 1395 u32 sclk; 1396 u32 mclk; 1397 }; 1398 1399 struct amdgpu_phase_shedding_limits_table { 1400 u32 count; 1401 struct amdgpu_phase_shedding_limits_entry *entries; 1402 }; 1403 1404 struct amdgpu_uvd_clock_voltage_dependency_entry { 1405 u32 vclk; 1406 u32 dclk; 1407 u16 v; 1408 }; 1409 1410 struct amdgpu_uvd_clock_voltage_dependency_table { 1411 u8 count; 1412 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1413 }; 1414 1415 struct amdgpu_vce_clock_voltage_dependency_entry { 1416 u32 ecclk; 1417 u32 evclk; 1418 u16 v; 1419 }; 1420 1421 struct amdgpu_vce_clock_voltage_dependency_table { 1422 u8 count; 1423 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1424 }; 1425 1426 struct amdgpu_ppm_table { 1427 u8 ppm_design; 1428 u16 cpu_core_number; 1429 u32 platform_tdp; 1430 u32 small_ac_platform_tdp; 1431 u32 platform_tdc; 1432 u32 small_ac_platform_tdc; 1433 u32 apu_tdp; 1434 u32 dgpu_tdp; 1435 u32 dgpu_ulv_power; 1436 u32 tj_max; 1437 }; 1438 1439 struct amdgpu_cac_tdp_table { 1440 u16 tdp; 1441 u16 configurable_tdp; 1442 u16 tdc; 1443 u16 battery_power_limit; 1444 u16 small_power_limit; 1445 u16 low_cac_leakage; 1446 u16 high_cac_leakage; 1447 u16 maximum_power_delivery_limit; 1448 }; 1449 1450 struct amdgpu_dpm_dynamic_state { 1451 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1452 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1453 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1454 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1455 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1456 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1457 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1458 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1459 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1460 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1461 struct amdgpu_clock_array valid_sclk_values; 1462 struct amdgpu_clock_array valid_mclk_values; 1463 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1464 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1465 u32 mclk_sclk_ratio; 1466 u32 sclk_mclk_delta; 1467 u16 vddc_vddci_delta; 1468 u16 min_vddc_for_pcie_gen2; 1469 struct amdgpu_cac_leakage_table cac_leakage_table; 1470 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1471 struct amdgpu_ppm_table *ppm_table; 1472 struct amdgpu_cac_tdp_table *cac_tdp_table; 1473 }; 1474 1475 struct amdgpu_dpm_fan { 1476 u16 t_min; 1477 u16 t_med; 1478 u16 t_high; 1479 u16 pwm_min; 1480 u16 pwm_med; 1481 u16 pwm_high; 1482 u8 t_hyst; 1483 u32 cycle_delay; 1484 u16 t_max; 1485 u8 control_mode; 1486 u16 default_max_fan_pwm; 1487 u16 default_fan_output_sensitivity; 1488 u16 fan_output_sensitivity; 1489 bool ucode_fan_control; 1490 }; 1491 1492 enum amdgpu_pcie_gen { 1493 AMDGPU_PCIE_GEN1 = 0, 1494 AMDGPU_PCIE_GEN2 = 1, 1495 AMDGPU_PCIE_GEN3 = 2, 1496 AMDGPU_PCIE_GEN_INVALID = 0xffff 1497 }; 1498 1499 enum amdgpu_dpm_forced_level { 1500 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1501 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1502 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1503 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1504 }; 1505 1506 struct amdgpu_vce_state { 1507 /* vce clocks */ 1508 u32 evclk; 1509 u32 ecclk; 1510 /* gpu clocks */ 1511 u32 sclk; 1512 u32 mclk; 1513 u8 clk_idx; 1514 u8 pstate; 1515 }; 1516 1517 struct amdgpu_dpm_funcs { 1518 int (*get_temperature)(struct amdgpu_device *adev); 1519 int (*pre_set_power_state)(struct amdgpu_device *adev); 1520 int (*set_power_state)(struct amdgpu_device *adev); 1521 void (*post_set_power_state)(struct amdgpu_device *adev); 1522 void (*display_configuration_changed)(struct amdgpu_device *adev); 1523 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1524 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1525 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1526 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1527 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1528 bool (*vblank_too_short)(struct amdgpu_device *adev); 1529 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1530 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1531 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1532 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1533 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1534 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1535 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1536 }; 1537 1538 struct amdgpu_dpm { 1539 struct amdgpu_ps *ps; 1540 /* number of valid power states */ 1541 int num_ps; 1542 /* current power state that is active */ 1543 struct amdgpu_ps *current_ps; 1544 /* requested power state */ 1545 struct amdgpu_ps *requested_ps; 1546 /* boot up power state */ 1547 struct amdgpu_ps *boot_ps; 1548 /* default uvd power state */ 1549 struct amdgpu_ps *uvd_ps; 1550 /* vce requirements */ 1551 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1552 enum amdgpu_vce_level vce_level; 1553 enum amd_pm_state_type state; 1554 enum amd_pm_state_type user_state; 1555 u32 platform_caps; 1556 u32 voltage_response_time; 1557 u32 backbias_response_time; 1558 void *priv; 1559 u32 new_active_crtcs; 1560 int new_active_crtc_count; 1561 u32 current_active_crtcs; 1562 int current_active_crtc_count; 1563 struct amdgpu_dpm_dynamic_state dyn_state; 1564 struct amdgpu_dpm_fan fan; 1565 u32 tdp_limit; 1566 u32 near_tdp_limit; 1567 u32 near_tdp_limit_adjusted; 1568 u32 sq_ramping_threshold; 1569 u32 cac_leakage; 1570 u16 tdp_od_limit; 1571 u32 tdp_adjustment; 1572 u16 load_line_slope; 1573 bool power_control; 1574 bool ac_power; 1575 /* special states active */ 1576 bool thermal_active; 1577 bool uvd_active; 1578 bool vce_active; 1579 /* thermal handling */ 1580 struct amdgpu_dpm_thermal thermal; 1581 /* forced levels */ 1582 enum amdgpu_dpm_forced_level forced_level; 1583 }; 1584 1585 struct amdgpu_pm { 1586 struct mutex mutex; 1587 u32 current_sclk; 1588 u32 current_mclk; 1589 u32 default_sclk; 1590 u32 default_mclk; 1591 struct amdgpu_i2c_chan *i2c_bus; 1592 /* internal thermal controller on rv6xx+ */ 1593 enum amdgpu_int_thermal_type int_thermal_type; 1594 struct device *int_hwmon_dev; 1595 /* fan control parameters */ 1596 bool no_fan; 1597 u8 fan_pulses_per_revolution; 1598 u8 fan_min_rpm; 1599 u8 fan_max_rpm; 1600 /* dpm */ 1601 bool dpm_enabled; 1602 bool sysfs_initialized; 1603 struct amdgpu_dpm dpm; 1604 const struct firmware *fw; /* SMC firmware */ 1605 uint32_t fw_version; 1606 const struct amdgpu_dpm_funcs *funcs; 1607 uint32_t pcie_gen_mask; 1608 uint32_t pcie_mlw_mask; 1609 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1610 }; 1611 1612 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1613 1614 /* 1615 * UVD 1616 */ 1617 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1618 #define AMDGPU_MAX_UVD_HANDLES 40 1619 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1620 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1621 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1622 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1623 1624 struct amdgpu_uvd { 1625 struct amdgpu_bo *vcpu_bo; 1626 void *cpu_addr; 1627 uint64_t gpu_addr; 1628 void *saved_bo; 1629 unsigned max_handles; 1630 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1631 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1632 struct delayed_work idle_work; 1633 const struct firmware *fw; /* UVD firmware */ 1634 struct amdgpu_ring ring; 1635 struct amdgpu_irq_src irq; 1636 bool address_64_bit; 1637 struct amd_sched_entity entity; 1638 }; 1639 1640 /* 1641 * VCE 1642 */ 1643 #define AMDGPU_MAX_VCE_HANDLES 16 1644 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1645 1646 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1647 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1648 1649 struct amdgpu_vce { 1650 struct amdgpu_bo *vcpu_bo; 1651 uint64_t gpu_addr; 1652 unsigned fw_version; 1653 unsigned fb_version; 1654 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1655 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1656 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1657 struct delayed_work idle_work; 1658 const struct firmware *fw; /* VCE firmware */ 1659 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1660 struct amdgpu_irq_src irq; 1661 unsigned harvest_config; 1662 struct amd_sched_entity entity; 1663 }; 1664 1665 /* 1666 * SDMA 1667 */ 1668 struct amdgpu_sdma_instance { 1669 /* SDMA firmware */ 1670 const struct firmware *fw; 1671 uint32_t fw_version; 1672 uint32_t feature_version; 1673 1674 struct amdgpu_ring ring; 1675 bool burst_nop; 1676 }; 1677 1678 struct amdgpu_sdma { 1679 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1680 struct amdgpu_irq_src trap_irq; 1681 struct amdgpu_irq_src illegal_inst_irq; 1682 int num_instances; 1683 }; 1684 1685 /* 1686 * Firmware 1687 */ 1688 struct amdgpu_firmware { 1689 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1690 bool smu_load; 1691 struct amdgpu_bo *fw_buf; 1692 unsigned int fw_size; 1693 }; 1694 1695 /* 1696 * Benchmarking 1697 */ 1698 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1699 1700 1701 /* 1702 * Testing 1703 */ 1704 void amdgpu_test_moves(struct amdgpu_device *adev); 1705 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1706 struct amdgpu_ring *cpA, 1707 struct amdgpu_ring *cpB); 1708 void amdgpu_test_syncing(struct amdgpu_device *adev); 1709 1710 /* 1711 * MMU Notifier 1712 */ 1713 #if defined(CONFIG_MMU_NOTIFIER) 1714 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1715 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1716 #else 1717 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1718 { 1719 return -ENODEV; 1720 } 1721 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1722 #endif 1723 1724 /* 1725 * Debugfs 1726 */ 1727 struct amdgpu_debugfs { 1728 const struct drm_info_list *files; 1729 unsigned num_files; 1730 }; 1731 1732 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1733 const struct drm_info_list *files, 1734 unsigned nfiles); 1735 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1736 1737 #if defined(CONFIG_DEBUG_FS) 1738 int amdgpu_debugfs_init(struct drm_minor *minor); 1739 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1740 #endif 1741 1742 /* 1743 * amdgpu smumgr functions 1744 */ 1745 struct amdgpu_smumgr_funcs { 1746 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1747 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1748 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1749 }; 1750 1751 /* 1752 * amdgpu smumgr 1753 */ 1754 struct amdgpu_smumgr { 1755 struct amdgpu_bo *toc_buf; 1756 struct amdgpu_bo *smu_buf; 1757 /* asic priv smu data */ 1758 void *priv; 1759 spinlock_t smu_lock; 1760 /* smumgr functions */ 1761 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1762 /* ucode loading complete flag */ 1763 uint32_t fw_flags; 1764 }; 1765 1766 /* 1767 * ASIC specific register table accessible by UMD 1768 */ 1769 struct amdgpu_allowed_register_entry { 1770 uint32_t reg_offset; 1771 bool untouched; 1772 bool grbm_indexed; 1773 }; 1774 1775 struct amdgpu_cu_info { 1776 uint32_t number; /* total active CU number */ 1777 uint32_t ao_cu_mask; 1778 uint32_t bitmap[4][4]; 1779 }; 1780 1781 1782 /* 1783 * ASIC specific functions. 1784 */ 1785 struct amdgpu_asic_funcs { 1786 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1787 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1788 u8 *bios, u32 length_bytes); 1789 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1790 u32 sh_num, u32 reg_offset, u32 *value); 1791 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1792 int (*reset)(struct amdgpu_device *adev); 1793 /* wait for mc_idle */ 1794 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1795 /* get the reference clock */ 1796 u32 (*get_xclk)(struct amdgpu_device *adev); 1797 /* get the gpu clock counter */ 1798 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1799 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1800 /* MM block clocks */ 1801 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1802 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1803 }; 1804 1805 /* 1806 * IOCTL. 1807 */ 1808 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1809 struct drm_file *filp); 1810 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1811 struct drm_file *filp); 1812 1813 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1814 struct drm_file *filp); 1815 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1816 struct drm_file *filp); 1817 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1818 struct drm_file *filp); 1819 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1820 struct drm_file *filp); 1821 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1822 struct drm_file *filp); 1823 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1824 struct drm_file *filp); 1825 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1826 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1827 1828 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1829 struct drm_file *filp); 1830 1831 /* VRAM scratch page for HDP bug, default vram page */ 1832 struct amdgpu_vram_scratch { 1833 struct amdgpu_bo *robj; 1834 volatile uint32_t *ptr; 1835 u64 gpu_addr; 1836 }; 1837 1838 /* 1839 * ACPI 1840 */ 1841 struct amdgpu_atif_notification_cfg { 1842 bool enabled; 1843 int command_code; 1844 }; 1845 1846 struct amdgpu_atif_notifications { 1847 bool display_switch; 1848 bool expansion_mode_change; 1849 bool thermal_state; 1850 bool forced_power_state; 1851 bool system_power_state; 1852 bool display_conf_change; 1853 bool px_gfx_switch; 1854 bool brightness_change; 1855 bool dgpu_display_event; 1856 }; 1857 1858 struct amdgpu_atif_functions { 1859 bool system_params; 1860 bool sbios_requests; 1861 bool select_active_disp; 1862 bool lid_state; 1863 bool get_tv_standard; 1864 bool set_tv_standard; 1865 bool get_panel_expansion_mode; 1866 bool set_panel_expansion_mode; 1867 bool temperature_change; 1868 bool graphics_device_types; 1869 }; 1870 1871 struct amdgpu_atif { 1872 struct amdgpu_atif_notifications notifications; 1873 struct amdgpu_atif_functions functions; 1874 struct amdgpu_atif_notification_cfg notification_cfg; 1875 struct amdgpu_encoder *encoder_for_bl; 1876 }; 1877 1878 struct amdgpu_atcs_functions { 1879 bool get_ext_state; 1880 bool pcie_perf_req; 1881 bool pcie_dev_rdy; 1882 bool pcie_bus_width; 1883 }; 1884 1885 struct amdgpu_atcs { 1886 struct amdgpu_atcs_functions functions; 1887 }; 1888 1889 /* 1890 * CGS 1891 */ 1892 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1893 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1894 1895 1896 /* GPU virtualization */ 1897 struct amdgpu_virtualization { 1898 bool supports_sr_iov; 1899 }; 1900 1901 /* 1902 * Core structure, functions and helpers. 1903 */ 1904 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1905 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1906 1907 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1908 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1909 1910 struct amdgpu_ip_block_status { 1911 bool valid; 1912 bool sw; 1913 bool hw; 1914 }; 1915 1916 struct amdgpu_device { 1917 struct device *dev; 1918 struct drm_device *ddev; 1919 struct pci_dev *pdev; 1920 1921 #ifdef CONFIG_DRM_AMD_ACP 1922 struct amdgpu_acp acp; 1923 #endif 1924 1925 /* ASIC */ 1926 enum amd_asic_type asic_type; 1927 uint32_t family; 1928 uint32_t rev_id; 1929 uint32_t external_rev_id; 1930 unsigned long flags; 1931 int usec_timeout; 1932 const struct amdgpu_asic_funcs *asic_funcs; 1933 bool shutdown; 1934 bool need_dma32; 1935 bool accel_working; 1936 struct work_struct reset_work; 1937 struct notifier_block acpi_nb; 1938 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1939 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1940 unsigned debugfs_count; 1941 #if defined(CONFIG_DEBUG_FS) 1942 struct dentry *debugfs_regs; 1943 #endif 1944 struct amdgpu_atif atif; 1945 struct amdgpu_atcs atcs; 1946 struct mutex srbm_mutex; 1947 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1948 struct mutex grbm_idx_mutex; 1949 struct dev_pm_domain vga_pm_domain; 1950 bool have_disp_power_ref; 1951 1952 /* BIOS */ 1953 uint8_t *bios; 1954 bool is_atom_bios; 1955 struct amdgpu_bo *stollen_vga_memory; 1956 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1957 1958 /* Register/doorbell mmio */ 1959 resource_size_t rmmio_base; 1960 resource_size_t rmmio_size; 1961 void __iomem *rmmio; 1962 /* protects concurrent MM_INDEX/DATA based register access */ 1963 spinlock_t mmio_idx_lock; 1964 /* protects concurrent SMC based register access */ 1965 spinlock_t smc_idx_lock; 1966 amdgpu_rreg_t smc_rreg; 1967 amdgpu_wreg_t smc_wreg; 1968 /* protects concurrent PCIE register access */ 1969 spinlock_t pcie_idx_lock; 1970 amdgpu_rreg_t pcie_rreg; 1971 amdgpu_wreg_t pcie_wreg; 1972 /* protects concurrent UVD register access */ 1973 spinlock_t uvd_ctx_idx_lock; 1974 amdgpu_rreg_t uvd_ctx_rreg; 1975 amdgpu_wreg_t uvd_ctx_wreg; 1976 /* protects concurrent DIDT register access */ 1977 spinlock_t didt_idx_lock; 1978 amdgpu_rreg_t didt_rreg; 1979 amdgpu_wreg_t didt_wreg; 1980 /* protects concurrent ENDPOINT (audio) register access */ 1981 spinlock_t audio_endpt_idx_lock; 1982 amdgpu_block_rreg_t audio_endpt_rreg; 1983 amdgpu_block_wreg_t audio_endpt_wreg; 1984 void __iomem *rio_mem; 1985 resource_size_t rio_mem_size; 1986 struct amdgpu_doorbell doorbell; 1987 1988 /* clock/pll info */ 1989 struct amdgpu_clock clock; 1990 1991 /* MC */ 1992 struct amdgpu_mc mc; 1993 struct amdgpu_gart gart; 1994 struct amdgpu_dummy_page dummy_page; 1995 struct amdgpu_vm_manager vm_manager; 1996 1997 /* memory management */ 1998 struct amdgpu_mman mman; 1999 struct amdgpu_vram_scratch vram_scratch; 2000 struct amdgpu_wb wb; 2001 atomic64_t vram_usage; 2002 atomic64_t vram_vis_usage; 2003 atomic64_t gtt_usage; 2004 atomic64_t num_bytes_moved; 2005 atomic_t gpu_reset_counter; 2006 2007 /* display */ 2008 struct amdgpu_mode_info mode_info; 2009 struct work_struct hotplug_work; 2010 struct amdgpu_irq_src crtc_irq; 2011 struct amdgpu_irq_src pageflip_irq; 2012 struct amdgpu_irq_src hpd_irq; 2013 2014 /* rings */ 2015 unsigned fence_context; 2016 unsigned num_rings; 2017 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2018 bool ib_pool_ready; 2019 struct amdgpu_sa_manager ring_tmp_bo; 2020 2021 /* interrupts */ 2022 struct amdgpu_irq irq; 2023 2024 /* powerplay */ 2025 struct amd_powerplay powerplay; 2026 bool pp_enabled; 2027 bool pp_force_state_enabled; 2028 2029 /* dpm */ 2030 struct amdgpu_pm pm; 2031 u32 cg_flags; 2032 u32 pg_flags; 2033 2034 /* amdgpu smumgr */ 2035 struct amdgpu_smumgr smu; 2036 2037 /* gfx */ 2038 struct amdgpu_gfx gfx; 2039 2040 /* sdma */ 2041 struct amdgpu_sdma sdma; 2042 2043 /* uvd */ 2044 struct amdgpu_uvd uvd; 2045 2046 /* vce */ 2047 struct amdgpu_vce vce; 2048 2049 /* firmwares */ 2050 struct amdgpu_firmware firmware; 2051 2052 /* GDS */ 2053 struct amdgpu_gds gds; 2054 2055 const struct amdgpu_ip_block_version *ip_blocks; 2056 int num_ip_blocks; 2057 struct amdgpu_ip_block_status *ip_block_status; 2058 struct mutex mn_lock; 2059 DECLARE_HASHTABLE(mn_hash, 7); 2060 2061 /* tracking pinned memory */ 2062 u64 vram_pin_size; 2063 u64 gart_pin_size; 2064 2065 /* amdkfd interface */ 2066 struct kfd_dev *kfd; 2067 2068 struct amdgpu_virtualization virtualization; 2069 }; 2070 2071 bool amdgpu_device_is_px(struct drm_device *dev); 2072 int amdgpu_device_init(struct amdgpu_device *adev, 2073 struct drm_device *ddev, 2074 struct pci_dev *pdev, 2075 uint32_t flags); 2076 void amdgpu_device_fini(struct amdgpu_device *adev); 2077 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2078 2079 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2080 bool always_indirect); 2081 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2082 bool always_indirect); 2083 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2084 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2085 2086 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2087 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2088 2089 /* 2090 * Registers read & write functions. 2091 */ 2092 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2093 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2094 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2095 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2096 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2097 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2098 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2099 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2100 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2101 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2102 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2103 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2104 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2105 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2106 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2107 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2108 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2109 #define WREG32_P(reg, val, mask) \ 2110 do { \ 2111 uint32_t tmp_ = RREG32(reg); \ 2112 tmp_ &= (mask); \ 2113 tmp_ |= ((val) & ~(mask)); \ 2114 WREG32(reg, tmp_); \ 2115 } while (0) 2116 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2117 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2118 #define WREG32_PLL_P(reg, val, mask) \ 2119 do { \ 2120 uint32_t tmp_ = RREG32_PLL(reg); \ 2121 tmp_ &= (mask); \ 2122 tmp_ |= ((val) & ~(mask)); \ 2123 WREG32_PLL(reg, tmp_); \ 2124 } while (0) 2125 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2126 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2127 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2128 2129 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2130 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2131 2132 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2133 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2134 2135 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2136 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2137 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2138 2139 #define REG_GET_FIELD(value, reg, field) \ 2140 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2141 2142 /* 2143 * BIOS helpers. 2144 */ 2145 #define RBIOS8(i) (adev->bios[i]) 2146 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2147 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2148 2149 /* 2150 * RING helpers. 2151 */ 2152 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2153 { 2154 if (ring->count_dw <= 0) 2155 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2156 ring->ring[ring->wptr++] = v; 2157 ring->wptr &= ring->ptr_mask; 2158 ring->count_dw--; 2159 } 2160 2161 static inline struct amdgpu_sdma_instance * 2162 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2163 { 2164 struct amdgpu_device *adev = ring->adev; 2165 int i; 2166 2167 for (i = 0; i < adev->sdma.num_instances; i++) 2168 if (&adev->sdma.instance[i].ring == ring) 2169 break; 2170 2171 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2172 return &adev->sdma.instance[i]; 2173 else 2174 return NULL; 2175 } 2176 2177 /* 2178 * ASICs macro. 2179 */ 2180 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2181 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2182 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2183 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2184 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2185 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2186 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2187 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2188 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2189 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2190 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2191 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2192 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2193 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2194 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2195 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2196 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2197 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2198 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2199 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2200 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2201 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2202 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2203 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 2204 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2205 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2206 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2207 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2208 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 2209 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 2210 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 2211 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 2212 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2213 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2214 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2215 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2216 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2217 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2218 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2219 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2220 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2221 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2222 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2223 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2224 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2225 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2226 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2227 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2228 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2229 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2230 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2231 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2232 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2233 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2234 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2235 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2236 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2237 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2238 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2239 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2240 2241 #define amdgpu_dpm_get_temperature(adev) \ 2242 ((adev)->pp_enabled ? \ 2243 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2244 (adev)->pm.funcs->get_temperature((adev))) 2245 2246 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2247 ((adev)->pp_enabled ? \ 2248 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2249 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2250 2251 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2252 ((adev)->pp_enabled ? \ 2253 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2254 (adev)->pm.funcs->get_fan_control_mode((adev))) 2255 2256 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2257 ((adev)->pp_enabled ? \ 2258 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2259 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2260 2261 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2262 ((adev)->pp_enabled ? \ 2263 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2264 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2265 2266 #define amdgpu_dpm_get_sclk(adev, l) \ 2267 ((adev)->pp_enabled ? \ 2268 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2269 (adev)->pm.funcs->get_sclk((adev), (l))) 2270 2271 #define amdgpu_dpm_get_mclk(adev, l) \ 2272 ((adev)->pp_enabled ? \ 2273 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2274 (adev)->pm.funcs->get_mclk((adev), (l))) 2275 2276 2277 #define amdgpu_dpm_force_performance_level(adev, l) \ 2278 ((adev)->pp_enabled ? \ 2279 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2280 (adev)->pm.funcs->force_performance_level((adev), (l))) 2281 2282 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2283 ((adev)->pp_enabled ? \ 2284 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2285 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2286 2287 #define amdgpu_dpm_powergate_vce(adev, g) \ 2288 ((adev)->pp_enabled ? \ 2289 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2290 (adev)->pm.funcs->powergate_vce((adev), (g))) 2291 2292 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2293 ((adev)->pp_enabled ? \ 2294 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2295 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2296 2297 #define amdgpu_dpm_get_current_power_state(adev) \ 2298 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2299 2300 #define amdgpu_dpm_get_performance_level(adev) \ 2301 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2302 2303 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2304 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2305 2306 #define amdgpu_dpm_get_pp_table(adev, table) \ 2307 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2308 2309 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2310 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2311 2312 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2313 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2314 2315 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2316 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2317 2318 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2319 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2320 2321 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2322 2323 /* Common functions */ 2324 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2325 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2326 bool amdgpu_card_posted(struct amdgpu_device *adev); 2327 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2328 2329 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2330 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2331 u32 ip_instance, u32 ring, 2332 struct amdgpu_ring **out_ring); 2333 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2334 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2335 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 2336 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2337 uint32_t flags); 2338 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2339 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2340 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2341 unsigned long end); 2342 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 2343 int *last_invalidated); 2344 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2345 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2346 struct ttm_mem_reg *mem); 2347 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2348 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2349 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2350 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2351 const u32 *registers, 2352 const u32 array_size); 2353 2354 bool amdgpu_device_is_px(struct drm_device *dev); 2355 /* atpx handler */ 2356 #if defined(CONFIG_VGA_SWITCHEROO) 2357 void amdgpu_register_atpx_handler(void); 2358 void amdgpu_unregister_atpx_handler(void); 2359 #else 2360 static inline void amdgpu_register_atpx_handler(void) {} 2361 static inline void amdgpu_unregister_atpx_handler(void) {} 2362 #endif 2363 2364 /* 2365 * KMS 2366 */ 2367 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2368 extern const int amdgpu_max_kms_ioctl; 2369 2370 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2371 int amdgpu_driver_unload_kms(struct drm_device *dev); 2372 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2373 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2374 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2375 struct drm_file *file_priv); 2376 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2377 struct drm_file *file_priv); 2378 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2379 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2380 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2381 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2382 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2383 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2384 int *max_error, 2385 struct timeval *vblank_time, 2386 unsigned flags); 2387 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2388 unsigned long arg); 2389 2390 /* 2391 * functions used by amdgpu_encoder.c 2392 */ 2393 struct amdgpu_afmt_acr { 2394 u32 clock; 2395 2396 int n_32khz; 2397 int cts_32khz; 2398 2399 int n_44_1khz; 2400 int cts_44_1khz; 2401 2402 int n_48khz; 2403 int cts_48khz; 2404 2405 }; 2406 2407 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2408 2409 /* amdgpu_acpi.c */ 2410 #if defined(CONFIG_ACPI) 2411 int amdgpu_acpi_init(struct amdgpu_device *adev); 2412 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2413 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2414 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2415 u8 perf_req, bool advertise); 2416 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2417 #else 2418 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2419 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2420 #endif 2421 2422 struct amdgpu_bo_va_mapping * 2423 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2424 uint64_t addr, struct amdgpu_bo **bo); 2425 2426 #include "amdgpu_object.h" 2427 #endif 2428