1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 extern int amdgpu_powercontainment; 89 extern unsigned amdgpu_pcie_gen_cap; 90 extern unsigned amdgpu_pcie_lane_cap; 91 extern unsigned amdgpu_cg_mask; 92 extern unsigned amdgpu_pg_mask; 93 extern char *amdgpu_disable_cu; 94 95 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 96 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 97 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 98 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 99 #define AMDGPU_IB_POOL_SIZE 16 100 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 101 #define AMDGPUFB_CONN_LIMIT 4 102 #define AMDGPU_BIOS_NUM_SCRATCH 8 103 104 /* max number of rings */ 105 #define AMDGPU_MAX_RINGS 16 106 #define AMDGPU_MAX_GFX_RINGS 1 107 #define AMDGPU_MAX_COMPUTE_RINGS 8 108 #define AMDGPU_MAX_VCE_RINGS 2 109 110 /* max number of IP instances */ 111 #define AMDGPU_MAX_SDMA_INSTANCES 2 112 113 /* hardcode that limit for now */ 114 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 115 116 /* hard reset data */ 117 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 118 119 /* reset flags */ 120 #define AMDGPU_RESET_GFX (1 << 0) 121 #define AMDGPU_RESET_COMPUTE (1 << 1) 122 #define AMDGPU_RESET_DMA (1 << 2) 123 #define AMDGPU_RESET_CP (1 << 3) 124 #define AMDGPU_RESET_GRBM (1 << 4) 125 #define AMDGPU_RESET_DMA1 (1 << 5) 126 #define AMDGPU_RESET_RLC (1 << 6) 127 #define AMDGPU_RESET_SEM (1 << 7) 128 #define AMDGPU_RESET_IH (1 << 8) 129 #define AMDGPU_RESET_VMC (1 << 9) 130 #define AMDGPU_RESET_MC (1 << 10) 131 #define AMDGPU_RESET_DISPLAY (1 << 11) 132 #define AMDGPU_RESET_UVD (1 << 12) 133 #define AMDGPU_RESET_VCE (1 << 13) 134 #define AMDGPU_RESET_VCE1 (1 << 14) 135 136 /* GFX current status */ 137 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 138 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 139 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 140 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 141 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 142 143 /* max cursor sizes (in pixels) */ 144 #define CIK_CURSOR_WIDTH 128 145 #define CIK_CURSOR_HEIGHT 128 146 147 struct amdgpu_device; 148 struct amdgpu_ib; 149 struct amdgpu_vm; 150 struct amdgpu_ring; 151 struct amdgpu_cs_parser; 152 struct amdgpu_job; 153 struct amdgpu_irq_src; 154 struct amdgpu_fpriv; 155 156 enum amdgpu_cp_irq { 157 AMDGPU_CP_IRQ_GFX_EOP = 0, 158 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 159 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 162 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 163 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 166 167 AMDGPU_CP_IRQ_LAST 168 }; 169 170 enum amdgpu_sdma_irq { 171 AMDGPU_SDMA_IRQ_TRAP0 = 0, 172 AMDGPU_SDMA_IRQ_TRAP1, 173 174 AMDGPU_SDMA_IRQ_LAST 175 }; 176 177 enum amdgpu_thermal_irq { 178 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 179 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 180 181 AMDGPU_THERMAL_IRQ_LAST 182 }; 183 184 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 185 enum amd_ip_block_type block_type, 186 enum amd_clockgating_state state); 187 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 188 enum amd_ip_block_type block_type, 189 enum amd_powergating_state state); 190 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 191 enum amd_ip_block_type block_type); 192 bool amdgpu_is_idle(struct amdgpu_device *adev, 193 enum amd_ip_block_type block_type); 194 195 struct amdgpu_ip_block_version { 196 enum amd_ip_block_type type; 197 u32 major; 198 u32 minor; 199 u32 rev; 200 const struct amd_ip_funcs *funcs; 201 }; 202 203 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 204 enum amd_ip_block_type type, 205 u32 major, u32 minor); 206 207 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 208 struct amdgpu_device *adev, 209 enum amd_ip_block_type type); 210 211 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 212 struct amdgpu_buffer_funcs { 213 /* maximum bytes in a single operation */ 214 uint32_t copy_max_bytes; 215 216 /* number of dw to reserve per operation */ 217 unsigned copy_num_dw; 218 219 /* used for buffer migration */ 220 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 221 /* src addr in bytes */ 222 uint64_t src_offset, 223 /* dst addr in bytes */ 224 uint64_t dst_offset, 225 /* number of byte to transfer */ 226 uint32_t byte_count); 227 228 /* maximum bytes in a single operation */ 229 uint32_t fill_max_bytes; 230 231 /* number of dw to reserve per operation */ 232 unsigned fill_num_dw; 233 234 /* used for buffer clearing */ 235 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 236 /* value to write to memory */ 237 uint32_t src_data, 238 /* dst addr in bytes */ 239 uint64_t dst_offset, 240 /* number of byte to fill */ 241 uint32_t byte_count); 242 }; 243 244 /* provided by hw blocks that can write ptes, e.g., sdma */ 245 struct amdgpu_vm_pte_funcs { 246 /* copy pte entries from GART */ 247 void (*copy_pte)(struct amdgpu_ib *ib, 248 uint64_t pe, uint64_t src, 249 unsigned count); 250 /* write pte one entry at a time with addr mapping */ 251 void (*write_pte)(struct amdgpu_ib *ib, 252 const dma_addr_t *pages_addr, uint64_t pe, 253 uint64_t addr, unsigned count, 254 uint32_t incr, uint32_t flags); 255 /* for linear pte/pde updates without addr mapping */ 256 void (*set_pte_pde)(struct amdgpu_ib *ib, 257 uint64_t pe, 258 uint64_t addr, unsigned count, 259 uint32_t incr, uint32_t flags); 260 }; 261 262 /* provided by the gmc block */ 263 struct amdgpu_gart_funcs { 264 /* flush the vm tlb via mmio */ 265 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 266 uint32_t vmid); 267 /* write pte/pde updates using the cpu */ 268 int (*set_pte_pde)(struct amdgpu_device *adev, 269 void *cpu_pt_addr, /* cpu addr of page table */ 270 uint32_t gpu_page_idx, /* pte/pde to update */ 271 uint64_t addr, /* addr to write into pte/pde */ 272 uint32_t flags); /* access flags */ 273 }; 274 275 /* provided by the ih block */ 276 struct amdgpu_ih_funcs { 277 /* ring read/write ptr handling, called from interrupt context */ 278 u32 (*get_wptr)(struct amdgpu_device *adev); 279 void (*decode_iv)(struct amdgpu_device *adev, 280 struct amdgpu_iv_entry *entry); 281 void (*set_rptr)(struct amdgpu_device *adev); 282 }; 283 284 /* provided by hw blocks that expose a ring buffer for commands */ 285 struct amdgpu_ring_funcs { 286 /* ring read/write ptr handling */ 287 u32 (*get_rptr)(struct amdgpu_ring *ring); 288 u32 (*get_wptr)(struct amdgpu_ring *ring); 289 void (*set_wptr)(struct amdgpu_ring *ring); 290 /* validating and patching of IBs */ 291 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 292 /* command emit functions */ 293 void (*emit_ib)(struct amdgpu_ring *ring, 294 struct amdgpu_ib *ib, 295 unsigned vm_id, bool ctx_switch); 296 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 297 uint64_t seq, unsigned flags); 298 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 299 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 300 uint64_t pd_addr); 301 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 302 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 303 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 304 uint32_t gds_base, uint32_t gds_size, 305 uint32_t gws_base, uint32_t gws_size, 306 uint32_t oa_base, uint32_t oa_size); 307 /* testing functions */ 308 int (*test_ring)(struct amdgpu_ring *ring); 309 int (*test_ib)(struct amdgpu_ring *ring); 310 /* insert NOP packets */ 311 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 312 /* pad the indirect buffer to the necessary number of dw */ 313 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 314 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 315 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 316 }; 317 318 /* 319 * BIOS. 320 */ 321 bool amdgpu_get_bios(struct amdgpu_device *adev); 322 bool amdgpu_read_bios(struct amdgpu_device *adev); 323 324 /* 325 * Dummy page 326 */ 327 struct amdgpu_dummy_page { 328 struct page *page; 329 dma_addr_t addr; 330 }; 331 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 332 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 333 334 335 /* 336 * Clocks 337 */ 338 339 #define AMDGPU_MAX_PPLL 3 340 341 struct amdgpu_clock { 342 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 343 struct amdgpu_pll spll; 344 struct amdgpu_pll mpll; 345 /* 10 Khz units */ 346 uint32_t default_mclk; 347 uint32_t default_sclk; 348 uint32_t default_dispclk; 349 uint32_t current_dispclk; 350 uint32_t dp_extclk; 351 uint32_t max_pixel_clock; 352 }; 353 354 /* 355 * Fences. 356 */ 357 struct amdgpu_fence_driver { 358 uint64_t gpu_addr; 359 volatile uint32_t *cpu_addr; 360 /* sync_seq is protected by ring emission lock */ 361 uint32_t sync_seq; 362 atomic_t last_seq; 363 bool initialized; 364 struct amdgpu_irq_src *irq_src; 365 unsigned irq_type; 366 struct timer_list fallback_timer; 367 unsigned num_fences_mask; 368 spinlock_t lock; 369 struct fence **fences; 370 }; 371 372 /* some special values for the owner field */ 373 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 374 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 375 376 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 377 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 378 379 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 380 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 381 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 382 383 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 384 unsigned num_hw_submission); 385 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 386 struct amdgpu_irq_src *irq_src, 387 unsigned irq_type); 388 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 389 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 390 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 391 void amdgpu_fence_process(struct amdgpu_ring *ring); 392 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 393 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 394 395 /* 396 * TTM. 397 */ 398 399 #define AMDGPU_TTM_LRU_SIZE 20 400 401 struct amdgpu_mman_lru { 402 struct list_head *lru[TTM_NUM_MEM_TYPES]; 403 struct list_head *swap_lru; 404 }; 405 406 struct amdgpu_mman { 407 struct ttm_bo_global_ref bo_global_ref; 408 struct drm_global_reference mem_global_ref; 409 struct ttm_bo_device bdev; 410 bool mem_global_referenced; 411 bool initialized; 412 413 #if defined(CONFIG_DEBUG_FS) 414 struct dentry *vram; 415 struct dentry *gtt; 416 #endif 417 418 /* buffer handling */ 419 const struct amdgpu_buffer_funcs *buffer_funcs; 420 struct amdgpu_ring *buffer_funcs_ring; 421 /* Scheduler entity for buffer moves */ 422 struct amd_sched_entity entity; 423 424 /* custom LRU management */ 425 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; 426 }; 427 428 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 429 uint64_t src_offset, 430 uint64_t dst_offset, 431 uint32_t byte_count, 432 struct reservation_object *resv, 433 struct fence **fence); 434 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 435 436 struct amdgpu_bo_list_entry { 437 struct amdgpu_bo *robj; 438 struct ttm_validate_buffer tv; 439 struct amdgpu_bo_va *bo_va; 440 uint32_t priority; 441 struct page **user_pages; 442 int user_invalidated; 443 }; 444 445 struct amdgpu_bo_va_mapping { 446 struct list_head list; 447 struct interval_tree_node it; 448 uint64_t offset; 449 uint32_t flags; 450 }; 451 452 /* bo virtual addresses in a specific vm */ 453 struct amdgpu_bo_va { 454 /* protected by bo being reserved */ 455 struct list_head bo_list; 456 struct fence *last_pt_update; 457 unsigned ref_count; 458 459 /* protected by vm mutex and spinlock */ 460 struct list_head vm_status; 461 462 /* mappings for this bo_va */ 463 struct list_head invalids; 464 struct list_head valids; 465 466 /* constant after initialization */ 467 struct amdgpu_vm *vm; 468 struct amdgpu_bo *bo; 469 }; 470 471 #define AMDGPU_GEM_DOMAIN_MAX 0x3 472 473 struct amdgpu_bo { 474 /* Protected by gem.mutex */ 475 struct list_head list; 476 /* Protected by tbo.reserved */ 477 u32 prefered_domains; 478 u32 allowed_domains; 479 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 480 struct ttm_placement placement; 481 struct ttm_buffer_object tbo; 482 struct ttm_bo_kmap_obj kmap; 483 u64 flags; 484 unsigned pin_count; 485 void *kptr; 486 u64 tiling_flags; 487 u64 metadata_flags; 488 void *metadata; 489 u32 metadata_size; 490 /* list of all virtual address to which this bo 491 * is associated to 492 */ 493 struct list_head va; 494 /* Constant after initialization */ 495 struct amdgpu_device *adev; 496 struct drm_gem_object gem_base; 497 struct amdgpu_bo *parent; 498 499 struct ttm_bo_kmap_obj dma_buf_vmap; 500 struct amdgpu_mn *mn; 501 struct list_head mn_list; 502 }; 503 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 504 505 void amdgpu_gem_object_free(struct drm_gem_object *obj); 506 int amdgpu_gem_object_open(struct drm_gem_object *obj, 507 struct drm_file *file_priv); 508 void amdgpu_gem_object_close(struct drm_gem_object *obj, 509 struct drm_file *file_priv); 510 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 511 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 512 struct drm_gem_object * 513 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 514 struct dma_buf_attachment *attach, 515 struct sg_table *sg); 516 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 517 struct drm_gem_object *gobj, 518 int flags); 519 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 520 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 521 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 522 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 523 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 524 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 525 526 /* sub-allocation manager, it has to be protected by another lock. 527 * By conception this is an helper for other part of the driver 528 * like the indirect buffer or semaphore, which both have their 529 * locking. 530 * 531 * Principe is simple, we keep a list of sub allocation in offset 532 * order (first entry has offset == 0, last entry has the highest 533 * offset). 534 * 535 * When allocating new object we first check if there is room at 536 * the end total_size - (last_object_offset + last_object_size) >= 537 * alloc_size. If so we allocate new object there. 538 * 539 * When there is not enough room at the end, we start waiting for 540 * each sub object until we reach object_offset+object_size >= 541 * alloc_size, this object then become the sub object we return. 542 * 543 * Alignment can't be bigger than page size. 544 * 545 * Hole are not considered for allocation to keep things simple. 546 * Assumption is that there won't be hole (all object on same 547 * alignment). 548 */ 549 550 #define AMDGPU_SA_NUM_FENCE_LISTS 32 551 552 struct amdgpu_sa_manager { 553 wait_queue_head_t wq; 554 struct amdgpu_bo *bo; 555 struct list_head *hole; 556 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 557 struct list_head olist; 558 unsigned size; 559 uint64_t gpu_addr; 560 void *cpu_ptr; 561 uint32_t domain; 562 uint32_t align; 563 }; 564 565 /* sub-allocation buffer */ 566 struct amdgpu_sa_bo { 567 struct list_head olist; 568 struct list_head flist; 569 struct amdgpu_sa_manager *manager; 570 unsigned soffset; 571 unsigned eoffset; 572 struct fence *fence; 573 }; 574 575 /* 576 * GEM objects. 577 */ 578 void amdgpu_gem_force_release(struct amdgpu_device *adev); 579 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 580 int alignment, u32 initial_domain, 581 u64 flags, bool kernel, 582 struct drm_gem_object **obj); 583 584 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 585 struct drm_device *dev, 586 struct drm_mode_create_dumb *args); 587 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 588 struct drm_device *dev, 589 uint32_t handle, uint64_t *offset_p); 590 /* 591 * Synchronization 592 */ 593 struct amdgpu_sync { 594 DECLARE_HASHTABLE(fences, 4); 595 struct fence *last_vm_update; 596 }; 597 598 void amdgpu_sync_create(struct amdgpu_sync *sync); 599 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 600 struct fence *f); 601 int amdgpu_sync_resv(struct amdgpu_device *adev, 602 struct amdgpu_sync *sync, 603 struct reservation_object *resv, 604 void *owner); 605 struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, 606 struct amdgpu_ring *ring); 607 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 608 void amdgpu_sync_free(struct amdgpu_sync *sync); 609 int amdgpu_sync_init(void); 610 void amdgpu_sync_fini(void); 611 int amdgpu_fence_slab_init(void); 612 void amdgpu_fence_slab_fini(void); 613 614 /* 615 * GART structures, functions & helpers 616 */ 617 struct amdgpu_mc; 618 619 #define AMDGPU_GPU_PAGE_SIZE 4096 620 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 621 #define AMDGPU_GPU_PAGE_SHIFT 12 622 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 623 624 struct amdgpu_gart { 625 dma_addr_t table_addr; 626 struct amdgpu_bo *robj; 627 void *ptr; 628 unsigned num_gpu_pages; 629 unsigned num_cpu_pages; 630 unsigned table_size; 631 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 632 struct page **pages; 633 #endif 634 bool ready; 635 const struct amdgpu_gart_funcs *gart_funcs; 636 }; 637 638 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 639 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 640 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 641 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 642 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 643 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 644 int amdgpu_gart_init(struct amdgpu_device *adev); 645 void amdgpu_gart_fini(struct amdgpu_device *adev); 646 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 647 int pages); 648 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 649 int pages, struct page **pagelist, 650 dma_addr_t *dma_addr, uint32_t flags); 651 652 /* 653 * GPU MC structures, functions & helpers 654 */ 655 struct amdgpu_mc { 656 resource_size_t aper_size; 657 resource_size_t aper_base; 658 resource_size_t agp_base; 659 /* for some chips with <= 32MB we need to lie 660 * about vram size near mc fb location */ 661 u64 mc_vram_size; 662 u64 visible_vram_size; 663 u64 gtt_size; 664 u64 gtt_start; 665 u64 gtt_end; 666 u64 vram_start; 667 u64 vram_end; 668 unsigned vram_width; 669 u64 real_vram_size; 670 int vram_mtrr; 671 u64 gtt_base_align; 672 u64 mc_mask; 673 const struct firmware *fw; /* MC firmware */ 674 uint32_t fw_version; 675 struct amdgpu_irq_src vm_fault; 676 uint32_t vram_type; 677 }; 678 679 /* 680 * GPU doorbell structures, functions & helpers 681 */ 682 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 683 { 684 AMDGPU_DOORBELL_KIQ = 0x000, 685 AMDGPU_DOORBELL_HIQ = 0x001, 686 AMDGPU_DOORBELL_DIQ = 0x002, 687 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 688 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 689 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 690 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 691 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 692 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 693 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 694 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 695 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 696 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 697 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 698 AMDGPU_DOORBELL_IH = 0x1E8, 699 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 700 AMDGPU_DOORBELL_INVALID = 0xFFFF 701 } AMDGPU_DOORBELL_ASSIGNMENT; 702 703 struct amdgpu_doorbell { 704 /* doorbell mmio */ 705 resource_size_t base; 706 resource_size_t size; 707 u32 __iomem *ptr; 708 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 709 }; 710 711 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 712 phys_addr_t *aperture_base, 713 size_t *aperture_size, 714 size_t *start_offset); 715 716 /* 717 * IRQS. 718 */ 719 720 struct amdgpu_flip_work { 721 struct work_struct flip_work; 722 struct work_struct unpin_work; 723 struct amdgpu_device *adev; 724 int crtc_id; 725 uint64_t base; 726 struct drm_pending_vblank_event *event; 727 struct amdgpu_bo *old_rbo; 728 struct fence *excl; 729 unsigned shared_count; 730 struct fence **shared; 731 struct fence_cb cb; 732 bool async; 733 }; 734 735 736 /* 737 * CP & rings. 738 */ 739 740 struct amdgpu_ib { 741 struct amdgpu_sa_bo *sa_bo; 742 uint32_t length_dw; 743 uint64_t gpu_addr; 744 uint32_t *ptr; 745 uint32_t flags; 746 }; 747 748 enum amdgpu_ring_type { 749 AMDGPU_RING_TYPE_GFX, 750 AMDGPU_RING_TYPE_COMPUTE, 751 AMDGPU_RING_TYPE_SDMA, 752 AMDGPU_RING_TYPE_UVD, 753 AMDGPU_RING_TYPE_VCE 754 }; 755 756 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 757 758 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 759 struct amdgpu_job **job, struct amdgpu_vm *vm); 760 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 761 struct amdgpu_job **job); 762 763 void amdgpu_job_free_resources(struct amdgpu_job *job); 764 void amdgpu_job_free(struct amdgpu_job *job); 765 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 766 struct amd_sched_entity *entity, void *owner, 767 struct fence **f); 768 769 struct amdgpu_ring { 770 struct amdgpu_device *adev; 771 const struct amdgpu_ring_funcs *funcs; 772 struct amdgpu_fence_driver fence_drv; 773 struct amd_gpu_scheduler sched; 774 775 spinlock_t fence_lock; 776 struct amdgpu_bo *ring_obj; 777 volatile uint32_t *ring; 778 unsigned rptr_offs; 779 unsigned wptr; 780 unsigned wptr_old; 781 unsigned ring_size; 782 unsigned max_dw; 783 int count_dw; 784 uint64_t gpu_addr; 785 uint32_t align_mask; 786 uint32_t ptr_mask; 787 bool ready; 788 u32 nop; 789 u32 idx; 790 u32 me; 791 u32 pipe; 792 u32 queue; 793 struct amdgpu_bo *mqd_obj; 794 u32 doorbell_index; 795 bool use_doorbell; 796 unsigned wptr_offs; 797 unsigned fence_offs; 798 uint64_t current_ctx; 799 enum amdgpu_ring_type type; 800 char name[16]; 801 unsigned cond_exe_offs; 802 u64 cond_exe_gpu_addr; 803 volatile u32 *cond_exe_cpu_addr; 804 #if defined(CONFIG_DEBUG_FS) 805 struct dentry *ent; 806 #endif 807 }; 808 809 /* 810 * VM 811 */ 812 813 /* maximum number of VMIDs */ 814 #define AMDGPU_NUM_VM 16 815 816 /* number of entries in page table */ 817 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 818 819 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 820 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 821 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 822 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 823 824 #define AMDGPU_PTE_VALID (1 << 0) 825 #define AMDGPU_PTE_SYSTEM (1 << 1) 826 #define AMDGPU_PTE_SNOOPED (1 << 2) 827 828 /* VI only */ 829 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 830 831 #define AMDGPU_PTE_READABLE (1 << 5) 832 #define AMDGPU_PTE_WRITEABLE (1 << 6) 833 834 /* PTE (Page Table Entry) fragment field for different page sizes */ 835 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 836 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 837 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 838 839 /* How to programm VM fault handling */ 840 #define AMDGPU_VM_FAULT_STOP_NEVER 0 841 #define AMDGPU_VM_FAULT_STOP_FIRST 1 842 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 843 844 struct amdgpu_vm_pt { 845 struct amdgpu_bo_list_entry entry; 846 uint64_t addr; 847 }; 848 849 struct amdgpu_vm { 850 /* tree of virtual addresses mapped */ 851 struct rb_root va; 852 853 /* protecting invalidated */ 854 spinlock_t status_lock; 855 856 /* BOs moved, but not yet updated in the PT */ 857 struct list_head invalidated; 858 859 /* BOs cleared in the PT because of a move */ 860 struct list_head cleared; 861 862 /* BO mappings freed, but not yet updated in the PT */ 863 struct list_head freed; 864 865 /* contains the page directory */ 866 struct amdgpu_bo *page_directory; 867 unsigned max_pde_used; 868 struct fence *page_directory_fence; 869 uint64_t last_eviction_counter; 870 871 /* array of page tables, one for each page directory entry */ 872 struct amdgpu_vm_pt *page_tables; 873 874 /* for id and flush management per ring */ 875 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 876 877 /* protecting freed */ 878 spinlock_t freed_lock; 879 880 /* Scheduler entity for page table updates */ 881 struct amd_sched_entity entity; 882 883 /* client id */ 884 u64 client_id; 885 }; 886 887 struct amdgpu_vm_id { 888 struct list_head list; 889 struct fence *first; 890 struct amdgpu_sync active; 891 struct fence *last_flush; 892 atomic64_t owner; 893 894 uint64_t pd_gpu_addr; 895 /* last flushed PD/PT update */ 896 struct fence *flushed_updates; 897 898 uint32_t current_gpu_reset_count; 899 900 uint32_t gds_base; 901 uint32_t gds_size; 902 uint32_t gws_base; 903 uint32_t gws_size; 904 uint32_t oa_base; 905 uint32_t oa_size; 906 }; 907 908 struct amdgpu_vm_manager { 909 /* Handling of VMIDs */ 910 struct mutex lock; 911 unsigned num_ids; 912 struct list_head ids_lru; 913 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 914 915 /* Handling of VM fences */ 916 u64 fence_context; 917 unsigned seqno[AMDGPU_MAX_RINGS]; 918 919 uint32_t max_pfn; 920 /* vram base address for page table entry */ 921 u64 vram_base_offset; 922 /* is vm enabled? */ 923 bool enabled; 924 /* vm pte handling */ 925 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 926 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 927 unsigned vm_pte_num_rings; 928 atomic_t vm_pte_next_ring; 929 /* client id counter */ 930 atomic64_t client_counter; 931 }; 932 933 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 934 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 935 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 936 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 937 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 938 struct list_head *validated, 939 struct amdgpu_bo_list_entry *entry); 940 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 941 struct list_head *duplicates); 942 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 943 struct amdgpu_vm *vm); 944 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 945 struct amdgpu_sync *sync, struct fence *fence, 946 struct amdgpu_job *job); 947 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); 948 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 949 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 950 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 951 struct amdgpu_vm *vm); 952 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 953 struct amdgpu_vm *vm); 954 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 955 struct amdgpu_sync *sync); 956 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 957 struct amdgpu_bo_va *bo_va, 958 struct ttm_mem_reg *mem); 959 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 960 struct amdgpu_bo *bo); 961 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 962 struct amdgpu_bo *bo); 963 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 964 struct amdgpu_vm *vm, 965 struct amdgpu_bo *bo); 966 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 967 struct amdgpu_bo_va *bo_va, 968 uint64_t addr, uint64_t offset, 969 uint64_t size, uint32_t flags); 970 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 971 struct amdgpu_bo_va *bo_va, 972 uint64_t addr); 973 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 974 struct amdgpu_bo_va *bo_va); 975 976 /* 977 * context related structures 978 */ 979 980 struct amdgpu_ctx_ring { 981 uint64_t sequence; 982 struct fence **fences; 983 struct amd_sched_entity entity; 984 }; 985 986 struct amdgpu_ctx { 987 struct kref refcount; 988 struct amdgpu_device *adev; 989 unsigned reset_counter; 990 spinlock_t ring_lock; 991 struct fence **fences; 992 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 993 }; 994 995 struct amdgpu_ctx_mgr { 996 struct amdgpu_device *adev; 997 struct mutex lock; 998 /* protected by lock */ 999 struct idr ctx_handles; 1000 }; 1001 1002 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1003 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1004 1005 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1006 struct fence *fence); 1007 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1008 struct amdgpu_ring *ring, uint64_t seq); 1009 1010 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1011 struct drm_file *filp); 1012 1013 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1014 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1015 1016 /* 1017 * file private structure 1018 */ 1019 1020 struct amdgpu_fpriv { 1021 struct amdgpu_vm vm; 1022 struct mutex bo_list_lock; 1023 struct idr bo_list_handles; 1024 struct amdgpu_ctx_mgr ctx_mgr; 1025 }; 1026 1027 /* 1028 * residency list 1029 */ 1030 1031 struct amdgpu_bo_list { 1032 struct mutex lock; 1033 struct amdgpu_bo *gds_obj; 1034 struct amdgpu_bo *gws_obj; 1035 struct amdgpu_bo *oa_obj; 1036 unsigned first_userptr; 1037 unsigned num_entries; 1038 struct amdgpu_bo_list_entry *array; 1039 }; 1040 1041 struct amdgpu_bo_list * 1042 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1043 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1044 struct list_head *validated); 1045 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1046 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1047 1048 /* 1049 * GFX stuff 1050 */ 1051 #include "clearstate_defs.h" 1052 1053 struct amdgpu_rlc_funcs { 1054 void (*enter_safe_mode)(struct amdgpu_device *adev); 1055 void (*exit_safe_mode)(struct amdgpu_device *adev); 1056 }; 1057 1058 struct amdgpu_rlc { 1059 /* for power gating */ 1060 struct amdgpu_bo *save_restore_obj; 1061 uint64_t save_restore_gpu_addr; 1062 volatile uint32_t *sr_ptr; 1063 const u32 *reg_list; 1064 u32 reg_list_size; 1065 /* for clear state */ 1066 struct amdgpu_bo *clear_state_obj; 1067 uint64_t clear_state_gpu_addr; 1068 volatile uint32_t *cs_ptr; 1069 const struct cs_section_def *cs_data; 1070 u32 clear_state_size; 1071 /* for cp tables */ 1072 struct amdgpu_bo *cp_table_obj; 1073 uint64_t cp_table_gpu_addr; 1074 volatile uint32_t *cp_table_ptr; 1075 u32 cp_table_size; 1076 1077 /* safe mode for updating CG/PG state */ 1078 bool in_safe_mode; 1079 const struct amdgpu_rlc_funcs *funcs; 1080 1081 /* for firmware data */ 1082 u32 save_and_restore_offset; 1083 u32 clear_state_descriptor_offset; 1084 u32 avail_scratch_ram_locations; 1085 u32 reg_restore_list_size; 1086 u32 reg_list_format_start; 1087 u32 reg_list_format_separate_start; 1088 u32 starting_offsets_start; 1089 u32 reg_list_format_size_bytes; 1090 u32 reg_list_size_bytes; 1091 1092 u32 *register_list_format; 1093 u32 *register_restore; 1094 }; 1095 1096 struct amdgpu_mec { 1097 struct amdgpu_bo *hpd_eop_obj; 1098 u64 hpd_eop_gpu_addr; 1099 u32 num_pipe; 1100 u32 num_mec; 1101 u32 num_queue; 1102 }; 1103 1104 /* 1105 * GPU scratch registers structures, functions & helpers 1106 */ 1107 struct amdgpu_scratch { 1108 unsigned num_reg; 1109 uint32_t reg_base; 1110 bool free[32]; 1111 uint32_t reg[32]; 1112 }; 1113 1114 /* 1115 * GFX configurations 1116 */ 1117 struct amdgpu_gca_config { 1118 unsigned max_shader_engines; 1119 unsigned max_tile_pipes; 1120 unsigned max_cu_per_sh; 1121 unsigned max_sh_per_se; 1122 unsigned max_backends_per_se; 1123 unsigned max_texture_channel_caches; 1124 unsigned max_gprs; 1125 unsigned max_gs_threads; 1126 unsigned max_hw_contexts; 1127 unsigned sc_prim_fifo_size_frontend; 1128 unsigned sc_prim_fifo_size_backend; 1129 unsigned sc_hiz_tile_fifo_size; 1130 unsigned sc_earlyz_tile_fifo_size; 1131 1132 unsigned num_tile_pipes; 1133 unsigned backend_enable_mask; 1134 unsigned mem_max_burst_length_bytes; 1135 unsigned mem_row_size_in_kb; 1136 unsigned shader_engine_tile_size; 1137 unsigned num_gpus; 1138 unsigned multi_gpu_tile_size; 1139 unsigned mc_arb_ramcfg; 1140 unsigned gb_addr_config; 1141 unsigned num_rbs; 1142 1143 uint32_t tile_mode_array[32]; 1144 uint32_t macrotile_mode_array[16]; 1145 }; 1146 1147 struct amdgpu_cu_info { 1148 uint32_t number; /* total active CU number */ 1149 uint32_t ao_cu_mask; 1150 uint32_t bitmap[4][4]; 1151 }; 1152 1153 struct amdgpu_gfx_funcs { 1154 /* get the gpu clock counter */ 1155 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1156 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 1157 }; 1158 1159 struct amdgpu_gfx { 1160 struct mutex gpu_clock_mutex; 1161 struct amdgpu_gca_config config; 1162 struct amdgpu_rlc rlc; 1163 struct amdgpu_mec mec; 1164 struct amdgpu_scratch scratch; 1165 const struct firmware *me_fw; /* ME firmware */ 1166 uint32_t me_fw_version; 1167 const struct firmware *pfp_fw; /* PFP firmware */ 1168 uint32_t pfp_fw_version; 1169 const struct firmware *ce_fw; /* CE firmware */ 1170 uint32_t ce_fw_version; 1171 const struct firmware *rlc_fw; /* RLC firmware */ 1172 uint32_t rlc_fw_version; 1173 const struct firmware *mec_fw; /* MEC firmware */ 1174 uint32_t mec_fw_version; 1175 const struct firmware *mec2_fw; /* MEC2 firmware */ 1176 uint32_t mec2_fw_version; 1177 uint32_t me_feature_version; 1178 uint32_t ce_feature_version; 1179 uint32_t pfp_feature_version; 1180 uint32_t rlc_feature_version; 1181 uint32_t mec_feature_version; 1182 uint32_t mec2_feature_version; 1183 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1184 unsigned num_gfx_rings; 1185 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1186 unsigned num_compute_rings; 1187 struct amdgpu_irq_src eop_irq; 1188 struct amdgpu_irq_src priv_reg_irq; 1189 struct amdgpu_irq_src priv_inst_irq; 1190 /* gfx status */ 1191 uint32_t gfx_current_status; 1192 /* ce ram size*/ 1193 unsigned ce_ram_size; 1194 struct amdgpu_cu_info cu_info; 1195 const struct amdgpu_gfx_funcs *funcs; 1196 }; 1197 1198 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1199 unsigned size, struct amdgpu_ib *ib); 1200 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1201 struct fence *f); 1202 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1203 struct amdgpu_ib *ib, struct fence *last_vm_update, 1204 struct amdgpu_job *job, struct fence **f); 1205 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1206 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1207 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1208 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1209 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1210 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 1211 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1212 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1213 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1214 unsigned ring_size, u32 nop, u32 align_mask, 1215 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1216 enum amdgpu_ring_type ring_type); 1217 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1218 1219 /* 1220 * CS. 1221 */ 1222 struct amdgpu_cs_chunk { 1223 uint32_t chunk_id; 1224 uint32_t length_dw; 1225 void *kdata; 1226 }; 1227 1228 struct amdgpu_cs_parser { 1229 struct amdgpu_device *adev; 1230 struct drm_file *filp; 1231 struct amdgpu_ctx *ctx; 1232 1233 /* chunks */ 1234 unsigned nchunks; 1235 struct amdgpu_cs_chunk *chunks; 1236 1237 /* scheduler job object */ 1238 struct amdgpu_job *job; 1239 1240 /* buffer objects */ 1241 struct ww_acquire_ctx ticket; 1242 struct amdgpu_bo_list *bo_list; 1243 struct amdgpu_bo_list_entry vm_pd; 1244 struct list_head validated; 1245 struct fence *fence; 1246 uint64_t bytes_moved_threshold; 1247 uint64_t bytes_moved; 1248 1249 /* user fence */ 1250 struct amdgpu_bo_list_entry uf_entry; 1251 }; 1252 1253 struct amdgpu_job { 1254 struct amd_sched_job base; 1255 struct amdgpu_device *adev; 1256 struct amdgpu_vm *vm; 1257 struct amdgpu_ring *ring; 1258 struct amdgpu_sync sync; 1259 struct amdgpu_ib *ibs; 1260 struct fence *fence; /* the hw fence */ 1261 uint32_t num_ibs; 1262 void *owner; 1263 uint64_t ctx; 1264 bool vm_needs_flush; 1265 unsigned vm_id; 1266 uint64_t vm_pd_addr; 1267 uint32_t gds_base, gds_size; 1268 uint32_t gws_base, gws_size; 1269 uint32_t oa_base, oa_size; 1270 1271 /* user fence handling */ 1272 uint64_t uf_addr; 1273 uint64_t uf_sequence; 1274 1275 }; 1276 #define to_amdgpu_job(sched_job) \ 1277 container_of((sched_job), struct amdgpu_job, base) 1278 1279 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1280 uint32_t ib_idx, int idx) 1281 { 1282 return p->job->ibs[ib_idx].ptr[idx]; 1283 } 1284 1285 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1286 uint32_t ib_idx, int idx, 1287 uint32_t value) 1288 { 1289 p->job->ibs[ib_idx].ptr[idx] = value; 1290 } 1291 1292 /* 1293 * Writeback 1294 */ 1295 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1296 1297 struct amdgpu_wb { 1298 struct amdgpu_bo *wb_obj; 1299 volatile uint32_t *wb; 1300 uint64_t gpu_addr; 1301 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1302 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1303 }; 1304 1305 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1306 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1307 1308 1309 1310 enum amdgpu_int_thermal_type { 1311 THERMAL_TYPE_NONE, 1312 THERMAL_TYPE_EXTERNAL, 1313 THERMAL_TYPE_EXTERNAL_GPIO, 1314 THERMAL_TYPE_RV6XX, 1315 THERMAL_TYPE_RV770, 1316 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1317 THERMAL_TYPE_EVERGREEN, 1318 THERMAL_TYPE_SUMO, 1319 THERMAL_TYPE_NI, 1320 THERMAL_TYPE_SI, 1321 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1322 THERMAL_TYPE_CI, 1323 THERMAL_TYPE_KV, 1324 }; 1325 1326 enum amdgpu_dpm_auto_throttle_src { 1327 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1328 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1329 }; 1330 1331 enum amdgpu_dpm_event_src { 1332 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1333 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1334 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1335 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1336 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1337 }; 1338 1339 #define AMDGPU_MAX_VCE_LEVELS 6 1340 1341 enum amdgpu_vce_level { 1342 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1343 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1344 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1345 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1346 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1347 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1348 }; 1349 1350 struct amdgpu_ps { 1351 u32 caps; /* vbios flags */ 1352 u32 class; /* vbios flags */ 1353 u32 class2; /* vbios flags */ 1354 /* UVD clocks */ 1355 u32 vclk; 1356 u32 dclk; 1357 /* VCE clocks */ 1358 u32 evclk; 1359 u32 ecclk; 1360 bool vce_active; 1361 enum amdgpu_vce_level vce_level; 1362 /* asic priv */ 1363 void *ps_priv; 1364 }; 1365 1366 struct amdgpu_dpm_thermal { 1367 /* thermal interrupt work */ 1368 struct work_struct work; 1369 /* low temperature threshold */ 1370 int min_temp; 1371 /* high temperature threshold */ 1372 int max_temp; 1373 /* was last interrupt low to high or high to low */ 1374 bool high_to_low; 1375 /* interrupt source */ 1376 struct amdgpu_irq_src irq; 1377 }; 1378 1379 enum amdgpu_clk_action 1380 { 1381 AMDGPU_SCLK_UP = 1, 1382 AMDGPU_SCLK_DOWN 1383 }; 1384 1385 struct amdgpu_blacklist_clocks 1386 { 1387 u32 sclk; 1388 u32 mclk; 1389 enum amdgpu_clk_action action; 1390 }; 1391 1392 struct amdgpu_clock_and_voltage_limits { 1393 u32 sclk; 1394 u32 mclk; 1395 u16 vddc; 1396 u16 vddci; 1397 }; 1398 1399 struct amdgpu_clock_array { 1400 u32 count; 1401 u32 *values; 1402 }; 1403 1404 struct amdgpu_clock_voltage_dependency_entry { 1405 u32 clk; 1406 u16 v; 1407 }; 1408 1409 struct amdgpu_clock_voltage_dependency_table { 1410 u32 count; 1411 struct amdgpu_clock_voltage_dependency_entry *entries; 1412 }; 1413 1414 union amdgpu_cac_leakage_entry { 1415 struct { 1416 u16 vddc; 1417 u32 leakage; 1418 }; 1419 struct { 1420 u16 vddc1; 1421 u16 vddc2; 1422 u16 vddc3; 1423 }; 1424 }; 1425 1426 struct amdgpu_cac_leakage_table { 1427 u32 count; 1428 union amdgpu_cac_leakage_entry *entries; 1429 }; 1430 1431 struct amdgpu_phase_shedding_limits_entry { 1432 u16 voltage; 1433 u32 sclk; 1434 u32 mclk; 1435 }; 1436 1437 struct amdgpu_phase_shedding_limits_table { 1438 u32 count; 1439 struct amdgpu_phase_shedding_limits_entry *entries; 1440 }; 1441 1442 struct amdgpu_uvd_clock_voltage_dependency_entry { 1443 u32 vclk; 1444 u32 dclk; 1445 u16 v; 1446 }; 1447 1448 struct amdgpu_uvd_clock_voltage_dependency_table { 1449 u8 count; 1450 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1451 }; 1452 1453 struct amdgpu_vce_clock_voltage_dependency_entry { 1454 u32 ecclk; 1455 u32 evclk; 1456 u16 v; 1457 }; 1458 1459 struct amdgpu_vce_clock_voltage_dependency_table { 1460 u8 count; 1461 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1462 }; 1463 1464 struct amdgpu_ppm_table { 1465 u8 ppm_design; 1466 u16 cpu_core_number; 1467 u32 platform_tdp; 1468 u32 small_ac_platform_tdp; 1469 u32 platform_tdc; 1470 u32 small_ac_platform_tdc; 1471 u32 apu_tdp; 1472 u32 dgpu_tdp; 1473 u32 dgpu_ulv_power; 1474 u32 tj_max; 1475 }; 1476 1477 struct amdgpu_cac_tdp_table { 1478 u16 tdp; 1479 u16 configurable_tdp; 1480 u16 tdc; 1481 u16 battery_power_limit; 1482 u16 small_power_limit; 1483 u16 low_cac_leakage; 1484 u16 high_cac_leakage; 1485 u16 maximum_power_delivery_limit; 1486 }; 1487 1488 struct amdgpu_dpm_dynamic_state { 1489 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1490 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1491 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1492 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1493 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1494 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1495 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1496 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1497 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1498 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1499 struct amdgpu_clock_array valid_sclk_values; 1500 struct amdgpu_clock_array valid_mclk_values; 1501 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1502 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1503 u32 mclk_sclk_ratio; 1504 u32 sclk_mclk_delta; 1505 u16 vddc_vddci_delta; 1506 u16 min_vddc_for_pcie_gen2; 1507 struct amdgpu_cac_leakage_table cac_leakage_table; 1508 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1509 struct amdgpu_ppm_table *ppm_table; 1510 struct amdgpu_cac_tdp_table *cac_tdp_table; 1511 }; 1512 1513 struct amdgpu_dpm_fan { 1514 u16 t_min; 1515 u16 t_med; 1516 u16 t_high; 1517 u16 pwm_min; 1518 u16 pwm_med; 1519 u16 pwm_high; 1520 u8 t_hyst; 1521 u32 cycle_delay; 1522 u16 t_max; 1523 u8 control_mode; 1524 u16 default_max_fan_pwm; 1525 u16 default_fan_output_sensitivity; 1526 u16 fan_output_sensitivity; 1527 bool ucode_fan_control; 1528 }; 1529 1530 enum amdgpu_pcie_gen { 1531 AMDGPU_PCIE_GEN1 = 0, 1532 AMDGPU_PCIE_GEN2 = 1, 1533 AMDGPU_PCIE_GEN3 = 2, 1534 AMDGPU_PCIE_GEN_INVALID = 0xffff 1535 }; 1536 1537 enum amdgpu_dpm_forced_level { 1538 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1539 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1540 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1541 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1542 }; 1543 1544 struct amdgpu_vce_state { 1545 /* vce clocks */ 1546 u32 evclk; 1547 u32 ecclk; 1548 /* gpu clocks */ 1549 u32 sclk; 1550 u32 mclk; 1551 u8 clk_idx; 1552 u8 pstate; 1553 }; 1554 1555 struct amdgpu_dpm_funcs { 1556 int (*get_temperature)(struct amdgpu_device *adev); 1557 int (*pre_set_power_state)(struct amdgpu_device *adev); 1558 int (*set_power_state)(struct amdgpu_device *adev); 1559 void (*post_set_power_state)(struct amdgpu_device *adev); 1560 void (*display_configuration_changed)(struct amdgpu_device *adev); 1561 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1562 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1563 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1564 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1565 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1566 bool (*vblank_too_short)(struct amdgpu_device *adev); 1567 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1568 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1569 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1570 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1571 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1572 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1573 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1574 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); 1575 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); 1576 int (*get_sclk_od)(struct amdgpu_device *adev); 1577 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); 1578 int (*get_mclk_od)(struct amdgpu_device *adev); 1579 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); 1580 }; 1581 1582 struct amdgpu_dpm { 1583 struct amdgpu_ps *ps; 1584 /* number of valid power states */ 1585 int num_ps; 1586 /* current power state that is active */ 1587 struct amdgpu_ps *current_ps; 1588 /* requested power state */ 1589 struct amdgpu_ps *requested_ps; 1590 /* boot up power state */ 1591 struct amdgpu_ps *boot_ps; 1592 /* default uvd power state */ 1593 struct amdgpu_ps *uvd_ps; 1594 /* vce requirements */ 1595 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1596 enum amdgpu_vce_level vce_level; 1597 enum amd_pm_state_type state; 1598 enum amd_pm_state_type user_state; 1599 u32 platform_caps; 1600 u32 voltage_response_time; 1601 u32 backbias_response_time; 1602 void *priv; 1603 u32 new_active_crtcs; 1604 int new_active_crtc_count; 1605 u32 current_active_crtcs; 1606 int current_active_crtc_count; 1607 struct amdgpu_dpm_dynamic_state dyn_state; 1608 struct amdgpu_dpm_fan fan; 1609 u32 tdp_limit; 1610 u32 near_tdp_limit; 1611 u32 near_tdp_limit_adjusted; 1612 u32 sq_ramping_threshold; 1613 u32 cac_leakage; 1614 u16 tdp_od_limit; 1615 u32 tdp_adjustment; 1616 u16 load_line_slope; 1617 bool power_control; 1618 bool ac_power; 1619 /* special states active */ 1620 bool thermal_active; 1621 bool uvd_active; 1622 bool vce_active; 1623 /* thermal handling */ 1624 struct amdgpu_dpm_thermal thermal; 1625 /* forced levels */ 1626 enum amdgpu_dpm_forced_level forced_level; 1627 }; 1628 1629 struct amdgpu_pm { 1630 struct mutex mutex; 1631 u32 current_sclk; 1632 u32 current_mclk; 1633 u32 default_sclk; 1634 u32 default_mclk; 1635 struct amdgpu_i2c_chan *i2c_bus; 1636 /* internal thermal controller on rv6xx+ */ 1637 enum amdgpu_int_thermal_type int_thermal_type; 1638 struct device *int_hwmon_dev; 1639 /* fan control parameters */ 1640 bool no_fan; 1641 u8 fan_pulses_per_revolution; 1642 u8 fan_min_rpm; 1643 u8 fan_max_rpm; 1644 /* dpm */ 1645 bool dpm_enabled; 1646 bool sysfs_initialized; 1647 struct amdgpu_dpm dpm; 1648 const struct firmware *fw; /* SMC firmware */ 1649 uint32_t fw_version; 1650 const struct amdgpu_dpm_funcs *funcs; 1651 uint32_t pcie_gen_mask; 1652 uint32_t pcie_mlw_mask; 1653 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1654 }; 1655 1656 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1657 1658 /* 1659 * UVD 1660 */ 1661 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1662 #define AMDGPU_MAX_UVD_HANDLES 40 1663 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1664 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1665 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1666 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1667 1668 struct amdgpu_uvd { 1669 struct amdgpu_bo *vcpu_bo; 1670 void *cpu_addr; 1671 uint64_t gpu_addr; 1672 unsigned fw_version; 1673 void *saved_bo; 1674 unsigned max_handles; 1675 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1676 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1677 struct delayed_work idle_work; 1678 const struct firmware *fw; /* UVD firmware */ 1679 struct amdgpu_ring ring; 1680 struct amdgpu_irq_src irq; 1681 bool address_64_bit; 1682 struct amd_sched_entity entity; 1683 }; 1684 1685 /* 1686 * VCE 1687 */ 1688 #define AMDGPU_MAX_VCE_HANDLES 16 1689 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1690 1691 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1692 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1693 1694 struct amdgpu_vce { 1695 struct amdgpu_bo *vcpu_bo; 1696 uint64_t gpu_addr; 1697 unsigned fw_version; 1698 unsigned fb_version; 1699 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1700 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1701 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1702 struct delayed_work idle_work; 1703 const struct firmware *fw; /* VCE firmware */ 1704 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1705 struct amdgpu_irq_src irq; 1706 unsigned harvest_config; 1707 struct amd_sched_entity entity; 1708 }; 1709 1710 /* 1711 * SDMA 1712 */ 1713 struct amdgpu_sdma_instance { 1714 /* SDMA firmware */ 1715 const struct firmware *fw; 1716 uint32_t fw_version; 1717 uint32_t feature_version; 1718 1719 struct amdgpu_ring ring; 1720 bool burst_nop; 1721 }; 1722 1723 struct amdgpu_sdma { 1724 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1725 struct amdgpu_irq_src trap_irq; 1726 struct amdgpu_irq_src illegal_inst_irq; 1727 int num_instances; 1728 }; 1729 1730 /* 1731 * Firmware 1732 */ 1733 struct amdgpu_firmware { 1734 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1735 bool smu_load; 1736 struct amdgpu_bo *fw_buf; 1737 unsigned int fw_size; 1738 }; 1739 1740 /* 1741 * Benchmarking 1742 */ 1743 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1744 1745 1746 /* 1747 * Testing 1748 */ 1749 void amdgpu_test_moves(struct amdgpu_device *adev); 1750 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1751 struct amdgpu_ring *cpA, 1752 struct amdgpu_ring *cpB); 1753 void amdgpu_test_syncing(struct amdgpu_device *adev); 1754 1755 /* 1756 * MMU Notifier 1757 */ 1758 #if defined(CONFIG_MMU_NOTIFIER) 1759 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1760 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1761 #else 1762 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1763 { 1764 return -ENODEV; 1765 } 1766 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1767 #endif 1768 1769 /* 1770 * Debugfs 1771 */ 1772 struct amdgpu_debugfs { 1773 const struct drm_info_list *files; 1774 unsigned num_files; 1775 }; 1776 1777 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1778 const struct drm_info_list *files, 1779 unsigned nfiles); 1780 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1781 1782 #if defined(CONFIG_DEBUG_FS) 1783 int amdgpu_debugfs_init(struct drm_minor *minor); 1784 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1785 #endif 1786 1787 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1788 1789 /* 1790 * amdgpu smumgr functions 1791 */ 1792 struct amdgpu_smumgr_funcs { 1793 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1794 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1795 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1796 }; 1797 1798 /* 1799 * amdgpu smumgr 1800 */ 1801 struct amdgpu_smumgr { 1802 struct amdgpu_bo *toc_buf; 1803 struct amdgpu_bo *smu_buf; 1804 /* asic priv smu data */ 1805 void *priv; 1806 spinlock_t smu_lock; 1807 /* smumgr functions */ 1808 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1809 /* ucode loading complete flag */ 1810 uint32_t fw_flags; 1811 }; 1812 1813 /* 1814 * ASIC specific register table accessible by UMD 1815 */ 1816 struct amdgpu_allowed_register_entry { 1817 uint32_t reg_offset; 1818 bool untouched; 1819 bool grbm_indexed; 1820 }; 1821 1822 /* 1823 * ASIC specific functions. 1824 */ 1825 struct amdgpu_asic_funcs { 1826 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1827 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1828 u8 *bios, u32 length_bytes); 1829 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1830 u32 sh_num, u32 reg_offset, u32 *value); 1831 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1832 int (*reset)(struct amdgpu_device *adev); 1833 /* get the reference clock */ 1834 u32 (*get_xclk)(struct amdgpu_device *adev); 1835 /* MM block clocks */ 1836 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1837 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1838 /* query virtual capabilities */ 1839 u32 (*get_virtual_caps)(struct amdgpu_device *adev); 1840 }; 1841 1842 /* 1843 * IOCTL. 1844 */ 1845 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1846 struct drm_file *filp); 1847 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1848 struct drm_file *filp); 1849 1850 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1853 struct drm_file *filp); 1854 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1857 struct drm_file *filp); 1858 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1859 struct drm_file *filp); 1860 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1861 struct drm_file *filp); 1862 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1863 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1864 1865 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1866 struct drm_file *filp); 1867 1868 /* VRAM scratch page for HDP bug, default vram page */ 1869 struct amdgpu_vram_scratch { 1870 struct amdgpu_bo *robj; 1871 volatile uint32_t *ptr; 1872 u64 gpu_addr; 1873 }; 1874 1875 /* 1876 * ACPI 1877 */ 1878 struct amdgpu_atif_notification_cfg { 1879 bool enabled; 1880 int command_code; 1881 }; 1882 1883 struct amdgpu_atif_notifications { 1884 bool display_switch; 1885 bool expansion_mode_change; 1886 bool thermal_state; 1887 bool forced_power_state; 1888 bool system_power_state; 1889 bool display_conf_change; 1890 bool px_gfx_switch; 1891 bool brightness_change; 1892 bool dgpu_display_event; 1893 }; 1894 1895 struct amdgpu_atif_functions { 1896 bool system_params; 1897 bool sbios_requests; 1898 bool select_active_disp; 1899 bool lid_state; 1900 bool get_tv_standard; 1901 bool set_tv_standard; 1902 bool get_panel_expansion_mode; 1903 bool set_panel_expansion_mode; 1904 bool temperature_change; 1905 bool graphics_device_types; 1906 }; 1907 1908 struct amdgpu_atif { 1909 struct amdgpu_atif_notifications notifications; 1910 struct amdgpu_atif_functions functions; 1911 struct amdgpu_atif_notification_cfg notification_cfg; 1912 struct amdgpu_encoder *encoder_for_bl; 1913 }; 1914 1915 struct amdgpu_atcs_functions { 1916 bool get_ext_state; 1917 bool pcie_perf_req; 1918 bool pcie_dev_rdy; 1919 bool pcie_bus_width; 1920 }; 1921 1922 struct amdgpu_atcs { 1923 struct amdgpu_atcs_functions functions; 1924 }; 1925 1926 /* 1927 * CGS 1928 */ 1929 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1930 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1931 1932 1933 /* GPU virtualization */ 1934 #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0) 1935 #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1) 1936 struct amdgpu_virtualization { 1937 bool supports_sr_iov; 1938 bool is_virtual; 1939 u32 caps; 1940 }; 1941 1942 /* 1943 * Core structure, functions and helpers. 1944 */ 1945 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1946 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1947 1948 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1949 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1950 1951 struct amdgpu_ip_block_status { 1952 bool valid; 1953 bool sw; 1954 bool hw; 1955 }; 1956 1957 struct amdgpu_device { 1958 struct device *dev; 1959 struct drm_device *ddev; 1960 struct pci_dev *pdev; 1961 1962 #ifdef CONFIG_DRM_AMD_ACP 1963 struct amdgpu_acp acp; 1964 #endif 1965 1966 /* ASIC */ 1967 enum amd_asic_type asic_type; 1968 uint32_t family; 1969 uint32_t rev_id; 1970 uint32_t external_rev_id; 1971 unsigned long flags; 1972 int usec_timeout; 1973 const struct amdgpu_asic_funcs *asic_funcs; 1974 bool shutdown; 1975 bool need_dma32; 1976 bool accel_working; 1977 struct work_struct reset_work; 1978 struct notifier_block acpi_nb; 1979 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1980 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1981 unsigned debugfs_count; 1982 #if defined(CONFIG_DEBUG_FS) 1983 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1984 #endif 1985 struct amdgpu_atif atif; 1986 struct amdgpu_atcs atcs; 1987 struct mutex srbm_mutex; 1988 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1989 struct mutex grbm_idx_mutex; 1990 struct dev_pm_domain vga_pm_domain; 1991 bool have_disp_power_ref; 1992 1993 /* BIOS */ 1994 uint8_t *bios; 1995 bool is_atom_bios; 1996 struct amdgpu_bo *stollen_vga_memory; 1997 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1998 1999 /* Register/doorbell mmio */ 2000 resource_size_t rmmio_base; 2001 resource_size_t rmmio_size; 2002 void __iomem *rmmio; 2003 /* protects concurrent MM_INDEX/DATA based register access */ 2004 spinlock_t mmio_idx_lock; 2005 /* protects concurrent SMC based register access */ 2006 spinlock_t smc_idx_lock; 2007 amdgpu_rreg_t smc_rreg; 2008 amdgpu_wreg_t smc_wreg; 2009 /* protects concurrent PCIE register access */ 2010 spinlock_t pcie_idx_lock; 2011 amdgpu_rreg_t pcie_rreg; 2012 amdgpu_wreg_t pcie_wreg; 2013 /* protects concurrent UVD register access */ 2014 spinlock_t uvd_ctx_idx_lock; 2015 amdgpu_rreg_t uvd_ctx_rreg; 2016 amdgpu_wreg_t uvd_ctx_wreg; 2017 /* protects concurrent DIDT register access */ 2018 spinlock_t didt_idx_lock; 2019 amdgpu_rreg_t didt_rreg; 2020 amdgpu_wreg_t didt_wreg; 2021 /* protects concurrent ENDPOINT (audio) register access */ 2022 spinlock_t audio_endpt_idx_lock; 2023 amdgpu_block_rreg_t audio_endpt_rreg; 2024 amdgpu_block_wreg_t audio_endpt_wreg; 2025 void __iomem *rio_mem; 2026 resource_size_t rio_mem_size; 2027 struct amdgpu_doorbell doorbell; 2028 2029 /* clock/pll info */ 2030 struct amdgpu_clock clock; 2031 2032 /* MC */ 2033 struct amdgpu_mc mc; 2034 struct amdgpu_gart gart; 2035 struct amdgpu_dummy_page dummy_page; 2036 struct amdgpu_vm_manager vm_manager; 2037 2038 /* memory management */ 2039 struct amdgpu_mman mman; 2040 struct amdgpu_vram_scratch vram_scratch; 2041 struct amdgpu_wb wb; 2042 atomic64_t vram_usage; 2043 atomic64_t vram_vis_usage; 2044 atomic64_t gtt_usage; 2045 atomic64_t num_bytes_moved; 2046 atomic64_t num_evictions; 2047 atomic_t gpu_reset_counter; 2048 2049 /* display */ 2050 struct amdgpu_mode_info mode_info; 2051 struct work_struct hotplug_work; 2052 struct amdgpu_irq_src crtc_irq; 2053 struct amdgpu_irq_src pageflip_irq; 2054 struct amdgpu_irq_src hpd_irq; 2055 2056 /* rings */ 2057 u64 fence_context; 2058 unsigned num_rings; 2059 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2060 bool ib_pool_ready; 2061 struct amdgpu_sa_manager ring_tmp_bo; 2062 2063 /* interrupts */ 2064 struct amdgpu_irq irq; 2065 2066 /* powerplay */ 2067 struct amd_powerplay powerplay; 2068 bool pp_enabled; 2069 bool pp_force_state_enabled; 2070 2071 /* dpm */ 2072 struct amdgpu_pm pm; 2073 u32 cg_flags; 2074 u32 pg_flags; 2075 2076 /* amdgpu smumgr */ 2077 struct amdgpu_smumgr smu; 2078 2079 /* gfx */ 2080 struct amdgpu_gfx gfx; 2081 2082 /* sdma */ 2083 struct amdgpu_sdma sdma; 2084 2085 /* uvd */ 2086 struct amdgpu_uvd uvd; 2087 2088 /* vce */ 2089 struct amdgpu_vce vce; 2090 2091 /* firmwares */ 2092 struct amdgpu_firmware firmware; 2093 2094 /* GDS */ 2095 struct amdgpu_gds gds; 2096 2097 const struct amdgpu_ip_block_version *ip_blocks; 2098 int num_ip_blocks; 2099 struct amdgpu_ip_block_status *ip_block_status; 2100 struct mutex mn_lock; 2101 DECLARE_HASHTABLE(mn_hash, 7); 2102 2103 /* tracking pinned memory */ 2104 u64 vram_pin_size; 2105 u64 invisible_pin_size; 2106 u64 gart_pin_size; 2107 2108 /* amdkfd interface */ 2109 struct kfd_dev *kfd; 2110 2111 struct amdgpu_virtualization virtualization; 2112 }; 2113 2114 bool amdgpu_device_is_px(struct drm_device *dev); 2115 int amdgpu_device_init(struct amdgpu_device *adev, 2116 struct drm_device *ddev, 2117 struct pci_dev *pdev, 2118 uint32_t flags); 2119 void amdgpu_device_fini(struct amdgpu_device *adev); 2120 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2121 2122 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2123 bool always_indirect); 2124 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2125 bool always_indirect); 2126 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2127 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2128 2129 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2130 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2131 2132 /* 2133 * Registers read & write functions. 2134 */ 2135 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2136 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2137 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2138 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2139 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2140 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2141 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2142 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2143 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2144 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2145 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2146 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2147 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2148 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2149 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2150 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2151 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2152 #define WREG32_P(reg, val, mask) \ 2153 do { \ 2154 uint32_t tmp_ = RREG32(reg); \ 2155 tmp_ &= (mask); \ 2156 tmp_ |= ((val) & ~(mask)); \ 2157 WREG32(reg, tmp_); \ 2158 } while (0) 2159 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2160 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2161 #define WREG32_PLL_P(reg, val, mask) \ 2162 do { \ 2163 uint32_t tmp_ = RREG32_PLL(reg); \ 2164 tmp_ &= (mask); \ 2165 tmp_ |= ((val) & ~(mask)); \ 2166 WREG32_PLL(reg, tmp_); \ 2167 } while (0) 2168 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2169 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2170 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2171 2172 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2173 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2174 2175 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2176 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2177 2178 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2179 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2180 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2181 2182 #define REG_GET_FIELD(value, reg, field) \ 2183 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2184 2185 /* 2186 * BIOS helpers. 2187 */ 2188 #define RBIOS8(i) (adev->bios[i]) 2189 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2190 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2191 2192 /* 2193 * RING helpers. 2194 */ 2195 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2196 { 2197 if (ring->count_dw <= 0) 2198 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2199 ring->ring[ring->wptr++] = v; 2200 ring->wptr &= ring->ptr_mask; 2201 ring->count_dw--; 2202 } 2203 2204 static inline struct amdgpu_sdma_instance * 2205 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2206 { 2207 struct amdgpu_device *adev = ring->adev; 2208 int i; 2209 2210 for (i = 0; i < adev->sdma.num_instances; i++) 2211 if (&adev->sdma.instance[i].ring == ring) 2212 break; 2213 2214 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2215 return &adev->sdma.instance[i]; 2216 else 2217 return NULL; 2218 } 2219 2220 /* 2221 * ASICs macro. 2222 */ 2223 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2224 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2225 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2226 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2227 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2228 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev))) 2229 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2230 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2231 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2232 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2233 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2234 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2235 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2236 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2237 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2238 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2239 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2240 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2241 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2242 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2243 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 2244 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 2245 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2246 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2247 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2248 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2249 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 2250 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 2251 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 2252 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 2253 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2254 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2255 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2256 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2257 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2258 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2259 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2260 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2261 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2262 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2263 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2264 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2265 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2266 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 2267 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2268 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2269 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2270 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2271 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2272 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2273 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2274 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2275 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2276 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2277 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2278 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2279 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2280 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2281 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 2282 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 2283 2284 #define amdgpu_dpm_get_temperature(adev) \ 2285 ((adev)->pp_enabled ? \ 2286 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2287 (adev)->pm.funcs->get_temperature((adev))) 2288 2289 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2290 ((adev)->pp_enabled ? \ 2291 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2292 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2293 2294 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2295 ((adev)->pp_enabled ? \ 2296 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2297 (adev)->pm.funcs->get_fan_control_mode((adev))) 2298 2299 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2300 ((adev)->pp_enabled ? \ 2301 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2302 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2303 2304 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2305 ((adev)->pp_enabled ? \ 2306 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2307 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2308 2309 #define amdgpu_dpm_get_sclk(adev, l) \ 2310 ((adev)->pp_enabled ? \ 2311 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2312 (adev)->pm.funcs->get_sclk((adev), (l))) 2313 2314 #define amdgpu_dpm_get_mclk(adev, l) \ 2315 ((adev)->pp_enabled ? \ 2316 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2317 (adev)->pm.funcs->get_mclk((adev), (l))) 2318 2319 2320 #define amdgpu_dpm_force_performance_level(adev, l) \ 2321 ((adev)->pp_enabled ? \ 2322 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2323 (adev)->pm.funcs->force_performance_level((adev), (l))) 2324 2325 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2326 ((adev)->pp_enabled ? \ 2327 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2328 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2329 2330 #define amdgpu_dpm_powergate_vce(adev, g) \ 2331 ((adev)->pp_enabled ? \ 2332 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2333 (adev)->pm.funcs->powergate_vce((adev), (g))) 2334 2335 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2336 ((adev)->pp_enabled ? \ 2337 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2338 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2339 2340 #define amdgpu_dpm_get_current_power_state(adev) \ 2341 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2342 2343 #define amdgpu_dpm_get_performance_level(adev) \ 2344 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2345 2346 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2347 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2348 2349 #define amdgpu_dpm_get_pp_table(adev, table) \ 2350 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2351 2352 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2353 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2354 2355 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2356 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2357 2358 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2359 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2360 2361 #define amdgpu_dpm_get_sclk_od(adev) \ 2362 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) 2363 2364 #define amdgpu_dpm_set_sclk_od(adev, value) \ 2365 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) 2366 2367 #define amdgpu_dpm_get_mclk_od(adev) \ 2368 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 2369 2370 #define amdgpu_dpm_set_mclk_od(adev, value) \ 2371 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 2372 2373 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2374 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2375 2376 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2377 2378 /* Common functions */ 2379 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2380 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2381 bool amdgpu_card_posted(struct amdgpu_device *adev); 2382 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2383 2384 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2385 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2386 u32 ip_instance, u32 ring, 2387 struct amdgpu_ring **out_ring); 2388 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2389 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2390 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 2391 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2392 uint32_t flags); 2393 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2394 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2395 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2396 unsigned long end); 2397 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 2398 int *last_invalidated); 2399 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2400 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2401 struct ttm_mem_reg *mem); 2402 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2403 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2404 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2405 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2406 const u32 *registers, 2407 const u32 array_size); 2408 2409 bool amdgpu_device_is_px(struct drm_device *dev); 2410 /* atpx handler */ 2411 #if defined(CONFIG_VGA_SWITCHEROO) 2412 void amdgpu_register_atpx_handler(void); 2413 void amdgpu_unregister_atpx_handler(void); 2414 bool amdgpu_has_atpx_dgpu_power_cntl(void); 2415 bool amdgpu_is_atpx_hybrid(void); 2416 #else 2417 static inline void amdgpu_register_atpx_handler(void) {} 2418 static inline void amdgpu_unregister_atpx_handler(void) {} 2419 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 2420 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 2421 #endif 2422 2423 /* 2424 * KMS 2425 */ 2426 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2427 extern const int amdgpu_max_kms_ioctl; 2428 2429 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2430 int amdgpu_driver_unload_kms(struct drm_device *dev); 2431 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2432 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2433 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2434 struct drm_file *file_priv); 2435 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2436 struct drm_file *file_priv); 2437 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2438 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2439 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2440 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2441 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2442 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2443 int *max_error, 2444 struct timeval *vblank_time, 2445 unsigned flags); 2446 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2447 unsigned long arg); 2448 2449 /* 2450 * functions used by amdgpu_encoder.c 2451 */ 2452 struct amdgpu_afmt_acr { 2453 u32 clock; 2454 2455 int n_32khz; 2456 int cts_32khz; 2457 2458 int n_44_1khz; 2459 int cts_44_1khz; 2460 2461 int n_48khz; 2462 int cts_48khz; 2463 2464 }; 2465 2466 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2467 2468 /* amdgpu_acpi.c */ 2469 #if defined(CONFIG_ACPI) 2470 int amdgpu_acpi_init(struct amdgpu_device *adev); 2471 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2472 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2473 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2474 u8 perf_req, bool advertise); 2475 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2476 #else 2477 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2478 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2479 #endif 2480 2481 struct amdgpu_bo_va_mapping * 2482 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2483 uint64_t addr, struct amdgpu_bo **bo); 2484 2485 #include "amdgpu_object.h" 2486 #endif 2487