1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 116 #define MAX_GPU_INSTANCE 64 117 118 struct amdgpu_gpu_instance { 119 struct amdgpu_device *adev; 120 int mgpu_fan_enabled; 121 }; 122 123 struct amdgpu_mgpu_info { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct mutex mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 130 /* delayed reset_func for XGMI configuration if necessary */ 131 struct delayed_work delayed_reset_work; 132 bool pending_reset; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_hwip_reg_entry { 143 u32 hwip; 144 u32 inst; 145 u32 seg; 146 u32 reg_offset; 147 const char *reg_name; 148 }; 149 150 struct amdgpu_watchdog_timer { 151 bool timeout_fatal_disable; 152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 153 }; 154 155 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 156 157 /* 158 * Modules parameters. 159 */ 160 extern int amdgpu_modeset; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern uint amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_mes_kiq; 223 extern int amdgpu_noretry; 224 extern int amdgpu_force_asic_type; 225 extern int amdgpu_smartshift_bias; 226 extern int amdgpu_use_xgmi_p2p; 227 extern int amdgpu_mtype_local; 228 extern bool enforce_isolation; 229 #ifdef CONFIG_HSA_AMD 230 extern int sched_policy; 231 extern bool debug_evictions; 232 extern bool no_system_mem_limit; 233 extern int halt_if_hws_hang; 234 #else 235 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 236 static const bool __maybe_unused debug_evictions; /* = false */ 237 static const bool __maybe_unused no_system_mem_limit; 238 static const int __maybe_unused halt_if_hws_hang; 239 #endif 240 #ifdef CONFIG_HSA_AMD_P2P 241 extern bool pcie_p2p; 242 #endif 243 244 extern int amdgpu_tmz; 245 extern int amdgpu_reset_method; 246 247 #ifdef CONFIG_DRM_AMDGPU_SI 248 extern int amdgpu_si_support; 249 #endif 250 #ifdef CONFIG_DRM_AMDGPU_CIK 251 extern int amdgpu_cik_support; 252 #endif 253 extern int amdgpu_num_kcq; 254 255 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 256 extern int amdgpu_vcnfw_log; 257 extern int amdgpu_sg_display; 258 extern int amdgpu_umsch_mm; 259 extern int amdgpu_seamless; 260 261 extern int amdgpu_user_partt_mode; 262 extern int amdgpu_agp; 263 264 extern int amdgpu_wbrf; 265 266 #define AMDGPU_VM_MAX_NUM_CTX 4096 267 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 268 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 269 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 270 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 271 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 272 #define AMDGPUFB_CONN_LIMIT 4 273 #define AMDGPU_BIOS_NUM_SCRATCH 16 274 275 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 276 277 /* hard reset data */ 278 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 279 280 /* reset flags */ 281 #define AMDGPU_RESET_GFX (1 << 0) 282 #define AMDGPU_RESET_COMPUTE (1 << 1) 283 #define AMDGPU_RESET_DMA (1 << 2) 284 #define AMDGPU_RESET_CP (1 << 3) 285 #define AMDGPU_RESET_GRBM (1 << 4) 286 #define AMDGPU_RESET_DMA1 (1 << 5) 287 #define AMDGPU_RESET_RLC (1 << 6) 288 #define AMDGPU_RESET_SEM (1 << 7) 289 #define AMDGPU_RESET_IH (1 << 8) 290 #define AMDGPU_RESET_VMC (1 << 9) 291 #define AMDGPU_RESET_MC (1 << 10) 292 #define AMDGPU_RESET_DISPLAY (1 << 11) 293 #define AMDGPU_RESET_UVD (1 << 12) 294 #define AMDGPU_RESET_VCE (1 << 13) 295 #define AMDGPU_RESET_VCE1 (1 << 14) 296 297 /* max cursor sizes (in pixels) */ 298 #define CIK_CURSOR_WIDTH 128 299 #define CIK_CURSOR_HEIGHT 128 300 301 /* smart shift bias level limits */ 302 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 303 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 304 305 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 306 #define AMDGPU_SWCTF_EXTRA_DELAY 50 307 308 struct amdgpu_xcp_mgr; 309 struct amdgpu_device; 310 struct amdgpu_irq_src; 311 struct amdgpu_fpriv; 312 struct amdgpu_bo_va_mapping; 313 struct kfd_vm_fault_info; 314 struct amdgpu_hive_info; 315 struct amdgpu_reset_context; 316 struct amdgpu_reset_control; 317 318 enum amdgpu_cp_irq { 319 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 320 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 321 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 322 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 323 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 324 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 325 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 326 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 327 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 328 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 329 330 AMDGPU_CP_IRQ_LAST 331 }; 332 333 enum amdgpu_thermal_irq { 334 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 335 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 336 337 AMDGPU_THERMAL_IRQ_LAST 338 }; 339 340 enum amdgpu_kiq_irq { 341 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 342 AMDGPU_CP_KIQ_IRQ_LAST 343 }; 344 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 345 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 346 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 347 #define MAX_KIQ_REG_TRY 1000 348 349 int amdgpu_device_ip_set_clockgating_state(void *dev, 350 enum amd_ip_block_type block_type, 351 enum amd_clockgating_state state); 352 int amdgpu_device_ip_set_powergating_state(void *dev, 353 enum amd_ip_block_type block_type, 354 enum amd_powergating_state state); 355 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 356 u64 *flags); 357 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 358 enum amd_ip_block_type block_type); 359 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 360 enum amd_ip_block_type block_type); 361 362 #define AMDGPU_MAX_IP_NUM 16 363 364 struct amdgpu_ip_block_status { 365 bool valid; 366 bool sw; 367 bool hw; 368 bool late_initialized; 369 bool hang; 370 }; 371 372 struct amdgpu_ip_block_version { 373 const enum amd_ip_block_type type; 374 const u32 major; 375 const u32 minor; 376 const u32 rev; 377 const struct amd_ip_funcs *funcs; 378 }; 379 380 struct amdgpu_ip_block { 381 struct amdgpu_ip_block_status status; 382 const struct amdgpu_ip_block_version *version; 383 }; 384 385 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 386 enum amd_ip_block_type type, 387 u32 major, u32 minor); 388 389 struct amdgpu_ip_block * 390 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 391 enum amd_ip_block_type type); 392 393 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 394 const struct amdgpu_ip_block_version *ip_block_version); 395 396 /* 397 * BIOS. 398 */ 399 bool amdgpu_get_bios(struct amdgpu_device *adev); 400 bool amdgpu_read_bios(struct amdgpu_device *adev); 401 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 402 u8 *bios, u32 length_bytes); 403 /* 404 * Clocks 405 */ 406 407 #define AMDGPU_MAX_PPLL 3 408 409 struct amdgpu_clock { 410 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 411 struct amdgpu_pll spll; 412 struct amdgpu_pll mpll; 413 /* 10 Khz units */ 414 uint32_t default_mclk; 415 uint32_t default_sclk; 416 uint32_t default_dispclk; 417 uint32_t current_dispclk; 418 uint32_t dp_extclk; 419 uint32_t max_pixel_clock; 420 }; 421 422 /* sub-allocation manager, it has to be protected by another lock. 423 * By conception this is an helper for other part of the driver 424 * like the indirect buffer or semaphore, which both have their 425 * locking. 426 * 427 * Principe is simple, we keep a list of sub allocation in offset 428 * order (first entry has offset == 0, last entry has the highest 429 * offset). 430 * 431 * When allocating new object we first check if there is room at 432 * the end total_size - (last_object_offset + last_object_size) >= 433 * alloc_size. If so we allocate new object there. 434 * 435 * When there is not enough room at the end, we start waiting for 436 * each sub object until we reach object_offset+object_size >= 437 * alloc_size, this object then become the sub object we return. 438 * 439 * Alignment can't be bigger than page size. 440 * 441 * Hole are not considered for allocation to keep things simple. 442 * Assumption is that there won't be hole (all object on same 443 * alignment). 444 */ 445 446 struct amdgpu_sa_manager { 447 struct drm_suballoc_manager base; 448 struct amdgpu_bo *bo; 449 uint64_t gpu_addr; 450 void *cpu_ptr; 451 }; 452 453 int amdgpu_fence_slab_init(void); 454 void amdgpu_fence_slab_fini(void); 455 456 /* 457 * IRQS. 458 */ 459 460 struct amdgpu_flip_work { 461 struct delayed_work flip_work; 462 struct work_struct unpin_work; 463 struct amdgpu_device *adev; 464 int crtc_id; 465 u32 target_vblank; 466 uint64_t base; 467 struct drm_pending_vblank_event *event; 468 struct amdgpu_bo *old_abo; 469 unsigned shared_count; 470 struct dma_fence **shared; 471 struct dma_fence_cb cb; 472 bool async; 473 }; 474 475 476 /* 477 * file private structure 478 */ 479 480 struct amdgpu_fpriv { 481 struct amdgpu_vm vm; 482 struct amdgpu_bo_va *prt_va; 483 struct amdgpu_bo_va *csa_va; 484 struct amdgpu_bo_va *seq64_va; 485 struct mutex bo_list_lock; 486 struct idr bo_list_handles; 487 struct amdgpu_ctx_mgr ctx_mgr; 488 /** GPU partition selection */ 489 uint32_t xcp_id; 490 }; 491 492 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 493 494 /* 495 * Writeback 496 */ 497 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 498 499 struct amdgpu_wb { 500 struct amdgpu_bo *wb_obj; 501 volatile uint32_t *wb; 502 uint64_t gpu_addr; 503 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 504 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 505 }; 506 507 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 508 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 509 510 /* 511 * Benchmarking 512 */ 513 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 514 515 /* 516 * ASIC specific register table accessible by UMD 517 */ 518 struct amdgpu_allowed_register_entry { 519 uint32_t reg_offset; 520 bool grbm_indexed; 521 }; 522 523 /** 524 * enum amd_reset_method - Methods for resetting AMD GPU devices 525 * 526 * @AMD_RESET_METHOD_NONE: The device will not be reset. 527 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 528 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 529 * any device. 530 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 531 * individually. Suitable only for some discrete GPU, not 532 * available for all ASICs. 533 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 534 * are reset depends on the ASIC. Notably doesn't reset IPs 535 * shared with the CPU on APUs or the memory controllers (so 536 * VRAM is not lost). Not available on all ASICs. 537 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 538 * but without powering off the PCI bus. Suitable only for 539 * discrete GPUs. 540 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 541 * and does a secondary bus reset or FLR, depending on what the 542 * underlying hardware supports. 543 * 544 * Methods available for AMD GPU driver for resetting the device. Not all 545 * methods are suitable for every device. User can override the method using 546 * module parameter `reset_method`. 547 */ 548 enum amd_reset_method { 549 AMD_RESET_METHOD_NONE = -1, 550 AMD_RESET_METHOD_LEGACY = 0, 551 AMD_RESET_METHOD_MODE0, 552 AMD_RESET_METHOD_MODE1, 553 AMD_RESET_METHOD_MODE2, 554 AMD_RESET_METHOD_BACO, 555 AMD_RESET_METHOD_PCI, 556 }; 557 558 struct amdgpu_video_codec_info { 559 u32 codec_type; 560 u32 max_width; 561 u32 max_height; 562 u32 max_pixels_per_frame; 563 u32 max_level; 564 }; 565 566 #define codec_info_build(type, width, height, level) \ 567 .codec_type = type,\ 568 .max_width = width,\ 569 .max_height = height,\ 570 .max_pixels_per_frame = height * width,\ 571 .max_level = level, 572 573 struct amdgpu_video_codecs { 574 const u32 codec_count; 575 const struct amdgpu_video_codec_info *codec_array; 576 }; 577 578 /* 579 * ASIC specific functions. 580 */ 581 struct amdgpu_asic_funcs { 582 bool (*read_disabled_bios)(struct amdgpu_device *adev); 583 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 584 u8 *bios, u32 length_bytes); 585 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 586 u32 sh_num, u32 reg_offset, u32 *value); 587 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 588 int (*reset)(struct amdgpu_device *adev); 589 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 590 /* get the reference clock */ 591 u32 (*get_xclk)(struct amdgpu_device *adev); 592 /* MM block clocks */ 593 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 594 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 595 /* static power management */ 596 int (*get_pcie_lanes)(struct amdgpu_device *adev); 597 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 598 /* get config memsize register */ 599 u32 (*get_config_memsize)(struct amdgpu_device *adev); 600 /* flush hdp write queue */ 601 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 602 /* invalidate hdp read cache */ 603 void (*invalidate_hdp)(struct amdgpu_device *adev, 604 struct amdgpu_ring *ring); 605 /* check if the asic needs a full reset of if soft reset will work */ 606 bool (*need_full_reset)(struct amdgpu_device *adev); 607 /* initialize doorbell layout for specific asic*/ 608 void (*init_doorbell_index)(struct amdgpu_device *adev); 609 /* PCIe bandwidth usage */ 610 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 611 uint64_t *count1); 612 /* do we need to reset the asic at init time (e.g., kexec) */ 613 bool (*need_reset_on_init)(struct amdgpu_device *adev); 614 /* PCIe replay counter */ 615 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 616 /* device supports BACO */ 617 int (*supports_baco)(struct amdgpu_device *adev); 618 /* pre asic_init quirks */ 619 void (*pre_asic_init)(struct amdgpu_device *adev); 620 /* enter/exit umd stable pstate */ 621 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 622 /* query video codecs */ 623 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 624 const struct amdgpu_video_codecs **codecs); 625 /* encode "> 32bits" smn addressing */ 626 u64 (*encode_ext_smn_addressing)(int ext_id); 627 628 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 629 enum amdgpu_reg_state reg_state, void *buf, 630 size_t max_size); 631 }; 632 633 /* 634 * IOCTL. 635 */ 636 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 637 struct drm_file *filp); 638 639 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 640 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 641 struct drm_file *filp); 642 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 643 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 644 struct drm_file *filp); 645 646 /* VRAM scratch page for HDP bug, default vram page */ 647 struct amdgpu_mem_scratch { 648 struct amdgpu_bo *robj; 649 volatile uint32_t *ptr; 650 u64 gpu_addr; 651 }; 652 653 /* 654 * CGS 655 */ 656 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 657 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 658 659 /* 660 * Core structure, functions and helpers. 661 */ 662 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 663 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 664 665 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 666 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 667 668 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 669 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 670 671 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 672 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 673 674 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 675 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 676 677 struct amdgpu_mmio_remap { 678 u32 reg_offset; 679 resource_size_t bus_addr; 680 }; 681 682 /* Define the HW IP blocks will be used in driver , add more if necessary */ 683 enum amd_hw_ip_block_type { 684 GC_HWIP = 1, 685 HDP_HWIP, 686 SDMA0_HWIP, 687 SDMA1_HWIP, 688 SDMA2_HWIP, 689 SDMA3_HWIP, 690 SDMA4_HWIP, 691 SDMA5_HWIP, 692 SDMA6_HWIP, 693 SDMA7_HWIP, 694 LSDMA_HWIP, 695 MMHUB_HWIP, 696 ATHUB_HWIP, 697 NBIO_HWIP, 698 MP0_HWIP, 699 MP1_HWIP, 700 UVD_HWIP, 701 VCN_HWIP = UVD_HWIP, 702 JPEG_HWIP = VCN_HWIP, 703 VCN1_HWIP, 704 VCE_HWIP, 705 VPE_HWIP, 706 DF_HWIP, 707 DCE_HWIP, 708 OSSSYS_HWIP, 709 SMUIO_HWIP, 710 PWR_HWIP, 711 NBIF_HWIP, 712 THM_HWIP, 713 CLK_HWIP, 714 UMC_HWIP, 715 RSMU_HWIP, 716 XGMI_HWIP, 717 DCI_HWIP, 718 PCIE_HWIP, 719 MAX_HWIP 720 }; 721 722 #define HWIP_MAX_INSTANCE 44 723 724 #define HW_ID_MAX 300 725 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 726 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 727 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 728 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 729 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 730 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 731 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 732 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 733 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 734 735 struct amdgpu_ip_map_info { 736 /* Map of logical to actual dev instances/mask */ 737 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 738 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 739 enum amd_hw_ip_block_type block, 740 int8_t inst); 741 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 742 enum amd_hw_ip_block_type block, 743 uint32_t mask); 744 }; 745 746 struct amd_powerplay { 747 void *pp_handle; 748 const struct amd_pm_funcs *pp_funcs; 749 }; 750 751 struct ip_discovery_top; 752 753 /* polaris10 kickers */ 754 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 755 ((rid == 0xE3) || \ 756 (rid == 0xE4) || \ 757 (rid == 0xE5) || \ 758 (rid == 0xE7) || \ 759 (rid == 0xEF))) || \ 760 ((did == 0x6FDF) && \ 761 ((rid == 0xE7) || \ 762 (rid == 0xEF) || \ 763 (rid == 0xFF)))) 764 765 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 766 ((rid == 0xE1) || \ 767 (rid == 0xF7))) 768 769 /* polaris11 kickers */ 770 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 771 ((rid == 0xE0) || \ 772 (rid == 0xE5))) || \ 773 ((did == 0x67FF) && \ 774 ((rid == 0xCF) || \ 775 (rid == 0xEF) || \ 776 (rid == 0xFF)))) 777 778 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 779 ((rid == 0xE2))) 780 781 /* polaris12 kickers */ 782 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 783 ((rid == 0xC0) || \ 784 (rid == 0xC1) || \ 785 (rid == 0xC3) || \ 786 (rid == 0xC7))) || \ 787 ((did == 0x6981) && \ 788 ((rid == 0x00) || \ 789 (rid == 0x01) || \ 790 (rid == 0x10)))) 791 792 struct amdgpu_mqd_prop { 793 uint64_t mqd_gpu_addr; 794 uint64_t hqd_base_gpu_addr; 795 uint64_t rptr_gpu_addr; 796 uint64_t wptr_gpu_addr; 797 uint32_t queue_size; 798 bool use_doorbell; 799 uint32_t doorbell_index; 800 uint64_t eop_gpu_addr; 801 uint32_t hqd_pipe_priority; 802 uint32_t hqd_queue_priority; 803 bool allow_tunneling; 804 bool hqd_active; 805 }; 806 807 struct amdgpu_mqd { 808 unsigned mqd_size; 809 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 810 struct amdgpu_mqd_prop *p); 811 }; 812 813 #define AMDGPU_RESET_MAGIC_NUM 64 814 #define AMDGPU_MAX_DF_PERFMONS 4 815 struct amdgpu_reset_domain; 816 struct amdgpu_fru_info; 817 818 struct amdgpu_reset_info { 819 /* reset dump register */ 820 u32 *reset_dump_reg_list; 821 u32 *reset_dump_reg_value; 822 int num_regs; 823 824 #ifdef CONFIG_DEV_COREDUMP 825 struct amdgpu_coredump_info *coredump_info; 826 #endif 827 }; 828 829 /* 830 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 831 */ 832 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 833 834 struct amdgpu_device { 835 struct device *dev; 836 struct pci_dev *pdev; 837 struct drm_device ddev; 838 839 #ifdef CONFIG_DRM_AMD_ACP 840 struct amdgpu_acp acp; 841 #endif 842 struct amdgpu_hive_info *hive; 843 struct amdgpu_xcp_mgr *xcp_mgr; 844 /* ASIC */ 845 enum amd_asic_type asic_type; 846 uint32_t family; 847 uint32_t rev_id; 848 uint32_t external_rev_id; 849 unsigned long flags; 850 unsigned long apu_flags; 851 int usec_timeout; 852 const struct amdgpu_asic_funcs *asic_funcs; 853 bool shutdown; 854 bool need_swiotlb; 855 bool accel_working; 856 struct notifier_block acpi_nb; 857 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 858 struct debugfs_blob_wrapper debugfs_vbios_blob; 859 struct debugfs_blob_wrapper debugfs_discovery_blob; 860 struct mutex srbm_mutex; 861 /* GRBM index mutex. Protects concurrent access to GRBM index */ 862 struct mutex grbm_idx_mutex; 863 struct dev_pm_domain vga_pm_domain; 864 bool have_disp_power_ref; 865 bool have_atomics_support; 866 867 /* BIOS */ 868 bool is_atom_fw; 869 uint8_t *bios; 870 uint32_t bios_size; 871 uint32_t bios_scratch_reg_offset; 872 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 873 874 /* Register/doorbell mmio */ 875 resource_size_t rmmio_base; 876 resource_size_t rmmio_size; 877 void __iomem *rmmio; 878 /* protects concurrent MM_INDEX/DATA based register access */ 879 spinlock_t mmio_idx_lock; 880 struct amdgpu_mmio_remap rmmio_remap; 881 /* protects concurrent SMC based register access */ 882 spinlock_t smc_idx_lock; 883 amdgpu_rreg_t smc_rreg; 884 amdgpu_wreg_t smc_wreg; 885 /* protects concurrent PCIE register access */ 886 spinlock_t pcie_idx_lock; 887 amdgpu_rreg_t pcie_rreg; 888 amdgpu_wreg_t pcie_wreg; 889 amdgpu_rreg_t pciep_rreg; 890 amdgpu_wreg_t pciep_wreg; 891 amdgpu_rreg_ext_t pcie_rreg_ext; 892 amdgpu_wreg_ext_t pcie_wreg_ext; 893 amdgpu_rreg64_t pcie_rreg64; 894 amdgpu_wreg64_t pcie_wreg64; 895 amdgpu_rreg64_ext_t pcie_rreg64_ext; 896 amdgpu_wreg64_ext_t pcie_wreg64_ext; 897 /* protects concurrent UVD register access */ 898 spinlock_t uvd_ctx_idx_lock; 899 amdgpu_rreg_t uvd_ctx_rreg; 900 amdgpu_wreg_t uvd_ctx_wreg; 901 /* protects concurrent DIDT register access */ 902 spinlock_t didt_idx_lock; 903 amdgpu_rreg_t didt_rreg; 904 amdgpu_wreg_t didt_wreg; 905 /* protects concurrent gc_cac register access */ 906 spinlock_t gc_cac_idx_lock; 907 amdgpu_rreg_t gc_cac_rreg; 908 amdgpu_wreg_t gc_cac_wreg; 909 /* protects concurrent se_cac register access */ 910 spinlock_t se_cac_idx_lock; 911 amdgpu_rreg_t se_cac_rreg; 912 amdgpu_wreg_t se_cac_wreg; 913 /* protects concurrent ENDPOINT (audio) register access */ 914 spinlock_t audio_endpt_idx_lock; 915 amdgpu_block_rreg_t audio_endpt_rreg; 916 amdgpu_block_wreg_t audio_endpt_wreg; 917 struct amdgpu_doorbell doorbell; 918 919 /* clock/pll info */ 920 struct amdgpu_clock clock; 921 922 /* MC */ 923 struct amdgpu_gmc gmc; 924 struct amdgpu_gart gart; 925 dma_addr_t dummy_page_addr; 926 struct amdgpu_vm_manager vm_manager; 927 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 928 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 929 930 /* memory management */ 931 struct amdgpu_mman mman; 932 struct amdgpu_mem_scratch mem_scratch; 933 struct amdgpu_wb wb; 934 atomic64_t num_bytes_moved; 935 atomic64_t num_evictions; 936 atomic64_t num_vram_cpu_page_faults; 937 atomic_t gpu_reset_counter; 938 atomic_t vram_lost_counter; 939 940 /* data for buffer migration throttling */ 941 struct { 942 spinlock_t lock; 943 s64 last_update_us; 944 s64 accum_us; /* accumulated microseconds */ 945 s64 accum_us_vis; /* for visible VRAM */ 946 u32 log2_max_MBps; 947 } mm_stats; 948 949 /* display */ 950 bool enable_virtual_display; 951 struct amdgpu_vkms_output *amdgpu_vkms_output; 952 struct amdgpu_mode_info mode_info; 953 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 954 struct delayed_work hotplug_work; 955 struct amdgpu_irq_src crtc_irq; 956 struct amdgpu_irq_src vline0_irq; 957 struct amdgpu_irq_src vupdate_irq; 958 struct amdgpu_irq_src pageflip_irq; 959 struct amdgpu_irq_src hpd_irq; 960 struct amdgpu_irq_src dmub_trace_irq; 961 struct amdgpu_irq_src dmub_outbox_irq; 962 963 /* rings */ 964 u64 fence_context; 965 unsigned num_rings; 966 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 967 struct dma_fence __rcu *gang_submit; 968 bool ib_pool_ready; 969 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 970 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 971 972 /* interrupts */ 973 struct amdgpu_irq irq; 974 975 /* powerplay */ 976 struct amd_powerplay powerplay; 977 struct amdgpu_pm pm; 978 u64 cg_flags; 979 u32 pg_flags; 980 981 /* nbio */ 982 struct amdgpu_nbio nbio; 983 984 /* hdp */ 985 struct amdgpu_hdp hdp; 986 987 /* smuio */ 988 struct amdgpu_smuio smuio; 989 990 /* mmhub */ 991 struct amdgpu_mmhub mmhub; 992 993 /* gfxhub */ 994 struct amdgpu_gfxhub gfxhub; 995 996 /* gfx */ 997 struct amdgpu_gfx gfx; 998 999 /* sdma */ 1000 struct amdgpu_sdma sdma; 1001 1002 /* lsdma */ 1003 struct amdgpu_lsdma lsdma; 1004 1005 /* uvd */ 1006 struct amdgpu_uvd uvd; 1007 1008 /* vce */ 1009 struct amdgpu_vce vce; 1010 1011 /* vcn */ 1012 struct amdgpu_vcn vcn; 1013 1014 /* jpeg */ 1015 struct amdgpu_jpeg jpeg; 1016 1017 /* vpe */ 1018 struct amdgpu_vpe vpe; 1019 1020 /* umsch */ 1021 struct amdgpu_umsch_mm umsch_mm; 1022 bool enable_umsch_mm; 1023 1024 /* firmwares */ 1025 struct amdgpu_firmware firmware; 1026 1027 /* PSP */ 1028 struct psp_context psp; 1029 1030 /* GDS */ 1031 struct amdgpu_gds gds; 1032 1033 /* for userq and VM fences */ 1034 struct amdgpu_seq64 seq64; 1035 1036 /* KFD */ 1037 struct amdgpu_kfd_dev kfd; 1038 1039 /* UMC */ 1040 struct amdgpu_umc umc; 1041 1042 /* display related functionality */ 1043 struct amdgpu_display_manager dm; 1044 1045 /* mes */ 1046 bool enable_mes; 1047 bool enable_mes_kiq; 1048 struct amdgpu_mes mes; 1049 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1050 1051 /* df */ 1052 struct amdgpu_df df; 1053 1054 /* MCA */ 1055 struct amdgpu_mca mca; 1056 1057 /* ACA */ 1058 struct amdgpu_aca aca; 1059 1060 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1061 uint32_t harvest_ip_mask; 1062 int num_ip_blocks; 1063 struct mutex mn_lock; 1064 DECLARE_HASHTABLE(mn_hash, 7); 1065 1066 /* tracking pinned memory */ 1067 atomic64_t vram_pin_size; 1068 atomic64_t visible_pin_size; 1069 atomic64_t gart_pin_size; 1070 1071 /* soc15 register offset based on ip, instance and segment */ 1072 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1073 struct amdgpu_ip_map_info ip_map; 1074 1075 /* delayed work_func for deferring clockgating during resume */ 1076 struct delayed_work delayed_init_work; 1077 1078 struct amdgpu_virt virt; 1079 1080 /* link all shadow bo */ 1081 struct list_head shadow_list; 1082 struct mutex shadow_list_lock; 1083 1084 /* record hw reset is performed */ 1085 bool has_hw_reset; 1086 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1087 1088 /* s3/s4 mask */ 1089 bool in_suspend; 1090 bool in_s3; 1091 bool in_s4; 1092 bool in_s0ix; 1093 /* indicate amdgpu suspension status */ 1094 bool suspend_complete; 1095 1096 enum pp_mp1_state mp1_state; 1097 struct amdgpu_doorbell_index doorbell_index; 1098 1099 struct mutex notifier_lock; 1100 1101 int asic_reset_res; 1102 struct work_struct xgmi_reset_work; 1103 struct list_head reset_list; 1104 1105 long gfx_timeout; 1106 long sdma_timeout; 1107 long video_timeout; 1108 long compute_timeout; 1109 long psp_timeout; 1110 1111 uint64_t unique_id; 1112 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1113 1114 /* enable runtime pm on the device */ 1115 bool in_runpm; 1116 bool has_pr3; 1117 1118 bool ucode_sysfs_en; 1119 1120 struct amdgpu_fru_info *fru_info; 1121 atomic_t throttling_logging_enabled; 1122 struct ratelimit_state throttling_logging_rs; 1123 uint32_t ras_hw_enabled; 1124 uint32_t ras_enabled; 1125 1126 bool no_hw_access; 1127 struct pci_saved_state *pci_state; 1128 pci_channel_state_t pci_channel_state; 1129 1130 /* Track auto wait count on s_barrier settings */ 1131 bool barrier_has_auto_waitcnt; 1132 1133 struct amdgpu_reset_control *reset_cntl; 1134 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1135 1136 bool ram_is_direct_mapped; 1137 1138 struct list_head ras_list; 1139 1140 struct ip_discovery_top *ip_top; 1141 1142 struct amdgpu_reset_domain *reset_domain; 1143 1144 struct mutex benchmark_mutex; 1145 1146 struct amdgpu_reset_info reset_info; 1147 1148 bool scpm_enabled; 1149 uint32_t scpm_status; 1150 1151 struct work_struct reset_work; 1152 1153 bool job_hang; 1154 bool dc_enabled; 1155 /* Mask of active clusters */ 1156 uint32_t aid_mask; 1157 1158 /* Debug */ 1159 bool debug_vm; 1160 bool debug_largebar; 1161 bool debug_disable_soft_recovery; 1162 bool debug_use_vram_fw_buf; 1163 }; 1164 1165 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1166 uint8_t ip, uint8_t inst) 1167 { 1168 /* This considers only major/minor/rev and ignores 1169 * subrevision/variant fields. 1170 */ 1171 return adev->ip_versions[ip][inst] & ~0xFFU; 1172 } 1173 1174 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1175 uint8_t ip, uint8_t inst) 1176 { 1177 /* This returns full version - major/minor/rev/variant/subrevision */ 1178 return adev->ip_versions[ip][inst]; 1179 } 1180 1181 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1182 { 1183 return container_of(ddev, struct amdgpu_device, ddev); 1184 } 1185 1186 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1187 { 1188 return &adev->ddev; 1189 } 1190 1191 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1192 { 1193 return container_of(bdev, struct amdgpu_device, mman.bdev); 1194 } 1195 1196 int amdgpu_device_init(struct amdgpu_device *adev, 1197 uint32_t flags); 1198 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1199 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1200 1201 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1202 1203 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1204 void *buf, size_t size, bool write); 1205 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1206 void *buf, size_t size, bool write); 1207 1208 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1209 void *buf, size_t size, bool write); 1210 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1211 uint32_t inst, uint32_t reg_addr, char reg_name[], 1212 uint32_t expected_value, uint32_t mask); 1213 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1214 uint32_t reg, uint32_t acc_flags); 1215 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1216 u64 reg_addr); 1217 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1218 uint32_t reg, uint32_t acc_flags, 1219 uint32_t xcc_id); 1220 void amdgpu_device_wreg(struct amdgpu_device *adev, 1221 uint32_t reg, uint32_t v, 1222 uint32_t acc_flags); 1223 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1224 u64 reg_addr, u32 reg_data); 1225 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1226 uint32_t reg, uint32_t v, 1227 uint32_t acc_flags, 1228 uint32_t xcc_id); 1229 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1230 uint32_t reg, uint32_t v, uint32_t xcc_id); 1231 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1232 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1233 1234 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1235 u32 reg_addr); 1236 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1237 u32 reg_addr); 1238 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1239 u64 reg_addr); 1240 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1241 u32 reg_addr, u32 reg_data); 1242 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1243 u32 reg_addr, u64 reg_data); 1244 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1245 u64 reg_addr, u64 reg_data); 1246 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1247 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1248 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1249 1250 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1251 1252 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1253 struct amdgpu_reset_context *reset_context); 1254 1255 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1256 struct amdgpu_reset_context *reset_context); 1257 1258 int emu_soc_asic_init(struct amdgpu_device *adev); 1259 1260 /* 1261 * Registers read & write functions. 1262 */ 1263 #define AMDGPU_REGS_NO_KIQ (1<<1) 1264 #define AMDGPU_REGS_RLC (1<<2) 1265 1266 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1267 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1268 1269 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1270 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1271 1272 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1273 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1274 1275 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1276 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1277 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1278 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1279 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1280 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1281 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1282 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1283 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1284 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1285 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1286 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1287 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1288 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1289 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1290 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1291 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1292 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1293 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1294 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1295 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1296 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1297 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1298 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1299 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1300 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1301 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1302 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1303 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1304 #define WREG32_P(reg, val, mask) \ 1305 do { \ 1306 uint32_t tmp_ = RREG32(reg); \ 1307 tmp_ &= (mask); \ 1308 tmp_ |= ((val) & ~(mask)); \ 1309 WREG32(reg, tmp_); \ 1310 } while (0) 1311 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1312 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1313 #define WREG32_PLL_P(reg, val, mask) \ 1314 do { \ 1315 uint32_t tmp_ = RREG32_PLL(reg); \ 1316 tmp_ &= (mask); \ 1317 tmp_ |= ((val) & ~(mask)); \ 1318 WREG32_PLL(reg, tmp_); \ 1319 } while (0) 1320 1321 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1322 do { \ 1323 u32 tmp = RREG32_SMC(_Reg); \ 1324 tmp &= (_Mask); \ 1325 tmp |= ((_Val) & ~(_Mask)); \ 1326 WREG32_SMC(_Reg, tmp); \ 1327 } while (0) 1328 1329 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1330 1331 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1332 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1333 1334 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1335 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1336 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1337 1338 #define REG_GET_FIELD(value, reg, field) \ 1339 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1340 1341 #define WREG32_FIELD(reg, field, val) \ 1342 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1343 1344 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1345 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1346 1347 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1348 /* 1349 * BIOS helpers. 1350 */ 1351 #define RBIOS8(i) (adev->bios[i]) 1352 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1353 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1354 1355 /* 1356 * ASICs macro. 1357 */ 1358 #define amdgpu_asic_set_vga_state(adev, state) \ 1359 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1360 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1361 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1362 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1363 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1364 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1365 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1366 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1367 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1368 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1369 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1370 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1371 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1372 #define amdgpu_asic_flush_hdp(adev, r) \ 1373 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1374 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1375 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1376 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1377 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1378 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1379 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1380 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1381 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1382 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1383 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1384 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1385 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1386 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1387 1388 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1389 1390 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1391 #define for_each_inst(i, inst_mask) \ 1392 for (i = ffs(inst_mask); i-- != 0; \ 1393 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1394 1395 /* Common functions */ 1396 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1397 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1398 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1399 struct amdgpu_job *job, 1400 struct amdgpu_reset_context *reset_context); 1401 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1402 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1403 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1404 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1405 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1406 1407 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1408 u64 num_vis_bytes); 1409 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1410 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1411 const u32 *registers, 1412 const u32 array_size); 1413 1414 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1415 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1416 bool amdgpu_device_supports_px(struct drm_device *dev); 1417 bool amdgpu_device_supports_boco(struct drm_device *dev); 1418 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1419 int amdgpu_device_supports_baco(struct drm_device *dev); 1420 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1421 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1422 struct amdgpu_device *peer_adev); 1423 int amdgpu_device_baco_enter(struct drm_device *dev); 1424 int amdgpu_device_baco_exit(struct drm_device *dev); 1425 1426 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1427 struct amdgpu_ring *ring); 1428 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1429 struct amdgpu_ring *ring); 1430 1431 void amdgpu_device_halt(struct amdgpu_device *adev); 1432 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1433 u32 reg); 1434 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1435 u32 reg, u32 v); 1436 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1437 struct dma_fence *gang); 1438 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1439 1440 /* atpx handler */ 1441 #if defined(CONFIG_VGA_SWITCHEROO) 1442 void amdgpu_register_atpx_handler(void); 1443 void amdgpu_unregister_atpx_handler(void); 1444 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1445 bool amdgpu_is_atpx_hybrid(void); 1446 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1447 bool amdgpu_has_atpx(void); 1448 #else 1449 static inline void amdgpu_register_atpx_handler(void) {} 1450 static inline void amdgpu_unregister_atpx_handler(void) {} 1451 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1452 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1453 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1454 static inline bool amdgpu_has_atpx(void) { return false; } 1455 #endif 1456 1457 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1458 void *amdgpu_atpx_get_dhandle(void); 1459 #else 1460 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1461 #endif 1462 1463 /* 1464 * KMS 1465 */ 1466 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1467 extern const int amdgpu_max_kms_ioctl; 1468 1469 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1470 void amdgpu_driver_unload_kms(struct drm_device *dev); 1471 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1472 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1473 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1474 struct drm_file *file_priv); 1475 void amdgpu_driver_release_kms(struct drm_device *dev); 1476 1477 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1478 int amdgpu_device_prepare(struct drm_device *dev); 1479 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1480 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1481 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1482 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1483 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1484 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1485 struct drm_file *filp); 1486 1487 /* 1488 * functions used by amdgpu_encoder.c 1489 */ 1490 struct amdgpu_afmt_acr { 1491 u32 clock; 1492 1493 int n_32khz; 1494 int cts_32khz; 1495 1496 int n_44_1khz; 1497 int cts_44_1khz; 1498 1499 int n_48khz; 1500 int cts_48khz; 1501 1502 }; 1503 1504 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1505 1506 /* amdgpu_acpi.c */ 1507 1508 struct amdgpu_numa_info { 1509 uint64_t size; 1510 int pxm; 1511 int nid; 1512 }; 1513 1514 /* ATCS Device/Driver State */ 1515 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1516 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1517 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1518 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1519 1520 #if defined(CONFIG_ACPI) 1521 int amdgpu_acpi_init(struct amdgpu_device *adev); 1522 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1523 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1524 bool amdgpu_acpi_is_power_shift_control_supported(void); 1525 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1526 u8 perf_req, bool advertise); 1527 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1528 u8 dev_state, bool drv_state); 1529 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1530 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1531 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1532 u64 *tmr_size); 1533 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1534 struct amdgpu_numa_info *numa_info); 1535 1536 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1537 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1538 void amdgpu_acpi_detect(void); 1539 void amdgpu_acpi_release(void); 1540 #else 1541 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1542 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1543 u64 *tmr_offset, u64 *tmr_size) 1544 { 1545 return -EINVAL; 1546 } 1547 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1548 int xcc_id, 1549 struct amdgpu_numa_info *numa_info) 1550 { 1551 return -EINVAL; 1552 } 1553 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1554 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1555 static inline void amdgpu_acpi_detect(void) { } 1556 static inline void amdgpu_acpi_release(void) { } 1557 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1558 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1559 u8 dev_state, bool drv_state) { return 0; } 1560 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1561 enum amdgpu_ss ss_state) { return 0; } 1562 #endif 1563 1564 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1565 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1566 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1567 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1568 #else 1569 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1570 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1571 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1572 #endif 1573 1574 #if defined(CONFIG_DRM_AMD_DC) 1575 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1576 #else 1577 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1578 #endif 1579 1580 1581 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1582 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1583 1584 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1585 pci_channel_state_t state); 1586 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1587 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1588 void amdgpu_pci_resume(struct pci_dev *pdev); 1589 1590 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1591 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1592 1593 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1594 1595 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1596 enum amd_clockgating_state state); 1597 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1598 enum amd_powergating_state state); 1599 1600 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1601 { 1602 return amdgpu_gpu_recovery != 0 && 1603 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1604 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1605 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1606 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1607 } 1608 1609 #include "amdgpu_object.h" 1610 1611 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1612 { 1613 return adev->gmc.tmz_enabled; 1614 } 1615 1616 int amdgpu_in_reset(struct amdgpu_device *adev); 1617 1618 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1619 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1620 extern const struct attribute_group amdgpu_flash_attr_group; 1621 1622 #endif 1623