1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 #if defined(CONFIG_DRM_AMD_ISP) 116 #include "amdgpu_isp.h" 117 #endif 118 119 #define MAX_GPU_INSTANCE 64 120 121 #define GFX_SLICE_PERIOD msecs_to_jiffies(250) 122 123 struct amdgpu_gpu_instance { 124 struct amdgpu_device *adev; 125 int mgpu_fan_enabled; 126 }; 127 128 struct amdgpu_mgpu_info { 129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 130 struct mutex mutex; 131 uint32_t num_gpu; 132 uint32_t num_dgpu; 133 uint32_t num_apu; 134 135 /* delayed reset_func for XGMI configuration if necessary */ 136 struct delayed_work delayed_reset_work; 137 bool pending_reset; 138 }; 139 140 enum amdgpu_ss { 141 AMDGPU_SS_DRV_LOAD, 142 AMDGPU_SS_DEV_D0, 143 AMDGPU_SS_DEV_D3, 144 AMDGPU_SS_DRV_UNLOAD 145 }; 146 147 struct amdgpu_hwip_reg_entry { 148 u32 hwip; 149 u32 inst; 150 u32 seg; 151 u32 reg_offset; 152 const char *reg_name; 153 }; 154 155 struct amdgpu_watchdog_timer { 156 bool timeout_fatal_disable; 157 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 158 }; 159 160 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 161 162 /* 163 * Modules parameters. 164 */ 165 extern int amdgpu_modeset; 166 extern unsigned int amdgpu_vram_limit; 167 extern int amdgpu_vis_vram_limit; 168 extern int amdgpu_gart_size; 169 extern int amdgpu_gtt_size; 170 extern int amdgpu_moverate; 171 extern int amdgpu_audio; 172 extern int amdgpu_disp_priority; 173 extern int amdgpu_hw_i2c; 174 extern int amdgpu_pcie_gen2; 175 extern int amdgpu_msi; 176 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 177 extern int amdgpu_dpm; 178 extern int amdgpu_fw_load_type; 179 extern int amdgpu_aspm; 180 extern int amdgpu_runtime_pm; 181 extern uint amdgpu_ip_block_mask; 182 extern int amdgpu_bapm; 183 extern int amdgpu_deep_color; 184 extern int amdgpu_vm_size; 185 extern int amdgpu_vm_block_size; 186 extern int amdgpu_vm_fragment_size; 187 extern int amdgpu_vm_fault_stop; 188 extern int amdgpu_vm_debug; 189 extern int amdgpu_vm_update_mode; 190 extern int amdgpu_exp_hw_support; 191 extern int amdgpu_dc; 192 extern int amdgpu_sched_jobs; 193 extern int amdgpu_sched_hw_submission; 194 extern uint amdgpu_pcie_gen_cap; 195 extern uint amdgpu_pcie_lane_cap; 196 extern u64 amdgpu_cg_mask; 197 extern uint amdgpu_pg_mask; 198 extern uint amdgpu_sdma_phase_quantum; 199 extern char *amdgpu_disable_cu; 200 extern char *amdgpu_virtual_display; 201 extern uint amdgpu_pp_feature_mask; 202 extern uint amdgpu_force_long_training; 203 extern int amdgpu_lbpw; 204 extern int amdgpu_compute_multipipe; 205 extern int amdgpu_gpu_recovery; 206 extern int amdgpu_emu_mode; 207 extern uint amdgpu_smu_memory_pool_size; 208 extern int amdgpu_smu_pptable_id; 209 extern uint amdgpu_dc_feature_mask; 210 extern uint amdgpu_freesync_vid_mode; 211 extern uint amdgpu_dc_debug_mask; 212 extern uint amdgpu_dc_visual_confirm; 213 extern int amdgpu_dm_abm_level; 214 extern int amdgpu_backlight; 215 extern int amdgpu_damage_clips; 216 extern struct amdgpu_mgpu_info mgpu_info; 217 extern int amdgpu_ras_enable; 218 extern uint amdgpu_ras_mask; 219 extern int amdgpu_bad_page_threshold; 220 extern bool amdgpu_ignore_bad_page_threshold; 221 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 222 extern int amdgpu_async_gfx_ring; 223 extern int amdgpu_mcbp; 224 extern int amdgpu_discovery; 225 extern int amdgpu_mes; 226 extern int amdgpu_mes_log_enable; 227 extern int amdgpu_mes_kiq; 228 extern int amdgpu_uni_mes; 229 extern int amdgpu_noretry; 230 extern int amdgpu_force_asic_type; 231 extern int amdgpu_smartshift_bias; 232 extern int amdgpu_use_xgmi_p2p; 233 extern int amdgpu_mtype_local; 234 extern bool enforce_isolation; 235 #ifdef CONFIG_HSA_AMD 236 extern int sched_policy; 237 extern bool debug_evictions; 238 extern bool no_system_mem_limit; 239 extern int halt_if_hws_hang; 240 extern uint amdgpu_svm_default_granularity; 241 #else 242 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 243 static const bool __maybe_unused debug_evictions; /* = false */ 244 static const bool __maybe_unused no_system_mem_limit; 245 static const int __maybe_unused halt_if_hws_hang; 246 #endif 247 #ifdef CONFIG_HSA_AMD_P2P 248 extern bool pcie_p2p; 249 #endif 250 251 extern int amdgpu_tmz; 252 extern int amdgpu_reset_method; 253 254 #ifdef CONFIG_DRM_AMDGPU_SI 255 extern int amdgpu_si_support; 256 #endif 257 #ifdef CONFIG_DRM_AMDGPU_CIK 258 extern int amdgpu_cik_support; 259 #endif 260 extern int amdgpu_num_kcq; 261 262 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 263 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 264 extern int amdgpu_vcnfw_log; 265 extern int amdgpu_sg_display; 266 extern int amdgpu_umsch_mm; 267 extern int amdgpu_seamless; 268 extern int amdgpu_umsch_mm_fwlog; 269 270 extern int amdgpu_user_partt_mode; 271 extern int amdgpu_agp; 272 273 extern int amdgpu_wbrf; 274 275 #define AMDGPU_VM_MAX_NUM_CTX 4096 276 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 277 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 278 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 279 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 280 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 281 #define AMDGPUFB_CONN_LIMIT 4 282 #define AMDGPU_BIOS_NUM_SCRATCH 16 283 284 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 285 286 /* hard reset data */ 287 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 288 289 /* reset flags */ 290 #define AMDGPU_RESET_GFX (1 << 0) 291 #define AMDGPU_RESET_COMPUTE (1 << 1) 292 #define AMDGPU_RESET_DMA (1 << 2) 293 #define AMDGPU_RESET_CP (1 << 3) 294 #define AMDGPU_RESET_GRBM (1 << 4) 295 #define AMDGPU_RESET_DMA1 (1 << 5) 296 #define AMDGPU_RESET_RLC (1 << 6) 297 #define AMDGPU_RESET_SEM (1 << 7) 298 #define AMDGPU_RESET_IH (1 << 8) 299 #define AMDGPU_RESET_VMC (1 << 9) 300 #define AMDGPU_RESET_MC (1 << 10) 301 #define AMDGPU_RESET_DISPLAY (1 << 11) 302 #define AMDGPU_RESET_UVD (1 << 12) 303 #define AMDGPU_RESET_VCE (1 << 13) 304 #define AMDGPU_RESET_VCE1 (1 << 14) 305 306 /* max cursor sizes (in pixels) */ 307 #define CIK_CURSOR_WIDTH 128 308 #define CIK_CURSOR_HEIGHT 128 309 310 /* smart shift bias level limits */ 311 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 312 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 313 314 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 315 #define AMDGPU_SWCTF_EXTRA_DELAY 50 316 317 struct amdgpu_xcp_mgr; 318 struct amdgpu_device; 319 struct amdgpu_irq_src; 320 struct amdgpu_fpriv; 321 struct amdgpu_bo_va_mapping; 322 struct kfd_vm_fault_info; 323 struct amdgpu_hive_info; 324 struct amdgpu_reset_context; 325 struct amdgpu_reset_control; 326 327 enum amdgpu_cp_irq { 328 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 329 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 330 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 331 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 332 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 333 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 334 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 338 339 AMDGPU_CP_IRQ_LAST 340 }; 341 342 enum amdgpu_thermal_irq { 343 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 344 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 345 346 AMDGPU_THERMAL_IRQ_LAST 347 }; 348 349 enum amdgpu_kiq_irq { 350 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 351 AMDGPU_CP_KIQ_IRQ_LAST 352 }; 353 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 354 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 355 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 356 #define MAX_KIQ_REG_TRY 1000 357 358 int amdgpu_device_ip_set_clockgating_state(void *dev, 359 enum amd_ip_block_type block_type, 360 enum amd_clockgating_state state); 361 int amdgpu_device_ip_set_powergating_state(void *dev, 362 enum amd_ip_block_type block_type, 363 enum amd_powergating_state state); 364 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 365 u64 *flags); 366 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 367 enum amd_ip_block_type block_type); 368 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 369 enum amd_ip_block_type block_type); 370 371 #define AMDGPU_MAX_IP_NUM 16 372 373 struct amdgpu_ip_block_status { 374 bool valid; 375 bool sw; 376 bool hw; 377 bool late_initialized; 378 bool hang; 379 }; 380 381 struct amdgpu_ip_block_version { 382 const enum amd_ip_block_type type; 383 const u32 major; 384 const u32 minor; 385 const u32 rev; 386 const struct amd_ip_funcs *funcs; 387 }; 388 389 struct amdgpu_ip_block { 390 struct amdgpu_ip_block_status status; 391 const struct amdgpu_ip_block_version *version; 392 struct amdgpu_device *adev; 393 }; 394 395 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 396 enum amd_ip_block_type type, 397 u32 major, u32 minor); 398 399 struct amdgpu_ip_block * 400 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 401 enum amd_ip_block_type type); 402 403 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 404 const struct amdgpu_ip_block_version *ip_block_version); 405 406 /* 407 * BIOS. 408 */ 409 bool amdgpu_get_bios(struct amdgpu_device *adev); 410 bool amdgpu_read_bios(struct amdgpu_device *adev); 411 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 412 u8 *bios, u32 length_bytes); 413 /* 414 * Clocks 415 */ 416 417 #define AMDGPU_MAX_PPLL 3 418 419 struct amdgpu_clock { 420 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 421 struct amdgpu_pll spll; 422 struct amdgpu_pll mpll; 423 /* 10 Khz units */ 424 uint32_t default_mclk; 425 uint32_t default_sclk; 426 uint32_t default_dispclk; 427 uint32_t current_dispclk; 428 uint32_t dp_extclk; 429 uint32_t max_pixel_clock; 430 }; 431 432 /* sub-allocation manager, it has to be protected by another lock. 433 * By conception this is an helper for other part of the driver 434 * like the indirect buffer or semaphore, which both have their 435 * locking. 436 * 437 * Principe is simple, we keep a list of sub allocation in offset 438 * order (first entry has offset == 0, last entry has the highest 439 * offset). 440 * 441 * When allocating new object we first check if there is room at 442 * the end total_size - (last_object_offset + last_object_size) >= 443 * alloc_size. If so we allocate new object there. 444 * 445 * When there is not enough room at the end, we start waiting for 446 * each sub object until we reach object_offset+object_size >= 447 * alloc_size, this object then become the sub object we return. 448 * 449 * Alignment can't be bigger than page size. 450 * 451 * Hole are not considered for allocation to keep things simple. 452 * Assumption is that there won't be hole (all object on same 453 * alignment). 454 */ 455 456 struct amdgpu_sa_manager { 457 struct drm_suballoc_manager base; 458 struct amdgpu_bo *bo; 459 uint64_t gpu_addr; 460 void *cpu_ptr; 461 }; 462 463 int amdgpu_fence_slab_init(void); 464 void amdgpu_fence_slab_fini(void); 465 466 /* 467 * IRQS. 468 */ 469 470 struct amdgpu_flip_work { 471 struct delayed_work flip_work; 472 struct work_struct unpin_work; 473 struct amdgpu_device *adev; 474 int crtc_id; 475 u32 target_vblank; 476 uint64_t base; 477 struct drm_pending_vblank_event *event; 478 struct amdgpu_bo *old_abo; 479 unsigned shared_count; 480 struct dma_fence **shared; 481 struct dma_fence_cb cb; 482 bool async; 483 }; 484 485 486 /* 487 * file private structure 488 */ 489 490 struct amdgpu_fpriv { 491 struct amdgpu_vm vm; 492 struct amdgpu_bo_va *prt_va; 493 struct amdgpu_bo_va *csa_va; 494 struct amdgpu_bo_va *seq64_va; 495 struct mutex bo_list_lock; 496 struct idr bo_list_handles; 497 struct amdgpu_ctx_mgr ctx_mgr; 498 /** GPU partition selection */ 499 uint32_t xcp_id; 500 }; 501 502 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 503 504 /* 505 * Writeback 506 */ 507 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 508 509 struct amdgpu_wb { 510 struct amdgpu_bo *wb_obj; 511 volatile uint32_t *wb; 512 uint64_t gpu_addr; 513 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 514 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 515 spinlock_t lock; 516 }; 517 518 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 519 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 520 521 /* 522 * Benchmarking 523 */ 524 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 525 526 /* 527 * ASIC specific register table accessible by UMD 528 */ 529 struct amdgpu_allowed_register_entry { 530 uint32_t reg_offset; 531 bool grbm_indexed; 532 }; 533 534 /** 535 * enum amd_reset_method - Methods for resetting AMD GPU devices 536 * 537 * @AMD_RESET_METHOD_NONE: The device will not be reset. 538 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 539 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 540 * any device. 541 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 542 * individually. Suitable only for some discrete GPU, not 543 * available for all ASICs. 544 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 545 * are reset depends on the ASIC. Notably doesn't reset IPs 546 * shared with the CPU on APUs or the memory controllers (so 547 * VRAM is not lost). Not available on all ASICs. 548 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 549 * but without powering off the PCI bus. Suitable only for 550 * discrete GPUs. 551 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 552 * and does a secondary bus reset or FLR, depending on what the 553 * underlying hardware supports. 554 * 555 * Methods available for AMD GPU driver for resetting the device. Not all 556 * methods are suitable for every device. User can override the method using 557 * module parameter `reset_method`. 558 */ 559 enum amd_reset_method { 560 AMD_RESET_METHOD_NONE = -1, 561 AMD_RESET_METHOD_LEGACY = 0, 562 AMD_RESET_METHOD_MODE0, 563 AMD_RESET_METHOD_MODE1, 564 AMD_RESET_METHOD_MODE2, 565 AMD_RESET_METHOD_BACO, 566 AMD_RESET_METHOD_PCI, 567 AMD_RESET_METHOD_ON_INIT, 568 }; 569 570 struct amdgpu_video_codec_info { 571 u32 codec_type; 572 u32 max_width; 573 u32 max_height; 574 u32 max_pixels_per_frame; 575 u32 max_level; 576 }; 577 578 #define codec_info_build(type, width, height, level) \ 579 .codec_type = type,\ 580 .max_width = width,\ 581 .max_height = height,\ 582 .max_pixels_per_frame = height * width,\ 583 .max_level = level, 584 585 struct amdgpu_video_codecs { 586 const u32 codec_count; 587 const struct amdgpu_video_codec_info *codec_array; 588 }; 589 590 /* 591 * ASIC specific functions. 592 */ 593 struct amdgpu_asic_funcs { 594 bool (*read_disabled_bios)(struct amdgpu_device *adev); 595 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 596 u8 *bios, u32 length_bytes); 597 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 598 u32 sh_num, u32 reg_offset, u32 *value); 599 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 600 int (*reset)(struct amdgpu_device *adev); 601 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 602 /* get the reference clock */ 603 u32 (*get_xclk)(struct amdgpu_device *adev); 604 /* MM block clocks */ 605 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 606 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 607 /* static power management */ 608 int (*get_pcie_lanes)(struct amdgpu_device *adev); 609 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 610 /* get config memsize register */ 611 u32 (*get_config_memsize)(struct amdgpu_device *adev); 612 /* flush hdp write queue */ 613 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 614 /* invalidate hdp read cache */ 615 void (*invalidate_hdp)(struct amdgpu_device *adev, 616 struct amdgpu_ring *ring); 617 /* check if the asic needs a full reset of if soft reset will work */ 618 bool (*need_full_reset)(struct amdgpu_device *adev); 619 /* initialize doorbell layout for specific asic*/ 620 void (*init_doorbell_index)(struct amdgpu_device *adev); 621 /* PCIe bandwidth usage */ 622 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 623 uint64_t *count1); 624 /* do we need to reset the asic at init time (e.g., kexec) */ 625 bool (*need_reset_on_init)(struct amdgpu_device *adev); 626 /* PCIe replay counter */ 627 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 628 /* device supports BACO */ 629 int (*supports_baco)(struct amdgpu_device *adev); 630 /* pre asic_init quirks */ 631 void (*pre_asic_init)(struct amdgpu_device *adev); 632 /* enter/exit umd stable pstate */ 633 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 634 /* query video codecs */ 635 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 636 const struct amdgpu_video_codecs **codecs); 637 /* encode "> 32bits" smn addressing */ 638 u64 (*encode_ext_smn_addressing)(int ext_id); 639 640 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 641 enum amdgpu_reg_state reg_state, void *buf, 642 size_t max_size); 643 }; 644 645 /* 646 * IOCTL. 647 */ 648 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 649 struct drm_file *filp); 650 651 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 652 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 653 struct drm_file *filp); 654 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 655 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 656 struct drm_file *filp); 657 658 /* VRAM scratch page for HDP bug, default vram page */ 659 struct amdgpu_mem_scratch { 660 struct amdgpu_bo *robj; 661 volatile uint32_t *ptr; 662 u64 gpu_addr; 663 }; 664 665 /* 666 * CGS 667 */ 668 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 669 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 670 671 /* 672 * Core structure, functions and helpers. 673 */ 674 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 675 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 676 677 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 678 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 679 680 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 681 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 682 683 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 684 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 685 686 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 687 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 688 689 struct amdgpu_mmio_remap { 690 u32 reg_offset; 691 resource_size_t bus_addr; 692 }; 693 694 /* Define the HW IP blocks will be used in driver , add more if necessary */ 695 enum amd_hw_ip_block_type { 696 GC_HWIP = 1, 697 HDP_HWIP, 698 SDMA0_HWIP, 699 SDMA1_HWIP, 700 SDMA2_HWIP, 701 SDMA3_HWIP, 702 SDMA4_HWIP, 703 SDMA5_HWIP, 704 SDMA6_HWIP, 705 SDMA7_HWIP, 706 LSDMA_HWIP, 707 MMHUB_HWIP, 708 ATHUB_HWIP, 709 NBIO_HWIP, 710 MP0_HWIP, 711 MP1_HWIP, 712 UVD_HWIP, 713 VCN_HWIP = UVD_HWIP, 714 JPEG_HWIP = VCN_HWIP, 715 VCN1_HWIP, 716 VCE_HWIP, 717 VPE_HWIP, 718 DF_HWIP, 719 DCE_HWIP, 720 OSSSYS_HWIP, 721 SMUIO_HWIP, 722 PWR_HWIP, 723 NBIF_HWIP, 724 THM_HWIP, 725 CLK_HWIP, 726 UMC_HWIP, 727 RSMU_HWIP, 728 XGMI_HWIP, 729 DCI_HWIP, 730 PCIE_HWIP, 731 ISP_HWIP, 732 MAX_HWIP 733 }; 734 735 #define HWIP_MAX_INSTANCE 44 736 737 #define HW_ID_MAX 300 738 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 739 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 740 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 741 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 742 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 743 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 744 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 745 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 746 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 747 748 struct amdgpu_ip_map_info { 749 /* Map of logical to actual dev instances/mask */ 750 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 751 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 752 enum amd_hw_ip_block_type block, 753 int8_t inst); 754 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 755 enum amd_hw_ip_block_type block, 756 uint32_t mask); 757 }; 758 759 struct amd_powerplay { 760 void *pp_handle; 761 const struct amd_pm_funcs *pp_funcs; 762 }; 763 764 struct ip_discovery_top; 765 766 /* polaris10 kickers */ 767 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 768 ((rid == 0xE3) || \ 769 (rid == 0xE4) || \ 770 (rid == 0xE5) || \ 771 (rid == 0xE7) || \ 772 (rid == 0xEF))) || \ 773 ((did == 0x6FDF) && \ 774 ((rid == 0xE7) || \ 775 (rid == 0xEF) || \ 776 (rid == 0xFF)))) 777 778 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 779 ((rid == 0xE1) || \ 780 (rid == 0xF7))) 781 782 /* polaris11 kickers */ 783 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 784 ((rid == 0xE0) || \ 785 (rid == 0xE5))) || \ 786 ((did == 0x67FF) && \ 787 ((rid == 0xCF) || \ 788 (rid == 0xEF) || \ 789 (rid == 0xFF)))) 790 791 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 792 ((rid == 0xE2))) 793 794 /* polaris12 kickers */ 795 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 796 ((rid == 0xC0) || \ 797 (rid == 0xC1) || \ 798 (rid == 0xC3) || \ 799 (rid == 0xC7))) || \ 800 ((did == 0x6981) && \ 801 ((rid == 0x00) || \ 802 (rid == 0x01) || \ 803 (rid == 0x10)))) 804 805 struct amdgpu_mqd_prop { 806 uint64_t mqd_gpu_addr; 807 uint64_t hqd_base_gpu_addr; 808 uint64_t rptr_gpu_addr; 809 uint64_t wptr_gpu_addr; 810 uint32_t queue_size; 811 bool use_doorbell; 812 uint32_t doorbell_index; 813 uint64_t eop_gpu_addr; 814 uint32_t hqd_pipe_priority; 815 uint32_t hqd_queue_priority; 816 bool allow_tunneling; 817 bool hqd_active; 818 }; 819 820 struct amdgpu_mqd { 821 unsigned mqd_size; 822 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 823 struct amdgpu_mqd_prop *p); 824 }; 825 826 /* 827 * Custom Init levels could be defined for different situations where a full 828 * initialization of all hardware blocks are not expected. Sample cases are 829 * custom init sequences after resume after S0i3/S3, reset on initialization, 830 * partial reset of blocks etc. Presently, this defines only two levels. Levels 831 * are described in corresponding struct definitions - amdgpu_init_default, 832 * amdgpu_init_minimal_xgmi. 833 */ 834 enum amdgpu_init_lvl_id { 835 AMDGPU_INIT_LEVEL_DEFAULT, 836 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 837 }; 838 839 struct amdgpu_init_level { 840 enum amdgpu_init_lvl_id level; 841 uint32_t hwini_ip_block_mask; 842 }; 843 844 #define AMDGPU_RESET_MAGIC_NUM 64 845 #define AMDGPU_MAX_DF_PERFMONS 4 846 struct amdgpu_reset_domain; 847 struct amdgpu_fru_info; 848 849 /* 850 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 851 */ 852 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 853 854 struct amdgpu_device { 855 struct device *dev; 856 struct pci_dev *pdev; 857 struct drm_device ddev; 858 859 #ifdef CONFIG_DRM_AMD_ACP 860 struct amdgpu_acp acp; 861 #endif 862 struct amdgpu_hive_info *hive; 863 struct amdgpu_xcp_mgr *xcp_mgr; 864 /* ASIC */ 865 enum amd_asic_type asic_type; 866 uint32_t family; 867 uint32_t rev_id; 868 uint32_t external_rev_id; 869 unsigned long flags; 870 unsigned long apu_flags; 871 int usec_timeout; 872 const struct amdgpu_asic_funcs *asic_funcs; 873 bool shutdown; 874 bool need_swiotlb; 875 bool accel_working; 876 struct notifier_block acpi_nb; 877 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 878 struct debugfs_blob_wrapper debugfs_vbios_blob; 879 struct debugfs_blob_wrapper debugfs_discovery_blob; 880 struct mutex srbm_mutex; 881 /* GRBM index mutex. Protects concurrent access to GRBM index */ 882 struct mutex grbm_idx_mutex; 883 struct dev_pm_domain vga_pm_domain; 884 bool have_disp_power_ref; 885 bool have_atomics_support; 886 887 /* BIOS */ 888 bool is_atom_fw; 889 uint8_t *bios; 890 uint32_t bios_size; 891 uint32_t bios_scratch_reg_offset; 892 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 893 894 /* Register/doorbell mmio */ 895 resource_size_t rmmio_base; 896 resource_size_t rmmio_size; 897 void __iomem *rmmio; 898 /* protects concurrent MM_INDEX/DATA based register access */ 899 spinlock_t mmio_idx_lock; 900 struct amdgpu_mmio_remap rmmio_remap; 901 /* protects concurrent SMC based register access */ 902 spinlock_t smc_idx_lock; 903 amdgpu_rreg_t smc_rreg; 904 amdgpu_wreg_t smc_wreg; 905 /* protects concurrent PCIE register access */ 906 spinlock_t pcie_idx_lock; 907 amdgpu_rreg_t pcie_rreg; 908 amdgpu_wreg_t pcie_wreg; 909 amdgpu_rreg_t pciep_rreg; 910 amdgpu_wreg_t pciep_wreg; 911 amdgpu_rreg_ext_t pcie_rreg_ext; 912 amdgpu_wreg_ext_t pcie_wreg_ext; 913 amdgpu_rreg64_t pcie_rreg64; 914 amdgpu_wreg64_t pcie_wreg64; 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 /* protects concurrent UVD register access */ 918 spinlock_t uvd_ctx_idx_lock; 919 amdgpu_rreg_t uvd_ctx_rreg; 920 amdgpu_wreg_t uvd_ctx_wreg; 921 /* protects concurrent DIDT register access */ 922 spinlock_t didt_idx_lock; 923 amdgpu_rreg_t didt_rreg; 924 amdgpu_wreg_t didt_wreg; 925 /* protects concurrent gc_cac register access */ 926 spinlock_t gc_cac_idx_lock; 927 amdgpu_rreg_t gc_cac_rreg; 928 amdgpu_wreg_t gc_cac_wreg; 929 /* protects concurrent se_cac register access */ 930 spinlock_t se_cac_idx_lock; 931 amdgpu_rreg_t se_cac_rreg; 932 amdgpu_wreg_t se_cac_wreg; 933 /* protects concurrent ENDPOINT (audio) register access */ 934 spinlock_t audio_endpt_idx_lock; 935 amdgpu_block_rreg_t audio_endpt_rreg; 936 amdgpu_block_wreg_t audio_endpt_wreg; 937 struct amdgpu_doorbell doorbell; 938 939 /* clock/pll info */ 940 struct amdgpu_clock clock; 941 942 /* MC */ 943 struct amdgpu_gmc gmc; 944 struct amdgpu_gart gart; 945 dma_addr_t dummy_page_addr; 946 struct amdgpu_vm_manager vm_manager; 947 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 948 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 949 950 /* memory management */ 951 struct amdgpu_mman mman; 952 struct amdgpu_mem_scratch mem_scratch; 953 struct amdgpu_wb wb; 954 atomic64_t num_bytes_moved; 955 atomic64_t num_evictions; 956 atomic64_t num_vram_cpu_page_faults; 957 atomic_t gpu_reset_counter; 958 atomic_t vram_lost_counter; 959 960 /* data for buffer migration throttling */ 961 struct { 962 spinlock_t lock; 963 s64 last_update_us; 964 s64 accum_us; /* accumulated microseconds */ 965 s64 accum_us_vis; /* for visible VRAM */ 966 u32 log2_max_MBps; 967 } mm_stats; 968 969 /* display */ 970 bool enable_virtual_display; 971 struct amdgpu_vkms_output *amdgpu_vkms_output; 972 struct amdgpu_mode_info mode_info; 973 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 974 struct delayed_work hotplug_work; 975 struct amdgpu_irq_src crtc_irq; 976 struct amdgpu_irq_src vline0_irq; 977 struct amdgpu_irq_src vupdate_irq; 978 struct amdgpu_irq_src pageflip_irq; 979 struct amdgpu_irq_src hpd_irq; 980 struct amdgpu_irq_src dmub_trace_irq; 981 struct amdgpu_irq_src dmub_outbox_irq; 982 983 /* rings */ 984 u64 fence_context; 985 unsigned num_rings; 986 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 987 struct dma_fence __rcu *gang_submit; 988 bool ib_pool_ready; 989 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 990 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 991 992 /* interrupts */ 993 struct amdgpu_irq irq; 994 995 /* powerplay */ 996 struct amd_powerplay powerplay; 997 struct amdgpu_pm pm; 998 u64 cg_flags; 999 u32 pg_flags; 1000 1001 /* nbio */ 1002 struct amdgpu_nbio nbio; 1003 1004 /* hdp */ 1005 struct amdgpu_hdp hdp; 1006 1007 /* smuio */ 1008 struct amdgpu_smuio smuio; 1009 1010 /* mmhub */ 1011 struct amdgpu_mmhub mmhub; 1012 1013 /* gfxhub */ 1014 struct amdgpu_gfxhub gfxhub; 1015 1016 /* gfx */ 1017 struct amdgpu_gfx gfx; 1018 1019 /* sdma */ 1020 struct amdgpu_sdma sdma; 1021 1022 /* lsdma */ 1023 struct amdgpu_lsdma lsdma; 1024 1025 /* uvd */ 1026 struct amdgpu_uvd uvd; 1027 1028 /* vce */ 1029 struct amdgpu_vce vce; 1030 1031 /* vcn */ 1032 struct amdgpu_vcn vcn; 1033 1034 /* jpeg */ 1035 struct amdgpu_jpeg jpeg; 1036 1037 /* vpe */ 1038 struct amdgpu_vpe vpe; 1039 1040 /* umsch */ 1041 struct amdgpu_umsch_mm umsch_mm; 1042 bool enable_umsch_mm; 1043 1044 /* firmwares */ 1045 struct amdgpu_firmware firmware; 1046 1047 /* PSP */ 1048 struct psp_context psp; 1049 1050 /* GDS */ 1051 struct amdgpu_gds gds; 1052 1053 /* for userq and VM fences */ 1054 struct amdgpu_seq64 seq64; 1055 1056 /* KFD */ 1057 struct amdgpu_kfd_dev kfd; 1058 1059 /* UMC */ 1060 struct amdgpu_umc umc; 1061 1062 /* display related functionality */ 1063 struct amdgpu_display_manager dm; 1064 1065 #if defined(CONFIG_DRM_AMD_ISP) 1066 /* isp */ 1067 struct amdgpu_isp isp; 1068 #endif 1069 1070 /* mes */ 1071 bool enable_mes; 1072 bool enable_mes_kiq; 1073 bool enable_uni_mes; 1074 struct amdgpu_mes mes; 1075 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1076 1077 /* df */ 1078 struct amdgpu_df df; 1079 1080 /* MCA */ 1081 struct amdgpu_mca mca; 1082 1083 /* ACA */ 1084 struct amdgpu_aca aca; 1085 1086 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1087 uint32_t harvest_ip_mask; 1088 int num_ip_blocks; 1089 struct mutex mn_lock; 1090 DECLARE_HASHTABLE(mn_hash, 7); 1091 1092 /* tracking pinned memory */ 1093 atomic64_t vram_pin_size; 1094 atomic64_t visible_pin_size; 1095 atomic64_t gart_pin_size; 1096 1097 /* soc15 register offset based on ip, instance and segment */ 1098 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1099 struct amdgpu_ip_map_info ip_map; 1100 1101 /* delayed work_func for deferring clockgating during resume */ 1102 struct delayed_work delayed_init_work; 1103 1104 struct amdgpu_virt virt; 1105 1106 /* record hw reset is performed */ 1107 bool has_hw_reset; 1108 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1109 1110 /* s3/s4 mask */ 1111 bool in_suspend; 1112 bool in_s3; 1113 bool in_s4; 1114 bool in_s0ix; 1115 /* indicate amdgpu suspension status */ 1116 bool suspend_complete; 1117 1118 enum pp_mp1_state mp1_state; 1119 struct amdgpu_doorbell_index doorbell_index; 1120 1121 struct mutex notifier_lock; 1122 1123 int asic_reset_res; 1124 struct work_struct xgmi_reset_work; 1125 struct list_head reset_list; 1126 1127 long gfx_timeout; 1128 long sdma_timeout; 1129 long video_timeout; 1130 long compute_timeout; 1131 long psp_timeout; 1132 1133 uint64_t unique_id; 1134 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1135 1136 /* enable runtime pm on the device */ 1137 bool in_runpm; 1138 bool has_pr3; 1139 1140 bool ucode_sysfs_en; 1141 1142 struct amdgpu_fru_info *fru_info; 1143 atomic_t throttling_logging_enabled; 1144 struct ratelimit_state throttling_logging_rs; 1145 uint32_t ras_hw_enabled; 1146 uint32_t ras_enabled; 1147 1148 bool no_hw_access; 1149 struct pci_saved_state *pci_state; 1150 pci_channel_state_t pci_channel_state; 1151 1152 /* Track auto wait count on s_barrier settings */ 1153 bool barrier_has_auto_waitcnt; 1154 1155 struct amdgpu_reset_control *reset_cntl; 1156 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1157 1158 bool ram_is_direct_mapped; 1159 1160 struct list_head ras_list; 1161 1162 struct ip_discovery_top *ip_top; 1163 1164 struct amdgpu_reset_domain *reset_domain; 1165 1166 struct mutex benchmark_mutex; 1167 1168 bool scpm_enabled; 1169 uint32_t scpm_status; 1170 1171 struct work_struct reset_work; 1172 1173 bool job_hang; 1174 bool dc_enabled; 1175 /* Mask of active clusters */ 1176 uint32_t aid_mask; 1177 1178 /* Debug */ 1179 bool debug_vm; 1180 bool debug_largebar; 1181 bool debug_disable_soft_recovery; 1182 bool debug_use_vram_fw_buf; 1183 bool debug_enable_ras_aca; 1184 bool debug_exp_resets; 1185 1186 bool enforce_isolation[MAX_XCP]; 1187 /* Added this mutex for cleaner shader isolation between GFX and compute processes */ 1188 struct mutex enforce_isolation_mutex; 1189 1190 struct amdgpu_init_level *init_lvl; 1191 }; 1192 1193 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1194 uint8_t ip, uint8_t inst) 1195 { 1196 /* This considers only major/minor/rev and ignores 1197 * subrevision/variant fields. 1198 */ 1199 return adev->ip_versions[ip][inst] & ~0xFFU; 1200 } 1201 1202 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1203 uint8_t ip, uint8_t inst) 1204 { 1205 /* This returns full version - major/minor/rev/variant/subrevision */ 1206 return adev->ip_versions[ip][inst]; 1207 } 1208 1209 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1210 { 1211 return container_of(ddev, struct amdgpu_device, ddev); 1212 } 1213 1214 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1215 { 1216 return &adev->ddev; 1217 } 1218 1219 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1220 { 1221 return container_of(bdev, struct amdgpu_device, mman.bdev); 1222 } 1223 1224 int amdgpu_device_init(struct amdgpu_device *adev, 1225 uint32_t flags); 1226 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1227 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1228 1229 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1230 1231 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1232 void *buf, size_t size, bool write); 1233 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1234 void *buf, size_t size, bool write); 1235 1236 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1237 void *buf, size_t size, bool write); 1238 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1239 uint32_t inst, uint32_t reg_addr, char reg_name[], 1240 uint32_t expected_value, uint32_t mask); 1241 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1242 uint32_t reg, uint32_t acc_flags); 1243 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1244 u64 reg_addr); 1245 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1246 uint32_t reg, uint32_t acc_flags, 1247 uint32_t xcc_id); 1248 void amdgpu_device_wreg(struct amdgpu_device *adev, 1249 uint32_t reg, uint32_t v, 1250 uint32_t acc_flags); 1251 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1252 u64 reg_addr, u32 reg_data); 1253 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1254 uint32_t reg, uint32_t v, 1255 uint32_t acc_flags, 1256 uint32_t xcc_id); 1257 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1258 uint32_t reg, uint32_t v, uint32_t xcc_id); 1259 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1260 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1261 1262 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1263 u32 reg_addr); 1264 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1265 u32 reg_addr); 1266 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1267 u64 reg_addr); 1268 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1269 u32 reg_addr, u32 reg_data); 1270 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1271 u32 reg_addr, u64 reg_data); 1272 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1273 u64 reg_addr, u64 reg_data); 1274 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1275 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1276 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1277 1278 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1279 1280 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1281 struct amdgpu_reset_context *reset_context); 1282 1283 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1284 struct amdgpu_reset_context *reset_context); 1285 1286 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1287 1288 int emu_soc_asic_init(struct amdgpu_device *adev); 1289 1290 /* 1291 * Registers read & write functions. 1292 */ 1293 #define AMDGPU_REGS_NO_KIQ (1<<1) 1294 #define AMDGPU_REGS_RLC (1<<2) 1295 1296 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1297 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1298 1299 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1300 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1301 1302 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1303 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1304 1305 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1306 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1307 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1308 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1309 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1310 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1311 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1312 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1313 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1314 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1315 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1316 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1317 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1318 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1319 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1320 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1321 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1322 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1323 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1324 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1325 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1326 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1327 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1328 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1329 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1330 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1331 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1332 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1333 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1334 #define WREG32_P(reg, val, mask) \ 1335 do { \ 1336 uint32_t tmp_ = RREG32(reg); \ 1337 tmp_ &= (mask); \ 1338 tmp_ |= ((val) & ~(mask)); \ 1339 WREG32(reg, tmp_); \ 1340 } while (0) 1341 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1342 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1343 #define WREG32_PLL_P(reg, val, mask) \ 1344 do { \ 1345 uint32_t tmp_ = RREG32_PLL(reg); \ 1346 tmp_ &= (mask); \ 1347 tmp_ |= ((val) & ~(mask)); \ 1348 WREG32_PLL(reg, tmp_); \ 1349 } while (0) 1350 1351 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1352 do { \ 1353 u32 tmp = RREG32_SMC(_Reg); \ 1354 tmp &= (_Mask); \ 1355 tmp |= ((_Val) & ~(_Mask)); \ 1356 WREG32_SMC(_Reg, tmp); \ 1357 } while (0) 1358 1359 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1360 1361 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1362 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1363 1364 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1365 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1366 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1367 1368 #define REG_GET_FIELD(value, reg, field) \ 1369 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1370 1371 #define WREG32_FIELD(reg, field, val) \ 1372 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1373 1374 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1375 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1376 1377 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1378 /* 1379 * BIOS helpers. 1380 */ 1381 #define RBIOS8(i) (adev->bios[i]) 1382 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1383 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1384 1385 /* 1386 * ASICs macro. 1387 */ 1388 #define amdgpu_asic_set_vga_state(adev, state) \ 1389 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1390 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1391 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1392 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1393 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1394 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1395 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1396 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1397 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1398 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1399 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1400 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1401 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1402 #define amdgpu_asic_flush_hdp(adev, r) \ 1403 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1404 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1405 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1406 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1407 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1408 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1409 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1410 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1411 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1412 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1413 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1414 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1415 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1416 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1417 1418 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1419 1420 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1421 #define for_each_inst(i, inst_mask) \ 1422 for (i = ffs(inst_mask); i-- != 0; \ 1423 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1424 1425 /* Common functions */ 1426 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1427 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1428 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1429 struct amdgpu_job *job, 1430 struct amdgpu_reset_context *reset_context); 1431 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1432 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1433 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1434 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1435 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1436 1437 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1438 u64 num_vis_bytes); 1439 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1440 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1441 const u32 *registers, 1442 const u32 array_size); 1443 1444 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1445 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1446 bool amdgpu_device_supports_px(struct drm_device *dev); 1447 bool amdgpu_device_supports_boco(struct drm_device *dev); 1448 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1449 int amdgpu_device_supports_baco(struct drm_device *dev); 1450 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1451 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1452 struct amdgpu_device *peer_adev); 1453 int amdgpu_device_baco_enter(struct drm_device *dev); 1454 int amdgpu_device_baco_exit(struct drm_device *dev); 1455 1456 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1457 struct amdgpu_ring *ring); 1458 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1459 struct amdgpu_ring *ring); 1460 1461 void amdgpu_device_halt(struct amdgpu_device *adev); 1462 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1463 u32 reg); 1464 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1465 u32 reg, u32 v); 1466 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1467 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1468 struct dma_fence *gang); 1469 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1470 1471 /* atpx handler */ 1472 #if defined(CONFIG_VGA_SWITCHEROO) 1473 void amdgpu_register_atpx_handler(void); 1474 void amdgpu_unregister_atpx_handler(void); 1475 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1476 bool amdgpu_is_atpx_hybrid(void); 1477 bool amdgpu_has_atpx(void); 1478 #else 1479 static inline void amdgpu_register_atpx_handler(void) {} 1480 static inline void amdgpu_unregister_atpx_handler(void) {} 1481 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1482 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1483 static inline bool amdgpu_has_atpx(void) { return false; } 1484 #endif 1485 1486 /* 1487 * KMS 1488 */ 1489 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1490 extern const int amdgpu_max_kms_ioctl; 1491 1492 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1493 void amdgpu_driver_unload_kms(struct drm_device *dev); 1494 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1495 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1496 struct drm_file *file_priv); 1497 void amdgpu_driver_release_kms(struct drm_device *dev); 1498 1499 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1500 int amdgpu_device_prepare(struct drm_device *dev); 1501 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1502 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1503 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1504 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1505 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1506 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1507 struct drm_file *filp); 1508 1509 /* 1510 * functions used by amdgpu_encoder.c 1511 */ 1512 struct amdgpu_afmt_acr { 1513 u32 clock; 1514 1515 int n_32khz; 1516 int cts_32khz; 1517 1518 int n_44_1khz; 1519 int cts_44_1khz; 1520 1521 int n_48khz; 1522 int cts_48khz; 1523 1524 }; 1525 1526 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1527 1528 /* amdgpu_acpi.c */ 1529 1530 struct amdgpu_numa_info { 1531 uint64_t size; 1532 int pxm; 1533 int nid; 1534 }; 1535 1536 /* ATCS Device/Driver State */ 1537 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1538 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1539 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1540 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1541 1542 #if defined(CONFIG_ACPI) 1543 int amdgpu_acpi_init(struct amdgpu_device *adev); 1544 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1545 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1546 bool amdgpu_acpi_is_power_shift_control_supported(void); 1547 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1548 u8 perf_req, bool advertise); 1549 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1550 u8 dev_state, bool drv_state); 1551 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1552 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1553 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1554 u64 *tmr_size); 1555 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1556 struct amdgpu_numa_info *numa_info); 1557 1558 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1559 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1560 void amdgpu_acpi_detect(void); 1561 void amdgpu_acpi_release(void); 1562 #else 1563 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1564 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1565 u64 *tmr_offset, u64 *tmr_size) 1566 { 1567 return -EINVAL; 1568 } 1569 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1570 int xcc_id, 1571 struct amdgpu_numa_info *numa_info) 1572 { 1573 return -EINVAL; 1574 } 1575 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1576 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1577 static inline void amdgpu_acpi_detect(void) { } 1578 static inline void amdgpu_acpi_release(void) { } 1579 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1580 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1581 u8 dev_state, bool drv_state) { return 0; } 1582 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1583 enum amdgpu_ss ss_state) { return 0; } 1584 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1585 #endif 1586 1587 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1588 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1589 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1590 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1591 #else 1592 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1593 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1594 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1595 #endif 1596 1597 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1598 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1599 1600 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1601 pci_channel_state_t state); 1602 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1603 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1604 void amdgpu_pci_resume(struct pci_dev *pdev); 1605 1606 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1607 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1608 1609 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1610 1611 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1612 enum amd_clockgating_state state); 1613 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1614 enum amd_powergating_state state); 1615 1616 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1617 { 1618 return amdgpu_gpu_recovery != 0 && 1619 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1620 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1621 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1622 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1623 } 1624 1625 #include "amdgpu_object.h" 1626 1627 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1628 { 1629 return adev->gmc.tmz_enabled; 1630 } 1631 1632 int amdgpu_in_reset(struct amdgpu_device *adev); 1633 1634 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1635 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1636 extern const struct attribute_group amdgpu_flash_attr_group; 1637 1638 void amdgpu_set_init_level(struct amdgpu_device *adev, 1639 enum amdgpu_init_lvl_id lvl); 1640 #endif 1641