1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <drm/ttm/ttm_bo_api.h> 40 #include <drm/ttm/ttm_bo_driver.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 #include <drm/gpu_scheduler.h> 49 50 #include <kgd_kfd_interface.h> 51 #include "dm_pp_interface.h" 52 #include "kgd_pp_interface.h" 53 54 #include "amd_shared.h" 55 #include "amdgpu_mode.h" 56 #include "amdgpu_ih.h" 57 #include "amdgpu_irq.h" 58 #include "amdgpu_ucode.h" 59 #include "amdgpu_ttm.h" 60 #include "amdgpu_psp.h" 61 #include "amdgpu_gds.h" 62 #include "amdgpu_sync.h" 63 #include "amdgpu_ring.h" 64 #include "amdgpu_vm.h" 65 #include "amdgpu_dpm.h" 66 #include "amdgpu_acp.h" 67 #include "amdgpu_uvd.h" 68 #include "amdgpu_vce.h" 69 #include "amdgpu_vcn.h" 70 #include "amdgpu_mn.h" 71 #include "amdgpu_gmc.h" 72 #include "amdgpu_dm.h" 73 #include "amdgpu_virt.h" 74 #include "amdgpu_gart.h" 75 #include "amdgpu_debugfs.h" 76 77 /* 78 * Modules parameters. 79 */ 80 extern int amdgpu_modeset; 81 extern int amdgpu_vram_limit; 82 extern int amdgpu_vis_vram_limit; 83 extern int amdgpu_gart_size; 84 extern int amdgpu_gtt_size; 85 extern int amdgpu_moverate; 86 extern int amdgpu_benchmarking; 87 extern int amdgpu_testing; 88 extern int amdgpu_audio; 89 extern int amdgpu_disp_priority; 90 extern int amdgpu_hw_i2c; 91 extern int amdgpu_pcie_gen2; 92 extern int amdgpu_msi; 93 extern int amdgpu_lockup_timeout; 94 extern int amdgpu_dpm; 95 extern int amdgpu_fw_load_type; 96 extern int amdgpu_aspm; 97 extern int amdgpu_runtime_pm; 98 extern uint amdgpu_ip_block_mask; 99 extern int amdgpu_bapm; 100 extern int amdgpu_deep_color; 101 extern int amdgpu_vm_size; 102 extern int amdgpu_vm_block_size; 103 extern int amdgpu_vm_fragment_size; 104 extern int amdgpu_vm_fault_stop; 105 extern int amdgpu_vm_debug; 106 extern int amdgpu_vm_update_mode; 107 extern int amdgpu_dc; 108 extern int amdgpu_dc_log; 109 extern int amdgpu_sched_jobs; 110 extern int amdgpu_sched_hw_submission; 111 extern int amdgpu_no_evict; 112 extern int amdgpu_direct_gma_size; 113 extern uint amdgpu_pcie_gen_cap; 114 extern uint amdgpu_pcie_lane_cap; 115 extern uint amdgpu_cg_mask; 116 extern uint amdgpu_pg_mask; 117 extern uint amdgpu_sdma_phase_quantum; 118 extern char *amdgpu_disable_cu; 119 extern char *amdgpu_virtual_display; 120 extern uint amdgpu_pp_feature_mask; 121 extern int amdgpu_vram_page_split; 122 extern int amdgpu_ngg; 123 extern int amdgpu_prim_buf_per_se; 124 extern int amdgpu_pos_buf_per_se; 125 extern int amdgpu_cntl_sb_buf_per_se; 126 extern int amdgpu_param_buf_per_se; 127 extern int amdgpu_job_hang_limit; 128 extern int amdgpu_lbpw; 129 extern int amdgpu_compute_multipipe; 130 extern int amdgpu_gpu_recovery; 131 extern int amdgpu_emu_mode; 132 extern uint amdgpu_smu_memory_pool_size; 133 134 #ifdef CONFIG_DRM_AMDGPU_SI 135 extern int amdgpu_si_support; 136 #endif 137 #ifdef CONFIG_DRM_AMDGPU_CIK 138 extern int amdgpu_cik_support; 139 #endif 140 141 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 142 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 143 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 144 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 145 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 146 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 147 #define AMDGPU_IB_POOL_SIZE 16 148 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 149 #define AMDGPUFB_CONN_LIMIT 4 150 #define AMDGPU_BIOS_NUM_SCRATCH 16 151 152 /* max number of IP instances */ 153 #define AMDGPU_MAX_SDMA_INSTANCES 2 154 155 /* hard reset data */ 156 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 157 158 /* reset flags */ 159 #define AMDGPU_RESET_GFX (1 << 0) 160 #define AMDGPU_RESET_COMPUTE (1 << 1) 161 #define AMDGPU_RESET_DMA (1 << 2) 162 #define AMDGPU_RESET_CP (1 << 3) 163 #define AMDGPU_RESET_GRBM (1 << 4) 164 #define AMDGPU_RESET_DMA1 (1 << 5) 165 #define AMDGPU_RESET_RLC (1 << 6) 166 #define AMDGPU_RESET_SEM (1 << 7) 167 #define AMDGPU_RESET_IH (1 << 8) 168 #define AMDGPU_RESET_VMC (1 << 9) 169 #define AMDGPU_RESET_MC (1 << 10) 170 #define AMDGPU_RESET_DISPLAY (1 << 11) 171 #define AMDGPU_RESET_UVD (1 << 12) 172 #define AMDGPU_RESET_VCE (1 << 13) 173 #define AMDGPU_RESET_VCE1 (1 << 14) 174 175 /* GFX current status */ 176 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 177 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 178 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 179 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 180 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 181 182 /* max cursor sizes (in pixels) */ 183 #define CIK_CURSOR_WIDTH 128 184 #define CIK_CURSOR_HEIGHT 128 185 186 struct amdgpu_device; 187 struct amdgpu_ib; 188 struct amdgpu_cs_parser; 189 struct amdgpu_job; 190 struct amdgpu_irq_src; 191 struct amdgpu_fpriv; 192 struct amdgpu_bo_va_mapping; 193 194 enum amdgpu_cp_irq { 195 AMDGPU_CP_IRQ_GFX_EOP = 0, 196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 204 205 AMDGPU_CP_IRQ_LAST 206 }; 207 208 enum amdgpu_sdma_irq { 209 AMDGPU_SDMA_IRQ_TRAP0 = 0, 210 AMDGPU_SDMA_IRQ_TRAP1, 211 212 AMDGPU_SDMA_IRQ_LAST 213 }; 214 215 enum amdgpu_thermal_irq { 216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 218 219 AMDGPU_THERMAL_IRQ_LAST 220 }; 221 222 enum amdgpu_kiq_irq { 223 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 224 AMDGPU_CP_KIQ_IRQ_LAST 225 }; 226 227 int amdgpu_device_ip_set_clockgating_state(void *dev, 228 enum amd_ip_block_type block_type, 229 enum amd_clockgating_state state); 230 int amdgpu_device_ip_set_powergating_state(void *dev, 231 enum amd_ip_block_type block_type, 232 enum amd_powergating_state state); 233 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 234 u32 *flags); 235 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 236 enum amd_ip_block_type block_type); 237 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 238 enum amd_ip_block_type block_type); 239 240 #define AMDGPU_MAX_IP_NUM 16 241 242 struct amdgpu_ip_block_status { 243 bool valid; 244 bool sw; 245 bool hw; 246 bool late_initialized; 247 bool hang; 248 }; 249 250 struct amdgpu_ip_block_version { 251 const enum amd_ip_block_type type; 252 const u32 major; 253 const u32 minor; 254 const u32 rev; 255 const struct amd_ip_funcs *funcs; 256 }; 257 258 struct amdgpu_ip_block { 259 struct amdgpu_ip_block_status status; 260 const struct amdgpu_ip_block_version *version; 261 }; 262 263 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 264 enum amd_ip_block_type type, 265 u32 major, u32 minor); 266 267 struct amdgpu_ip_block * 268 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 269 enum amd_ip_block_type type); 270 271 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 272 const struct amdgpu_ip_block_version *ip_block_version); 273 274 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 275 struct amdgpu_buffer_funcs { 276 /* maximum bytes in a single operation */ 277 uint32_t copy_max_bytes; 278 279 /* number of dw to reserve per operation */ 280 unsigned copy_num_dw; 281 282 /* used for buffer migration */ 283 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 284 /* src addr in bytes */ 285 uint64_t src_offset, 286 /* dst addr in bytes */ 287 uint64_t dst_offset, 288 /* number of byte to transfer */ 289 uint32_t byte_count); 290 291 /* maximum bytes in a single operation */ 292 uint32_t fill_max_bytes; 293 294 /* number of dw to reserve per operation */ 295 unsigned fill_num_dw; 296 297 /* used for buffer clearing */ 298 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 299 /* value to write to memory */ 300 uint32_t src_data, 301 /* dst addr in bytes */ 302 uint64_t dst_offset, 303 /* number of byte to fill */ 304 uint32_t byte_count); 305 }; 306 307 /* provided by hw blocks that can write ptes, e.g., sdma */ 308 struct amdgpu_vm_pte_funcs { 309 /* number of dw to reserve per operation */ 310 unsigned copy_pte_num_dw; 311 312 /* copy pte entries from GART */ 313 void (*copy_pte)(struct amdgpu_ib *ib, 314 uint64_t pe, uint64_t src, 315 unsigned count); 316 317 /* write pte one entry at a time with addr mapping */ 318 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 319 uint64_t value, unsigned count, 320 uint32_t incr); 321 /* for linear pte/pde updates without addr mapping */ 322 void (*set_pte_pde)(struct amdgpu_ib *ib, 323 uint64_t pe, 324 uint64_t addr, unsigned count, 325 uint32_t incr, uint64_t flags); 326 }; 327 328 /* provided by the ih block */ 329 struct amdgpu_ih_funcs { 330 /* ring read/write ptr handling, called from interrupt context */ 331 u32 (*get_wptr)(struct amdgpu_device *adev); 332 bool (*prescreen_iv)(struct amdgpu_device *adev); 333 void (*decode_iv)(struct amdgpu_device *adev, 334 struct amdgpu_iv_entry *entry); 335 void (*set_rptr)(struct amdgpu_device *adev); 336 }; 337 338 /* 339 * BIOS. 340 */ 341 bool amdgpu_get_bios(struct amdgpu_device *adev); 342 bool amdgpu_read_bios(struct amdgpu_device *adev); 343 344 /* 345 * Clocks 346 */ 347 348 #define AMDGPU_MAX_PPLL 3 349 350 struct amdgpu_clock { 351 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 352 struct amdgpu_pll spll; 353 struct amdgpu_pll mpll; 354 /* 10 Khz units */ 355 uint32_t default_mclk; 356 uint32_t default_sclk; 357 uint32_t default_dispclk; 358 uint32_t current_dispclk; 359 uint32_t dp_extclk; 360 uint32_t max_pixel_clock; 361 }; 362 363 /* 364 * GEM. 365 */ 366 367 #define AMDGPU_GEM_DOMAIN_MAX 0x3 368 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 369 370 void amdgpu_gem_object_free(struct drm_gem_object *obj); 371 int amdgpu_gem_object_open(struct drm_gem_object *obj, 372 struct drm_file *file_priv); 373 void amdgpu_gem_object_close(struct drm_gem_object *obj, 374 struct drm_file *file_priv); 375 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 376 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 377 struct drm_gem_object * 378 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 379 struct dma_buf_attachment *attach, 380 struct sg_table *sg); 381 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 382 struct drm_gem_object *gobj, 383 int flags); 384 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, 385 struct dma_buf *dma_buf); 386 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 387 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 388 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 389 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 390 391 /* sub-allocation manager, it has to be protected by another lock. 392 * By conception this is an helper for other part of the driver 393 * like the indirect buffer or semaphore, which both have their 394 * locking. 395 * 396 * Principe is simple, we keep a list of sub allocation in offset 397 * order (first entry has offset == 0, last entry has the highest 398 * offset). 399 * 400 * When allocating new object we first check if there is room at 401 * the end total_size - (last_object_offset + last_object_size) >= 402 * alloc_size. If so we allocate new object there. 403 * 404 * When there is not enough room at the end, we start waiting for 405 * each sub object until we reach object_offset+object_size >= 406 * alloc_size, this object then become the sub object we return. 407 * 408 * Alignment can't be bigger than page size. 409 * 410 * Hole are not considered for allocation to keep things simple. 411 * Assumption is that there won't be hole (all object on same 412 * alignment). 413 */ 414 415 #define AMDGPU_SA_NUM_FENCE_LISTS 32 416 417 struct amdgpu_sa_manager { 418 wait_queue_head_t wq; 419 struct amdgpu_bo *bo; 420 struct list_head *hole; 421 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 422 struct list_head olist; 423 unsigned size; 424 uint64_t gpu_addr; 425 void *cpu_ptr; 426 uint32_t domain; 427 uint32_t align; 428 }; 429 430 /* sub-allocation buffer */ 431 struct amdgpu_sa_bo { 432 struct list_head olist; 433 struct list_head flist; 434 struct amdgpu_sa_manager *manager; 435 unsigned soffset; 436 unsigned eoffset; 437 struct dma_fence *fence; 438 }; 439 440 /* 441 * GEM objects. 442 */ 443 void amdgpu_gem_force_release(struct amdgpu_device *adev); 444 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 445 int alignment, u32 initial_domain, 446 u64 flags, enum ttm_bo_type type, 447 struct reservation_object *resv, 448 struct drm_gem_object **obj); 449 450 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 451 struct drm_device *dev, 452 struct drm_mode_create_dumb *args); 453 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 454 struct drm_device *dev, 455 uint32_t handle, uint64_t *offset_p); 456 int amdgpu_fence_slab_init(void); 457 void amdgpu_fence_slab_fini(void); 458 459 /* 460 * GPU doorbell structures, functions & helpers 461 */ 462 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 463 { 464 AMDGPU_DOORBELL_KIQ = 0x000, 465 AMDGPU_DOORBELL_HIQ = 0x001, 466 AMDGPU_DOORBELL_DIQ = 0x002, 467 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 468 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 469 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 470 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 471 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 472 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 473 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 474 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 475 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 476 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 477 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 478 AMDGPU_DOORBELL_IH = 0x1E8, 479 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 480 AMDGPU_DOORBELL_INVALID = 0xFFFF 481 } AMDGPU_DOORBELL_ASSIGNMENT; 482 483 struct amdgpu_doorbell { 484 /* doorbell mmio */ 485 resource_size_t base; 486 resource_size_t size; 487 u32 __iomem *ptr; 488 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 489 }; 490 491 /* 492 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 493 */ 494 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 495 { 496 /* 497 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 498 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 499 * Compute related doorbells are allocated from 0x00 to 0x8a 500 */ 501 502 503 /* kernel scheduling */ 504 AMDGPU_DOORBELL64_KIQ = 0x00, 505 506 /* HSA interface queue and debug queue */ 507 AMDGPU_DOORBELL64_HIQ = 0x01, 508 AMDGPU_DOORBELL64_DIQ = 0x02, 509 510 /* Compute engines */ 511 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 512 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 513 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 514 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 515 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 516 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 517 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 518 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 519 520 /* User queue doorbell range (128 doorbells) */ 521 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 522 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 523 524 /* Graphics engine */ 525 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 526 527 /* 528 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 529 * Graphics voltage island aperture 1 530 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 531 */ 532 533 /* sDMA engines */ 534 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 535 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 536 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 537 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 538 539 /* Interrupt handler */ 540 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 541 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 542 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 543 544 /* VCN engine use 32 bits doorbell */ 545 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 546 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 547 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 548 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 549 550 /* overlap the doorbell assignment with VCN as they are mutually exclusive 551 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 552 */ 553 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 554 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 555 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 556 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 557 558 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 559 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 560 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 561 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 562 563 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 564 AMDGPU_DOORBELL64_INVALID = 0xFFFF 565 } AMDGPU_DOORBELL64_ASSIGNMENT; 566 567 /* 568 * IRQS. 569 */ 570 571 struct amdgpu_flip_work { 572 struct delayed_work flip_work; 573 struct work_struct unpin_work; 574 struct amdgpu_device *adev; 575 int crtc_id; 576 u32 target_vblank; 577 uint64_t base; 578 struct drm_pending_vblank_event *event; 579 struct amdgpu_bo *old_abo; 580 struct dma_fence *excl; 581 unsigned shared_count; 582 struct dma_fence **shared; 583 struct dma_fence_cb cb; 584 bool async; 585 }; 586 587 588 /* 589 * CP & rings. 590 */ 591 592 struct amdgpu_ib { 593 struct amdgpu_sa_bo *sa_bo; 594 uint32_t length_dw; 595 uint64_t gpu_addr; 596 uint32_t *ptr; 597 uint32_t flags; 598 }; 599 600 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 601 602 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 603 struct amdgpu_job **job, struct amdgpu_vm *vm); 604 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 605 struct amdgpu_job **job); 606 607 void amdgpu_job_free_resources(struct amdgpu_job *job); 608 void amdgpu_job_free(struct amdgpu_job *job); 609 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 610 struct drm_sched_entity *entity, void *owner, 611 struct dma_fence **f); 612 613 /* 614 * Queue manager 615 */ 616 struct amdgpu_queue_mapper { 617 int hw_ip; 618 struct mutex lock; 619 /* protected by lock */ 620 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 621 }; 622 623 struct amdgpu_queue_mgr { 624 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 625 }; 626 627 int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 628 struct amdgpu_queue_mgr *mgr); 629 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 630 struct amdgpu_queue_mgr *mgr); 631 int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 632 struct amdgpu_queue_mgr *mgr, 633 u32 hw_ip, u32 instance, u32 ring, 634 struct amdgpu_ring **out_ring); 635 636 /* 637 * context related structures 638 */ 639 640 struct amdgpu_ctx_ring { 641 uint64_t sequence; 642 struct dma_fence **fences; 643 struct drm_sched_entity entity; 644 }; 645 646 struct amdgpu_ctx { 647 struct kref refcount; 648 struct amdgpu_device *adev; 649 struct amdgpu_queue_mgr queue_mgr; 650 unsigned reset_counter; 651 unsigned reset_counter_query; 652 uint32_t vram_lost_counter; 653 spinlock_t ring_lock; 654 struct dma_fence **fences; 655 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 656 bool preamble_presented; 657 enum drm_sched_priority init_priority; 658 enum drm_sched_priority override_priority; 659 struct mutex lock; 660 atomic_t guilty; 661 }; 662 663 struct amdgpu_ctx_mgr { 664 struct amdgpu_device *adev; 665 struct mutex lock; 666 /* protected by lock */ 667 struct idr ctx_handles; 668 }; 669 670 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 671 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 672 673 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 674 struct dma_fence *fence, uint64_t *seq); 675 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 676 struct amdgpu_ring *ring, uint64_t seq); 677 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 678 enum drm_sched_priority priority); 679 680 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 681 struct drm_file *filp); 682 683 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); 684 685 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 686 void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr); 687 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); 688 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 689 690 691 /* 692 * file private structure 693 */ 694 695 struct amdgpu_fpriv { 696 struct amdgpu_vm vm; 697 struct amdgpu_bo_va *prt_va; 698 struct amdgpu_bo_va *csa_va; 699 struct mutex bo_list_lock; 700 struct idr bo_list_handles; 701 struct amdgpu_ctx_mgr ctx_mgr; 702 }; 703 704 /* 705 * residency list 706 */ 707 struct amdgpu_bo_list_entry { 708 struct amdgpu_bo *robj; 709 struct ttm_validate_buffer tv; 710 struct amdgpu_bo_va *bo_va; 711 uint32_t priority; 712 struct page **user_pages; 713 int user_invalidated; 714 }; 715 716 struct amdgpu_bo_list { 717 struct mutex lock; 718 struct rcu_head rhead; 719 struct kref refcount; 720 struct amdgpu_bo *gds_obj; 721 struct amdgpu_bo *gws_obj; 722 struct amdgpu_bo *oa_obj; 723 unsigned first_userptr; 724 unsigned num_entries; 725 struct amdgpu_bo_list_entry *array; 726 }; 727 728 struct amdgpu_bo_list * 729 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 730 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 731 struct list_head *validated); 732 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 733 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 734 735 /* 736 * GFX stuff 737 */ 738 #include "clearstate_defs.h" 739 740 struct amdgpu_rlc_funcs { 741 void (*enter_safe_mode)(struct amdgpu_device *adev); 742 void (*exit_safe_mode)(struct amdgpu_device *adev); 743 }; 744 745 struct amdgpu_rlc { 746 /* for power gating */ 747 struct amdgpu_bo *save_restore_obj; 748 uint64_t save_restore_gpu_addr; 749 volatile uint32_t *sr_ptr; 750 const u32 *reg_list; 751 u32 reg_list_size; 752 /* for clear state */ 753 struct amdgpu_bo *clear_state_obj; 754 uint64_t clear_state_gpu_addr; 755 volatile uint32_t *cs_ptr; 756 const struct cs_section_def *cs_data; 757 u32 clear_state_size; 758 /* for cp tables */ 759 struct amdgpu_bo *cp_table_obj; 760 uint64_t cp_table_gpu_addr; 761 volatile uint32_t *cp_table_ptr; 762 u32 cp_table_size; 763 764 /* safe mode for updating CG/PG state */ 765 bool in_safe_mode; 766 const struct amdgpu_rlc_funcs *funcs; 767 768 /* for firmware data */ 769 u32 save_and_restore_offset; 770 u32 clear_state_descriptor_offset; 771 u32 avail_scratch_ram_locations; 772 u32 reg_restore_list_size; 773 u32 reg_list_format_start; 774 u32 reg_list_format_separate_start; 775 u32 starting_offsets_start; 776 u32 reg_list_format_size_bytes; 777 u32 reg_list_size_bytes; 778 u32 reg_list_format_direct_reg_list_length; 779 u32 save_restore_list_cntl_size_bytes; 780 u32 save_restore_list_gpm_size_bytes; 781 u32 save_restore_list_srm_size_bytes; 782 783 u32 *register_list_format; 784 u32 *register_restore; 785 u8 *save_restore_list_cntl; 786 u8 *save_restore_list_gpm; 787 u8 *save_restore_list_srm; 788 789 bool is_rlc_v2_1; 790 }; 791 792 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 793 794 struct amdgpu_mec { 795 struct amdgpu_bo *hpd_eop_obj; 796 u64 hpd_eop_gpu_addr; 797 struct amdgpu_bo *mec_fw_obj; 798 u64 mec_fw_gpu_addr; 799 u32 num_mec; 800 u32 num_pipe_per_mec; 801 u32 num_queue_per_pipe; 802 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 803 804 /* These are the resources for which amdgpu takes ownership */ 805 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 806 }; 807 808 struct amdgpu_kiq { 809 u64 eop_gpu_addr; 810 struct amdgpu_bo *eop_obj; 811 spinlock_t ring_lock; 812 struct amdgpu_ring ring; 813 struct amdgpu_irq_src irq; 814 }; 815 816 /* 817 * GPU scratch registers structures, functions & helpers 818 */ 819 struct amdgpu_scratch { 820 unsigned num_reg; 821 uint32_t reg_base; 822 uint32_t free_mask; 823 }; 824 825 /* 826 * GFX configurations 827 */ 828 #define AMDGPU_GFX_MAX_SE 4 829 #define AMDGPU_GFX_MAX_SH_PER_SE 2 830 831 struct amdgpu_rb_config { 832 uint32_t rb_backend_disable; 833 uint32_t user_rb_backend_disable; 834 uint32_t raster_config; 835 uint32_t raster_config_1; 836 }; 837 838 struct gb_addr_config { 839 uint16_t pipe_interleave_size; 840 uint8_t num_pipes; 841 uint8_t max_compress_frags; 842 uint8_t num_banks; 843 uint8_t num_se; 844 uint8_t num_rb_per_se; 845 }; 846 847 struct amdgpu_gfx_config { 848 unsigned max_shader_engines; 849 unsigned max_tile_pipes; 850 unsigned max_cu_per_sh; 851 unsigned max_sh_per_se; 852 unsigned max_backends_per_se; 853 unsigned max_texture_channel_caches; 854 unsigned max_gprs; 855 unsigned max_gs_threads; 856 unsigned max_hw_contexts; 857 unsigned sc_prim_fifo_size_frontend; 858 unsigned sc_prim_fifo_size_backend; 859 unsigned sc_hiz_tile_fifo_size; 860 unsigned sc_earlyz_tile_fifo_size; 861 862 unsigned num_tile_pipes; 863 unsigned backend_enable_mask; 864 unsigned mem_max_burst_length_bytes; 865 unsigned mem_row_size_in_kb; 866 unsigned shader_engine_tile_size; 867 unsigned num_gpus; 868 unsigned multi_gpu_tile_size; 869 unsigned mc_arb_ramcfg; 870 unsigned gb_addr_config; 871 unsigned num_rbs; 872 unsigned gs_vgt_table_depth; 873 unsigned gs_prim_buffer_depth; 874 875 uint32_t tile_mode_array[32]; 876 uint32_t macrotile_mode_array[16]; 877 878 struct gb_addr_config gb_addr_config_fields; 879 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 880 881 /* gfx configure feature */ 882 uint32_t double_offchip_lds_buf; 883 /* cached value of DB_DEBUG2 */ 884 uint32_t db_debug2; 885 }; 886 887 struct amdgpu_cu_info { 888 uint32_t simd_per_cu; 889 uint32_t max_waves_per_simd; 890 uint32_t wave_front_size; 891 uint32_t max_scratch_slots_per_cu; 892 uint32_t lds_size; 893 894 /* total active CU number */ 895 uint32_t number; 896 uint32_t ao_cu_mask; 897 uint32_t ao_cu_bitmap[4][4]; 898 uint32_t bitmap[4][4]; 899 }; 900 901 struct amdgpu_gfx_funcs { 902 /* get the gpu clock counter */ 903 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 904 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 905 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 906 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 907 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 908 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue); 909 }; 910 911 struct amdgpu_ngg_buf { 912 struct amdgpu_bo *bo; 913 uint64_t gpu_addr; 914 uint32_t size; 915 uint32_t bo_size; 916 }; 917 918 enum { 919 NGG_PRIM = 0, 920 NGG_POS, 921 NGG_CNTL, 922 NGG_PARAM, 923 NGG_BUF_MAX 924 }; 925 926 struct amdgpu_ngg { 927 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 928 uint32_t gds_reserve_addr; 929 uint32_t gds_reserve_size; 930 bool init; 931 }; 932 933 struct amdgpu_gfx { 934 struct mutex gpu_clock_mutex; 935 struct amdgpu_gfx_config config; 936 struct amdgpu_rlc rlc; 937 struct amdgpu_mec mec; 938 struct amdgpu_kiq kiq; 939 struct amdgpu_scratch scratch; 940 const struct firmware *me_fw; /* ME firmware */ 941 uint32_t me_fw_version; 942 const struct firmware *pfp_fw; /* PFP firmware */ 943 uint32_t pfp_fw_version; 944 const struct firmware *ce_fw; /* CE firmware */ 945 uint32_t ce_fw_version; 946 const struct firmware *rlc_fw; /* RLC firmware */ 947 uint32_t rlc_fw_version; 948 const struct firmware *mec_fw; /* MEC firmware */ 949 uint32_t mec_fw_version; 950 const struct firmware *mec2_fw; /* MEC2 firmware */ 951 uint32_t mec2_fw_version; 952 uint32_t me_feature_version; 953 uint32_t ce_feature_version; 954 uint32_t pfp_feature_version; 955 uint32_t rlc_feature_version; 956 uint32_t rlc_srlc_fw_version; 957 uint32_t rlc_srlc_feature_version; 958 uint32_t rlc_srlg_fw_version; 959 uint32_t rlc_srlg_feature_version; 960 uint32_t rlc_srls_fw_version; 961 uint32_t rlc_srls_feature_version; 962 uint32_t mec_feature_version; 963 uint32_t mec2_feature_version; 964 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 965 unsigned num_gfx_rings; 966 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 967 unsigned num_compute_rings; 968 struct amdgpu_irq_src eop_irq; 969 struct amdgpu_irq_src priv_reg_irq; 970 struct amdgpu_irq_src priv_inst_irq; 971 struct amdgpu_irq_src cp_ecc_error_irq; 972 struct amdgpu_irq_src sq_irq; 973 /* gfx status */ 974 uint32_t gfx_current_status; 975 /* ce ram size*/ 976 unsigned ce_ram_size; 977 struct amdgpu_cu_info cu_info; 978 const struct amdgpu_gfx_funcs *funcs; 979 980 /* reset mask */ 981 uint32_t grbm_soft_reset; 982 uint32_t srbm_soft_reset; 983 /* s3/s4 mask */ 984 bool in_suspend; 985 /* NGG */ 986 struct amdgpu_ngg ngg; 987 988 /* pipe reservation */ 989 struct mutex pipe_reserve_mutex; 990 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 991 }; 992 993 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 994 unsigned size, struct amdgpu_ib *ib); 995 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 996 struct dma_fence *f); 997 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 998 struct amdgpu_ib *ibs, struct amdgpu_job *job, 999 struct dma_fence **f); 1000 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1001 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1002 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1003 1004 /* 1005 * CS. 1006 */ 1007 struct amdgpu_cs_chunk { 1008 uint32_t chunk_id; 1009 uint32_t length_dw; 1010 void *kdata; 1011 }; 1012 1013 struct amdgpu_cs_parser { 1014 struct amdgpu_device *adev; 1015 struct drm_file *filp; 1016 struct amdgpu_ctx *ctx; 1017 1018 /* chunks */ 1019 unsigned nchunks; 1020 struct amdgpu_cs_chunk *chunks; 1021 1022 /* scheduler job object */ 1023 struct amdgpu_job *job; 1024 1025 /* buffer objects */ 1026 struct ww_acquire_ctx ticket; 1027 struct amdgpu_bo_list *bo_list; 1028 struct amdgpu_mn *mn; 1029 struct amdgpu_bo_list_entry vm_pd; 1030 struct list_head validated; 1031 struct dma_fence *fence; 1032 uint64_t bytes_moved_threshold; 1033 uint64_t bytes_moved_vis_threshold; 1034 uint64_t bytes_moved; 1035 uint64_t bytes_moved_vis; 1036 struct amdgpu_bo_list_entry *evictable; 1037 1038 /* user fence */ 1039 struct amdgpu_bo_list_entry uf_entry; 1040 1041 unsigned num_post_dep_syncobjs; 1042 struct drm_syncobj **post_dep_syncobjs; 1043 }; 1044 1045 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1046 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1047 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1048 1049 struct amdgpu_job { 1050 struct drm_sched_job base; 1051 struct amdgpu_device *adev; 1052 struct amdgpu_vm *vm; 1053 struct amdgpu_ring *ring; 1054 struct amdgpu_sync sync; 1055 struct amdgpu_sync sched_sync; 1056 struct amdgpu_ib *ibs; 1057 struct dma_fence *fence; /* the hw fence */ 1058 uint32_t preamble_status; 1059 uint32_t num_ibs; 1060 void *owner; 1061 uint64_t fence_ctx; /* the fence_context this job uses */ 1062 bool vm_needs_flush; 1063 uint64_t vm_pd_addr; 1064 unsigned vmid; 1065 unsigned pasid; 1066 uint32_t gds_base, gds_size; 1067 uint32_t gws_base, gws_size; 1068 uint32_t oa_base, oa_size; 1069 uint32_t vram_lost_counter; 1070 1071 /* user fence handling */ 1072 uint64_t uf_addr; 1073 uint64_t uf_sequence; 1074 1075 }; 1076 #define to_amdgpu_job(sched_job) \ 1077 container_of((sched_job), struct amdgpu_job, base) 1078 1079 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1080 uint32_t ib_idx, int idx) 1081 { 1082 return p->job->ibs[ib_idx].ptr[idx]; 1083 } 1084 1085 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1086 uint32_t ib_idx, int idx, 1087 uint32_t value) 1088 { 1089 p->job->ibs[ib_idx].ptr[idx] = value; 1090 } 1091 1092 /* 1093 * Writeback 1094 */ 1095 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 1096 1097 struct amdgpu_wb { 1098 struct amdgpu_bo *wb_obj; 1099 volatile uint32_t *wb; 1100 uint64_t gpu_addr; 1101 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1102 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1103 }; 1104 1105 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 1106 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 1107 1108 /* 1109 * SDMA 1110 */ 1111 struct amdgpu_sdma_instance { 1112 /* SDMA firmware */ 1113 const struct firmware *fw; 1114 uint32_t fw_version; 1115 uint32_t feature_version; 1116 1117 struct amdgpu_ring ring; 1118 bool burst_nop; 1119 }; 1120 1121 struct amdgpu_sdma { 1122 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1123 #ifdef CONFIG_DRM_AMDGPU_SI 1124 //SI DMA has a difference trap irq number for the second engine 1125 struct amdgpu_irq_src trap_irq_1; 1126 #endif 1127 struct amdgpu_irq_src trap_irq; 1128 struct amdgpu_irq_src illegal_inst_irq; 1129 int num_instances; 1130 uint32_t srbm_soft_reset; 1131 }; 1132 1133 /* 1134 * Firmware 1135 */ 1136 enum amdgpu_firmware_load_type { 1137 AMDGPU_FW_LOAD_DIRECT = 0, 1138 AMDGPU_FW_LOAD_SMU, 1139 AMDGPU_FW_LOAD_PSP, 1140 }; 1141 1142 struct amdgpu_firmware { 1143 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1144 enum amdgpu_firmware_load_type load_type; 1145 struct amdgpu_bo *fw_buf; 1146 unsigned int fw_size; 1147 unsigned int max_ucodes; 1148 /* firmwares are loaded by psp instead of smu from vega10 */ 1149 const struct amdgpu_psp_funcs *funcs; 1150 struct amdgpu_bo *rbuf; 1151 struct mutex mutex; 1152 1153 /* gpu info firmware data pointer */ 1154 const struct firmware *gpu_info_fw; 1155 1156 void *fw_buf_ptr; 1157 uint64_t fw_buf_mc; 1158 }; 1159 1160 /* 1161 * Benchmarking 1162 */ 1163 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1164 1165 1166 /* 1167 * Testing 1168 */ 1169 void amdgpu_test_moves(struct amdgpu_device *adev); 1170 1171 1172 /* 1173 * amdgpu smumgr functions 1174 */ 1175 struct amdgpu_smumgr_funcs { 1176 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1177 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1178 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1179 }; 1180 1181 /* 1182 * amdgpu smumgr 1183 */ 1184 struct amdgpu_smumgr { 1185 struct amdgpu_bo *toc_buf; 1186 struct amdgpu_bo *smu_buf; 1187 /* asic priv smu data */ 1188 void *priv; 1189 spinlock_t smu_lock; 1190 /* smumgr functions */ 1191 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1192 /* ucode loading complete flag */ 1193 uint32_t fw_flags; 1194 }; 1195 1196 /* 1197 * ASIC specific register table accessible by UMD 1198 */ 1199 struct amdgpu_allowed_register_entry { 1200 uint32_t reg_offset; 1201 bool grbm_indexed; 1202 }; 1203 1204 /* 1205 * ASIC specific functions. 1206 */ 1207 struct amdgpu_asic_funcs { 1208 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1209 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1210 u8 *bios, u32 length_bytes); 1211 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1212 u32 sh_num, u32 reg_offset, u32 *value); 1213 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1214 int (*reset)(struct amdgpu_device *adev); 1215 /* get the reference clock */ 1216 u32 (*get_xclk)(struct amdgpu_device *adev); 1217 /* MM block clocks */ 1218 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1219 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1220 /* static power management */ 1221 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1222 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1223 /* get config memsize register */ 1224 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1225 /* flush hdp write queue */ 1226 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 1227 /* invalidate hdp read cache */ 1228 void (*invalidate_hdp)(struct amdgpu_device *adev, 1229 struct amdgpu_ring *ring); 1230 /* check if the asic needs a full reset of if soft reset will work */ 1231 bool (*need_full_reset)(struct amdgpu_device *adev); 1232 }; 1233 1234 /* 1235 * IOCTL. 1236 */ 1237 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1238 struct drm_file *filp); 1239 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1240 struct drm_file *filp); 1241 1242 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1243 struct drm_file *filp); 1244 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1245 struct drm_file *filp); 1246 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1247 struct drm_file *filp); 1248 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1249 struct drm_file *filp); 1250 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1251 struct drm_file *filp); 1252 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1253 struct drm_file *filp); 1254 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1255 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 1256 struct drm_file *filp); 1257 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1258 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1259 struct drm_file *filp); 1260 1261 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1262 struct drm_file *filp); 1263 1264 /* VRAM scratch page for HDP bug, default vram page */ 1265 struct amdgpu_vram_scratch { 1266 struct amdgpu_bo *robj; 1267 volatile uint32_t *ptr; 1268 u64 gpu_addr; 1269 }; 1270 1271 /* 1272 * ACPI 1273 */ 1274 struct amdgpu_atif_notification_cfg { 1275 bool enabled; 1276 int command_code; 1277 }; 1278 1279 struct amdgpu_atif_notifications { 1280 bool display_switch; 1281 bool expansion_mode_change; 1282 bool thermal_state; 1283 bool forced_power_state; 1284 bool system_power_state; 1285 bool display_conf_change; 1286 bool px_gfx_switch; 1287 bool brightness_change; 1288 bool dgpu_display_event; 1289 }; 1290 1291 struct amdgpu_atif_functions { 1292 bool system_params; 1293 bool sbios_requests; 1294 bool select_active_disp; 1295 bool lid_state; 1296 bool get_tv_standard; 1297 bool set_tv_standard; 1298 bool get_panel_expansion_mode; 1299 bool set_panel_expansion_mode; 1300 bool temperature_change; 1301 bool graphics_device_types; 1302 }; 1303 1304 struct amdgpu_atif { 1305 struct amdgpu_atif_notifications notifications; 1306 struct amdgpu_atif_functions functions; 1307 struct amdgpu_atif_notification_cfg notification_cfg; 1308 struct amdgpu_encoder *encoder_for_bl; 1309 }; 1310 1311 struct amdgpu_atcs_functions { 1312 bool get_ext_state; 1313 bool pcie_perf_req; 1314 bool pcie_dev_rdy; 1315 bool pcie_bus_width; 1316 }; 1317 1318 struct amdgpu_atcs { 1319 struct amdgpu_atcs_functions functions; 1320 }; 1321 1322 /* 1323 * Firmware VRAM reservation 1324 */ 1325 struct amdgpu_fw_vram_usage { 1326 u64 start_offset; 1327 u64 size; 1328 struct amdgpu_bo *reserved_bo; 1329 void *va; 1330 }; 1331 1332 /* 1333 * CGS 1334 */ 1335 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1336 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1337 1338 /* 1339 * Core structure, functions and helpers. 1340 */ 1341 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1342 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1343 1344 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1345 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1346 1347 1348 /* 1349 * amdgpu nbio functions 1350 * 1351 */ 1352 struct nbio_hdp_flush_reg { 1353 u32 ref_and_mask_cp0; 1354 u32 ref_and_mask_cp1; 1355 u32 ref_and_mask_cp2; 1356 u32 ref_and_mask_cp3; 1357 u32 ref_and_mask_cp4; 1358 u32 ref_and_mask_cp5; 1359 u32 ref_and_mask_cp6; 1360 u32 ref_and_mask_cp7; 1361 u32 ref_and_mask_cp8; 1362 u32 ref_and_mask_cp9; 1363 u32 ref_and_mask_sdma0; 1364 u32 ref_and_mask_sdma1; 1365 }; 1366 1367 struct amdgpu_nbio_funcs { 1368 const struct nbio_hdp_flush_reg *hdp_flush_reg; 1369 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 1370 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 1371 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 1372 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 1373 u32 (*get_rev_id)(struct amdgpu_device *adev); 1374 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 1375 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 1376 u32 (*get_memsize)(struct amdgpu_device *adev); 1377 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 1378 bool use_doorbell, int doorbell_index); 1379 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 1380 bool enable); 1381 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 1382 bool enable); 1383 void (*ih_doorbell_range)(struct amdgpu_device *adev, 1384 bool use_doorbell, int doorbell_index); 1385 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 1386 bool enable); 1387 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 1388 bool enable); 1389 void (*get_clockgating_state)(struct amdgpu_device *adev, 1390 u32 *flags); 1391 void (*ih_control)(struct amdgpu_device *adev); 1392 void (*init_registers)(struct amdgpu_device *adev); 1393 void (*detect_hw_virt)(struct amdgpu_device *adev); 1394 }; 1395 1396 struct amdgpu_df_funcs { 1397 void (*init)(struct amdgpu_device *adev); 1398 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 1399 bool enable); 1400 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 1401 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 1402 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 1403 bool enable); 1404 void (*get_clockgating_state)(struct amdgpu_device *adev, 1405 u32 *flags); 1406 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 1407 bool enable); 1408 }; 1409 /* Define the HW IP blocks will be used in driver , add more if necessary */ 1410 enum amd_hw_ip_block_type { 1411 GC_HWIP = 1, 1412 HDP_HWIP, 1413 SDMA0_HWIP, 1414 SDMA1_HWIP, 1415 MMHUB_HWIP, 1416 ATHUB_HWIP, 1417 NBIO_HWIP, 1418 MP0_HWIP, 1419 MP1_HWIP, 1420 UVD_HWIP, 1421 VCN_HWIP = UVD_HWIP, 1422 VCE_HWIP, 1423 DF_HWIP, 1424 DCE_HWIP, 1425 OSSSYS_HWIP, 1426 SMUIO_HWIP, 1427 PWR_HWIP, 1428 NBIF_HWIP, 1429 THM_HWIP, 1430 MAX_HWIP 1431 }; 1432 1433 #define HWIP_MAX_INSTANCE 6 1434 1435 struct amd_powerplay { 1436 void *pp_handle; 1437 const struct amd_pm_funcs *pp_funcs; 1438 uint32_t pp_feature; 1439 }; 1440 1441 #define AMDGPU_RESET_MAGIC_NUM 64 1442 struct amdgpu_device { 1443 struct device *dev; 1444 struct drm_device *ddev; 1445 struct pci_dev *pdev; 1446 1447 #ifdef CONFIG_DRM_AMD_ACP 1448 struct amdgpu_acp acp; 1449 #endif 1450 1451 /* ASIC */ 1452 enum amd_asic_type asic_type; 1453 uint32_t family; 1454 uint32_t rev_id; 1455 uint32_t external_rev_id; 1456 unsigned long flags; 1457 int usec_timeout; 1458 const struct amdgpu_asic_funcs *asic_funcs; 1459 bool shutdown; 1460 bool need_dma32; 1461 bool need_swiotlb; 1462 bool accel_working; 1463 struct work_struct reset_work; 1464 struct notifier_block acpi_nb; 1465 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1466 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1467 unsigned debugfs_count; 1468 #if defined(CONFIG_DEBUG_FS) 1469 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1470 #endif 1471 struct amdgpu_atif atif; 1472 struct amdgpu_atcs atcs; 1473 struct mutex srbm_mutex; 1474 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1475 struct mutex grbm_idx_mutex; 1476 struct dev_pm_domain vga_pm_domain; 1477 bool have_disp_power_ref; 1478 1479 /* BIOS */ 1480 bool is_atom_fw; 1481 uint8_t *bios; 1482 uint32_t bios_size; 1483 struct amdgpu_bo *stolen_vga_memory; 1484 uint32_t bios_scratch_reg_offset; 1485 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1486 1487 /* Register/doorbell mmio */ 1488 resource_size_t rmmio_base; 1489 resource_size_t rmmio_size; 1490 void __iomem *rmmio; 1491 /* protects concurrent MM_INDEX/DATA based register access */ 1492 spinlock_t mmio_idx_lock; 1493 /* protects concurrent SMC based register access */ 1494 spinlock_t smc_idx_lock; 1495 amdgpu_rreg_t smc_rreg; 1496 amdgpu_wreg_t smc_wreg; 1497 /* protects concurrent PCIE register access */ 1498 spinlock_t pcie_idx_lock; 1499 amdgpu_rreg_t pcie_rreg; 1500 amdgpu_wreg_t pcie_wreg; 1501 amdgpu_rreg_t pciep_rreg; 1502 amdgpu_wreg_t pciep_wreg; 1503 /* protects concurrent UVD register access */ 1504 spinlock_t uvd_ctx_idx_lock; 1505 amdgpu_rreg_t uvd_ctx_rreg; 1506 amdgpu_wreg_t uvd_ctx_wreg; 1507 /* protects concurrent DIDT register access */ 1508 spinlock_t didt_idx_lock; 1509 amdgpu_rreg_t didt_rreg; 1510 amdgpu_wreg_t didt_wreg; 1511 /* protects concurrent gc_cac register access */ 1512 spinlock_t gc_cac_idx_lock; 1513 amdgpu_rreg_t gc_cac_rreg; 1514 amdgpu_wreg_t gc_cac_wreg; 1515 /* protects concurrent se_cac register access */ 1516 spinlock_t se_cac_idx_lock; 1517 amdgpu_rreg_t se_cac_rreg; 1518 amdgpu_wreg_t se_cac_wreg; 1519 /* protects concurrent ENDPOINT (audio) register access */ 1520 spinlock_t audio_endpt_idx_lock; 1521 amdgpu_block_rreg_t audio_endpt_rreg; 1522 amdgpu_block_wreg_t audio_endpt_wreg; 1523 void __iomem *rio_mem; 1524 resource_size_t rio_mem_size; 1525 struct amdgpu_doorbell doorbell; 1526 1527 /* clock/pll info */ 1528 struct amdgpu_clock clock; 1529 1530 /* MC */ 1531 struct amdgpu_gmc gmc; 1532 struct amdgpu_gart gart; 1533 dma_addr_t dummy_page_addr; 1534 struct amdgpu_vm_manager vm_manager; 1535 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1536 1537 /* memory management */ 1538 struct amdgpu_mman mman; 1539 struct amdgpu_vram_scratch vram_scratch; 1540 struct amdgpu_wb wb; 1541 atomic64_t num_bytes_moved; 1542 atomic64_t num_evictions; 1543 atomic64_t num_vram_cpu_page_faults; 1544 atomic_t gpu_reset_counter; 1545 atomic_t vram_lost_counter; 1546 1547 /* data for buffer migration throttling */ 1548 struct { 1549 spinlock_t lock; 1550 s64 last_update_us; 1551 s64 accum_us; /* accumulated microseconds */ 1552 s64 accum_us_vis; /* for visible VRAM */ 1553 u32 log2_max_MBps; 1554 } mm_stats; 1555 1556 /* display */ 1557 bool enable_virtual_display; 1558 struct amdgpu_mode_info mode_info; 1559 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1560 struct work_struct hotplug_work; 1561 struct amdgpu_irq_src crtc_irq; 1562 struct amdgpu_irq_src pageflip_irq; 1563 struct amdgpu_irq_src hpd_irq; 1564 1565 /* rings */ 1566 u64 fence_context; 1567 unsigned num_rings; 1568 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1569 bool ib_pool_ready; 1570 struct amdgpu_sa_manager ring_tmp_bo; 1571 1572 /* interrupts */ 1573 struct amdgpu_irq irq; 1574 1575 /* powerplay */ 1576 struct amd_powerplay powerplay; 1577 bool pp_force_state_enabled; 1578 1579 /* dpm */ 1580 struct amdgpu_pm pm; 1581 u32 cg_flags; 1582 u32 pg_flags; 1583 1584 /* amdgpu smumgr */ 1585 struct amdgpu_smumgr smu; 1586 1587 /* gfx */ 1588 struct amdgpu_gfx gfx; 1589 1590 /* sdma */ 1591 struct amdgpu_sdma sdma; 1592 1593 /* uvd */ 1594 struct amdgpu_uvd uvd; 1595 1596 /* vce */ 1597 struct amdgpu_vce vce; 1598 1599 /* vcn */ 1600 struct amdgpu_vcn vcn; 1601 1602 /* firmwares */ 1603 struct amdgpu_firmware firmware; 1604 1605 /* PSP */ 1606 struct psp_context psp; 1607 1608 /* GDS */ 1609 struct amdgpu_gds gds; 1610 1611 /* display related functionality */ 1612 struct amdgpu_display_manager dm; 1613 1614 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1615 int num_ip_blocks; 1616 struct mutex mn_lock; 1617 DECLARE_HASHTABLE(mn_hash, 7); 1618 1619 /* tracking pinned memory */ 1620 u64 vram_pin_size; 1621 u64 invisible_pin_size; 1622 u64 gart_pin_size; 1623 1624 /* amdkfd interface */ 1625 struct kfd_dev *kfd; 1626 1627 /* soc15 register offset based on ip, instance and segment */ 1628 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1629 1630 const struct amdgpu_nbio_funcs *nbio_funcs; 1631 const struct amdgpu_df_funcs *df_funcs; 1632 1633 /* delayed work_func for deferring clockgating during resume */ 1634 struct delayed_work late_init_work; 1635 1636 struct amdgpu_virt virt; 1637 /* firmware VRAM reservation */ 1638 struct amdgpu_fw_vram_usage fw_vram_usage; 1639 1640 /* link all shadow bo */ 1641 struct list_head shadow_list; 1642 struct mutex shadow_list_lock; 1643 /* keep an lru list of rings by HW IP */ 1644 struct list_head ring_lru_list; 1645 spinlock_t ring_lru_list_lock; 1646 1647 /* record hw reset is performed */ 1648 bool has_hw_reset; 1649 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1650 1651 /* record last mm index being written through WREG32*/ 1652 unsigned long last_mm_index; 1653 bool in_gpu_reset; 1654 struct mutex lock_reset; 1655 }; 1656 1657 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1658 { 1659 return container_of(bdev, struct amdgpu_device, mman.bdev); 1660 } 1661 1662 int amdgpu_device_init(struct amdgpu_device *adev, 1663 struct drm_device *ddev, 1664 struct pci_dev *pdev, 1665 uint32_t flags); 1666 void amdgpu_device_fini(struct amdgpu_device *adev); 1667 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1668 1669 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1670 uint32_t acc_flags); 1671 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1672 uint32_t acc_flags); 1673 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1674 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1675 1676 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1677 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1678 1679 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1680 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1681 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1682 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1683 1684 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1685 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1686 1687 int emu_soc_asic_init(struct amdgpu_device *adev); 1688 1689 /* 1690 * Registers read & write functions. 1691 */ 1692 1693 #define AMDGPU_REGS_IDX (1<<0) 1694 #define AMDGPU_REGS_NO_KIQ (1<<1) 1695 1696 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1697 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1698 1699 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1700 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1701 1702 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1703 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1704 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1705 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1706 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1707 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1708 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1709 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1710 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1711 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1712 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1713 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1714 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1715 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1716 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1717 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1718 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1719 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1720 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1721 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1722 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1723 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1724 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1725 #define WREG32_P(reg, val, mask) \ 1726 do { \ 1727 uint32_t tmp_ = RREG32(reg); \ 1728 tmp_ &= (mask); \ 1729 tmp_ |= ((val) & ~(mask)); \ 1730 WREG32(reg, tmp_); \ 1731 } while (0) 1732 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1733 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1734 #define WREG32_PLL_P(reg, val, mask) \ 1735 do { \ 1736 uint32_t tmp_ = RREG32_PLL(reg); \ 1737 tmp_ &= (mask); \ 1738 tmp_ |= ((val) & ~(mask)); \ 1739 WREG32_PLL(reg, tmp_); \ 1740 } while (0) 1741 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1742 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1743 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1744 1745 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1746 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1747 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1748 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1749 1750 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1751 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1752 1753 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1754 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1755 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1756 1757 #define REG_GET_FIELD(value, reg, field) \ 1758 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1759 1760 #define WREG32_FIELD(reg, field, val) \ 1761 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1762 1763 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1764 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1765 1766 /* 1767 * BIOS helpers. 1768 */ 1769 #define RBIOS8(i) (adev->bios[i]) 1770 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1771 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1772 1773 static inline struct amdgpu_sdma_instance * 1774 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1775 { 1776 struct amdgpu_device *adev = ring->adev; 1777 int i; 1778 1779 for (i = 0; i < adev->sdma.num_instances; i++) 1780 if (&adev->sdma.instance[i].ring == ring) 1781 break; 1782 1783 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1784 return &adev->sdma.instance[i]; 1785 else 1786 return NULL; 1787 } 1788 1789 /* 1790 * ASICs macro. 1791 */ 1792 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1793 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1794 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1795 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1796 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1797 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1798 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1799 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1800 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1801 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1802 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1803 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1804 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1805 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1806 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1807 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) 1808 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 1809 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 1810 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1811 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 1812 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags)) 1813 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1814 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1815 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1816 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1817 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1818 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1819 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1820 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1821 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1822 #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c)) 1823 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1824 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1825 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1826 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1827 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1828 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1829 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1830 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1831 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1832 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 1833 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 1834 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 1835 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1836 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1837 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1838 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1839 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 1840 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1841 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1842 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1843 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1844 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1845 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1846 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1847 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1848 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1849 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1850 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1851 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1852 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1853 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1854 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1855 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1856 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1857 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1858 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1859 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) 1860 1861 /* Common functions */ 1862 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1863 struct amdgpu_job* job, bool force); 1864 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1865 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1866 void amdgpu_display_update_priority(struct amdgpu_device *adev); 1867 1868 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1869 u64 num_vis_bytes); 1870 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1871 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1872 void amdgpu_device_vram_location(struct amdgpu_device *adev, 1873 struct amdgpu_gmc *mc, u64 base); 1874 void amdgpu_device_gart_location(struct amdgpu_device *adev, 1875 struct amdgpu_gmc *mc); 1876 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1877 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1878 const u32 *registers, 1879 const u32 array_size); 1880 1881 bool amdgpu_device_is_px(struct drm_device *dev); 1882 /* atpx handler */ 1883 #if defined(CONFIG_VGA_SWITCHEROO) 1884 void amdgpu_register_atpx_handler(void); 1885 void amdgpu_unregister_atpx_handler(void); 1886 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1887 bool amdgpu_is_atpx_hybrid(void); 1888 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1889 bool amdgpu_has_atpx(void); 1890 #else 1891 static inline void amdgpu_register_atpx_handler(void) {} 1892 static inline void amdgpu_unregister_atpx_handler(void) {} 1893 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1894 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1895 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1896 static inline bool amdgpu_has_atpx(void) { return false; } 1897 #endif 1898 1899 /* 1900 * KMS 1901 */ 1902 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1903 extern const int amdgpu_max_kms_ioctl; 1904 1905 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1906 void amdgpu_driver_unload_kms(struct drm_device *dev); 1907 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1908 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1909 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1910 struct drm_file *file_priv); 1911 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1912 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1913 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1914 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1915 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1916 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1917 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1918 unsigned long arg); 1919 1920 /* 1921 * functions used by amdgpu_encoder.c 1922 */ 1923 struct amdgpu_afmt_acr { 1924 u32 clock; 1925 1926 int n_32khz; 1927 int cts_32khz; 1928 1929 int n_44_1khz; 1930 int cts_44_1khz; 1931 1932 int n_48khz; 1933 int cts_48khz; 1934 1935 }; 1936 1937 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1938 1939 /* amdgpu_acpi.c */ 1940 #if defined(CONFIG_ACPI) 1941 int amdgpu_acpi_init(struct amdgpu_device *adev); 1942 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1943 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1944 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1945 u8 perf_req, bool advertise); 1946 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1947 #else 1948 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1949 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1950 #endif 1951 1952 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1953 uint64_t addr, struct amdgpu_bo **bo, 1954 struct amdgpu_bo_va_mapping **mapping); 1955 1956 #if defined(CONFIG_DRM_AMD_DC) 1957 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1958 #else 1959 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1960 #endif 1961 1962 #include "amdgpu_object.h" 1963 #endif 1964