1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <[email protected]> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 54 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 55 56 #define DESCRIPTOR_OUTPUT_MORE 0 57 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 58 #define DESCRIPTOR_INPUT_MORE (2 << 12) 59 #define DESCRIPTOR_INPUT_LAST (3 << 12) 60 #define DESCRIPTOR_STATUS (1 << 11) 61 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 62 #define DESCRIPTOR_PING (1 << 7) 63 #define DESCRIPTOR_YY (1 << 6) 64 #define DESCRIPTOR_NO_IRQ (0 << 4) 65 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 66 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 67 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 68 #define DESCRIPTOR_WAIT (3 << 0) 69 70 #define DESCRIPTOR_CMD (0xf << 12) 71 72 struct descriptor { 73 __le16 req_count; 74 __le16 control; 75 __le32 data_address; 76 __le32 branch_address; 77 __le16 res_count; 78 __le16 transfer_status; 79 } __aligned(16); 80 81 #define CONTROL_SET(regs) (regs) 82 #define CONTROL_CLEAR(regs) ((regs) + 4) 83 #define COMMAND_PTR(regs) ((regs) + 12) 84 #define CONTEXT_MATCH(regs) ((regs) + 16) 85 86 #define AR_BUFFER_SIZE (32*1024) 87 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 88 /* we need at least two pages for proper list management */ 89 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 90 91 #define MAX_ASYNC_PAYLOAD 4096 92 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 93 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 94 95 struct ar_context { 96 struct fw_ohci *ohci; 97 struct page *pages[AR_BUFFERS]; 98 void *buffer; 99 struct descriptor *descriptors; 100 dma_addr_t descriptors_bus; 101 void *pointer; 102 unsigned int last_buffer_index; 103 u32 regs; 104 struct tasklet_struct tasklet; 105 }; 106 107 struct context; 108 109 typedef int (*descriptor_callback_t)(struct context *ctx, 110 struct descriptor *d, 111 struct descriptor *last); 112 113 /* 114 * A buffer that contains a block of DMA-able coherent memory used for 115 * storing a portion of a DMA descriptor program. 116 */ 117 struct descriptor_buffer { 118 struct list_head list; 119 dma_addr_t buffer_bus; 120 size_t buffer_size; 121 size_t used; 122 struct descriptor buffer[]; 123 }; 124 125 struct context { 126 struct fw_ohci *ohci; 127 u32 regs; 128 int total_allocation; 129 u32 current_bus; 130 bool running; 131 bool flushing; 132 133 /* 134 * List of page-sized buffers for storing DMA descriptors. 135 * Head of list contains buffers in use and tail of list contains 136 * free buffers. 137 */ 138 struct list_head buffer_list; 139 140 /* 141 * Pointer to a buffer inside buffer_list that contains the tail 142 * end of the current DMA program. 143 */ 144 struct descriptor_buffer *buffer_tail; 145 146 /* 147 * The descriptor containing the branch address of the first 148 * descriptor that has not yet been filled by the device. 149 */ 150 struct descriptor *last; 151 152 /* 153 * The last descriptor block in the DMA program. It contains the branch 154 * address that must be updated upon appending a new descriptor. 155 */ 156 struct descriptor *prev; 157 int prev_z; 158 159 descriptor_callback_t callback; 160 161 struct tasklet_struct tasklet; 162 }; 163 164 struct iso_context { 165 struct fw_iso_context base; 166 struct context context; 167 void *header; 168 size_t header_length; 169 u32 mc_buffer_bus; 170 u16 mc_completed; 171 u16 last_timestamp; 172 u8 sync; 173 u8 tags; 174 }; 175 176 #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) 177 178 struct fw_ohci { 179 struct fw_card card; 180 181 __iomem char *registers; 182 int node_id; 183 int generation; 184 int request_generation; /* for timestamping incoming requests */ 185 unsigned quirks; 186 unsigned int pri_req_max; 187 u32 bus_time; 188 bool bus_time_running; 189 bool is_root; 190 bool csr_state_setclear_abdicate; 191 int n_ir; 192 int n_it; 193 /* 194 * Spinlock for accessing fw_ohci data. Never call out of 195 * this driver with this lock held. 196 */ 197 spinlock_t lock; 198 199 struct mutex phy_reg_mutex; 200 201 void *misc_buffer; 202 dma_addr_t misc_buffer_bus; 203 204 struct ar_context ar_request_ctx; 205 struct ar_context ar_response_ctx; 206 struct context at_request_ctx; 207 struct context at_response_ctx; 208 209 u32 it_context_support; 210 u32 it_context_mask; /* unoccupied IT contexts */ 211 struct iso_context *it_context_list; 212 u64 ir_context_channels; /* unoccupied channels */ 213 u32 ir_context_support; 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id; 226 dma_addr_t self_id_bus; 227 struct work_struct bus_reset_work; 228 229 u32 self_id_buffer[512]; 230 }; 231 232 static struct workqueue_struct *selfid_workqueue; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_VERSION_1_1 0x010010 259 260 static char ohci_driver_name[] = KBUILD_MODNAME; 261 262 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 263 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 264 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 266 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 267 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 268 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 269 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 270 #define PCI_REV_ID_VIA_VT6306 0x46 271 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 272 273 #define QUIRK_CYCLE_TIMER 0x1 274 #define QUIRK_RESET_PACKET 0x2 275 #define QUIRK_BE_HEADERS 0x4 276 #define QUIRK_NO_1394A 0x8 277 #define QUIRK_NO_MSI 0x10 278 #define QUIRK_TI_SLLZ059 0x20 279 #define QUIRK_IR_WAKE 0x40 280 281 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 282 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 283 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 284 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 285 // while it is probable due to detection of any type of PCIe error. 286 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 287 288 #if IS_ENABLED(CONFIG_X86) 289 290 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 291 { 292 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 293 } 294 295 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 296 297 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 298 { 299 const struct pci_dev *pcie_to_pci_bridge; 300 301 // Detect any type of AMD Ryzen machine. 302 if (!static_cpu_has(X86_FEATURE_ZEN)) 303 return false; 304 305 // Detect VIA VT6306/6307/6308. 306 if (pdev->vendor != PCI_VENDOR_ID_VIA) 307 return false; 308 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 309 return false; 310 311 // Detect Asmedia ASM1083/1085. 312 pcie_to_pci_bridge = pdev->bus->self; 313 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 314 return false; 315 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 316 return false; 317 318 return true; 319 } 320 321 #else 322 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 323 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 324 #endif 325 326 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 327 static const struct { 328 unsigned short vendor, device, revision, flags; 329 } ohci_quirks[] = { 330 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 331 QUIRK_CYCLE_TIMER}, 332 333 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 334 QUIRK_BE_HEADERS}, 335 336 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 337 QUIRK_NO_MSI}, 338 339 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 340 QUIRK_RESET_PACKET}, 341 342 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 343 QUIRK_NO_MSI}, 344 345 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 346 QUIRK_CYCLE_TIMER}, 347 348 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 349 QUIRK_NO_MSI}, 350 351 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 352 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 353 354 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 355 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 356 357 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 358 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 359 360 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 361 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 362 363 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 364 QUIRK_RESET_PACKET}, 365 366 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 367 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 368 369 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 370 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 371 372 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 373 QUIRK_NO_MSI}, 374 375 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 376 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 377 }; 378 379 /* This overrides anything that was found in ohci_quirks[]. */ 380 static int param_quirks; 381 module_param_named(quirks, param_quirks, int, 0644); 382 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 383 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 384 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 385 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 386 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 387 ", disable MSI = " __stringify(QUIRK_NO_MSI) 388 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 389 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 390 ")"); 391 392 #define OHCI_PARAM_DEBUG_AT_AR 1 393 #define OHCI_PARAM_DEBUG_SELFIDS 2 394 #define OHCI_PARAM_DEBUG_IRQS 4 395 396 static int param_debug; 397 module_param_named(debug, param_debug, int, 0644); 398 MODULE_PARM_DESC(debug, "Verbose logging, deprecated in v6.11 kernel or later. (default = 0" 399 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 400 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 401 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 402 ", or a combination, or all = -1)"); 403 404 static bool param_remote_dma; 405 module_param_named(remote_dma, param_remote_dma, bool, 0444); 406 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 407 408 static void log_irqs(struct fw_ohci *ohci, u32 evt) 409 { 410 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 411 return; 412 413 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 414 evt & OHCI1394_selfIDComplete ? " selfID" : "", 415 evt & OHCI1394_RQPkt ? " AR_req" : "", 416 evt & OHCI1394_RSPkt ? " AR_resp" : "", 417 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 418 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 419 evt & OHCI1394_isochRx ? " IR" : "", 420 evt & OHCI1394_isochTx ? " IT" : "", 421 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 422 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 423 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 424 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 425 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 426 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 427 evt & OHCI1394_busReset ? " busReset" : "", 428 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 429 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 430 OHCI1394_respTxComplete | OHCI1394_isochRx | 431 OHCI1394_isochTx | OHCI1394_postedWriteErr | 432 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 433 OHCI1394_cycleInconsistent | 434 OHCI1394_regAccessFail | OHCI1394_busReset) 435 ? " ?" : ""); 436 } 437 438 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 439 { 440 static const char *const speed[] = { 441 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 442 }; 443 static const char *const power[] = { 444 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 445 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 446 }; 447 static const char port[] = { 448 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 449 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 450 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 451 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 452 }; 453 struct self_id_sequence_enumerator enumerator = { 454 .cursor = ohci->self_id_buffer, 455 .quadlet_count = self_id_count, 456 }; 457 458 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 459 return; 460 461 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 462 self_id_count, generation, ohci->node_id); 463 464 while (enumerator.quadlet_count > 0) { 465 unsigned int quadlet_count; 466 unsigned int port_index; 467 const u32 *s; 468 int i; 469 470 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 471 if (IS_ERR(s)) 472 break; 473 474 ohci_notice(ohci, 475 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 476 *s, 477 phy_packet_self_id_get_phy_id(*s), 478 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 479 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 480 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 481 speed[*s >> 14 & 3], *s >> 16 & 63, 482 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 483 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 484 485 port_index = 3; 486 for (i = 1; i < quadlet_count; ++i) { 487 ohci_notice(ohci, 488 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 489 s[i], 490 phy_packet_self_id_get_phy_id(s[i]), 491 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 492 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 493 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 494 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 495 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 496 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 497 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 498 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 499 ); 500 501 port_index += 8; 502 } 503 } 504 } 505 506 static const char *evts[] = { 507 [0x00] = "evt_no_status", [0x01] = "-reserved-", 508 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 509 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 510 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 511 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 512 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 513 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 514 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 515 [0x10] = "-reserved-", [0x11] = "ack_complete", 516 [0x12] = "ack_pending ", [0x13] = "-reserved-", 517 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 518 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 519 [0x18] = "-reserved-", [0x19] = "-reserved-", 520 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 521 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 522 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 523 [0x20] = "pending/cancelled", 524 }; 525 526 static void log_ar_at_event(struct fw_ohci *ohci, 527 char dir, int speed, u32 *header, int evt) 528 { 529 static const char *const tcodes[] = { 530 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 531 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 532 [TCODE_WRITE_RESPONSE] = "W resp", 533 [0x3] = "-reserved-", 534 [TCODE_READ_QUADLET_REQUEST] = "QR req", 535 [TCODE_READ_BLOCK_REQUEST] = "BR req", 536 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 537 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 538 [TCODE_CYCLE_START] = "cycle start", 539 [TCODE_LOCK_REQUEST] = "Lk req", 540 [TCODE_STREAM_DATA] = "async stream packet", 541 [TCODE_LOCK_RESPONSE] = "Lk resp", 542 [0xc] = "-reserved-", 543 [0xd] = "-reserved-", 544 [TCODE_LINK_INTERNAL] = "link internal", 545 [0xf] = "-reserved-", 546 }; 547 int tcode = async_header_get_tcode(header); 548 char specific[12]; 549 550 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 551 return; 552 553 if (unlikely(evt >= ARRAY_SIZE(evts))) 554 evt = 0x1f; 555 556 if (evt == OHCI1394_evt_bus_reset) { 557 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 558 dir, (header[2] >> 16) & 0xff); 559 return; 560 } 561 562 switch (tcode) { 563 case TCODE_WRITE_QUADLET_REQUEST: 564 case TCODE_READ_QUADLET_RESPONSE: 565 case TCODE_CYCLE_START: 566 snprintf(specific, sizeof(specific), " = %08x", 567 be32_to_cpu((__force __be32)header[3])); 568 break; 569 case TCODE_WRITE_BLOCK_REQUEST: 570 case TCODE_READ_BLOCK_REQUEST: 571 case TCODE_READ_BLOCK_RESPONSE: 572 case TCODE_LOCK_REQUEST: 573 case TCODE_LOCK_RESPONSE: 574 snprintf(specific, sizeof(specific), " %x,%x", 575 async_header_get_data_length(header), 576 async_header_get_extended_tcode(header)); 577 break; 578 default: 579 specific[0] = '\0'; 580 } 581 582 switch (tcode) { 583 case TCODE_STREAM_DATA: 584 ohci_notice(ohci, "A%c %s, %s\n", 585 dir, evts[evt], tcodes[tcode]); 586 break; 587 case TCODE_LINK_INTERNAL: 588 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 589 dir, evts[evt], header[1], header[2]); 590 break; 591 case TCODE_WRITE_QUADLET_REQUEST: 592 case TCODE_WRITE_BLOCK_REQUEST: 593 case TCODE_READ_QUADLET_REQUEST: 594 case TCODE_READ_BLOCK_REQUEST: 595 case TCODE_LOCK_REQUEST: 596 ohci_notice(ohci, 597 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 598 dir, speed, async_header_get_tlabel(header), 599 async_header_get_source(header), async_header_get_destination(header), 600 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 601 break; 602 default: 603 ohci_notice(ohci, 604 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 605 dir, speed, async_header_get_tlabel(header), 606 async_header_get_source(header), async_header_get_destination(header), 607 evts[evt], tcodes[tcode], specific); 608 } 609 } 610 611 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 612 { 613 writel(data, ohci->registers + offset); 614 } 615 616 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 617 { 618 return readl(ohci->registers + offset); 619 } 620 621 static inline void flush_writes(const struct fw_ohci *ohci) 622 { 623 /* Do a dummy read to flush writes. */ 624 reg_read(ohci, OHCI1394_Version); 625 } 626 627 /* 628 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 629 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 630 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 631 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 632 */ 633 static int read_phy_reg(struct fw_ohci *ohci, int addr) 634 { 635 u32 val; 636 int i; 637 638 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 639 for (i = 0; i < 3 + 100; i++) { 640 val = reg_read(ohci, OHCI1394_PhyControl); 641 if (!~val) 642 return -ENODEV; /* Card was ejected. */ 643 644 if (val & OHCI1394_PhyControl_ReadDone) 645 return OHCI1394_PhyControl_ReadData(val); 646 647 /* 648 * Try a few times without waiting. Sleeping is necessary 649 * only when the link/PHY interface is busy. 650 */ 651 if (i >= 3) 652 msleep(1); 653 } 654 ohci_err(ohci, "failed to read phy reg %d\n", addr); 655 dump_stack(); 656 657 return -EBUSY; 658 } 659 660 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 661 { 662 int i; 663 664 reg_write(ohci, OHCI1394_PhyControl, 665 OHCI1394_PhyControl_Write(addr, val)); 666 for (i = 0; i < 3 + 100; i++) { 667 val = reg_read(ohci, OHCI1394_PhyControl); 668 if (!~val) 669 return -ENODEV; /* Card was ejected. */ 670 671 if (!(val & OHCI1394_PhyControl_WritePending)) 672 return 0; 673 674 if (i >= 3) 675 msleep(1); 676 } 677 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 678 dump_stack(); 679 680 return -EBUSY; 681 } 682 683 static int update_phy_reg(struct fw_ohci *ohci, int addr, 684 int clear_bits, int set_bits) 685 { 686 int ret = read_phy_reg(ohci, addr); 687 if (ret < 0) 688 return ret; 689 690 /* 691 * The interrupt status bits are cleared by writing a one bit. 692 * Avoid clearing them unless explicitly requested in set_bits. 693 */ 694 if (addr == 5) 695 clear_bits |= PHY_INT_STATUS_BITS; 696 697 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 698 } 699 700 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 701 { 702 int ret; 703 704 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 705 if (ret < 0) 706 return ret; 707 708 return read_phy_reg(ohci, addr); 709 } 710 711 static int ohci_read_phy_reg(struct fw_card *card, int addr) 712 { 713 struct fw_ohci *ohci = fw_ohci(card); 714 715 guard(mutex)(&ohci->phy_reg_mutex); 716 717 return read_phy_reg(ohci, addr); 718 } 719 720 static int ohci_update_phy_reg(struct fw_card *card, int addr, 721 int clear_bits, int set_bits) 722 { 723 struct fw_ohci *ohci = fw_ohci(card); 724 725 guard(mutex)(&ohci->phy_reg_mutex); 726 727 return update_phy_reg(ohci, addr, clear_bits, set_bits); 728 } 729 730 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 731 { 732 return page_private(ctx->pages[i]); 733 } 734 735 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 736 { 737 struct descriptor *d; 738 739 d = &ctx->descriptors[index]; 740 d->branch_address &= cpu_to_le32(~0xf); 741 d->res_count = cpu_to_le16(PAGE_SIZE); 742 d->transfer_status = 0; 743 744 wmb(); /* finish init of new descriptors before branch_address update */ 745 d = &ctx->descriptors[ctx->last_buffer_index]; 746 d->branch_address |= cpu_to_le32(1); 747 748 ctx->last_buffer_index = index; 749 750 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 751 } 752 753 static void ar_context_release(struct ar_context *ctx) 754 { 755 struct device *dev = ctx->ohci->card.device; 756 unsigned int i; 757 758 if (!ctx->buffer) 759 return; 760 761 vunmap(ctx->buffer); 762 763 for (i = 0; i < AR_BUFFERS; i++) { 764 if (ctx->pages[i]) 765 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 766 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 767 } 768 } 769 770 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 771 { 772 struct fw_ohci *ohci = ctx->ohci; 773 774 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 775 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 776 flush_writes(ohci); 777 778 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 779 } 780 /* FIXME: restart? */ 781 } 782 783 static inline unsigned int ar_next_buffer_index(unsigned int index) 784 { 785 return (index + 1) % AR_BUFFERS; 786 } 787 788 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 789 { 790 return ar_next_buffer_index(ctx->last_buffer_index); 791 } 792 793 /* 794 * We search for the buffer that contains the last AR packet DMA data written 795 * by the controller. 796 */ 797 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 798 unsigned int *buffer_offset) 799 { 800 unsigned int i, next_i, last = ctx->last_buffer_index; 801 __le16 res_count, next_res_count; 802 803 i = ar_first_buffer_index(ctx); 804 res_count = READ_ONCE(ctx->descriptors[i].res_count); 805 806 /* A buffer that is not yet completely filled must be the last one. */ 807 while (i != last && res_count == 0) { 808 809 /* Peek at the next descriptor. */ 810 next_i = ar_next_buffer_index(i); 811 rmb(); /* read descriptors in order */ 812 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 813 /* 814 * If the next descriptor is still empty, we must stop at this 815 * descriptor. 816 */ 817 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 818 /* 819 * The exception is when the DMA data for one packet is 820 * split over three buffers; in this case, the middle 821 * buffer's descriptor might be never updated by the 822 * controller and look still empty, and we have to peek 823 * at the third one. 824 */ 825 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 826 next_i = ar_next_buffer_index(next_i); 827 rmb(); 828 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 829 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 830 goto next_buffer_is_active; 831 } 832 833 break; 834 } 835 836 next_buffer_is_active: 837 i = next_i; 838 res_count = next_res_count; 839 } 840 841 rmb(); /* read res_count before the DMA data */ 842 843 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 844 if (*buffer_offset > PAGE_SIZE) { 845 *buffer_offset = 0; 846 ar_context_abort(ctx, "corrupted descriptor"); 847 } 848 849 return i; 850 } 851 852 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 853 unsigned int end_buffer_index, 854 unsigned int end_buffer_offset) 855 { 856 unsigned int i; 857 858 i = ar_first_buffer_index(ctx); 859 while (i != end_buffer_index) { 860 dma_sync_single_for_cpu(ctx->ohci->card.device, 861 ar_buffer_bus(ctx, i), 862 PAGE_SIZE, DMA_FROM_DEVICE); 863 i = ar_next_buffer_index(i); 864 } 865 if (end_buffer_offset > 0) 866 dma_sync_single_for_cpu(ctx->ohci->card.device, 867 ar_buffer_bus(ctx, i), 868 end_buffer_offset, DMA_FROM_DEVICE); 869 } 870 871 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 872 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 873 { 874 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 875 } 876 877 static bool has_be_header_quirk(const struct fw_ohci *ohci) 878 { 879 return !!(ohci->quirks & QUIRK_BE_HEADERS); 880 } 881 #else 882 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 883 { 884 return le32_to_cpu(value); 885 } 886 887 static bool has_be_header_quirk(const struct fw_ohci *ohci) 888 { 889 return false; 890 } 891 #endif 892 893 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 894 { 895 struct fw_ohci *ohci = ctx->ohci; 896 struct fw_packet p; 897 u32 status, length, tcode; 898 int evt; 899 900 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 901 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 902 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 903 904 tcode = async_header_get_tcode(p.header); 905 switch (tcode) { 906 case TCODE_WRITE_QUADLET_REQUEST: 907 case TCODE_READ_QUADLET_RESPONSE: 908 p.header[3] = (__force __u32) buffer[3]; 909 p.header_length = 16; 910 p.payload_length = 0; 911 break; 912 913 case TCODE_READ_BLOCK_REQUEST : 914 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 915 p.header_length = 16; 916 p.payload_length = 0; 917 break; 918 919 case TCODE_WRITE_BLOCK_REQUEST: 920 case TCODE_READ_BLOCK_RESPONSE: 921 case TCODE_LOCK_REQUEST: 922 case TCODE_LOCK_RESPONSE: 923 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 924 p.header_length = 16; 925 p.payload_length = async_header_get_data_length(p.header); 926 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 927 ar_context_abort(ctx, "invalid packet length"); 928 return NULL; 929 } 930 break; 931 932 case TCODE_WRITE_RESPONSE: 933 case TCODE_READ_QUADLET_REQUEST: 934 case TCODE_LINK_INTERNAL: 935 p.header_length = 12; 936 p.payload_length = 0; 937 break; 938 939 default: 940 ar_context_abort(ctx, "invalid tcode"); 941 return NULL; 942 } 943 944 p.payload = (void *) buffer + p.header_length; 945 946 /* FIXME: What to do about evt_* errors? */ 947 length = (p.header_length + p.payload_length + 3) / 4; 948 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 949 evt = (status >> 16) & 0x1f; 950 951 p.ack = evt - 16; 952 p.speed = (status >> 21) & 0x7; 953 p.timestamp = status & 0xffff; 954 p.generation = ohci->request_generation; 955 956 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 957 958 /* 959 * Several controllers, notably from NEC and VIA, forget to 960 * write ack_complete status at PHY packet reception. 961 */ 962 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 963 p.ack = ACK_COMPLETE; 964 965 /* 966 * The OHCI bus reset handler synthesizes a PHY packet with 967 * the new generation number when a bus reset happens (see 968 * section 8.4.2.3). This helps us determine when a request 969 * was received and make sure we send the response in the same 970 * generation. We only need this for requests; for responses 971 * we use the unique tlabel for finding the matching 972 * request. 973 * 974 * Alas some chips sometimes emit bus reset packets with a 975 * wrong generation. We set the correct generation for these 976 * at a slightly incorrect time (in bus_reset_work). 977 */ 978 if (evt == OHCI1394_evt_bus_reset) { 979 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 980 ohci->request_generation = (p.header[2] >> 16) & 0xff; 981 } else if (ctx == &ohci->ar_request_ctx) { 982 fw_core_handle_request(&ohci->card, &p); 983 } else { 984 fw_core_handle_response(&ohci->card, &p); 985 } 986 987 return buffer + length + 1; 988 } 989 990 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 991 { 992 void *next; 993 994 while (p < end) { 995 next = handle_ar_packet(ctx, p); 996 if (!next) 997 return p; 998 p = next; 999 } 1000 1001 return p; 1002 } 1003 1004 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1005 { 1006 unsigned int i; 1007 1008 i = ar_first_buffer_index(ctx); 1009 while (i != end_buffer) { 1010 dma_sync_single_for_device(ctx->ohci->card.device, 1011 ar_buffer_bus(ctx, i), 1012 PAGE_SIZE, DMA_FROM_DEVICE); 1013 ar_context_link_page(ctx, i); 1014 i = ar_next_buffer_index(i); 1015 } 1016 } 1017 1018 static void ar_context_tasklet(unsigned long data) 1019 { 1020 struct ar_context *ctx = (struct ar_context *)data; 1021 unsigned int end_buffer_index, end_buffer_offset; 1022 void *p, *end; 1023 1024 p = ctx->pointer; 1025 if (!p) 1026 return; 1027 1028 end_buffer_index = ar_search_last_active_buffer(ctx, 1029 &end_buffer_offset); 1030 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1031 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1032 1033 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1034 /* 1035 * The filled part of the overall buffer wraps around; handle 1036 * all packets up to the buffer end here. If the last packet 1037 * wraps around, its tail will be visible after the buffer end 1038 * because the buffer start pages are mapped there again. 1039 */ 1040 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1041 p = handle_ar_packets(ctx, p, buffer_end); 1042 if (p < buffer_end) 1043 goto error; 1044 /* adjust p to point back into the actual buffer */ 1045 p -= AR_BUFFERS * PAGE_SIZE; 1046 } 1047 1048 p = handle_ar_packets(ctx, p, end); 1049 if (p != end) { 1050 if (p > end) 1051 ar_context_abort(ctx, "inconsistent descriptor"); 1052 goto error; 1053 } 1054 1055 ctx->pointer = p; 1056 ar_recycle_buffers(ctx, end_buffer_index); 1057 1058 return; 1059 1060 error: 1061 ctx->pointer = NULL; 1062 } 1063 1064 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1065 unsigned int descriptors_offset, u32 regs) 1066 { 1067 struct device *dev = ohci->card.device; 1068 unsigned int i; 1069 dma_addr_t dma_addr; 1070 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1071 struct descriptor *d; 1072 1073 ctx->regs = regs; 1074 ctx->ohci = ohci; 1075 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1076 1077 for (i = 0; i < AR_BUFFERS; i++) { 1078 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1079 DMA_FROM_DEVICE, GFP_KERNEL); 1080 if (!ctx->pages[i]) 1081 goto out_of_memory; 1082 set_page_private(ctx->pages[i], dma_addr); 1083 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1084 DMA_FROM_DEVICE); 1085 } 1086 1087 for (i = 0; i < AR_BUFFERS; i++) 1088 pages[i] = ctx->pages[i]; 1089 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1090 pages[AR_BUFFERS + i] = ctx->pages[i]; 1091 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1092 if (!ctx->buffer) 1093 goto out_of_memory; 1094 1095 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1096 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1097 1098 for (i = 0; i < AR_BUFFERS; i++) { 1099 d = &ctx->descriptors[i]; 1100 d->req_count = cpu_to_le16(PAGE_SIZE); 1101 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1102 DESCRIPTOR_STATUS | 1103 DESCRIPTOR_BRANCH_ALWAYS); 1104 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1105 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1106 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1107 } 1108 1109 return 0; 1110 1111 out_of_memory: 1112 ar_context_release(ctx); 1113 1114 return -ENOMEM; 1115 } 1116 1117 static void ar_context_run(struct ar_context *ctx) 1118 { 1119 unsigned int i; 1120 1121 for (i = 0; i < AR_BUFFERS; i++) 1122 ar_context_link_page(ctx, i); 1123 1124 ctx->pointer = ctx->buffer; 1125 1126 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1127 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1128 } 1129 1130 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1131 { 1132 __le16 branch; 1133 1134 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1135 1136 /* figure out which descriptor the branch address goes in */ 1137 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1138 return d; 1139 else 1140 return d + z - 1; 1141 } 1142 1143 static void context_tasklet(unsigned long data) 1144 { 1145 struct context *ctx = (struct context *) data; 1146 struct descriptor *d, *last; 1147 u32 address; 1148 int z; 1149 struct descriptor_buffer *desc; 1150 1151 desc = list_entry(ctx->buffer_list.next, 1152 struct descriptor_buffer, list); 1153 last = ctx->last; 1154 while (last->branch_address != 0) { 1155 struct descriptor_buffer *old_desc = desc; 1156 address = le32_to_cpu(last->branch_address); 1157 z = address & 0xf; 1158 address &= ~0xf; 1159 ctx->current_bus = address; 1160 1161 /* If the branch address points to a buffer outside of the 1162 * current buffer, advance to the next buffer. */ 1163 if (address < desc->buffer_bus || 1164 address >= desc->buffer_bus + desc->used) 1165 desc = list_entry(desc->list.next, 1166 struct descriptor_buffer, list); 1167 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1168 last = find_branch_descriptor(d, z); 1169 1170 if (!ctx->callback(ctx, d, last)) 1171 break; 1172 1173 if (old_desc != desc) { 1174 // If we've advanced to the next buffer, move the previous buffer to the 1175 // free list. 1176 old_desc->used = 0; 1177 guard(spinlock_irqsave)(&ctx->ohci->lock); 1178 list_move_tail(&old_desc->list, &ctx->buffer_list); 1179 } 1180 ctx->last = last; 1181 } 1182 } 1183 1184 /* 1185 * Allocate a new buffer and add it to the list of free buffers for this 1186 * context. Must be called with ohci->lock held. 1187 */ 1188 static int context_add_buffer(struct context *ctx) 1189 { 1190 struct descriptor_buffer *desc; 1191 dma_addr_t bus_addr; 1192 int offset; 1193 1194 /* 1195 * 16MB of descriptors should be far more than enough for any DMA 1196 * program. This will catch run-away userspace or DoS attacks. 1197 */ 1198 if (ctx->total_allocation >= 16*1024*1024) 1199 return -ENOMEM; 1200 1201 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1202 if (!desc) 1203 return -ENOMEM; 1204 1205 offset = (void *)&desc->buffer - (void *)desc; 1206 /* 1207 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1208 * for descriptors, even 0x10-byte ones. This can cause page faults when 1209 * an IOMMU is in use and the oversized read crosses a page boundary. 1210 * Work around this by always leaving at least 0x10 bytes of padding. 1211 */ 1212 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1213 desc->buffer_bus = bus_addr + offset; 1214 desc->used = 0; 1215 1216 list_add_tail(&desc->list, &ctx->buffer_list); 1217 ctx->total_allocation += PAGE_SIZE; 1218 1219 return 0; 1220 } 1221 1222 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1223 u32 regs, descriptor_callback_t callback) 1224 { 1225 ctx->ohci = ohci; 1226 ctx->regs = regs; 1227 ctx->total_allocation = 0; 1228 1229 INIT_LIST_HEAD(&ctx->buffer_list); 1230 if (context_add_buffer(ctx) < 0) 1231 return -ENOMEM; 1232 1233 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1234 struct descriptor_buffer, list); 1235 1236 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1237 ctx->callback = callback; 1238 1239 /* 1240 * We put a dummy descriptor in the buffer that has a NULL 1241 * branch address and looks like it's been sent. That way we 1242 * have a descriptor to append DMA programs to. 1243 */ 1244 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1245 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1246 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1247 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1248 ctx->last = ctx->buffer_tail->buffer; 1249 ctx->prev = ctx->buffer_tail->buffer; 1250 ctx->prev_z = 1; 1251 1252 return 0; 1253 } 1254 1255 static void context_release(struct context *ctx) 1256 { 1257 struct fw_card *card = &ctx->ohci->card; 1258 struct descriptor_buffer *desc, *tmp; 1259 1260 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1261 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1262 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1263 } 1264 } 1265 1266 /* Must be called with ohci->lock held */ 1267 static struct descriptor *context_get_descriptors(struct context *ctx, 1268 int z, dma_addr_t *d_bus) 1269 { 1270 struct descriptor *d = NULL; 1271 struct descriptor_buffer *desc = ctx->buffer_tail; 1272 1273 if (z * sizeof(*d) > desc->buffer_size) 1274 return NULL; 1275 1276 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1277 /* No room for the descriptor in this buffer, so advance to the 1278 * next one. */ 1279 1280 if (desc->list.next == &ctx->buffer_list) { 1281 /* If there is no free buffer next in the list, 1282 * allocate one. */ 1283 if (context_add_buffer(ctx) < 0) 1284 return NULL; 1285 } 1286 desc = list_entry(desc->list.next, 1287 struct descriptor_buffer, list); 1288 ctx->buffer_tail = desc; 1289 } 1290 1291 d = desc->buffer + desc->used / sizeof(*d); 1292 memset(d, 0, z * sizeof(*d)); 1293 *d_bus = desc->buffer_bus + desc->used; 1294 1295 return d; 1296 } 1297 1298 static void context_run(struct context *ctx, u32 extra) 1299 { 1300 struct fw_ohci *ohci = ctx->ohci; 1301 1302 reg_write(ohci, COMMAND_PTR(ctx->regs), 1303 le32_to_cpu(ctx->last->branch_address)); 1304 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1305 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1306 ctx->running = true; 1307 flush_writes(ohci); 1308 } 1309 1310 static void context_append(struct context *ctx, 1311 struct descriptor *d, int z, int extra) 1312 { 1313 dma_addr_t d_bus; 1314 struct descriptor_buffer *desc = ctx->buffer_tail; 1315 struct descriptor *d_branch; 1316 1317 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1318 1319 desc->used += (z + extra) * sizeof(*d); 1320 1321 wmb(); /* finish init of new descriptors before branch_address update */ 1322 1323 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1324 d_branch->branch_address = cpu_to_le32(d_bus | z); 1325 1326 /* 1327 * VT6306 incorrectly checks only the single descriptor at the 1328 * CommandPtr when the wake bit is written, so if it's a 1329 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1330 * the branch address in the first descriptor. 1331 * 1332 * Not doing this for transmit contexts since not sure how it interacts 1333 * with skip addresses. 1334 */ 1335 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1336 d_branch != ctx->prev && 1337 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1338 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1339 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1340 } 1341 1342 ctx->prev = d; 1343 ctx->prev_z = z; 1344 } 1345 1346 static void context_stop(struct context *ctx) 1347 { 1348 struct fw_ohci *ohci = ctx->ohci; 1349 u32 reg; 1350 int i; 1351 1352 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1353 ctx->running = false; 1354 1355 for (i = 0; i < 1000; i++) { 1356 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1357 if ((reg & CONTEXT_ACTIVE) == 0) 1358 return; 1359 1360 if (i) 1361 udelay(10); 1362 } 1363 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1364 } 1365 1366 struct driver_data { 1367 u8 inline_data[8]; 1368 struct fw_packet *packet; 1369 }; 1370 1371 /* 1372 * This function apppends a packet to the DMA queue for transmission. 1373 * Must always be called with the ochi->lock held to ensure proper 1374 * generation handling and locking around packet queue manipulation. 1375 */ 1376 static int at_context_queue_packet(struct context *ctx, 1377 struct fw_packet *packet) 1378 { 1379 struct fw_ohci *ohci = ctx->ohci; 1380 dma_addr_t d_bus, payload_bus; 1381 struct driver_data *driver_data; 1382 struct descriptor *d, *last; 1383 __le32 *header; 1384 int z, tcode; 1385 1386 d = context_get_descriptors(ctx, 4, &d_bus); 1387 if (d == NULL) { 1388 packet->ack = RCODE_SEND_ERROR; 1389 return -1; 1390 } 1391 1392 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1393 d[0].res_count = cpu_to_le16(packet->timestamp); 1394 1395 tcode = async_header_get_tcode(packet->header); 1396 header = (__le32 *) &d[1]; 1397 switch (tcode) { 1398 case TCODE_WRITE_QUADLET_REQUEST: 1399 case TCODE_WRITE_BLOCK_REQUEST: 1400 case TCODE_WRITE_RESPONSE: 1401 case TCODE_READ_QUADLET_REQUEST: 1402 case TCODE_READ_BLOCK_REQUEST: 1403 case TCODE_READ_QUADLET_RESPONSE: 1404 case TCODE_READ_BLOCK_RESPONSE: 1405 case TCODE_LOCK_REQUEST: 1406 case TCODE_LOCK_RESPONSE: 1407 ohci1394_at_data_set_src_bus_id(header, false); 1408 ohci1394_at_data_set_speed(header, packet->speed); 1409 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1410 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1411 ohci1394_at_data_set_tcode(header, tcode); 1412 1413 ohci1394_at_data_set_destination_id(header, 1414 async_header_get_destination(packet->header)); 1415 1416 if (ctx == &ctx->ohci->at_response_ctx) { 1417 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1418 } else { 1419 ohci1394_at_data_set_destination_offset(header, 1420 async_header_get_offset(packet->header)); 1421 } 1422 1423 if (tcode_is_block_packet(tcode)) 1424 header[3] = cpu_to_le32(packet->header[3]); 1425 else 1426 header[3] = (__force __le32) packet->header[3]; 1427 1428 d[0].req_count = cpu_to_le16(packet->header_length); 1429 break; 1430 case TCODE_LINK_INTERNAL: 1431 ohci1394_at_data_set_speed(header, packet->speed); 1432 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1433 1434 header[1] = cpu_to_le32(packet->header[1]); 1435 header[2] = cpu_to_le32(packet->header[2]); 1436 d[0].req_count = cpu_to_le16(12); 1437 1438 if (is_ping_packet(&packet->header[1])) 1439 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1440 break; 1441 1442 case TCODE_STREAM_DATA: 1443 ohci1394_it_data_set_speed(header, packet->speed); 1444 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0])); 1445 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0])); 1446 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 1447 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0])); 1448 1449 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0])); 1450 1451 d[0].req_count = cpu_to_le16(8); 1452 break; 1453 1454 default: 1455 /* BUG(); */ 1456 packet->ack = RCODE_SEND_ERROR; 1457 return -1; 1458 } 1459 1460 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1461 driver_data = (struct driver_data *) &d[3]; 1462 driver_data->packet = packet; 1463 packet->driver_data = driver_data; 1464 1465 if (packet->payload_length > 0) { 1466 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1467 payload_bus = dma_map_single(ohci->card.device, 1468 packet->payload, 1469 packet->payload_length, 1470 DMA_TO_DEVICE); 1471 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1472 packet->ack = RCODE_SEND_ERROR; 1473 return -1; 1474 } 1475 packet->payload_bus = payload_bus; 1476 packet->payload_mapped = true; 1477 } else { 1478 memcpy(driver_data->inline_data, packet->payload, 1479 packet->payload_length); 1480 payload_bus = d_bus + 3 * sizeof(*d); 1481 } 1482 1483 d[2].req_count = cpu_to_le16(packet->payload_length); 1484 d[2].data_address = cpu_to_le32(payload_bus); 1485 last = &d[2]; 1486 z = 3; 1487 } else { 1488 last = &d[0]; 1489 z = 2; 1490 } 1491 1492 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1493 DESCRIPTOR_IRQ_ALWAYS | 1494 DESCRIPTOR_BRANCH_ALWAYS); 1495 1496 /* FIXME: Document how the locking works. */ 1497 if (ohci->generation != packet->generation) { 1498 if (packet->payload_mapped) 1499 dma_unmap_single(ohci->card.device, payload_bus, 1500 packet->payload_length, DMA_TO_DEVICE); 1501 packet->ack = RCODE_GENERATION; 1502 return -1; 1503 } 1504 1505 context_append(ctx, d, z, 4 - z); 1506 1507 if (ctx->running) 1508 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1509 else 1510 context_run(ctx, 0); 1511 1512 return 0; 1513 } 1514 1515 static void at_context_flush(struct context *ctx) 1516 { 1517 tasklet_disable(&ctx->tasklet); 1518 1519 ctx->flushing = true; 1520 context_tasklet((unsigned long)ctx); 1521 ctx->flushing = false; 1522 1523 tasklet_enable(&ctx->tasklet); 1524 } 1525 1526 static int handle_at_packet(struct context *context, 1527 struct descriptor *d, 1528 struct descriptor *last) 1529 { 1530 struct driver_data *driver_data; 1531 struct fw_packet *packet; 1532 struct fw_ohci *ohci = context->ohci; 1533 int evt; 1534 1535 if (last->transfer_status == 0 && !context->flushing) 1536 /* This descriptor isn't done yet, stop iteration. */ 1537 return 0; 1538 1539 driver_data = (struct driver_data *) &d[3]; 1540 packet = driver_data->packet; 1541 if (packet == NULL) 1542 /* This packet was cancelled, just continue. */ 1543 return 1; 1544 1545 if (packet->payload_mapped) 1546 dma_unmap_single(ohci->card.device, packet->payload_bus, 1547 packet->payload_length, DMA_TO_DEVICE); 1548 1549 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1550 packet->timestamp = le16_to_cpu(last->res_count); 1551 1552 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1553 1554 switch (evt) { 1555 case OHCI1394_evt_timeout: 1556 /* Async response transmit timed out. */ 1557 packet->ack = RCODE_CANCELLED; 1558 break; 1559 1560 case OHCI1394_evt_flushed: 1561 /* 1562 * The packet was flushed should give same error as 1563 * when we try to use a stale generation count. 1564 */ 1565 packet->ack = RCODE_GENERATION; 1566 break; 1567 1568 case OHCI1394_evt_missing_ack: 1569 if (context->flushing) 1570 packet->ack = RCODE_GENERATION; 1571 else { 1572 /* 1573 * Using a valid (current) generation count, but the 1574 * node is not on the bus or not sending acks. 1575 */ 1576 packet->ack = RCODE_NO_ACK; 1577 } 1578 break; 1579 1580 case ACK_COMPLETE + 0x10: 1581 case ACK_PENDING + 0x10: 1582 case ACK_BUSY_X + 0x10: 1583 case ACK_BUSY_A + 0x10: 1584 case ACK_BUSY_B + 0x10: 1585 case ACK_DATA_ERROR + 0x10: 1586 case ACK_TYPE_ERROR + 0x10: 1587 packet->ack = evt - 0x10; 1588 break; 1589 1590 case OHCI1394_evt_no_status: 1591 if (context->flushing) { 1592 packet->ack = RCODE_GENERATION; 1593 break; 1594 } 1595 fallthrough; 1596 1597 default: 1598 packet->ack = RCODE_SEND_ERROR; 1599 break; 1600 } 1601 1602 packet->callback(packet, &ohci->card, packet->ack); 1603 1604 return 1; 1605 } 1606 1607 static u32 get_cycle_time(struct fw_ohci *ohci); 1608 1609 static void handle_local_rom(struct fw_ohci *ohci, 1610 struct fw_packet *packet, u32 csr) 1611 { 1612 struct fw_packet response; 1613 int tcode, length, i; 1614 1615 tcode = async_header_get_tcode(packet->header); 1616 if (tcode_is_block_packet(tcode)) 1617 length = async_header_get_data_length(packet->header); 1618 else 1619 length = 4; 1620 1621 i = csr - CSR_CONFIG_ROM; 1622 if (i + length > CONFIG_ROM_SIZE) { 1623 fw_fill_response(&response, packet->header, 1624 RCODE_ADDRESS_ERROR, NULL, 0); 1625 } else if (!tcode_is_read_request(tcode)) { 1626 fw_fill_response(&response, packet->header, 1627 RCODE_TYPE_ERROR, NULL, 0); 1628 } else { 1629 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1630 (void *) ohci->config_rom + i, length); 1631 } 1632 1633 // Timestamping on behalf of the hardware. 1634 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1635 fw_core_handle_response(&ohci->card, &response); 1636 } 1637 1638 static void handle_local_lock(struct fw_ohci *ohci, 1639 struct fw_packet *packet, u32 csr) 1640 { 1641 struct fw_packet response; 1642 int tcode, length, ext_tcode, sel, try; 1643 __be32 *payload, lock_old; 1644 u32 lock_arg, lock_data; 1645 1646 tcode = async_header_get_tcode(packet->header); 1647 length = async_header_get_data_length(packet->header); 1648 payload = packet->payload; 1649 ext_tcode = async_header_get_extended_tcode(packet->header); 1650 1651 if (tcode == TCODE_LOCK_REQUEST && 1652 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1653 lock_arg = be32_to_cpu(payload[0]); 1654 lock_data = be32_to_cpu(payload[1]); 1655 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1656 lock_arg = 0; 1657 lock_data = 0; 1658 } else { 1659 fw_fill_response(&response, packet->header, 1660 RCODE_TYPE_ERROR, NULL, 0); 1661 goto out; 1662 } 1663 1664 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1665 reg_write(ohci, OHCI1394_CSRData, lock_data); 1666 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1667 reg_write(ohci, OHCI1394_CSRControl, sel); 1668 1669 for (try = 0; try < 20; try++) 1670 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1671 lock_old = cpu_to_be32(reg_read(ohci, 1672 OHCI1394_CSRData)); 1673 fw_fill_response(&response, packet->header, 1674 RCODE_COMPLETE, 1675 &lock_old, sizeof(lock_old)); 1676 goto out; 1677 } 1678 1679 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1680 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1681 1682 out: 1683 // Timestamping on behalf of the hardware. 1684 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1685 fw_core_handle_response(&ohci->card, &response); 1686 } 1687 1688 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1689 { 1690 u64 offset, csr; 1691 1692 if (ctx == &ctx->ohci->at_request_ctx) { 1693 packet->ack = ACK_PENDING; 1694 packet->callback(packet, &ctx->ohci->card, packet->ack); 1695 } 1696 1697 offset = async_header_get_offset(packet->header); 1698 csr = offset - CSR_REGISTER_BASE; 1699 1700 /* Handle config rom reads. */ 1701 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1702 handle_local_rom(ctx->ohci, packet, csr); 1703 else switch (csr) { 1704 case CSR_BUS_MANAGER_ID: 1705 case CSR_BANDWIDTH_AVAILABLE: 1706 case CSR_CHANNELS_AVAILABLE_HI: 1707 case CSR_CHANNELS_AVAILABLE_LO: 1708 handle_local_lock(ctx->ohci, packet, csr); 1709 break; 1710 default: 1711 if (ctx == &ctx->ohci->at_request_ctx) 1712 fw_core_handle_request(&ctx->ohci->card, packet); 1713 else 1714 fw_core_handle_response(&ctx->ohci->card, packet); 1715 break; 1716 } 1717 1718 if (ctx == &ctx->ohci->at_response_ctx) { 1719 packet->ack = ACK_COMPLETE; 1720 packet->callback(packet, &ctx->ohci->card, packet->ack); 1721 } 1722 } 1723 1724 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1725 { 1726 unsigned long flags; 1727 int ret; 1728 1729 spin_lock_irqsave(&ctx->ohci->lock, flags); 1730 1731 if (async_header_get_destination(packet->header) == ctx->ohci->node_id && 1732 ctx->ohci->generation == packet->generation) { 1733 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1734 1735 // Timestamping on behalf of the hardware. 1736 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1737 1738 handle_local_request(ctx, packet); 1739 return; 1740 } 1741 1742 ret = at_context_queue_packet(ctx, packet); 1743 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1744 1745 if (ret < 0) { 1746 // Timestamping on behalf of the hardware. 1747 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1748 1749 packet->callback(packet, &ctx->ohci->card, packet->ack); 1750 } 1751 } 1752 1753 static void detect_dead_context(struct fw_ohci *ohci, 1754 const char *name, unsigned int regs) 1755 { 1756 u32 ctl; 1757 1758 ctl = reg_read(ohci, CONTROL_SET(regs)); 1759 if (ctl & CONTEXT_DEAD) 1760 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1761 name, evts[ctl & 0x1f]); 1762 } 1763 1764 static void handle_dead_contexts(struct fw_ohci *ohci) 1765 { 1766 unsigned int i; 1767 char name[8]; 1768 1769 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1770 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1771 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1772 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1773 for (i = 0; i < 32; ++i) { 1774 if (!(ohci->it_context_support & (1 << i))) 1775 continue; 1776 sprintf(name, "IT%u", i); 1777 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1778 } 1779 for (i = 0; i < 32; ++i) { 1780 if (!(ohci->ir_context_support & (1 << i))) 1781 continue; 1782 sprintf(name, "IR%u", i); 1783 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1784 } 1785 /* TODO: maybe try to flush and restart the dead contexts */ 1786 } 1787 1788 static u32 cycle_timer_ticks(u32 cycle_timer) 1789 { 1790 u32 ticks; 1791 1792 ticks = cycle_timer & 0xfff; 1793 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1794 ticks += (3072 * 8000) * (cycle_timer >> 25); 1795 1796 return ticks; 1797 } 1798 1799 /* 1800 * Some controllers exhibit one or more of the following bugs when updating the 1801 * iso cycle timer register: 1802 * - When the lowest six bits are wrapping around to zero, a read that happens 1803 * at the same time will return garbage in the lowest ten bits. 1804 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1805 * not incremented for about 60 ns. 1806 * - Occasionally, the entire register reads zero. 1807 * 1808 * To catch these, we read the register three times and ensure that the 1809 * difference between each two consecutive reads is approximately the same, i.e. 1810 * less than twice the other. Furthermore, any negative difference indicates an 1811 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1812 * execute, so we have enough precision to compute the ratio of the differences.) 1813 */ 1814 static u32 get_cycle_time(struct fw_ohci *ohci) 1815 { 1816 u32 c0, c1, c2; 1817 u32 t0, t1, t2; 1818 s32 diff01, diff12; 1819 int i; 1820 1821 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1822 return 0; 1823 1824 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1825 1826 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1827 i = 0; 1828 c1 = c2; 1829 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1830 do { 1831 c0 = c1; 1832 c1 = c2; 1833 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1834 t0 = cycle_timer_ticks(c0); 1835 t1 = cycle_timer_ticks(c1); 1836 t2 = cycle_timer_ticks(c2); 1837 diff01 = t1 - t0; 1838 diff12 = t2 - t1; 1839 } while ((diff01 <= 0 || diff12 <= 0 || 1840 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1841 && i++ < 20); 1842 } 1843 1844 return c2; 1845 } 1846 1847 /* 1848 * This function has to be called at least every 64 seconds. The bus_time 1849 * field stores not only the upper 25 bits of the BUS_TIME register but also 1850 * the most significant bit of the cycle timer in bit 6 so that we can detect 1851 * changes in this bit. 1852 */ 1853 static u32 update_bus_time(struct fw_ohci *ohci) 1854 { 1855 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1856 1857 if (unlikely(!ohci->bus_time_running)) { 1858 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1859 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1860 (cycle_time_seconds & 0x40); 1861 ohci->bus_time_running = true; 1862 } 1863 1864 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1865 ohci->bus_time += 0x40; 1866 1867 return ohci->bus_time | cycle_time_seconds; 1868 } 1869 1870 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1871 enum phy_packet_self_id_port_status *status) 1872 { 1873 int reg; 1874 1875 scoped_guard(mutex, &ohci->phy_reg_mutex) { 1876 reg = write_phy_reg(ohci, 7, port_index); 1877 if (reg < 0) 1878 return reg; 1879 1880 reg = read_phy_reg(ohci, 8); 1881 if (reg < 0) 1882 return reg; 1883 } 1884 1885 switch (reg & 0x0f) { 1886 case 0x06: 1887 // is child node (connected to parent node) 1888 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1889 break; 1890 case 0x0e: 1891 // is parent node (connected to child node) 1892 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1893 break; 1894 default: 1895 // not connected 1896 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1897 break; 1898 } 1899 1900 return 0; 1901 } 1902 1903 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1904 int self_id_count) 1905 { 1906 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1907 int i; 1908 1909 for (i = 0; i < self_id_count; i++) { 1910 u32 entry = ohci->self_id_buffer[i]; 1911 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1912 1913 if (left_phy_id == right_phy_id) 1914 return -1; 1915 if (left_phy_id < right_phy_id) 1916 return i; 1917 } 1918 return i; 1919 } 1920 1921 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset) 1922 { 1923 int reg; 1924 1925 guard(mutex)(&ohci->phy_reg_mutex); 1926 1927 // Select page 7 1928 reg = write_phy_reg(ohci, 7, 0xe0); 1929 if (reg < 0) 1930 return reg; 1931 1932 reg = read_phy_reg(ohci, 8); 1933 if (reg < 0) 1934 return reg; 1935 1936 // set PMODE bit 1937 reg |= 0x40; 1938 reg = write_phy_reg(ohci, 8, reg); 1939 if (reg < 0) 1940 return reg; 1941 1942 // read register 12 1943 reg = read_phy_reg(ohci, 12); 1944 if (reg < 0) 1945 return reg; 1946 1947 // bit 3 indicates "initiated reset" 1948 *is_initiated_reset = !!((reg & 0x08) == 0x08); 1949 1950 return 0; 1951 } 1952 1953 /* 1954 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1955 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1956 * Construct the selfID from phy register contents. 1957 */ 1958 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1959 { 1960 int reg, i, pos, err; 1961 bool is_initiated_reset; 1962 u32 self_id = 0; 1963 1964 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 1965 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 1966 phy_packet_self_id_zero_set_link_active(&self_id, true); 1967 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 1968 phy_packet_self_id_zero_set_contender(&self_id, true); 1969 1970 reg = reg_read(ohci, OHCI1394_NodeID); 1971 if (!(reg & OHCI1394_NodeID_idValid)) { 1972 ohci_notice(ohci, 1973 "node ID not valid, new bus reset in progress\n"); 1974 return -EBUSY; 1975 } 1976 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 1977 1978 reg = ohci_read_phy_reg(&ohci->card, 4); 1979 if (reg < 0) 1980 return reg; 1981 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 1982 1983 reg = ohci_read_phy_reg(&ohci->card, 1); 1984 if (reg < 0) 1985 return reg; 1986 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 1987 1988 for (i = 0; i < 3; i++) { 1989 enum phy_packet_self_id_port_status status; 1990 1991 err = get_status_for_port(ohci, i, &status); 1992 if (err < 0) 1993 return err; 1994 1995 self_id_sequence_set_port_status(&self_id, 1, i, status); 1996 } 1997 1998 err = detect_initiated_reset(ohci, &is_initiated_reset); 1999 if (err < 0) 2000 return err; 2001 phy_packet_self_id_zero_set_initiated_reset(&self_id, is_initiated_reset); 2002 2003 pos = get_self_id_pos(ohci, self_id, self_id_count); 2004 if (pos >= 0) { 2005 memmove(&(ohci->self_id_buffer[pos+1]), 2006 &(ohci->self_id_buffer[pos]), 2007 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2008 ohci->self_id_buffer[pos] = self_id; 2009 self_id_count++; 2010 } 2011 return self_id_count; 2012 } 2013 2014 static void bus_reset_work(struct work_struct *work) 2015 { 2016 struct fw_ohci *ohci = 2017 container_of(work, struct fw_ohci, bus_reset_work); 2018 int self_id_count, generation, new_generation, i, j; 2019 u32 reg, quadlet; 2020 void *free_rom = NULL; 2021 dma_addr_t free_rom_bus = 0; 2022 bool is_new_root; 2023 2024 reg = reg_read(ohci, OHCI1394_NodeID); 2025 if (!(reg & OHCI1394_NodeID_idValid)) { 2026 ohci_notice(ohci, 2027 "node ID not valid, new bus reset in progress\n"); 2028 return; 2029 } 2030 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2031 ohci_notice(ohci, "malconfigured bus\n"); 2032 return; 2033 } 2034 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2035 OHCI1394_NodeID_nodeNumber); 2036 2037 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2038 if (!(ohci->is_root && is_new_root)) 2039 reg_write(ohci, OHCI1394_LinkControlSet, 2040 OHCI1394_LinkControl_cycleMaster); 2041 ohci->is_root = is_new_root; 2042 2043 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2044 if (ohci1394_self_id_count_is_error(reg)) { 2045 ohci_notice(ohci, "self ID receive error\n"); 2046 return; 2047 } 2048 /* 2049 * The count in the SelfIDCount register is the number of 2050 * bytes in the self ID receive buffer. Since we also receive 2051 * the inverted quadlets and a header quadlet, we shift one 2052 * bit extra to get the actual number of self IDs. 2053 */ 2054 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2055 2056 if (self_id_count > 252) { 2057 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2058 return; 2059 } 2060 2061 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2062 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2063 rmb(); 2064 2065 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2066 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2067 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2068 2069 if (id != ~id2) { 2070 /* 2071 * If the invalid data looks like a cycle start packet, 2072 * it's likely to be the result of the cycle master 2073 * having a wrong gap count. In this case, the self IDs 2074 * so far are valid and should be processed so that the 2075 * bus manager can then correct the gap count. 2076 */ 2077 if (id == 0xffff008f) { 2078 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2079 self_id_count = j; 2080 break; 2081 } 2082 2083 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2084 j, self_id_count, id, id2); 2085 return; 2086 } 2087 ohci->self_id_buffer[j] = id; 2088 } 2089 2090 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2091 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2092 if (self_id_count < 0) { 2093 ohci_notice(ohci, 2094 "could not construct local self ID\n"); 2095 return; 2096 } 2097 } 2098 2099 if (self_id_count == 0) { 2100 ohci_notice(ohci, "no self IDs\n"); 2101 return; 2102 } 2103 rmb(); 2104 2105 /* 2106 * Check the consistency of the self IDs we just read. The 2107 * problem we face is that a new bus reset can start while we 2108 * read out the self IDs from the DMA buffer. If this happens, 2109 * the DMA buffer will be overwritten with new self IDs and we 2110 * will read out inconsistent data. The OHCI specification 2111 * (section 11.2) recommends a technique similar to 2112 * linux/seqlock.h, where we remember the generation of the 2113 * self IDs in the buffer before reading them out and compare 2114 * it to the current generation after reading them out. If 2115 * the two generations match we know we have a consistent set 2116 * of self IDs. 2117 */ 2118 2119 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2120 new_generation = ohci1394_self_id_count_get_generation(reg); 2121 if (new_generation != generation) { 2122 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2123 return; 2124 } 2125 2126 // FIXME: Document how the locking works. 2127 scoped_guard(spinlock_irq, &ohci->lock) { 2128 ohci->generation = -1; // prevent AT packet queueing 2129 context_stop(&ohci->at_request_ctx); 2130 context_stop(&ohci->at_response_ctx); 2131 } 2132 2133 /* 2134 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2135 * packets in the AT queues and software needs to drain them. 2136 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2137 */ 2138 at_context_flush(&ohci->at_request_ctx); 2139 at_context_flush(&ohci->at_response_ctx); 2140 2141 scoped_guard(spinlock_irq, &ohci->lock) { 2142 ohci->generation = generation; 2143 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2144 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2145 2146 if (ohci->quirks & QUIRK_RESET_PACKET) 2147 ohci->request_generation = generation; 2148 2149 // This next bit is unrelated to the AT context stuff but we have to do it under the 2150 // spinlock also. If a new config rom was set up before this reset, the old one is 2151 // now no longer in use and we can free it. Update the config rom pointers to point 2152 // to the current config rom and clear the next_config_rom pointer so a new update 2153 // can take place. 2154 if (ohci->next_config_rom != NULL) { 2155 if (ohci->next_config_rom != ohci->config_rom) { 2156 free_rom = ohci->config_rom; 2157 free_rom_bus = ohci->config_rom_bus; 2158 } 2159 ohci->config_rom = ohci->next_config_rom; 2160 ohci->config_rom_bus = ohci->next_config_rom_bus; 2161 ohci->next_config_rom = NULL; 2162 2163 // Restore config_rom image and manually update config_rom registers. 2164 // Writing the header quadlet will indicate that the config rom is ready, 2165 // so we do that last. 2166 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); 2167 ohci->config_rom[0] = ohci->next_header; 2168 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header)); 2169 } 2170 2171 if (param_remote_dma) { 2172 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2173 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2174 } 2175 } 2176 2177 if (free_rom) 2178 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2179 2180 log_selfids(ohci, generation, self_id_count); 2181 2182 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2183 self_id_count, ohci->self_id_buffer, 2184 ohci->csr_state_setclear_abdicate); 2185 ohci->csr_state_setclear_abdicate = false; 2186 } 2187 2188 static irqreturn_t irq_handler(int irq, void *data) 2189 { 2190 struct fw_ohci *ohci = data; 2191 u32 event, iso_event; 2192 int i; 2193 2194 event = reg_read(ohci, OHCI1394_IntEventClear); 2195 2196 if (!event || !~event) 2197 return IRQ_NONE; 2198 2199 if (unlikely(param_debug > 0)) { 2200 dev_notice_ratelimited(ohci->card.device, 2201 "The debug parameter is superceded by tracepoints events, and deprecated."); 2202 } 2203 2204 /* 2205 * busReset and postedWriteErr events must not be cleared yet 2206 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2207 */ 2208 reg_write(ohci, OHCI1394_IntEventClear, 2209 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2210 trace_irqs(ohci->card.index, event); 2211 log_irqs(ohci, event); 2212 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2213 if (event & OHCI1394_busReset) 2214 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2215 2216 if (event & OHCI1394_selfIDComplete) { 2217 if (trace_self_id_complete_enabled()) { 2218 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2219 2220 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2221 has_be_header_quirk(ohci)); 2222 } 2223 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2224 } 2225 2226 if (event & OHCI1394_RQPkt) 2227 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2228 2229 if (event & OHCI1394_RSPkt) 2230 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2231 2232 if (event & OHCI1394_reqTxComplete) 2233 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2234 2235 if (event & OHCI1394_respTxComplete) 2236 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2237 2238 if (event & OHCI1394_isochRx) { 2239 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2240 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2241 2242 while (iso_event) { 2243 i = ffs(iso_event) - 1; 2244 fw_iso_context_schedule_flush_completions(&ohci->ir_context_list[i].base); 2245 iso_event &= ~(1 << i); 2246 } 2247 } 2248 2249 if (event & OHCI1394_isochTx) { 2250 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2251 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2252 2253 while (iso_event) { 2254 i = ffs(iso_event) - 1; 2255 fw_iso_context_schedule_flush_completions(&ohci->it_context_list[i].base); 2256 iso_event &= ~(1 << i); 2257 } 2258 } 2259 2260 if (unlikely(event & OHCI1394_regAccessFail)) 2261 ohci_err(ohci, "register access failure\n"); 2262 2263 if (unlikely(event & OHCI1394_postedWriteErr)) { 2264 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2265 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2266 reg_write(ohci, OHCI1394_IntEventClear, 2267 OHCI1394_postedWriteErr); 2268 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n"); 2269 } 2270 2271 if (unlikely(event & OHCI1394_cycleTooLong)) { 2272 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n"); 2273 reg_write(ohci, OHCI1394_LinkControlSet, 2274 OHCI1394_LinkControl_cycleMaster); 2275 } 2276 2277 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2278 /* 2279 * We need to clear this event bit in order to make 2280 * cycleMatch isochronous I/O work. In theory we should 2281 * stop active cycleMatch iso contexts now and restart 2282 * them at least two cycles later. (FIXME?) 2283 */ 2284 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n"); 2285 } 2286 2287 if (unlikely(event & OHCI1394_unrecoverableError)) 2288 handle_dead_contexts(ohci); 2289 2290 if (event & OHCI1394_cycle64Seconds) { 2291 guard(spinlock)(&ohci->lock); 2292 update_bus_time(ohci); 2293 } else 2294 flush_writes(ohci); 2295 2296 return IRQ_HANDLED; 2297 } 2298 2299 static int software_reset(struct fw_ohci *ohci) 2300 { 2301 u32 val; 2302 int i; 2303 2304 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2305 for (i = 0; i < 500; i++) { 2306 val = reg_read(ohci, OHCI1394_HCControlSet); 2307 if (!~val) 2308 return -ENODEV; /* Card was ejected. */ 2309 2310 if (!(val & OHCI1394_HCControl_softReset)) 2311 return 0; 2312 2313 msleep(1); 2314 } 2315 2316 return -EBUSY; 2317 } 2318 2319 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2320 { 2321 size_t size = length * 4; 2322 2323 memcpy(dest, src, size); 2324 if (size < CONFIG_ROM_SIZE) 2325 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2326 } 2327 2328 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2329 { 2330 bool enable_1394a; 2331 int ret, clear, set, offset; 2332 2333 /* Check if the driver should configure link and PHY. */ 2334 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2335 OHCI1394_HCControl_programPhyEnable)) 2336 return 0; 2337 2338 /* Paranoia: check whether the PHY supports 1394a, too. */ 2339 enable_1394a = false; 2340 ret = read_phy_reg(ohci, 2); 2341 if (ret < 0) 2342 return ret; 2343 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2344 ret = read_paged_phy_reg(ohci, 1, 8); 2345 if (ret < 0) 2346 return ret; 2347 if (ret >= 1) 2348 enable_1394a = true; 2349 } 2350 2351 if (ohci->quirks & QUIRK_NO_1394A) 2352 enable_1394a = false; 2353 2354 /* Configure PHY and link consistently. */ 2355 if (enable_1394a) { 2356 clear = 0; 2357 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2358 } else { 2359 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2360 set = 0; 2361 } 2362 ret = update_phy_reg(ohci, 5, clear, set); 2363 if (ret < 0) 2364 return ret; 2365 2366 if (enable_1394a) 2367 offset = OHCI1394_HCControlSet; 2368 else 2369 offset = OHCI1394_HCControlClear; 2370 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2371 2372 /* Clean up: configuration has been taken care of. */ 2373 reg_write(ohci, OHCI1394_HCControlClear, 2374 OHCI1394_HCControl_programPhyEnable); 2375 2376 return 0; 2377 } 2378 2379 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2380 { 2381 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2382 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2383 int reg, i; 2384 2385 reg = read_phy_reg(ohci, 2); 2386 if (reg < 0) 2387 return reg; 2388 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2389 return 0; 2390 2391 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2392 reg = read_paged_phy_reg(ohci, 1, i + 10); 2393 if (reg < 0) 2394 return reg; 2395 if (reg != id[i]) 2396 return 0; 2397 } 2398 return 1; 2399 } 2400 2401 static int ohci_enable(struct fw_card *card, 2402 const __be32 *config_rom, size_t length) 2403 { 2404 struct fw_ohci *ohci = fw_ohci(card); 2405 u32 lps, version, irqs; 2406 int i, ret; 2407 2408 ret = software_reset(ohci); 2409 if (ret < 0) { 2410 ohci_err(ohci, "failed to reset ohci card\n"); 2411 return ret; 2412 } 2413 2414 /* 2415 * Now enable LPS, which we need in order to start accessing 2416 * most of the registers. In fact, on some cards (ALI M5251), 2417 * accessing registers in the SClk domain without LPS enabled 2418 * will lock up the machine. Wait 50msec to make sure we have 2419 * full link enabled. However, with some cards (well, at least 2420 * a JMicron PCIe card), we have to try again sometimes. 2421 * 2422 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2423 * cannot actually use the phy at that time. These need tens of 2424 * millisecods pause between LPS write and first phy access too. 2425 */ 2426 2427 reg_write(ohci, OHCI1394_HCControlSet, 2428 OHCI1394_HCControl_LPS | 2429 OHCI1394_HCControl_postedWriteEnable); 2430 flush_writes(ohci); 2431 2432 for (lps = 0, i = 0; !lps && i < 3; i++) { 2433 msleep(50); 2434 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2435 OHCI1394_HCControl_LPS; 2436 } 2437 2438 if (!lps) { 2439 ohci_err(ohci, "failed to set Link Power Status\n"); 2440 return -EIO; 2441 } 2442 2443 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2444 ret = probe_tsb41ba3d(ohci); 2445 if (ret < 0) 2446 return ret; 2447 if (ret) 2448 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2449 else 2450 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2451 } 2452 2453 reg_write(ohci, OHCI1394_HCControlClear, 2454 OHCI1394_HCControl_noByteSwapData); 2455 2456 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2457 reg_write(ohci, OHCI1394_LinkControlSet, 2458 OHCI1394_LinkControl_cycleTimerEnable | 2459 OHCI1394_LinkControl_cycleMaster); 2460 2461 reg_write(ohci, OHCI1394_ATRetries, 2462 OHCI1394_MAX_AT_REQ_RETRIES | 2463 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2464 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2465 (200 << 16)); 2466 2467 ohci->bus_time_running = false; 2468 2469 for (i = 0; i < 32; i++) 2470 if (ohci->ir_context_support & (1 << i)) 2471 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2472 IR_CONTEXT_MULTI_CHANNEL_MODE); 2473 2474 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2475 if (version >= OHCI_VERSION_1_1) { 2476 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2477 0xfffffffe); 2478 card->broadcast_channel_auto_allocated = true; 2479 } 2480 2481 /* Get implemented bits of the priority arbitration request counter. */ 2482 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2483 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2484 reg_write(ohci, OHCI1394_FairnessControl, 0); 2485 card->priority_budget_implemented = ohci->pri_req_max != 0; 2486 2487 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2488 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2489 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2490 2491 ret = configure_1394a_enhancements(ohci); 2492 if (ret < 0) 2493 return ret; 2494 2495 /* Activate link_on bit and contender bit in our self ID packets.*/ 2496 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2497 if (ret < 0) 2498 return ret; 2499 2500 /* 2501 * When the link is not yet enabled, the atomic config rom 2502 * update mechanism described below in ohci_set_config_rom() 2503 * is not active. We have to update ConfigRomHeader and 2504 * BusOptions manually, and the write to ConfigROMmap takes 2505 * effect immediately. We tie this to the enabling of the 2506 * link, so we have a valid config rom before enabling - the 2507 * OHCI requires that ConfigROMhdr and BusOptions have valid 2508 * values before enabling. 2509 * 2510 * However, when the ConfigROMmap is written, some controllers 2511 * always read back quadlets 0 and 2 from the config rom to 2512 * the ConfigRomHeader and BusOptions registers on bus reset. 2513 * They shouldn't do that in this initial case where the link 2514 * isn't enabled. This means we have to use the same 2515 * workaround here, setting the bus header to 0 and then write 2516 * the right values in the bus reset tasklet. 2517 */ 2518 2519 if (config_rom) { 2520 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2521 &ohci->next_config_rom_bus, GFP_KERNEL); 2522 if (ohci->next_config_rom == NULL) 2523 return -ENOMEM; 2524 2525 copy_config_rom(ohci->next_config_rom, config_rom, length); 2526 } else { 2527 /* 2528 * In the suspend case, config_rom is NULL, which 2529 * means that we just reuse the old config rom. 2530 */ 2531 ohci->next_config_rom = ohci->config_rom; 2532 ohci->next_config_rom_bus = ohci->config_rom_bus; 2533 } 2534 2535 ohci->next_header = ohci->next_config_rom[0]; 2536 ohci->next_config_rom[0] = 0; 2537 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2538 reg_write(ohci, OHCI1394_BusOptions, 2539 be32_to_cpu(ohci->next_config_rom[2])); 2540 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2541 2542 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2543 2544 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2545 OHCI1394_RQPkt | OHCI1394_RSPkt | 2546 OHCI1394_isochTx | OHCI1394_isochRx | 2547 OHCI1394_postedWriteErr | 2548 OHCI1394_selfIDComplete | 2549 OHCI1394_regAccessFail | 2550 OHCI1394_cycleInconsistent | 2551 OHCI1394_unrecoverableError | 2552 OHCI1394_cycleTooLong | 2553 OHCI1394_masterIntEnable | 2554 OHCI1394_busReset; 2555 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2556 2557 reg_write(ohci, OHCI1394_HCControlSet, 2558 OHCI1394_HCControl_linkEnable | 2559 OHCI1394_HCControl_BIBimageValid); 2560 2561 reg_write(ohci, OHCI1394_LinkControlSet, 2562 OHCI1394_LinkControl_rcvSelfID | 2563 OHCI1394_LinkControl_rcvPhyPkt); 2564 2565 ar_context_run(&ohci->ar_request_ctx); 2566 ar_context_run(&ohci->ar_response_ctx); 2567 2568 flush_writes(ohci); 2569 2570 /* We are ready to go, reset bus to finish initialization. */ 2571 fw_schedule_bus_reset(&ohci->card, false, true); 2572 2573 return 0; 2574 } 2575 2576 static int ohci_set_config_rom(struct fw_card *card, 2577 const __be32 *config_rom, size_t length) 2578 { 2579 struct fw_ohci *ohci; 2580 __be32 *next_config_rom; 2581 dma_addr_t next_config_rom_bus; 2582 2583 ohci = fw_ohci(card); 2584 2585 /* 2586 * When the OHCI controller is enabled, the config rom update 2587 * mechanism is a bit tricky, but easy enough to use. See 2588 * section 5.5.6 in the OHCI specification. 2589 * 2590 * The OHCI controller caches the new config rom address in a 2591 * shadow register (ConfigROMmapNext) and needs a bus reset 2592 * for the changes to take place. When the bus reset is 2593 * detected, the controller loads the new values for the 2594 * ConfigRomHeader and BusOptions registers from the specified 2595 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2596 * shadow register. All automatically and atomically. 2597 * 2598 * Now, there's a twist to this story. The automatic load of 2599 * ConfigRomHeader and BusOptions doesn't honor the 2600 * noByteSwapData bit, so with a be32 config rom, the 2601 * controller will load be32 values in to these registers 2602 * during the atomic update, even on litte endian 2603 * architectures. The workaround we use is to put a 0 in the 2604 * header quadlet; 0 is endian agnostic and means that the 2605 * config rom isn't ready yet. In the bus reset tasklet we 2606 * then set up the real values for the two registers. 2607 * 2608 * We use ohci->lock to avoid racing with the code that sets 2609 * ohci->next_config_rom to NULL (see bus_reset_work). 2610 */ 2611 2612 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2613 &next_config_rom_bus, GFP_KERNEL); 2614 if (next_config_rom == NULL) 2615 return -ENOMEM; 2616 2617 scoped_guard(spinlock_irq, &ohci->lock) { 2618 // If there is not an already pending config_rom update, push our new allocation 2619 // into the ohci->next_config_rom and then mark the local variable as null so that 2620 // we won't deallocate the new buffer. 2621 // 2622 // OTOH, if there is a pending config_rom update, just use that buffer with the new 2623 // config_rom data, and let this routine free the unused DMA allocation. 2624 if (ohci->next_config_rom == NULL) { 2625 ohci->next_config_rom = next_config_rom; 2626 ohci->next_config_rom_bus = next_config_rom_bus; 2627 next_config_rom = NULL; 2628 } 2629 2630 copy_config_rom(ohci->next_config_rom, config_rom, length); 2631 2632 ohci->next_header = config_rom[0]; 2633 ohci->next_config_rom[0] = 0; 2634 2635 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2636 } 2637 2638 /* If we didn't use the DMA allocation, delete it. */ 2639 if (next_config_rom != NULL) { 2640 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2641 next_config_rom_bus); 2642 } 2643 2644 /* 2645 * Now initiate a bus reset to have the changes take 2646 * effect. We clean up the old config rom memory and DMA 2647 * mappings in the bus reset tasklet, since the OHCI 2648 * controller could need to access it before the bus reset 2649 * takes effect. 2650 */ 2651 2652 fw_schedule_bus_reset(&ohci->card, true, true); 2653 2654 return 0; 2655 } 2656 2657 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2658 { 2659 struct fw_ohci *ohci = fw_ohci(card); 2660 2661 at_context_transmit(&ohci->at_request_ctx, packet); 2662 } 2663 2664 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2665 { 2666 struct fw_ohci *ohci = fw_ohci(card); 2667 2668 at_context_transmit(&ohci->at_response_ctx, packet); 2669 } 2670 2671 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2672 { 2673 struct fw_ohci *ohci = fw_ohci(card); 2674 struct context *ctx = &ohci->at_request_ctx; 2675 struct driver_data *driver_data = packet->driver_data; 2676 int ret = -ENOENT; 2677 2678 tasklet_disable_in_atomic(&ctx->tasklet); 2679 2680 if (packet->ack != 0) 2681 goto out; 2682 2683 if (packet->payload_mapped) 2684 dma_unmap_single(ohci->card.device, packet->payload_bus, 2685 packet->payload_length, DMA_TO_DEVICE); 2686 2687 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2688 driver_data->packet = NULL; 2689 packet->ack = RCODE_CANCELLED; 2690 2691 // Timestamping on behalf of the hardware. 2692 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2693 2694 packet->callback(packet, &ohci->card, packet->ack); 2695 ret = 0; 2696 out: 2697 tasklet_enable(&ctx->tasklet); 2698 2699 return ret; 2700 } 2701 2702 static int ohci_enable_phys_dma(struct fw_card *card, 2703 int node_id, int generation) 2704 { 2705 struct fw_ohci *ohci = fw_ohci(card); 2706 int n, ret = 0; 2707 2708 if (param_remote_dma) 2709 return 0; 2710 2711 /* 2712 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2713 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2714 */ 2715 2716 guard(spinlock_irqsave)(&ohci->lock); 2717 2718 if (ohci->generation != generation) 2719 return -ESTALE; 2720 2721 /* 2722 * Note, if the node ID contains a non-local bus ID, physical DMA is 2723 * enabled for _all_ nodes on remote buses. 2724 */ 2725 2726 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2727 if (n < 32) 2728 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2729 else 2730 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2731 2732 flush_writes(ohci); 2733 2734 return ret; 2735 } 2736 2737 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2738 { 2739 struct fw_ohci *ohci = fw_ohci(card); 2740 u32 value; 2741 2742 switch (csr_offset) { 2743 case CSR_STATE_CLEAR: 2744 case CSR_STATE_SET: 2745 if (ohci->is_root && 2746 (reg_read(ohci, OHCI1394_LinkControlSet) & 2747 OHCI1394_LinkControl_cycleMaster)) 2748 value = CSR_STATE_BIT_CMSTR; 2749 else 2750 value = 0; 2751 if (ohci->csr_state_setclear_abdicate) 2752 value |= CSR_STATE_BIT_ABDICATE; 2753 2754 return value; 2755 2756 case CSR_NODE_IDS: 2757 return reg_read(ohci, OHCI1394_NodeID) << 16; 2758 2759 case CSR_CYCLE_TIME: 2760 return get_cycle_time(ohci); 2761 2762 case CSR_BUS_TIME: 2763 { 2764 // We might be called just after the cycle timer has wrapped around but just before 2765 // the cycle64Seconds handler, so we better check here, too, if the bus time needs 2766 // to be updated. 2767 2768 guard(spinlock_irqsave)(&ohci->lock); 2769 return update_bus_time(ohci); 2770 } 2771 case CSR_BUSY_TIMEOUT: 2772 value = reg_read(ohci, OHCI1394_ATRetries); 2773 return (value >> 4) & 0x0ffff00f; 2774 2775 case CSR_PRIORITY_BUDGET: 2776 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2777 (ohci->pri_req_max << 8); 2778 2779 default: 2780 WARN_ON(1); 2781 return 0; 2782 } 2783 } 2784 2785 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2786 { 2787 struct fw_ohci *ohci = fw_ohci(card); 2788 2789 switch (csr_offset) { 2790 case CSR_STATE_CLEAR: 2791 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2792 reg_write(ohci, OHCI1394_LinkControlClear, 2793 OHCI1394_LinkControl_cycleMaster); 2794 flush_writes(ohci); 2795 } 2796 if (value & CSR_STATE_BIT_ABDICATE) 2797 ohci->csr_state_setclear_abdicate = false; 2798 break; 2799 2800 case CSR_STATE_SET: 2801 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2802 reg_write(ohci, OHCI1394_LinkControlSet, 2803 OHCI1394_LinkControl_cycleMaster); 2804 flush_writes(ohci); 2805 } 2806 if (value & CSR_STATE_BIT_ABDICATE) 2807 ohci->csr_state_setclear_abdicate = true; 2808 break; 2809 2810 case CSR_NODE_IDS: 2811 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2812 flush_writes(ohci); 2813 break; 2814 2815 case CSR_CYCLE_TIME: 2816 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2817 reg_write(ohci, OHCI1394_IntEventSet, 2818 OHCI1394_cycleInconsistent); 2819 flush_writes(ohci); 2820 break; 2821 2822 case CSR_BUS_TIME: 2823 { 2824 guard(spinlock_irqsave)(&ohci->lock); 2825 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); 2826 break; 2827 } 2828 case CSR_BUSY_TIMEOUT: 2829 value = (value & 0xf) | ((value & 0xf) << 4) | 2830 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2831 reg_write(ohci, OHCI1394_ATRetries, value); 2832 flush_writes(ohci); 2833 break; 2834 2835 case CSR_PRIORITY_BUDGET: 2836 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2837 flush_writes(ohci); 2838 break; 2839 2840 default: 2841 WARN_ON(1); 2842 break; 2843 } 2844 } 2845 2846 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2847 { 2848 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2849 ctx->header_length); 2850 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2851 ctx->header_length); 2852 2853 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2854 ctx->header_length, ctx->header, 2855 ctx->base.callback_data); 2856 ctx->header_length = 0; 2857 } 2858 2859 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2860 { 2861 u32 *ctx_hdr; 2862 2863 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2864 if (ctx->base.drop_overflow_headers) 2865 return; 2866 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2867 } 2868 2869 ctx_hdr = ctx->header + ctx->header_length; 2870 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2871 2872 /* 2873 * The two iso header quadlets are byteswapped to little 2874 * endian by the controller, but we want to present them 2875 * as big endian for consistency with the bus endianness. 2876 */ 2877 if (ctx->base.header_size > 0) 2878 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2879 if (ctx->base.header_size > 4) 2880 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2881 if (ctx->base.header_size > 8) 2882 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2883 ctx->header_length += ctx->base.header_size; 2884 } 2885 2886 static int handle_ir_packet_per_buffer(struct context *context, 2887 struct descriptor *d, 2888 struct descriptor *last) 2889 { 2890 struct iso_context *ctx = 2891 container_of(context, struct iso_context, context); 2892 struct descriptor *pd; 2893 u32 buffer_dma; 2894 2895 for (pd = d; pd <= last; pd++) 2896 if (pd->transfer_status) 2897 break; 2898 if (pd > last) 2899 /* Descriptor(s) not done yet, stop iteration */ 2900 return 0; 2901 2902 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2903 d++; 2904 buffer_dma = le32_to_cpu(d->data_address); 2905 dma_sync_single_range_for_cpu(context->ohci->card.device, 2906 buffer_dma & PAGE_MASK, 2907 buffer_dma & ~PAGE_MASK, 2908 le16_to_cpu(d->req_count), 2909 DMA_FROM_DEVICE); 2910 } 2911 2912 copy_iso_headers(ctx, (u32 *) (last + 1)); 2913 2914 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2915 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2916 2917 return 1; 2918 } 2919 2920 /* d == last because each descriptor block is only a single descriptor. */ 2921 static int handle_ir_buffer_fill(struct context *context, 2922 struct descriptor *d, 2923 struct descriptor *last) 2924 { 2925 struct iso_context *ctx = 2926 container_of(context, struct iso_context, context); 2927 unsigned int req_count, res_count, completed; 2928 u32 buffer_dma; 2929 2930 req_count = le16_to_cpu(last->req_count); 2931 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2932 completed = req_count - res_count; 2933 buffer_dma = le32_to_cpu(last->data_address); 2934 2935 if (completed > 0) { 2936 ctx->mc_buffer_bus = buffer_dma; 2937 ctx->mc_completed = completed; 2938 } 2939 2940 if (res_count != 0) 2941 /* Descriptor(s) not done yet, stop iteration */ 2942 return 0; 2943 2944 dma_sync_single_range_for_cpu(context->ohci->card.device, 2945 buffer_dma & PAGE_MASK, 2946 buffer_dma & ~PAGE_MASK, 2947 completed, DMA_FROM_DEVICE); 2948 2949 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2950 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2951 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2952 2953 ctx->base.callback.mc(&ctx->base, 2954 buffer_dma + completed, 2955 ctx->base.callback_data); 2956 ctx->mc_completed = 0; 2957 } 2958 2959 return 1; 2960 } 2961 2962 static void flush_ir_buffer_fill(struct iso_context *ctx) 2963 { 2964 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2965 ctx->mc_buffer_bus & PAGE_MASK, 2966 ctx->mc_buffer_bus & ~PAGE_MASK, 2967 ctx->mc_completed, DMA_FROM_DEVICE); 2968 2969 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 2970 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 2971 2972 ctx->base.callback.mc(&ctx->base, 2973 ctx->mc_buffer_bus + ctx->mc_completed, 2974 ctx->base.callback_data); 2975 ctx->mc_completed = 0; 2976 } 2977 2978 static inline void sync_it_packet_for_cpu(struct context *context, 2979 struct descriptor *pd) 2980 { 2981 __le16 control; 2982 u32 buffer_dma; 2983 2984 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2985 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2986 return; 2987 2988 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2989 pd += 2; 2990 2991 /* 2992 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2993 * data buffer is in the context program's coherent page and must not 2994 * be synced. 2995 */ 2996 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2997 (context->current_bus & PAGE_MASK)) { 2998 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2999 return; 3000 pd++; 3001 } 3002 3003 do { 3004 buffer_dma = le32_to_cpu(pd->data_address); 3005 dma_sync_single_range_for_cpu(context->ohci->card.device, 3006 buffer_dma & PAGE_MASK, 3007 buffer_dma & ~PAGE_MASK, 3008 le16_to_cpu(pd->req_count), 3009 DMA_TO_DEVICE); 3010 control = pd->control; 3011 pd++; 3012 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3013 } 3014 3015 static int handle_it_packet(struct context *context, 3016 struct descriptor *d, 3017 struct descriptor *last) 3018 { 3019 struct iso_context *ctx = 3020 container_of(context, struct iso_context, context); 3021 struct descriptor *pd; 3022 __be32 *ctx_hdr; 3023 3024 for (pd = d; pd <= last; pd++) 3025 if (pd->transfer_status) 3026 break; 3027 if (pd > last) 3028 /* Descriptor(s) not done yet, stop iteration */ 3029 return 0; 3030 3031 sync_it_packet_for_cpu(context, d); 3032 3033 if (ctx->header_length + 4 > PAGE_SIZE) { 3034 if (ctx->base.drop_overflow_headers) 3035 return 1; 3036 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3037 } 3038 3039 ctx_hdr = ctx->header + ctx->header_length; 3040 ctx->last_timestamp = le16_to_cpu(last->res_count); 3041 /* Present this value as big-endian to match the receive code */ 3042 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3043 le16_to_cpu(pd->res_count)); 3044 ctx->header_length += 4; 3045 3046 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3047 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 3048 3049 return 1; 3050 } 3051 3052 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3053 { 3054 u32 hi = channels >> 32, lo = channels; 3055 3056 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3057 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3058 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3059 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3060 ohci->mc_channels = channels; 3061 } 3062 3063 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3064 int type, int channel, size_t header_size) 3065 { 3066 struct fw_ohci *ohci = fw_ohci(card); 3067 struct iso_context *ctx; 3068 descriptor_callback_t callback; 3069 u64 *channels; 3070 u32 *mask, regs; 3071 int index, ret = -EBUSY; 3072 3073 scoped_guard(spinlock_irq, &ohci->lock) { 3074 switch (type) { 3075 case FW_ISO_CONTEXT_TRANSMIT: 3076 mask = &ohci->it_context_mask; 3077 callback = handle_it_packet; 3078 index = ffs(*mask) - 1; 3079 if (index >= 0) { 3080 *mask &= ~(1 << index); 3081 regs = OHCI1394_IsoXmitContextBase(index); 3082 ctx = &ohci->it_context_list[index]; 3083 } 3084 break; 3085 3086 case FW_ISO_CONTEXT_RECEIVE: 3087 channels = &ohci->ir_context_channels; 3088 mask = &ohci->ir_context_mask; 3089 callback = handle_ir_packet_per_buffer; 3090 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3091 if (index >= 0) { 3092 *channels &= ~(1ULL << channel); 3093 *mask &= ~(1 << index); 3094 regs = OHCI1394_IsoRcvContextBase(index); 3095 ctx = &ohci->ir_context_list[index]; 3096 } 3097 break; 3098 3099 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3100 mask = &ohci->ir_context_mask; 3101 callback = handle_ir_buffer_fill; 3102 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3103 if (index >= 0) { 3104 ohci->mc_allocated = true; 3105 *mask &= ~(1 << index); 3106 regs = OHCI1394_IsoRcvContextBase(index); 3107 ctx = &ohci->ir_context_list[index]; 3108 } 3109 break; 3110 3111 default: 3112 index = -1; 3113 ret = -ENOSYS; 3114 } 3115 3116 if (index < 0) 3117 return ERR_PTR(ret); 3118 } 3119 3120 memset(ctx, 0, sizeof(*ctx)); 3121 ctx->header_length = 0; 3122 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3123 if (ctx->header == NULL) { 3124 ret = -ENOMEM; 3125 goto out; 3126 } 3127 ret = context_init(&ctx->context, ohci, regs, callback); 3128 if (ret < 0) 3129 goto out_with_header; 3130 3131 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3132 set_multichannel_mask(ohci, 0); 3133 ctx->mc_completed = 0; 3134 } 3135 3136 return &ctx->base; 3137 3138 out_with_header: 3139 free_page((unsigned long)ctx->header); 3140 out: 3141 scoped_guard(spinlock_irq, &ohci->lock) { 3142 switch (type) { 3143 case FW_ISO_CONTEXT_RECEIVE: 3144 *channels |= 1ULL << channel; 3145 break; 3146 3147 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3148 ohci->mc_allocated = false; 3149 break; 3150 } 3151 *mask |= 1 << index; 3152 } 3153 3154 return ERR_PTR(ret); 3155 } 3156 3157 static int ohci_start_iso(struct fw_iso_context *base, 3158 s32 cycle, u32 sync, u32 tags) 3159 { 3160 struct iso_context *ctx = container_of(base, struct iso_context, base); 3161 struct fw_ohci *ohci = ctx->context.ohci; 3162 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3163 int index; 3164 3165 /* the controller cannot start without any queued packets */ 3166 if (ctx->context.last->branch_address == 0) 3167 return -ENODATA; 3168 3169 switch (ctx->base.type) { 3170 case FW_ISO_CONTEXT_TRANSMIT: 3171 index = ctx - ohci->it_context_list; 3172 match = 0; 3173 if (cycle >= 0) 3174 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3175 (cycle & 0x7fff) << 16; 3176 3177 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3178 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3179 context_run(&ctx->context, match); 3180 break; 3181 3182 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3183 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3184 fallthrough; 3185 case FW_ISO_CONTEXT_RECEIVE: 3186 index = ctx - ohci->ir_context_list; 3187 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3188 if (cycle >= 0) { 3189 match |= (cycle & 0x07fff) << 12; 3190 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3191 } 3192 3193 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3194 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3195 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3196 context_run(&ctx->context, control); 3197 3198 ctx->sync = sync; 3199 ctx->tags = tags; 3200 3201 break; 3202 } 3203 3204 return 0; 3205 } 3206 3207 static int ohci_stop_iso(struct fw_iso_context *base) 3208 { 3209 struct fw_ohci *ohci = fw_ohci(base->card); 3210 struct iso_context *ctx = container_of(base, struct iso_context, base); 3211 int index; 3212 3213 switch (ctx->base.type) { 3214 case FW_ISO_CONTEXT_TRANSMIT: 3215 index = ctx - ohci->it_context_list; 3216 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3217 break; 3218 3219 case FW_ISO_CONTEXT_RECEIVE: 3220 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3221 index = ctx - ohci->ir_context_list; 3222 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3223 break; 3224 } 3225 flush_writes(ohci); 3226 context_stop(&ctx->context); 3227 3228 return 0; 3229 } 3230 3231 static void ohci_free_iso_context(struct fw_iso_context *base) 3232 { 3233 struct fw_ohci *ohci = fw_ohci(base->card); 3234 struct iso_context *ctx = container_of(base, struct iso_context, base); 3235 int index; 3236 3237 ohci_stop_iso(base); 3238 context_release(&ctx->context); 3239 free_page((unsigned long)ctx->header); 3240 3241 guard(spinlock_irqsave)(&ohci->lock); 3242 3243 switch (base->type) { 3244 case FW_ISO_CONTEXT_TRANSMIT: 3245 index = ctx - ohci->it_context_list; 3246 ohci->it_context_mask |= 1 << index; 3247 break; 3248 3249 case FW_ISO_CONTEXT_RECEIVE: 3250 index = ctx - ohci->ir_context_list; 3251 ohci->ir_context_mask |= 1 << index; 3252 ohci->ir_context_channels |= 1ULL << base->channel; 3253 break; 3254 3255 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3256 index = ctx - ohci->ir_context_list; 3257 ohci->ir_context_mask |= 1 << index; 3258 ohci->ir_context_channels |= ohci->mc_channels; 3259 ohci->mc_channels = 0; 3260 ohci->mc_allocated = false; 3261 break; 3262 } 3263 } 3264 3265 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3266 { 3267 struct fw_ohci *ohci = fw_ohci(base->card); 3268 3269 switch (base->type) { 3270 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3271 { 3272 guard(spinlock_irqsave)(&ohci->lock); 3273 3274 // Don't allow multichannel to grab other contexts' channels. 3275 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3276 *channels = ohci->ir_context_channels; 3277 return -EBUSY; 3278 } else { 3279 set_multichannel_mask(ohci, *channels); 3280 return 0; 3281 } 3282 } 3283 default: 3284 return -EINVAL; 3285 } 3286 } 3287 3288 #ifdef CONFIG_PM 3289 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3290 { 3291 int i; 3292 struct iso_context *ctx; 3293 3294 for (i = 0 ; i < ohci->n_ir ; i++) { 3295 ctx = &ohci->ir_context_list[i]; 3296 if (ctx->context.running) 3297 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3298 } 3299 3300 for (i = 0 ; i < ohci->n_it ; i++) { 3301 ctx = &ohci->it_context_list[i]; 3302 if (ctx->context.running) 3303 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3304 } 3305 } 3306 #endif 3307 3308 static int queue_iso_transmit(struct iso_context *ctx, 3309 struct fw_iso_packet *packet, 3310 struct fw_iso_buffer *buffer, 3311 unsigned long payload) 3312 { 3313 struct descriptor *d, *last, *pd; 3314 struct fw_iso_packet *p; 3315 __le32 *header; 3316 dma_addr_t d_bus, page_bus; 3317 u32 z, header_z, payload_z, irq; 3318 u32 payload_index, payload_end_index, next_page_index; 3319 int page, end_page, i, length, offset; 3320 3321 p = packet; 3322 payload_index = payload; 3323 3324 if (p->skip) 3325 z = 1; 3326 else 3327 z = 2; 3328 if (p->header_length > 0) 3329 z++; 3330 3331 /* Determine the first page the payload isn't contained in. */ 3332 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3333 if (p->payload_length > 0) 3334 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3335 else 3336 payload_z = 0; 3337 3338 z += payload_z; 3339 3340 /* Get header size in number of descriptors. */ 3341 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3342 3343 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3344 if (d == NULL) 3345 return -ENOMEM; 3346 3347 if (!p->skip) { 3348 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3349 d[0].req_count = cpu_to_le16(8); 3350 /* 3351 * Link the skip address to this descriptor itself. This causes 3352 * a context to skip a cycle whenever lost cycles or FIFO 3353 * overruns occur, without dropping the data. The application 3354 * should then decide whether this is an error condition or not. 3355 * FIXME: Make the context's cycle-lost behaviour configurable? 3356 */ 3357 d[0].branch_address = cpu_to_le32(d_bus | z); 3358 3359 header = (__le32 *) &d[1]; 3360 3361 ohci1394_it_data_set_speed(header, ctx->base.speed); 3362 ohci1394_it_data_set_tag(header, p->tag); 3363 ohci1394_it_data_set_channel(header, ctx->base.channel); 3364 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 3365 ohci1394_it_data_set_sync(header, p->sy); 3366 3367 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length); 3368 } 3369 3370 if (p->header_length > 0) { 3371 d[2].req_count = cpu_to_le16(p->header_length); 3372 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3373 memcpy(&d[z], p->header, p->header_length); 3374 } 3375 3376 pd = d + z - payload_z; 3377 payload_end_index = payload_index + p->payload_length; 3378 for (i = 0; i < payload_z; i++) { 3379 page = payload_index >> PAGE_SHIFT; 3380 offset = payload_index & ~PAGE_MASK; 3381 next_page_index = (page + 1) << PAGE_SHIFT; 3382 length = 3383 min(next_page_index, payload_end_index) - payload_index; 3384 pd[i].req_count = cpu_to_le16(length); 3385 3386 page_bus = page_private(buffer->pages[page]); 3387 pd[i].data_address = cpu_to_le32(page_bus + offset); 3388 3389 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3390 page_bus, offset, length, 3391 DMA_TO_DEVICE); 3392 3393 payload_index += length; 3394 } 3395 3396 if (p->interrupt) 3397 irq = DESCRIPTOR_IRQ_ALWAYS; 3398 else 3399 irq = DESCRIPTOR_NO_IRQ; 3400 3401 last = z == 2 ? d : d + z - 1; 3402 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3403 DESCRIPTOR_STATUS | 3404 DESCRIPTOR_BRANCH_ALWAYS | 3405 irq); 3406 3407 context_append(&ctx->context, d, z, header_z); 3408 3409 return 0; 3410 } 3411 3412 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3413 struct fw_iso_packet *packet, 3414 struct fw_iso_buffer *buffer, 3415 unsigned long payload) 3416 { 3417 struct device *device = ctx->context.ohci->card.device; 3418 struct descriptor *d, *pd; 3419 dma_addr_t d_bus, page_bus; 3420 u32 z, header_z, rest; 3421 int i, j, length; 3422 int page, offset, packet_count, header_size, payload_per_buffer; 3423 3424 /* 3425 * The OHCI controller puts the isochronous header and trailer in the 3426 * buffer, so we need at least 8 bytes. 3427 */ 3428 packet_count = packet->header_length / ctx->base.header_size; 3429 header_size = max(ctx->base.header_size, (size_t)8); 3430 3431 /* Get header size in number of descriptors. */ 3432 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3433 page = payload >> PAGE_SHIFT; 3434 offset = payload & ~PAGE_MASK; 3435 payload_per_buffer = packet->payload_length / packet_count; 3436 3437 for (i = 0; i < packet_count; i++) { 3438 /* d points to the header descriptor */ 3439 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3440 d = context_get_descriptors(&ctx->context, 3441 z + header_z, &d_bus); 3442 if (d == NULL) 3443 return -ENOMEM; 3444 3445 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3446 DESCRIPTOR_INPUT_MORE); 3447 if (packet->skip && i == 0) 3448 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3449 d->req_count = cpu_to_le16(header_size); 3450 d->res_count = d->req_count; 3451 d->transfer_status = 0; 3452 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3453 3454 rest = payload_per_buffer; 3455 pd = d; 3456 for (j = 1; j < z; j++) { 3457 pd++; 3458 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3459 DESCRIPTOR_INPUT_MORE); 3460 3461 if (offset + rest < PAGE_SIZE) 3462 length = rest; 3463 else 3464 length = PAGE_SIZE - offset; 3465 pd->req_count = cpu_to_le16(length); 3466 pd->res_count = pd->req_count; 3467 pd->transfer_status = 0; 3468 3469 page_bus = page_private(buffer->pages[page]); 3470 pd->data_address = cpu_to_le32(page_bus + offset); 3471 3472 dma_sync_single_range_for_device(device, page_bus, 3473 offset, length, 3474 DMA_FROM_DEVICE); 3475 3476 offset = (offset + length) & ~PAGE_MASK; 3477 rest -= length; 3478 if (offset == 0) 3479 page++; 3480 } 3481 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3482 DESCRIPTOR_INPUT_LAST | 3483 DESCRIPTOR_BRANCH_ALWAYS); 3484 if (packet->interrupt && i == packet_count - 1) 3485 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3486 3487 context_append(&ctx->context, d, z, header_z); 3488 } 3489 3490 return 0; 3491 } 3492 3493 static int queue_iso_buffer_fill(struct iso_context *ctx, 3494 struct fw_iso_packet *packet, 3495 struct fw_iso_buffer *buffer, 3496 unsigned long payload) 3497 { 3498 struct descriptor *d; 3499 dma_addr_t d_bus, page_bus; 3500 int page, offset, rest, z, i, length; 3501 3502 page = payload >> PAGE_SHIFT; 3503 offset = payload & ~PAGE_MASK; 3504 rest = packet->payload_length; 3505 3506 /* We need one descriptor for each page in the buffer. */ 3507 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3508 3509 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3510 return -EFAULT; 3511 3512 for (i = 0; i < z; i++) { 3513 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3514 if (d == NULL) 3515 return -ENOMEM; 3516 3517 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3518 DESCRIPTOR_BRANCH_ALWAYS); 3519 if (packet->skip && i == 0) 3520 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3521 if (packet->interrupt && i == z - 1) 3522 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3523 3524 if (offset + rest < PAGE_SIZE) 3525 length = rest; 3526 else 3527 length = PAGE_SIZE - offset; 3528 d->req_count = cpu_to_le16(length); 3529 d->res_count = d->req_count; 3530 d->transfer_status = 0; 3531 3532 page_bus = page_private(buffer->pages[page]); 3533 d->data_address = cpu_to_le32(page_bus + offset); 3534 3535 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3536 page_bus, offset, length, 3537 DMA_FROM_DEVICE); 3538 3539 rest -= length; 3540 offset = 0; 3541 page++; 3542 3543 context_append(&ctx->context, d, 1, 0); 3544 } 3545 3546 return 0; 3547 } 3548 3549 static int ohci_queue_iso(struct fw_iso_context *base, 3550 struct fw_iso_packet *packet, 3551 struct fw_iso_buffer *buffer, 3552 unsigned long payload) 3553 { 3554 struct iso_context *ctx = container_of(base, struct iso_context, base); 3555 3556 guard(spinlock_irqsave)(&ctx->context.ohci->lock); 3557 3558 switch (base->type) { 3559 case FW_ISO_CONTEXT_TRANSMIT: 3560 return queue_iso_transmit(ctx, packet, buffer, payload); 3561 case FW_ISO_CONTEXT_RECEIVE: 3562 return queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3563 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3564 return queue_iso_buffer_fill(ctx, packet, buffer, payload); 3565 default: 3566 return -ENOSYS; 3567 } 3568 } 3569 3570 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3571 { 3572 struct context *ctx = 3573 &container_of(base, struct iso_context, base)->context; 3574 3575 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3576 } 3577 3578 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3579 { 3580 struct iso_context *ctx = container_of(base, struct iso_context, base); 3581 3582 // Note that tasklet softIRQ is not used to process isochronous context anymore. 3583 context_tasklet((unsigned long)&ctx->context); 3584 3585 switch (base->type) { 3586 case FW_ISO_CONTEXT_TRANSMIT: 3587 case FW_ISO_CONTEXT_RECEIVE: 3588 if (ctx->header_length != 0) 3589 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3590 return 0; 3591 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3592 if (ctx->mc_completed != 0) 3593 flush_ir_buffer_fill(ctx); 3594 return 0; 3595 default: 3596 return -ENOSYS; 3597 } 3598 } 3599 3600 static const struct fw_card_driver ohci_driver = { 3601 .enable = ohci_enable, 3602 .read_phy_reg = ohci_read_phy_reg, 3603 .update_phy_reg = ohci_update_phy_reg, 3604 .set_config_rom = ohci_set_config_rom, 3605 .send_request = ohci_send_request, 3606 .send_response = ohci_send_response, 3607 .cancel_packet = ohci_cancel_packet, 3608 .enable_phys_dma = ohci_enable_phys_dma, 3609 .read_csr = ohci_read_csr, 3610 .write_csr = ohci_write_csr, 3611 3612 .allocate_iso_context = ohci_allocate_iso_context, 3613 .free_iso_context = ohci_free_iso_context, 3614 .set_iso_channels = ohci_set_iso_channels, 3615 .queue_iso = ohci_queue_iso, 3616 .flush_queue_iso = ohci_flush_queue_iso, 3617 .flush_iso_completions = ohci_flush_iso_completions, 3618 .start_iso = ohci_start_iso, 3619 .stop_iso = ohci_stop_iso, 3620 }; 3621 3622 #ifdef CONFIG_PPC_PMAC 3623 static void pmac_ohci_on(struct pci_dev *dev) 3624 { 3625 if (machine_is(powermac)) { 3626 struct device_node *ofn = pci_device_to_OF_node(dev); 3627 3628 if (ofn) { 3629 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3630 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3631 } 3632 } 3633 } 3634 3635 static void pmac_ohci_off(struct pci_dev *dev) 3636 { 3637 if (machine_is(powermac)) { 3638 struct device_node *ofn = pci_device_to_OF_node(dev); 3639 3640 if (ofn) { 3641 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3642 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3643 } 3644 } 3645 } 3646 #else 3647 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3648 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3649 #endif /* CONFIG_PPC_PMAC */ 3650 3651 static void release_ohci(struct device *dev, void *data) 3652 { 3653 struct pci_dev *pdev = to_pci_dev(dev); 3654 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3655 3656 pmac_ohci_off(pdev); 3657 3658 ar_context_release(&ohci->ar_response_ctx); 3659 ar_context_release(&ohci->ar_request_ctx); 3660 3661 dev_notice(dev, "removed fw-ohci device\n"); 3662 } 3663 3664 static int pci_probe(struct pci_dev *dev, 3665 const struct pci_device_id *ent) 3666 { 3667 struct fw_ohci *ohci; 3668 u32 bus_options, max_receive, link_speed, version; 3669 u64 guid; 3670 int i, flags, irq, err; 3671 size_t size; 3672 3673 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3674 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3675 return -ENOSYS; 3676 } 3677 3678 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3679 if (ohci == NULL) 3680 return -ENOMEM; 3681 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3682 pci_set_drvdata(dev, ohci); 3683 pmac_ohci_on(dev); 3684 devres_add(&dev->dev, ohci); 3685 3686 err = pcim_enable_device(dev); 3687 if (err) { 3688 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3689 return err; 3690 } 3691 3692 pci_set_master(dev); 3693 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3694 3695 spin_lock_init(&ohci->lock); 3696 mutex_init(&ohci->phy_reg_mutex); 3697 3698 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3699 3700 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3701 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3702 ohci_err(ohci, "invalid MMIO resource\n"); 3703 return -ENXIO; 3704 } 3705 3706 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3707 if (err) { 3708 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3709 return -ENXIO; 3710 } 3711 ohci->registers = pcim_iomap_table(dev)[0]; 3712 3713 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3714 if ((ohci_quirks[i].vendor == dev->vendor) && 3715 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3716 ohci_quirks[i].device == dev->device) && 3717 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3718 ohci_quirks[i].revision >= dev->revision)) { 3719 ohci->quirks = ohci_quirks[i].flags; 3720 break; 3721 } 3722 if (param_quirks) 3723 ohci->quirks = param_quirks; 3724 3725 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3726 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3727 3728 /* 3729 * Because dma_alloc_coherent() allocates at least one page, 3730 * we save space by using a common buffer for the AR request/ 3731 * response descriptors and the self IDs buffer. 3732 */ 3733 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3734 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3735 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3736 GFP_KERNEL); 3737 if (!ohci->misc_buffer) 3738 return -ENOMEM; 3739 3740 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3741 OHCI1394_AsReqRcvContextControlSet); 3742 if (err < 0) 3743 return err; 3744 3745 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3746 OHCI1394_AsRspRcvContextControlSet); 3747 if (err < 0) 3748 return err; 3749 3750 err = context_init(&ohci->at_request_ctx, ohci, 3751 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3752 if (err < 0) 3753 return err; 3754 3755 err = context_init(&ohci->at_response_ctx, ohci, 3756 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3757 if (err < 0) 3758 return err; 3759 3760 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3761 ohci->ir_context_channels = ~0ULL; 3762 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3763 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3764 ohci->ir_context_mask = ohci->ir_context_support; 3765 ohci->n_ir = hweight32(ohci->ir_context_mask); 3766 size = sizeof(struct iso_context) * ohci->n_ir; 3767 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3768 if (!ohci->ir_context_list) 3769 return -ENOMEM; 3770 3771 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3772 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3773 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3774 if (!ohci->it_context_support) { 3775 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3776 ohci->it_context_support = 0xf; 3777 } 3778 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3779 ohci->it_context_mask = ohci->it_context_support; 3780 ohci->n_it = hweight32(ohci->it_context_mask); 3781 size = sizeof(struct iso_context) * ohci->n_it; 3782 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3783 if (!ohci->it_context_list) 3784 return -ENOMEM; 3785 3786 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3787 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3788 3789 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3790 max_receive = (bus_options >> 12) & 0xf; 3791 link_speed = bus_options & 0x7; 3792 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3793 reg_read(ohci, OHCI1394_GUIDLo); 3794 3795 flags = PCI_IRQ_INTX; 3796 if (!(ohci->quirks & QUIRK_NO_MSI)) 3797 flags |= PCI_IRQ_MSI; 3798 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3799 if (err < 0) 3800 return err; 3801 irq = pci_irq_vector(dev, 0); 3802 if (irq < 0) { 3803 err = irq; 3804 goto fail_msi; 3805 } 3806 3807 err = request_threaded_irq(irq, irq_handler, NULL, 3808 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3809 ohci); 3810 if (err < 0) { 3811 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3812 goto fail_msi; 3813 } 3814 3815 err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir); 3816 if (err) 3817 goto fail_irq; 3818 3819 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3820 ohci_notice(ohci, 3821 "added OHCI v%x.%x device as card %d, " 3822 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3823 version >> 16, version & 0xff, ohci->card.index, 3824 ohci->n_ir, ohci->n_it, ohci->quirks, 3825 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3826 ", physUB" : ""); 3827 3828 return 0; 3829 3830 fail_irq: 3831 free_irq(irq, ohci); 3832 fail_msi: 3833 pci_free_irq_vectors(dev); 3834 3835 return err; 3836 } 3837 3838 static void pci_remove(struct pci_dev *dev) 3839 { 3840 struct fw_ohci *ohci = pci_get_drvdata(dev); 3841 int irq; 3842 3843 /* 3844 * If the removal is happening from the suspend state, LPS won't be 3845 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3846 */ 3847 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3848 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3849 flush_writes(ohci); 3850 } 3851 cancel_work_sync(&ohci->bus_reset_work); 3852 fw_core_remove_card(&ohci->card); 3853 3854 /* 3855 * FIXME: Fail all pending packets here, now that the upper 3856 * layers can't queue any more. 3857 */ 3858 3859 software_reset(ohci); 3860 3861 irq = pci_irq_vector(dev, 0); 3862 if (irq >= 0) 3863 free_irq(irq, ohci); 3864 pci_free_irq_vectors(dev); 3865 3866 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3867 } 3868 3869 #ifdef CONFIG_PM 3870 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3871 { 3872 struct fw_ohci *ohci = pci_get_drvdata(dev); 3873 int err; 3874 3875 software_reset(ohci); 3876 err = pci_save_state(dev); 3877 if (err) { 3878 ohci_err(ohci, "pci_save_state failed\n"); 3879 return err; 3880 } 3881 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3882 if (err) 3883 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3884 pmac_ohci_off(dev); 3885 3886 return 0; 3887 } 3888 3889 static int pci_resume(struct pci_dev *dev) 3890 { 3891 struct fw_ohci *ohci = pci_get_drvdata(dev); 3892 int err; 3893 3894 pmac_ohci_on(dev); 3895 pci_set_power_state(dev, PCI_D0); 3896 pci_restore_state(dev); 3897 err = pci_enable_device(dev); 3898 if (err) { 3899 ohci_err(ohci, "pci_enable_device failed\n"); 3900 return err; 3901 } 3902 3903 /* Some systems don't setup GUID register on resume from ram */ 3904 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3905 !reg_read(ohci, OHCI1394_GUIDHi)) { 3906 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3907 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3908 } 3909 3910 err = ohci_enable(&ohci->card, NULL, 0); 3911 if (err) 3912 return err; 3913 3914 ohci_resume_iso_dma(ohci); 3915 3916 return 0; 3917 } 3918 #endif 3919 3920 static const struct pci_device_id pci_table[] = { 3921 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3922 { } 3923 }; 3924 3925 MODULE_DEVICE_TABLE(pci, pci_table); 3926 3927 static struct pci_driver fw_ohci_pci_driver = { 3928 .name = ohci_driver_name, 3929 .id_table = pci_table, 3930 .probe = pci_probe, 3931 .remove = pci_remove, 3932 #ifdef CONFIG_PM 3933 .resume = pci_resume, 3934 .suspend = pci_suspend, 3935 #endif 3936 }; 3937 3938 static int __init fw_ohci_init(void) 3939 { 3940 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3941 if (!selfid_workqueue) 3942 return -ENOMEM; 3943 3944 return pci_register_driver(&fw_ohci_pci_driver); 3945 } 3946 3947 static void __exit fw_ohci_cleanup(void) 3948 { 3949 pci_unregister_driver(&fw_ohci_pci_driver); 3950 destroy_workqueue(selfid_workqueue); 3951 } 3952 3953 module_init(fw_ohci_init); 3954 module_exit(fw_ohci_cleanup); 3955 3956 MODULE_AUTHOR("Kristian Hoegsberg <[email protected]>"); 3957 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3958 MODULE_LICENSE("GPL"); 3959 3960 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3961 MODULE_ALIAS("ohci1394"); 3962