1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <[email protected]> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 54 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 55 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 #define DESCRIPTOR_CMD (0xf << 12) 72 73 struct descriptor { 74 __le16 req_count; 75 __le16 control; 76 __le32 data_address; 77 __le32 branch_address; 78 __le16 res_count; 79 __le16 transfer_status; 80 } __attribute__((aligned(16))); 81 82 #define CONTROL_SET(regs) (regs) 83 #define CONTROL_CLEAR(regs) ((regs) + 4) 84 #define COMMAND_PTR(regs) ((regs) + 12) 85 #define CONTEXT_MATCH(regs) ((regs) + 16) 86 87 #define AR_BUFFER_SIZE (32*1024) 88 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 89 /* we need at least two pages for proper list management */ 90 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 91 92 #define MAX_ASYNC_PAYLOAD 4096 93 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 94 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 95 96 struct ar_context { 97 struct fw_ohci *ohci; 98 struct page *pages[AR_BUFFERS]; 99 void *buffer; 100 struct descriptor *descriptors; 101 dma_addr_t descriptors_bus; 102 void *pointer; 103 unsigned int last_buffer_index; 104 u32 regs; 105 struct tasklet_struct tasklet; 106 }; 107 108 struct context; 109 110 typedef int (*descriptor_callback_t)(struct context *ctx, 111 struct descriptor *d, 112 struct descriptor *last); 113 114 /* 115 * A buffer that contains a block of DMA-able coherent memory used for 116 * storing a portion of a DMA descriptor program. 117 */ 118 struct descriptor_buffer { 119 struct list_head list; 120 dma_addr_t buffer_bus; 121 size_t buffer_size; 122 size_t used; 123 struct descriptor buffer[]; 124 }; 125 126 struct context { 127 struct fw_ohci *ohci; 128 u32 regs; 129 int total_allocation; 130 u32 current_bus; 131 bool running; 132 bool flushing; 133 134 /* 135 * List of page-sized buffers for storing DMA descriptors. 136 * Head of list contains buffers in use and tail of list contains 137 * free buffers. 138 */ 139 struct list_head buffer_list; 140 141 /* 142 * Pointer to a buffer inside buffer_list that contains the tail 143 * end of the current DMA program. 144 */ 145 struct descriptor_buffer *buffer_tail; 146 147 /* 148 * The descriptor containing the branch address of the first 149 * descriptor that has not yet been filled by the device. 150 */ 151 struct descriptor *last; 152 153 /* 154 * The last descriptor block in the DMA program. It contains the branch 155 * address that must be updated upon appending a new descriptor. 156 */ 157 struct descriptor *prev; 158 int prev_z; 159 160 descriptor_callback_t callback; 161 162 struct tasklet_struct tasklet; 163 }; 164 165 #define IT_HEADER_SY(v) ((v) << 0) 166 #define IT_HEADER_TCODE(v) ((v) << 4) 167 #define IT_HEADER_CHANNEL(v) ((v) << 8) 168 #define IT_HEADER_TAG(v) ((v) << 14) 169 #define IT_HEADER_SPEED(v) ((v) << 16) 170 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 171 172 struct iso_context { 173 struct fw_iso_context base; 174 struct context context; 175 void *header; 176 size_t header_length; 177 unsigned long flushing_completions; 178 u32 mc_buffer_bus; 179 u16 mc_completed; 180 u16 last_timestamp; 181 u8 sync; 182 u8 tags; 183 }; 184 185 #define CONFIG_ROM_SIZE 1024 186 187 struct fw_ohci { 188 struct fw_card card; 189 190 __iomem char *registers; 191 int node_id; 192 int generation; 193 int request_generation; /* for timestamping incoming requests */ 194 unsigned quirks; 195 unsigned int pri_req_max; 196 u32 bus_time; 197 bool bus_time_running; 198 bool is_root; 199 bool csr_state_setclear_abdicate; 200 int n_ir; 201 int n_it; 202 /* 203 * Spinlock for accessing fw_ohci data. Never call out of 204 * this driver with this lock held. 205 */ 206 spinlock_t lock; 207 208 struct mutex phy_reg_mutex; 209 210 void *misc_buffer; 211 dma_addr_t misc_buffer_bus; 212 213 struct ar_context ar_request_ctx; 214 struct ar_context ar_response_ctx; 215 struct context at_request_ctx; 216 struct context at_response_ctx; 217 218 u32 it_context_support; 219 u32 it_context_mask; /* unoccupied IT contexts */ 220 struct iso_context *it_context_list; 221 u64 ir_context_channels; /* unoccupied channels */ 222 u32 ir_context_support; 223 u32 ir_context_mask; /* unoccupied IR contexts */ 224 struct iso_context *ir_context_list; 225 u64 mc_channels; /* channels in use by the multichannel IR context */ 226 bool mc_allocated; 227 228 __be32 *config_rom; 229 dma_addr_t config_rom_bus; 230 __be32 *next_config_rom; 231 dma_addr_t next_config_rom_bus; 232 __be32 next_header; 233 234 __le32 *self_id; 235 dma_addr_t self_id_bus; 236 struct work_struct bus_reset_work; 237 238 u32 self_id_buffer[512]; 239 }; 240 241 static struct workqueue_struct *selfid_workqueue; 242 243 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 244 { 245 return container_of(card, struct fw_ohci, card); 246 } 247 248 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 249 #define IR_CONTEXT_BUFFER_FILL 0x80000000 250 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 251 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 252 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 253 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 254 255 #define CONTEXT_RUN 0x8000 256 #define CONTEXT_WAKE 0x1000 257 #define CONTEXT_DEAD 0x0800 258 #define CONTEXT_ACTIVE 0x0400 259 260 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 261 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 262 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 263 264 #define OHCI1394_REGISTER_SIZE 0x800 265 #define OHCI1394_PCI_HCI_Control 0x40 266 #define SELF_ID_BUF_SIZE 0x800 267 #define OHCI_VERSION_1_1 0x010010 268 269 static char ohci_driver_name[] = KBUILD_MODNAME; 270 271 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 272 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 273 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 274 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 275 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 276 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 277 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 278 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 279 #define PCI_REV_ID_VIA_VT6306 0x46 280 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 281 282 #define QUIRK_CYCLE_TIMER 0x1 283 #define QUIRK_RESET_PACKET 0x2 284 #define QUIRK_BE_HEADERS 0x4 285 #define QUIRK_NO_1394A 0x8 286 #define QUIRK_NO_MSI 0x10 287 #define QUIRK_TI_SLLZ059 0x20 288 #define QUIRK_IR_WAKE 0x40 289 290 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 291 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 292 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 293 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 294 // while it is probable due to detection of any type of PCIe error. 295 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 296 297 #if IS_ENABLED(CONFIG_X86) 298 299 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 300 { 301 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 302 } 303 304 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 305 306 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 307 { 308 const struct pci_dev *pcie_to_pci_bridge; 309 310 // Detect any type of AMD Ryzen machine. 311 if (!static_cpu_has(X86_FEATURE_ZEN)) 312 return false; 313 314 // Detect VIA VT6306/6307/6308. 315 if (pdev->vendor != PCI_VENDOR_ID_VIA) 316 return false; 317 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 318 return false; 319 320 // Detect Asmedia ASM1083/1085. 321 pcie_to_pci_bridge = pdev->bus->self; 322 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 323 return false; 324 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 325 return false; 326 327 return true; 328 } 329 330 #else 331 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 332 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 333 #endif 334 335 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 336 static const struct { 337 unsigned short vendor, device, revision, flags; 338 } ohci_quirks[] = { 339 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 340 QUIRK_CYCLE_TIMER}, 341 342 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 343 QUIRK_BE_HEADERS}, 344 345 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 346 QUIRK_NO_MSI}, 347 348 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 349 QUIRK_RESET_PACKET}, 350 351 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 352 QUIRK_NO_MSI}, 353 354 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 355 QUIRK_CYCLE_TIMER}, 356 357 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 358 QUIRK_NO_MSI}, 359 360 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 361 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 362 363 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 364 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 365 366 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 367 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 368 369 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 370 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 371 372 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 373 QUIRK_RESET_PACKET}, 374 375 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 376 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 377 378 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 379 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 380 381 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 382 QUIRK_NO_MSI}, 383 384 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 385 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 386 }; 387 388 /* This overrides anything that was found in ohci_quirks[]. */ 389 static int param_quirks; 390 module_param_named(quirks, param_quirks, int, 0644); 391 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 392 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 393 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 394 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 395 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 396 ", disable MSI = " __stringify(QUIRK_NO_MSI) 397 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 398 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 399 ")"); 400 401 #define OHCI_PARAM_DEBUG_AT_AR 1 402 #define OHCI_PARAM_DEBUG_SELFIDS 2 403 #define OHCI_PARAM_DEBUG_IRQS 4 404 405 static int param_debug; 406 module_param_named(debug, param_debug, int, 0644); 407 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 408 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 409 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 410 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 411 ", or a combination, or all = -1)"); 412 413 static bool param_remote_dma; 414 module_param_named(remote_dma, param_remote_dma, bool, 0444); 415 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 416 417 static void log_irqs(struct fw_ohci *ohci, u32 evt) 418 { 419 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 420 return; 421 422 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 423 evt & OHCI1394_selfIDComplete ? " selfID" : "", 424 evt & OHCI1394_RQPkt ? " AR_req" : "", 425 evt & OHCI1394_RSPkt ? " AR_resp" : "", 426 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 427 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 428 evt & OHCI1394_isochRx ? " IR" : "", 429 evt & OHCI1394_isochTx ? " IT" : "", 430 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 431 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 432 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 433 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 434 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 435 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 436 evt & OHCI1394_busReset ? " busReset" : "", 437 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 438 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 439 OHCI1394_respTxComplete | OHCI1394_isochRx | 440 OHCI1394_isochTx | OHCI1394_postedWriteErr | 441 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 442 OHCI1394_cycleInconsistent | 443 OHCI1394_regAccessFail | OHCI1394_busReset) 444 ? " ?" : ""); 445 } 446 447 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 448 { 449 static const char *const speed[] = { 450 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 451 }; 452 static const char *const power[] = { 453 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 454 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 455 }; 456 static const char port[] = { 457 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 458 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 459 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 460 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 461 }; 462 struct self_id_sequence_enumerator enumerator = { 463 .cursor = ohci->self_id_buffer, 464 .quadlet_count = self_id_count, 465 }; 466 467 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 468 return; 469 470 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 471 self_id_count, generation, ohci->node_id); 472 473 while (enumerator.quadlet_count > 0) { 474 unsigned int quadlet_count; 475 unsigned int port_index; 476 const u32 *s; 477 int i; 478 479 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 480 if (IS_ERR(s)) 481 break; 482 483 ohci_notice(ohci, 484 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 485 *s, 486 phy_packet_self_id_get_phy_id(*s), 487 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 488 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 489 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 490 speed[*s >> 14 & 3], *s >> 16 & 63, 491 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 492 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 493 494 port_index = 3; 495 for (i = 1; i < quadlet_count; ++i) { 496 ohci_notice(ohci, 497 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 498 s[i], 499 phy_packet_self_id_get_phy_id(s[i]), 500 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 501 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 502 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 503 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 504 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 505 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 506 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 507 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 508 ); 509 510 port_index += 8; 511 } 512 } 513 } 514 515 static const char *evts[] = { 516 [0x00] = "evt_no_status", [0x01] = "-reserved-", 517 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 518 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 519 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 520 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 521 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 522 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 523 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 524 [0x10] = "-reserved-", [0x11] = "ack_complete", 525 [0x12] = "ack_pending ", [0x13] = "-reserved-", 526 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 527 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 528 [0x18] = "-reserved-", [0x19] = "-reserved-", 529 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 530 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 531 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 532 [0x20] = "pending/cancelled", 533 }; 534 535 static void log_ar_at_event(struct fw_ohci *ohci, 536 char dir, int speed, u32 *header, int evt) 537 { 538 static const char *const tcodes[] = { 539 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 540 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 541 [TCODE_WRITE_RESPONSE] = "W resp", 542 [0x3] = "-reserved-", 543 [TCODE_READ_QUADLET_REQUEST] = "QR req", 544 [TCODE_READ_BLOCK_REQUEST] = "BR req", 545 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 546 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 547 [TCODE_CYCLE_START] = "cycle start", 548 [TCODE_LOCK_REQUEST] = "Lk req", 549 [TCODE_STREAM_DATA] = "async stream packet", 550 [TCODE_LOCK_RESPONSE] = "Lk resp", 551 [0xc] = "-reserved-", 552 [0xd] = "-reserved-", 553 [TCODE_LINK_INTERNAL] = "link internal", 554 [0xf] = "-reserved-", 555 }; 556 int tcode = async_header_get_tcode(header); 557 char specific[12]; 558 559 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 560 return; 561 562 if (unlikely(evt >= ARRAY_SIZE(evts))) 563 evt = 0x1f; 564 565 if (evt == OHCI1394_evt_bus_reset) { 566 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 567 dir, (header[2] >> 16) & 0xff); 568 return; 569 } 570 571 switch (tcode) { 572 case TCODE_WRITE_QUADLET_REQUEST: 573 case TCODE_READ_QUADLET_RESPONSE: 574 case TCODE_CYCLE_START: 575 snprintf(specific, sizeof(specific), " = %08x", 576 be32_to_cpu((__force __be32)header[3])); 577 break; 578 case TCODE_WRITE_BLOCK_REQUEST: 579 case TCODE_READ_BLOCK_REQUEST: 580 case TCODE_READ_BLOCK_RESPONSE: 581 case TCODE_LOCK_REQUEST: 582 case TCODE_LOCK_RESPONSE: 583 snprintf(specific, sizeof(specific), " %x,%x", 584 async_header_get_data_length(header), 585 async_header_get_extended_tcode(header)); 586 break; 587 default: 588 specific[0] = '\0'; 589 } 590 591 switch (tcode) { 592 case TCODE_STREAM_DATA: 593 ohci_notice(ohci, "A%c %s, %s\n", 594 dir, evts[evt], tcodes[tcode]); 595 break; 596 case TCODE_LINK_INTERNAL: 597 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 598 dir, evts[evt], header[1], header[2]); 599 break; 600 case TCODE_WRITE_QUADLET_REQUEST: 601 case TCODE_WRITE_BLOCK_REQUEST: 602 case TCODE_READ_QUADLET_REQUEST: 603 case TCODE_READ_BLOCK_REQUEST: 604 case TCODE_LOCK_REQUEST: 605 ohci_notice(ohci, 606 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 607 dir, speed, async_header_get_tlabel(header), 608 async_header_get_source(header), async_header_get_destination(header), 609 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 610 break; 611 default: 612 ohci_notice(ohci, 613 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 614 dir, speed, async_header_get_tlabel(header), 615 async_header_get_source(header), async_header_get_destination(header), 616 evts[evt], tcodes[tcode], specific); 617 } 618 } 619 620 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 621 { 622 writel(data, ohci->registers + offset); 623 } 624 625 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 626 { 627 return readl(ohci->registers + offset); 628 } 629 630 static inline void flush_writes(const struct fw_ohci *ohci) 631 { 632 /* Do a dummy read to flush writes. */ 633 reg_read(ohci, OHCI1394_Version); 634 } 635 636 /* 637 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 638 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 639 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 640 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 641 */ 642 static int read_phy_reg(struct fw_ohci *ohci, int addr) 643 { 644 u32 val; 645 int i; 646 647 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 648 for (i = 0; i < 3 + 100; i++) { 649 val = reg_read(ohci, OHCI1394_PhyControl); 650 if (!~val) 651 return -ENODEV; /* Card was ejected. */ 652 653 if (val & OHCI1394_PhyControl_ReadDone) 654 return OHCI1394_PhyControl_ReadData(val); 655 656 /* 657 * Try a few times without waiting. Sleeping is necessary 658 * only when the link/PHY interface is busy. 659 */ 660 if (i >= 3) 661 msleep(1); 662 } 663 ohci_err(ohci, "failed to read phy reg %d\n", addr); 664 dump_stack(); 665 666 return -EBUSY; 667 } 668 669 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 670 { 671 int i; 672 673 reg_write(ohci, OHCI1394_PhyControl, 674 OHCI1394_PhyControl_Write(addr, val)); 675 for (i = 0; i < 3 + 100; i++) { 676 val = reg_read(ohci, OHCI1394_PhyControl); 677 if (!~val) 678 return -ENODEV; /* Card was ejected. */ 679 680 if (!(val & OHCI1394_PhyControl_WritePending)) 681 return 0; 682 683 if (i >= 3) 684 msleep(1); 685 } 686 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 687 dump_stack(); 688 689 return -EBUSY; 690 } 691 692 static int update_phy_reg(struct fw_ohci *ohci, int addr, 693 int clear_bits, int set_bits) 694 { 695 int ret = read_phy_reg(ohci, addr); 696 if (ret < 0) 697 return ret; 698 699 /* 700 * The interrupt status bits are cleared by writing a one bit. 701 * Avoid clearing them unless explicitly requested in set_bits. 702 */ 703 if (addr == 5) 704 clear_bits |= PHY_INT_STATUS_BITS; 705 706 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 707 } 708 709 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 710 { 711 int ret; 712 713 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 714 if (ret < 0) 715 return ret; 716 717 return read_phy_reg(ohci, addr); 718 } 719 720 static int ohci_read_phy_reg(struct fw_card *card, int addr) 721 { 722 struct fw_ohci *ohci = fw_ohci(card); 723 int ret; 724 725 mutex_lock(&ohci->phy_reg_mutex); 726 ret = read_phy_reg(ohci, addr); 727 mutex_unlock(&ohci->phy_reg_mutex); 728 729 return ret; 730 } 731 732 static int ohci_update_phy_reg(struct fw_card *card, int addr, 733 int clear_bits, int set_bits) 734 { 735 struct fw_ohci *ohci = fw_ohci(card); 736 int ret; 737 738 mutex_lock(&ohci->phy_reg_mutex); 739 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 740 mutex_unlock(&ohci->phy_reg_mutex); 741 742 return ret; 743 } 744 745 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 746 { 747 return page_private(ctx->pages[i]); 748 } 749 750 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 751 { 752 struct descriptor *d; 753 754 d = &ctx->descriptors[index]; 755 d->branch_address &= cpu_to_le32(~0xf); 756 d->res_count = cpu_to_le16(PAGE_SIZE); 757 d->transfer_status = 0; 758 759 wmb(); /* finish init of new descriptors before branch_address update */ 760 d = &ctx->descriptors[ctx->last_buffer_index]; 761 d->branch_address |= cpu_to_le32(1); 762 763 ctx->last_buffer_index = index; 764 765 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 766 } 767 768 static void ar_context_release(struct ar_context *ctx) 769 { 770 struct device *dev = ctx->ohci->card.device; 771 unsigned int i; 772 773 if (!ctx->buffer) 774 return; 775 776 vunmap(ctx->buffer); 777 778 for (i = 0; i < AR_BUFFERS; i++) { 779 if (ctx->pages[i]) 780 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 781 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 782 } 783 } 784 785 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 786 { 787 struct fw_ohci *ohci = ctx->ohci; 788 789 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 790 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 791 flush_writes(ohci); 792 793 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 794 } 795 /* FIXME: restart? */ 796 } 797 798 static inline unsigned int ar_next_buffer_index(unsigned int index) 799 { 800 return (index + 1) % AR_BUFFERS; 801 } 802 803 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 804 { 805 return ar_next_buffer_index(ctx->last_buffer_index); 806 } 807 808 /* 809 * We search for the buffer that contains the last AR packet DMA data written 810 * by the controller. 811 */ 812 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 813 unsigned int *buffer_offset) 814 { 815 unsigned int i, next_i, last = ctx->last_buffer_index; 816 __le16 res_count, next_res_count; 817 818 i = ar_first_buffer_index(ctx); 819 res_count = READ_ONCE(ctx->descriptors[i].res_count); 820 821 /* A buffer that is not yet completely filled must be the last one. */ 822 while (i != last && res_count == 0) { 823 824 /* Peek at the next descriptor. */ 825 next_i = ar_next_buffer_index(i); 826 rmb(); /* read descriptors in order */ 827 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 828 /* 829 * If the next descriptor is still empty, we must stop at this 830 * descriptor. 831 */ 832 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 833 /* 834 * The exception is when the DMA data for one packet is 835 * split over three buffers; in this case, the middle 836 * buffer's descriptor might be never updated by the 837 * controller and look still empty, and we have to peek 838 * at the third one. 839 */ 840 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 841 next_i = ar_next_buffer_index(next_i); 842 rmb(); 843 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 844 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 845 goto next_buffer_is_active; 846 } 847 848 break; 849 } 850 851 next_buffer_is_active: 852 i = next_i; 853 res_count = next_res_count; 854 } 855 856 rmb(); /* read res_count before the DMA data */ 857 858 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 859 if (*buffer_offset > PAGE_SIZE) { 860 *buffer_offset = 0; 861 ar_context_abort(ctx, "corrupted descriptor"); 862 } 863 864 return i; 865 } 866 867 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 868 unsigned int end_buffer_index, 869 unsigned int end_buffer_offset) 870 { 871 unsigned int i; 872 873 i = ar_first_buffer_index(ctx); 874 while (i != end_buffer_index) { 875 dma_sync_single_for_cpu(ctx->ohci->card.device, 876 ar_buffer_bus(ctx, i), 877 PAGE_SIZE, DMA_FROM_DEVICE); 878 i = ar_next_buffer_index(i); 879 } 880 if (end_buffer_offset > 0) 881 dma_sync_single_for_cpu(ctx->ohci->card.device, 882 ar_buffer_bus(ctx, i), 883 end_buffer_offset, DMA_FROM_DEVICE); 884 } 885 886 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 887 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 888 { 889 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 890 } 891 892 static bool has_be_header_quirk(const struct fw_ohci *ohci) 893 { 894 return !!(ohci->quirks & QUIRK_BE_HEADERS); 895 } 896 #else 897 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 898 { 899 return le32_to_cpu(value); 900 } 901 902 static bool has_be_header_quirk(const struct fw_ohci *ohci) 903 { 904 return false; 905 } 906 #endif 907 908 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 909 { 910 struct fw_ohci *ohci = ctx->ohci; 911 struct fw_packet p; 912 u32 status, length, tcode; 913 int evt; 914 915 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 916 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 917 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 918 919 tcode = async_header_get_tcode(p.header); 920 switch (tcode) { 921 case TCODE_WRITE_QUADLET_REQUEST: 922 case TCODE_READ_QUADLET_RESPONSE: 923 p.header[3] = (__force __u32) buffer[3]; 924 p.header_length = 16; 925 p.payload_length = 0; 926 break; 927 928 case TCODE_READ_BLOCK_REQUEST : 929 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 930 p.header_length = 16; 931 p.payload_length = 0; 932 break; 933 934 case TCODE_WRITE_BLOCK_REQUEST: 935 case TCODE_READ_BLOCK_RESPONSE: 936 case TCODE_LOCK_REQUEST: 937 case TCODE_LOCK_RESPONSE: 938 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 939 p.header_length = 16; 940 p.payload_length = async_header_get_data_length(p.header); 941 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 942 ar_context_abort(ctx, "invalid packet length"); 943 return NULL; 944 } 945 break; 946 947 case TCODE_WRITE_RESPONSE: 948 case TCODE_READ_QUADLET_REQUEST: 949 case TCODE_LINK_INTERNAL: 950 p.header_length = 12; 951 p.payload_length = 0; 952 break; 953 954 default: 955 ar_context_abort(ctx, "invalid tcode"); 956 return NULL; 957 } 958 959 p.payload = (void *) buffer + p.header_length; 960 961 /* FIXME: What to do about evt_* errors? */ 962 length = (p.header_length + p.payload_length + 3) / 4; 963 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 964 evt = (status >> 16) & 0x1f; 965 966 p.ack = evt - 16; 967 p.speed = (status >> 21) & 0x7; 968 p.timestamp = status & 0xffff; 969 p.generation = ohci->request_generation; 970 971 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 972 973 /* 974 * Several controllers, notably from NEC and VIA, forget to 975 * write ack_complete status at PHY packet reception. 976 */ 977 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 978 p.ack = ACK_COMPLETE; 979 980 /* 981 * The OHCI bus reset handler synthesizes a PHY packet with 982 * the new generation number when a bus reset happens (see 983 * section 8.4.2.3). This helps us determine when a request 984 * was received and make sure we send the response in the same 985 * generation. We only need this for requests; for responses 986 * we use the unique tlabel for finding the matching 987 * request. 988 * 989 * Alas some chips sometimes emit bus reset packets with a 990 * wrong generation. We set the correct generation for these 991 * at a slightly incorrect time (in bus_reset_work). 992 */ 993 if (evt == OHCI1394_evt_bus_reset) { 994 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 995 ohci->request_generation = (p.header[2] >> 16) & 0xff; 996 } else if (ctx == &ohci->ar_request_ctx) { 997 fw_core_handle_request(&ohci->card, &p); 998 } else { 999 fw_core_handle_response(&ohci->card, &p); 1000 } 1001 1002 return buffer + length + 1; 1003 } 1004 1005 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 1006 { 1007 void *next; 1008 1009 while (p < end) { 1010 next = handle_ar_packet(ctx, p); 1011 if (!next) 1012 return p; 1013 p = next; 1014 } 1015 1016 return p; 1017 } 1018 1019 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1020 { 1021 unsigned int i; 1022 1023 i = ar_first_buffer_index(ctx); 1024 while (i != end_buffer) { 1025 dma_sync_single_for_device(ctx->ohci->card.device, 1026 ar_buffer_bus(ctx, i), 1027 PAGE_SIZE, DMA_FROM_DEVICE); 1028 ar_context_link_page(ctx, i); 1029 i = ar_next_buffer_index(i); 1030 } 1031 } 1032 1033 static void ar_context_tasklet(unsigned long data) 1034 { 1035 struct ar_context *ctx = (struct ar_context *)data; 1036 unsigned int end_buffer_index, end_buffer_offset; 1037 void *p, *end; 1038 1039 p = ctx->pointer; 1040 if (!p) 1041 return; 1042 1043 end_buffer_index = ar_search_last_active_buffer(ctx, 1044 &end_buffer_offset); 1045 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1046 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1047 1048 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1049 /* 1050 * The filled part of the overall buffer wraps around; handle 1051 * all packets up to the buffer end here. If the last packet 1052 * wraps around, its tail will be visible after the buffer end 1053 * because the buffer start pages are mapped there again. 1054 */ 1055 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1056 p = handle_ar_packets(ctx, p, buffer_end); 1057 if (p < buffer_end) 1058 goto error; 1059 /* adjust p to point back into the actual buffer */ 1060 p -= AR_BUFFERS * PAGE_SIZE; 1061 } 1062 1063 p = handle_ar_packets(ctx, p, end); 1064 if (p != end) { 1065 if (p > end) 1066 ar_context_abort(ctx, "inconsistent descriptor"); 1067 goto error; 1068 } 1069 1070 ctx->pointer = p; 1071 ar_recycle_buffers(ctx, end_buffer_index); 1072 1073 return; 1074 1075 error: 1076 ctx->pointer = NULL; 1077 } 1078 1079 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1080 unsigned int descriptors_offset, u32 regs) 1081 { 1082 struct device *dev = ohci->card.device; 1083 unsigned int i; 1084 dma_addr_t dma_addr; 1085 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1086 struct descriptor *d; 1087 1088 ctx->regs = regs; 1089 ctx->ohci = ohci; 1090 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1091 1092 for (i = 0; i < AR_BUFFERS; i++) { 1093 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1094 DMA_FROM_DEVICE, GFP_KERNEL); 1095 if (!ctx->pages[i]) 1096 goto out_of_memory; 1097 set_page_private(ctx->pages[i], dma_addr); 1098 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1099 DMA_FROM_DEVICE); 1100 } 1101 1102 for (i = 0; i < AR_BUFFERS; i++) 1103 pages[i] = ctx->pages[i]; 1104 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1105 pages[AR_BUFFERS + i] = ctx->pages[i]; 1106 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1107 if (!ctx->buffer) 1108 goto out_of_memory; 1109 1110 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1111 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1112 1113 for (i = 0; i < AR_BUFFERS; i++) { 1114 d = &ctx->descriptors[i]; 1115 d->req_count = cpu_to_le16(PAGE_SIZE); 1116 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1117 DESCRIPTOR_STATUS | 1118 DESCRIPTOR_BRANCH_ALWAYS); 1119 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1120 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1121 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1122 } 1123 1124 return 0; 1125 1126 out_of_memory: 1127 ar_context_release(ctx); 1128 1129 return -ENOMEM; 1130 } 1131 1132 static void ar_context_run(struct ar_context *ctx) 1133 { 1134 unsigned int i; 1135 1136 for (i = 0; i < AR_BUFFERS; i++) 1137 ar_context_link_page(ctx, i); 1138 1139 ctx->pointer = ctx->buffer; 1140 1141 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1142 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1143 } 1144 1145 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1146 { 1147 __le16 branch; 1148 1149 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1150 1151 /* figure out which descriptor the branch address goes in */ 1152 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1153 return d; 1154 else 1155 return d + z - 1; 1156 } 1157 1158 static void context_tasklet(unsigned long data) 1159 { 1160 struct context *ctx = (struct context *) data; 1161 struct descriptor *d, *last; 1162 u32 address; 1163 int z; 1164 struct descriptor_buffer *desc; 1165 1166 desc = list_entry(ctx->buffer_list.next, 1167 struct descriptor_buffer, list); 1168 last = ctx->last; 1169 while (last->branch_address != 0) { 1170 struct descriptor_buffer *old_desc = desc; 1171 address = le32_to_cpu(last->branch_address); 1172 z = address & 0xf; 1173 address &= ~0xf; 1174 ctx->current_bus = address; 1175 1176 /* If the branch address points to a buffer outside of the 1177 * current buffer, advance to the next buffer. */ 1178 if (address < desc->buffer_bus || 1179 address >= desc->buffer_bus + desc->used) 1180 desc = list_entry(desc->list.next, 1181 struct descriptor_buffer, list); 1182 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1183 last = find_branch_descriptor(d, z); 1184 1185 if (!ctx->callback(ctx, d, last)) 1186 break; 1187 1188 if (old_desc != desc) { 1189 /* If we've advanced to the next buffer, move the 1190 * previous buffer to the free list. */ 1191 unsigned long flags; 1192 old_desc->used = 0; 1193 spin_lock_irqsave(&ctx->ohci->lock, flags); 1194 list_move_tail(&old_desc->list, &ctx->buffer_list); 1195 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1196 } 1197 ctx->last = last; 1198 } 1199 } 1200 1201 /* 1202 * Allocate a new buffer and add it to the list of free buffers for this 1203 * context. Must be called with ohci->lock held. 1204 */ 1205 static int context_add_buffer(struct context *ctx) 1206 { 1207 struct descriptor_buffer *desc; 1208 dma_addr_t bus_addr; 1209 int offset; 1210 1211 /* 1212 * 16MB of descriptors should be far more than enough for any DMA 1213 * program. This will catch run-away userspace or DoS attacks. 1214 */ 1215 if (ctx->total_allocation >= 16*1024*1024) 1216 return -ENOMEM; 1217 1218 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1219 if (!desc) 1220 return -ENOMEM; 1221 1222 offset = (void *)&desc->buffer - (void *)desc; 1223 /* 1224 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1225 * for descriptors, even 0x10-byte ones. This can cause page faults when 1226 * an IOMMU is in use and the oversized read crosses a page boundary. 1227 * Work around this by always leaving at least 0x10 bytes of padding. 1228 */ 1229 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1230 desc->buffer_bus = bus_addr + offset; 1231 desc->used = 0; 1232 1233 list_add_tail(&desc->list, &ctx->buffer_list); 1234 ctx->total_allocation += PAGE_SIZE; 1235 1236 return 0; 1237 } 1238 1239 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1240 u32 regs, descriptor_callback_t callback) 1241 { 1242 ctx->ohci = ohci; 1243 ctx->regs = regs; 1244 ctx->total_allocation = 0; 1245 1246 INIT_LIST_HEAD(&ctx->buffer_list); 1247 if (context_add_buffer(ctx) < 0) 1248 return -ENOMEM; 1249 1250 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1251 struct descriptor_buffer, list); 1252 1253 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1254 ctx->callback = callback; 1255 1256 /* 1257 * We put a dummy descriptor in the buffer that has a NULL 1258 * branch address and looks like it's been sent. That way we 1259 * have a descriptor to append DMA programs to. 1260 */ 1261 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1262 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1263 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1264 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1265 ctx->last = ctx->buffer_tail->buffer; 1266 ctx->prev = ctx->buffer_tail->buffer; 1267 ctx->prev_z = 1; 1268 1269 return 0; 1270 } 1271 1272 static void context_release(struct context *ctx) 1273 { 1274 struct fw_card *card = &ctx->ohci->card; 1275 struct descriptor_buffer *desc, *tmp; 1276 1277 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1278 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1279 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1280 } 1281 } 1282 1283 /* Must be called with ohci->lock held */ 1284 static struct descriptor *context_get_descriptors(struct context *ctx, 1285 int z, dma_addr_t *d_bus) 1286 { 1287 struct descriptor *d = NULL; 1288 struct descriptor_buffer *desc = ctx->buffer_tail; 1289 1290 if (z * sizeof(*d) > desc->buffer_size) 1291 return NULL; 1292 1293 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1294 /* No room for the descriptor in this buffer, so advance to the 1295 * next one. */ 1296 1297 if (desc->list.next == &ctx->buffer_list) { 1298 /* If there is no free buffer next in the list, 1299 * allocate one. */ 1300 if (context_add_buffer(ctx) < 0) 1301 return NULL; 1302 } 1303 desc = list_entry(desc->list.next, 1304 struct descriptor_buffer, list); 1305 ctx->buffer_tail = desc; 1306 } 1307 1308 d = desc->buffer + desc->used / sizeof(*d); 1309 memset(d, 0, z * sizeof(*d)); 1310 *d_bus = desc->buffer_bus + desc->used; 1311 1312 return d; 1313 } 1314 1315 static void context_run(struct context *ctx, u32 extra) 1316 { 1317 struct fw_ohci *ohci = ctx->ohci; 1318 1319 reg_write(ohci, COMMAND_PTR(ctx->regs), 1320 le32_to_cpu(ctx->last->branch_address)); 1321 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1322 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1323 ctx->running = true; 1324 flush_writes(ohci); 1325 } 1326 1327 static void context_append(struct context *ctx, 1328 struct descriptor *d, int z, int extra) 1329 { 1330 dma_addr_t d_bus; 1331 struct descriptor_buffer *desc = ctx->buffer_tail; 1332 struct descriptor *d_branch; 1333 1334 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1335 1336 desc->used += (z + extra) * sizeof(*d); 1337 1338 wmb(); /* finish init of new descriptors before branch_address update */ 1339 1340 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1341 d_branch->branch_address = cpu_to_le32(d_bus | z); 1342 1343 /* 1344 * VT6306 incorrectly checks only the single descriptor at the 1345 * CommandPtr when the wake bit is written, so if it's a 1346 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1347 * the branch address in the first descriptor. 1348 * 1349 * Not doing this for transmit contexts since not sure how it interacts 1350 * with skip addresses. 1351 */ 1352 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1353 d_branch != ctx->prev && 1354 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1355 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1356 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1357 } 1358 1359 ctx->prev = d; 1360 ctx->prev_z = z; 1361 } 1362 1363 static void context_stop(struct context *ctx) 1364 { 1365 struct fw_ohci *ohci = ctx->ohci; 1366 u32 reg; 1367 int i; 1368 1369 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1370 ctx->running = false; 1371 1372 for (i = 0; i < 1000; i++) { 1373 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1374 if ((reg & CONTEXT_ACTIVE) == 0) 1375 return; 1376 1377 if (i) 1378 udelay(10); 1379 } 1380 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1381 } 1382 1383 struct driver_data { 1384 u8 inline_data[8]; 1385 struct fw_packet *packet; 1386 }; 1387 1388 /* 1389 * This function apppends a packet to the DMA queue for transmission. 1390 * Must always be called with the ochi->lock held to ensure proper 1391 * generation handling and locking around packet queue manipulation. 1392 */ 1393 static int at_context_queue_packet(struct context *ctx, 1394 struct fw_packet *packet) 1395 { 1396 struct fw_ohci *ohci = ctx->ohci; 1397 dma_addr_t d_bus, payload_bus; 1398 struct driver_data *driver_data; 1399 struct descriptor *d, *last; 1400 __le32 *header; 1401 int z, tcode; 1402 1403 d = context_get_descriptors(ctx, 4, &d_bus); 1404 if (d == NULL) { 1405 packet->ack = RCODE_SEND_ERROR; 1406 return -1; 1407 } 1408 1409 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1410 d[0].res_count = cpu_to_le16(packet->timestamp); 1411 1412 tcode = async_header_get_tcode(packet->header); 1413 header = (__le32 *) &d[1]; 1414 switch (tcode) { 1415 case TCODE_WRITE_QUADLET_REQUEST: 1416 case TCODE_WRITE_BLOCK_REQUEST: 1417 case TCODE_WRITE_RESPONSE: 1418 case TCODE_READ_QUADLET_REQUEST: 1419 case TCODE_READ_BLOCK_REQUEST: 1420 case TCODE_READ_QUADLET_RESPONSE: 1421 case TCODE_READ_BLOCK_RESPONSE: 1422 case TCODE_LOCK_REQUEST: 1423 case TCODE_LOCK_RESPONSE: 1424 ohci1394_at_data_set_src_bus_id(header, false); 1425 ohci1394_at_data_set_speed(header, packet->speed); 1426 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1427 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1428 ohci1394_at_data_set_tcode(header, tcode); 1429 1430 ohci1394_at_data_set_destination_id(header, 1431 async_header_get_destination(packet->header)); 1432 1433 if (ctx == &ctx->ohci->at_response_ctx) { 1434 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1435 } else { 1436 ohci1394_at_data_set_destination_offset(header, 1437 async_header_get_offset(packet->header)); 1438 } 1439 1440 if (tcode_is_block_packet(tcode)) 1441 header[3] = cpu_to_le32(packet->header[3]); 1442 else 1443 header[3] = (__force __le32) packet->header[3]; 1444 1445 d[0].req_count = cpu_to_le16(packet->header_length); 1446 break; 1447 case TCODE_LINK_INTERNAL: 1448 ohci1394_at_data_set_speed(header, packet->speed); 1449 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1450 1451 header[1] = cpu_to_le32(packet->header[1]); 1452 header[2] = cpu_to_le32(packet->header[2]); 1453 d[0].req_count = cpu_to_le16(12); 1454 1455 if (is_ping_packet(&packet->header[1])) 1456 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1457 break; 1458 1459 case TCODE_STREAM_DATA: 1460 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1461 (packet->speed << 16)); 1462 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1463 d[0].req_count = cpu_to_le16(8); 1464 break; 1465 1466 default: 1467 /* BUG(); */ 1468 packet->ack = RCODE_SEND_ERROR; 1469 return -1; 1470 } 1471 1472 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1473 driver_data = (struct driver_data *) &d[3]; 1474 driver_data->packet = packet; 1475 packet->driver_data = driver_data; 1476 1477 if (packet->payload_length > 0) { 1478 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1479 payload_bus = dma_map_single(ohci->card.device, 1480 packet->payload, 1481 packet->payload_length, 1482 DMA_TO_DEVICE); 1483 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1484 packet->ack = RCODE_SEND_ERROR; 1485 return -1; 1486 } 1487 packet->payload_bus = payload_bus; 1488 packet->payload_mapped = true; 1489 } else { 1490 memcpy(driver_data->inline_data, packet->payload, 1491 packet->payload_length); 1492 payload_bus = d_bus + 3 * sizeof(*d); 1493 } 1494 1495 d[2].req_count = cpu_to_le16(packet->payload_length); 1496 d[2].data_address = cpu_to_le32(payload_bus); 1497 last = &d[2]; 1498 z = 3; 1499 } else { 1500 last = &d[0]; 1501 z = 2; 1502 } 1503 1504 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1505 DESCRIPTOR_IRQ_ALWAYS | 1506 DESCRIPTOR_BRANCH_ALWAYS); 1507 1508 /* FIXME: Document how the locking works. */ 1509 if (ohci->generation != packet->generation) { 1510 if (packet->payload_mapped) 1511 dma_unmap_single(ohci->card.device, payload_bus, 1512 packet->payload_length, DMA_TO_DEVICE); 1513 packet->ack = RCODE_GENERATION; 1514 return -1; 1515 } 1516 1517 context_append(ctx, d, z, 4 - z); 1518 1519 if (ctx->running) 1520 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1521 else 1522 context_run(ctx, 0); 1523 1524 return 0; 1525 } 1526 1527 static void at_context_flush(struct context *ctx) 1528 { 1529 tasklet_disable(&ctx->tasklet); 1530 1531 ctx->flushing = true; 1532 context_tasklet((unsigned long)ctx); 1533 ctx->flushing = false; 1534 1535 tasklet_enable(&ctx->tasklet); 1536 } 1537 1538 static int handle_at_packet(struct context *context, 1539 struct descriptor *d, 1540 struct descriptor *last) 1541 { 1542 struct driver_data *driver_data; 1543 struct fw_packet *packet; 1544 struct fw_ohci *ohci = context->ohci; 1545 int evt; 1546 1547 if (last->transfer_status == 0 && !context->flushing) 1548 /* This descriptor isn't done yet, stop iteration. */ 1549 return 0; 1550 1551 driver_data = (struct driver_data *) &d[3]; 1552 packet = driver_data->packet; 1553 if (packet == NULL) 1554 /* This packet was cancelled, just continue. */ 1555 return 1; 1556 1557 if (packet->payload_mapped) 1558 dma_unmap_single(ohci->card.device, packet->payload_bus, 1559 packet->payload_length, DMA_TO_DEVICE); 1560 1561 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1562 packet->timestamp = le16_to_cpu(last->res_count); 1563 1564 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1565 1566 switch (evt) { 1567 case OHCI1394_evt_timeout: 1568 /* Async response transmit timed out. */ 1569 packet->ack = RCODE_CANCELLED; 1570 break; 1571 1572 case OHCI1394_evt_flushed: 1573 /* 1574 * The packet was flushed should give same error as 1575 * when we try to use a stale generation count. 1576 */ 1577 packet->ack = RCODE_GENERATION; 1578 break; 1579 1580 case OHCI1394_evt_missing_ack: 1581 if (context->flushing) 1582 packet->ack = RCODE_GENERATION; 1583 else { 1584 /* 1585 * Using a valid (current) generation count, but the 1586 * node is not on the bus or not sending acks. 1587 */ 1588 packet->ack = RCODE_NO_ACK; 1589 } 1590 break; 1591 1592 case ACK_COMPLETE + 0x10: 1593 case ACK_PENDING + 0x10: 1594 case ACK_BUSY_X + 0x10: 1595 case ACK_BUSY_A + 0x10: 1596 case ACK_BUSY_B + 0x10: 1597 case ACK_DATA_ERROR + 0x10: 1598 case ACK_TYPE_ERROR + 0x10: 1599 packet->ack = evt - 0x10; 1600 break; 1601 1602 case OHCI1394_evt_no_status: 1603 if (context->flushing) { 1604 packet->ack = RCODE_GENERATION; 1605 break; 1606 } 1607 fallthrough; 1608 1609 default: 1610 packet->ack = RCODE_SEND_ERROR; 1611 break; 1612 } 1613 1614 packet->callback(packet, &ohci->card, packet->ack); 1615 1616 return 1; 1617 } 1618 1619 static u32 get_cycle_time(struct fw_ohci *ohci); 1620 1621 static void handle_local_rom(struct fw_ohci *ohci, 1622 struct fw_packet *packet, u32 csr) 1623 { 1624 struct fw_packet response; 1625 int tcode, length, i; 1626 1627 tcode = async_header_get_tcode(packet->header); 1628 if (tcode_is_block_packet(tcode)) 1629 length = async_header_get_data_length(packet->header); 1630 else 1631 length = 4; 1632 1633 i = csr - CSR_CONFIG_ROM; 1634 if (i + length > CONFIG_ROM_SIZE) { 1635 fw_fill_response(&response, packet->header, 1636 RCODE_ADDRESS_ERROR, NULL, 0); 1637 } else if (!tcode_is_read_request(tcode)) { 1638 fw_fill_response(&response, packet->header, 1639 RCODE_TYPE_ERROR, NULL, 0); 1640 } else { 1641 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1642 (void *) ohci->config_rom + i, length); 1643 } 1644 1645 // Timestamping on behalf of the hardware. 1646 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1647 fw_core_handle_response(&ohci->card, &response); 1648 } 1649 1650 static void handle_local_lock(struct fw_ohci *ohci, 1651 struct fw_packet *packet, u32 csr) 1652 { 1653 struct fw_packet response; 1654 int tcode, length, ext_tcode, sel, try; 1655 __be32 *payload, lock_old; 1656 u32 lock_arg, lock_data; 1657 1658 tcode = async_header_get_tcode(packet->header); 1659 length = async_header_get_data_length(packet->header); 1660 payload = packet->payload; 1661 ext_tcode = async_header_get_extended_tcode(packet->header); 1662 1663 if (tcode == TCODE_LOCK_REQUEST && 1664 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1665 lock_arg = be32_to_cpu(payload[0]); 1666 lock_data = be32_to_cpu(payload[1]); 1667 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1668 lock_arg = 0; 1669 lock_data = 0; 1670 } else { 1671 fw_fill_response(&response, packet->header, 1672 RCODE_TYPE_ERROR, NULL, 0); 1673 goto out; 1674 } 1675 1676 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1677 reg_write(ohci, OHCI1394_CSRData, lock_data); 1678 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1679 reg_write(ohci, OHCI1394_CSRControl, sel); 1680 1681 for (try = 0; try < 20; try++) 1682 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1683 lock_old = cpu_to_be32(reg_read(ohci, 1684 OHCI1394_CSRData)); 1685 fw_fill_response(&response, packet->header, 1686 RCODE_COMPLETE, 1687 &lock_old, sizeof(lock_old)); 1688 goto out; 1689 } 1690 1691 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1692 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1693 1694 out: 1695 // Timestamping on behalf of the hardware. 1696 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1697 fw_core_handle_response(&ohci->card, &response); 1698 } 1699 1700 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1701 { 1702 u64 offset, csr; 1703 1704 if (ctx == &ctx->ohci->at_request_ctx) { 1705 packet->ack = ACK_PENDING; 1706 packet->callback(packet, &ctx->ohci->card, packet->ack); 1707 } 1708 1709 offset = async_header_get_offset(packet->header); 1710 csr = offset - CSR_REGISTER_BASE; 1711 1712 /* Handle config rom reads. */ 1713 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1714 handle_local_rom(ctx->ohci, packet, csr); 1715 else switch (csr) { 1716 case CSR_BUS_MANAGER_ID: 1717 case CSR_BANDWIDTH_AVAILABLE: 1718 case CSR_CHANNELS_AVAILABLE_HI: 1719 case CSR_CHANNELS_AVAILABLE_LO: 1720 handle_local_lock(ctx->ohci, packet, csr); 1721 break; 1722 default: 1723 if (ctx == &ctx->ohci->at_request_ctx) 1724 fw_core_handle_request(&ctx->ohci->card, packet); 1725 else 1726 fw_core_handle_response(&ctx->ohci->card, packet); 1727 break; 1728 } 1729 1730 if (ctx == &ctx->ohci->at_response_ctx) { 1731 packet->ack = ACK_COMPLETE; 1732 packet->callback(packet, &ctx->ohci->card, packet->ack); 1733 } 1734 } 1735 1736 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1737 { 1738 unsigned long flags; 1739 int ret; 1740 1741 spin_lock_irqsave(&ctx->ohci->lock, flags); 1742 1743 if (async_header_get_destination(packet->header) == ctx->ohci->node_id && 1744 ctx->ohci->generation == packet->generation) { 1745 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1746 1747 // Timestamping on behalf of the hardware. 1748 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1749 1750 handle_local_request(ctx, packet); 1751 return; 1752 } 1753 1754 ret = at_context_queue_packet(ctx, packet); 1755 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1756 1757 if (ret < 0) { 1758 // Timestamping on behalf of the hardware. 1759 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1760 1761 packet->callback(packet, &ctx->ohci->card, packet->ack); 1762 } 1763 } 1764 1765 static void detect_dead_context(struct fw_ohci *ohci, 1766 const char *name, unsigned int regs) 1767 { 1768 u32 ctl; 1769 1770 ctl = reg_read(ohci, CONTROL_SET(regs)); 1771 if (ctl & CONTEXT_DEAD) 1772 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1773 name, evts[ctl & 0x1f]); 1774 } 1775 1776 static void handle_dead_contexts(struct fw_ohci *ohci) 1777 { 1778 unsigned int i; 1779 char name[8]; 1780 1781 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1782 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1783 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1784 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1785 for (i = 0; i < 32; ++i) { 1786 if (!(ohci->it_context_support & (1 << i))) 1787 continue; 1788 sprintf(name, "IT%u", i); 1789 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1790 } 1791 for (i = 0; i < 32; ++i) { 1792 if (!(ohci->ir_context_support & (1 << i))) 1793 continue; 1794 sprintf(name, "IR%u", i); 1795 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1796 } 1797 /* TODO: maybe try to flush and restart the dead contexts */ 1798 } 1799 1800 static u32 cycle_timer_ticks(u32 cycle_timer) 1801 { 1802 u32 ticks; 1803 1804 ticks = cycle_timer & 0xfff; 1805 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1806 ticks += (3072 * 8000) * (cycle_timer >> 25); 1807 1808 return ticks; 1809 } 1810 1811 /* 1812 * Some controllers exhibit one or more of the following bugs when updating the 1813 * iso cycle timer register: 1814 * - When the lowest six bits are wrapping around to zero, a read that happens 1815 * at the same time will return garbage in the lowest ten bits. 1816 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1817 * not incremented for about 60 ns. 1818 * - Occasionally, the entire register reads zero. 1819 * 1820 * To catch these, we read the register three times and ensure that the 1821 * difference between each two consecutive reads is approximately the same, i.e. 1822 * less than twice the other. Furthermore, any negative difference indicates an 1823 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1824 * execute, so we have enough precision to compute the ratio of the differences.) 1825 */ 1826 static u32 get_cycle_time(struct fw_ohci *ohci) 1827 { 1828 u32 c0, c1, c2; 1829 u32 t0, t1, t2; 1830 s32 diff01, diff12; 1831 int i; 1832 1833 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1834 return 0; 1835 1836 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1837 1838 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1839 i = 0; 1840 c1 = c2; 1841 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1842 do { 1843 c0 = c1; 1844 c1 = c2; 1845 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1846 t0 = cycle_timer_ticks(c0); 1847 t1 = cycle_timer_ticks(c1); 1848 t2 = cycle_timer_ticks(c2); 1849 diff01 = t1 - t0; 1850 diff12 = t2 - t1; 1851 } while ((diff01 <= 0 || diff12 <= 0 || 1852 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1853 && i++ < 20); 1854 } 1855 1856 return c2; 1857 } 1858 1859 /* 1860 * This function has to be called at least every 64 seconds. The bus_time 1861 * field stores not only the upper 25 bits of the BUS_TIME register but also 1862 * the most significant bit of the cycle timer in bit 6 so that we can detect 1863 * changes in this bit. 1864 */ 1865 static u32 update_bus_time(struct fw_ohci *ohci) 1866 { 1867 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1868 1869 if (unlikely(!ohci->bus_time_running)) { 1870 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1871 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1872 (cycle_time_seconds & 0x40); 1873 ohci->bus_time_running = true; 1874 } 1875 1876 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1877 ohci->bus_time += 0x40; 1878 1879 return ohci->bus_time | cycle_time_seconds; 1880 } 1881 1882 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1883 enum phy_packet_self_id_port_status *status) 1884 { 1885 int reg; 1886 1887 mutex_lock(&ohci->phy_reg_mutex); 1888 reg = write_phy_reg(ohci, 7, port_index); 1889 if (reg >= 0) 1890 reg = read_phy_reg(ohci, 8); 1891 mutex_unlock(&ohci->phy_reg_mutex); 1892 if (reg < 0) 1893 return reg; 1894 1895 switch (reg & 0x0f) { 1896 case 0x06: 1897 // is child node (connected to parent node) 1898 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1899 break; 1900 case 0x0e: 1901 // is parent node (connected to child node) 1902 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1903 break; 1904 default: 1905 // not connected 1906 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1907 break; 1908 } 1909 1910 return 0; 1911 } 1912 1913 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1914 int self_id_count) 1915 { 1916 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1917 int i; 1918 1919 for (i = 0; i < self_id_count; i++) { 1920 u32 entry = ohci->self_id_buffer[i]; 1921 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1922 1923 if (left_phy_id == right_phy_id) 1924 return -1; 1925 if (left_phy_id < right_phy_id) 1926 return i; 1927 } 1928 return i; 1929 } 1930 1931 static bool initiated_reset(struct fw_ohci *ohci) 1932 { 1933 int reg; 1934 int ret = false; 1935 1936 mutex_lock(&ohci->phy_reg_mutex); 1937 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1938 if (reg >= 0) { 1939 reg = read_phy_reg(ohci, 8); 1940 reg |= 0x40; 1941 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1942 if (reg >= 0) { 1943 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1944 if (reg >= 0) { 1945 if ((reg & 0x08) == 0x08) { 1946 /* bit 3 indicates "initiated reset" */ 1947 ret = true; 1948 } 1949 } 1950 } 1951 } 1952 mutex_unlock(&ohci->phy_reg_mutex); 1953 return ret; 1954 } 1955 1956 /* 1957 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1958 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1959 * Construct the selfID from phy register contents. 1960 */ 1961 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1962 { 1963 int reg, i, pos; 1964 u32 self_id = 0; 1965 1966 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 1967 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 1968 phy_packet_self_id_zero_set_link_active(&self_id, true); 1969 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 1970 phy_packet_self_id_zero_set_contender(&self_id, true); 1971 1972 reg = reg_read(ohci, OHCI1394_NodeID); 1973 if (!(reg & OHCI1394_NodeID_idValid)) { 1974 ohci_notice(ohci, 1975 "node ID not valid, new bus reset in progress\n"); 1976 return -EBUSY; 1977 } 1978 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 1979 1980 reg = ohci_read_phy_reg(&ohci->card, 4); 1981 if (reg < 0) 1982 return reg; 1983 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 1984 1985 reg = ohci_read_phy_reg(&ohci->card, 1); 1986 if (reg < 0) 1987 return reg; 1988 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 1989 1990 for (i = 0; i < 3; i++) { 1991 enum phy_packet_self_id_port_status status; 1992 int err; 1993 1994 err = get_status_for_port(ohci, i, &status); 1995 if (err < 0) 1996 return err; 1997 1998 self_id_sequence_set_port_status(&self_id, 1, i, status); 1999 } 2000 2001 phy_packet_self_id_zero_set_initiated_reset(&self_id, initiated_reset(ohci)); 2002 2003 pos = get_self_id_pos(ohci, self_id, self_id_count); 2004 if (pos >= 0) { 2005 memmove(&(ohci->self_id_buffer[pos+1]), 2006 &(ohci->self_id_buffer[pos]), 2007 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2008 ohci->self_id_buffer[pos] = self_id; 2009 self_id_count++; 2010 } 2011 return self_id_count; 2012 } 2013 2014 static void bus_reset_work(struct work_struct *work) 2015 { 2016 struct fw_ohci *ohci = 2017 container_of(work, struct fw_ohci, bus_reset_work); 2018 int self_id_count, generation, new_generation, i, j; 2019 u32 reg, quadlet; 2020 void *free_rom = NULL; 2021 dma_addr_t free_rom_bus = 0; 2022 bool is_new_root; 2023 2024 reg = reg_read(ohci, OHCI1394_NodeID); 2025 if (!(reg & OHCI1394_NodeID_idValid)) { 2026 ohci_notice(ohci, 2027 "node ID not valid, new bus reset in progress\n"); 2028 return; 2029 } 2030 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2031 ohci_notice(ohci, "malconfigured bus\n"); 2032 return; 2033 } 2034 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2035 OHCI1394_NodeID_nodeNumber); 2036 2037 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2038 if (!(ohci->is_root && is_new_root)) 2039 reg_write(ohci, OHCI1394_LinkControlSet, 2040 OHCI1394_LinkControl_cycleMaster); 2041 ohci->is_root = is_new_root; 2042 2043 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2044 if (ohci1394_self_id_count_is_error(reg)) { 2045 ohci_notice(ohci, "self ID receive error\n"); 2046 return; 2047 } 2048 /* 2049 * The count in the SelfIDCount register is the number of 2050 * bytes in the self ID receive buffer. Since we also receive 2051 * the inverted quadlets and a header quadlet, we shift one 2052 * bit extra to get the actual number of self IDs. 2053 */ 2054 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2055 2056 if (self_id_count > 252) { 2057 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2058 return; 2059 } 2060 2061 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2062 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2063 rmb(); 2064 2065 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2066 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2067 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2068 2069 if (id != ~id2) { 2070 /* 2071 * If the invalid data looks like a cycle start packet, 2072 * it's likely to be the result of the cycle master 2073 * having a wrong gap count. In this case, the self IDs 2074 * so far are valid and should be processed so that the 2075 * bus manager can then correct the gap count. 2076 */ 2077 if (id == 0xffff008f) { 2078 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2079 self_id_count = j; 2080 break; 2081 } 2082 2083 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2084 j, self_id_count, id, id2); 2085 return; 2086 } 2087 ohci->self_id_buffer[j] = id; 2088 } 2089 2090 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2091 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2092 if (self_id_count < 0) { 2093 ohci_notice(ohci, 2094 "could not construct local self ID\n"); 2095 return; 2096 } 2097 } 2098 2099 if (self_id_count == 0) { 2100 ohci_notice(ohci, "no self IDs\n"); 2101 return; 2102 } 2103 rmb(); 2104 2105 /* 2106 * Check the consistency of the self IDs we just read. The 2107 * problem we face is that a new bus reset can start while we 2108 * read out the self IDs from the DMA buffer. If this happens, 2109 * the DMA buffer will be overwritten with new self IDs and we 2110 * will read out inconsistent data. The OHCI specification 2111 * (section 11.2) recommends a technique similar to 2112 * linux/seqlock.h, where we remember the generation of the 2113 * self IDs in the buffer before reading them out and compare 2114 * it to the current generation after reading them out. If 2115 * the two generations match we know we have a consistent set 2116 * of self IDs. 2117 */ 2118 2119 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2120 new_generation = ohci1394_self_id_count_get_generation(reg); 2121 if (new_generation != generation) { 2122 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2123 return; 2124 } 2125 2126 /* FIXME: Document how the locking works. */ 2127 spin_lock_irq(&ohci->lock); 2128 2129 ohci->generation = -1; /* prevent AT packet queueing */ 2130 context_stop(&ohci->at_request_ctx); 2131 context_stop(&ohci->at_response_ctx); 2132 2133 spin_unlock_irq(&ohci->lock); 2134 2135 /* 2136 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2137 * packets in the AT queues and software needs to drain them. 2138 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2139 */ 2140 at_context_flush(&ohci->at_request_ctx); 2141 at_context_flush(&ohci->at_response_ctx); 2142 2143 spin_lock_irq(&ohci->lock); 2144 2145 ohci->generation = generation; 2146 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2147 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2148 2149 if (ohci->quirks & QUIRK_RESET_PACKET) 2150 ohci->request_generation = generation; 2151 2152 /* 2153 * This next bit is unrelated to the AT context stuff but we 2154 * have to do it under the spinlock also. If a new config rom 2155 * was set up before this reset, the old one is now no longer 2156 * in use and we can free it. Update the config rom pointers 2157 * to point to the current config rom and clear the 2158 * next_config_rom pointer so a new update can take place. 2159 */ 2160 2161 if (ohci->next_config_rom != NULL) { 2162 if (ohci->next_config_rom != ohci->config_rom) { 2163 free_rom = ohci->config_rom; 2164 free_rom_bus = ohci->config_rom_bus; 2165 } 2166 ohci->config_rom = ohci->next_config_rom; 2167 ohci->config_rom_bus = ohci->next_config_rom_bus; 2168 ohci->next_config_rom = NULL; 2169 2170 /* 2171 * Restore config_rom image and manually update 2172 * config_rom registers. Writing the header quadlet 2173 * will indicate that the config rom is ready, so we 2174 * do that last. 2175 */ 2176 reg_write(ohci, OHCI1394_BusOptions, 2177 be32_to_cpu(ohci->config_rom[2])); 2178 ohci->config_rom[0] = ohci->next_header; 2179 reg_write(ohci, OHCI1394_ConfigROMhdr, 2180 be32_to_cpu(ohci->next_header)); 2181 } 2182 2183 if (param_remote_dma) { 2184 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2185 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2186 } 2187 2188 spin_unlock_irq(&ohci->lock); 2189 2190 if (free_rom) 2191 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2192 2193 log_selfids(ohci, generation, self_id_count); 2194 2195 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2196 self_id_count, ohci->self_id_buffer, 2197 ohci->csr_state_setclear_abdicate); 2198 ohci->csr_state_setclear_abdicate = false; 2199 } 2200 2201 static irqreturn_t irq_handler(int irq, void *data) 2202 { 2203 struct fw_ohci *ohci = data; 2204 u32 event, iso_event; 2205 int i; 2206 2207 event = reg_read(ohci, OHCI1394_IntEventClear); 2208 2209 if (!event || !~event) 2210 return IRQ_NONE; 2211 2212 /* 2213 * busReset and postedWriteErr events must not be cleared yet 2214 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2215 */ 2216 reg_write(ohci, OHCI1394_IntEventClear, 2217 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2218 trace_irqs(ohci->card.index, event); 2219 log_irqs(ohci, event); 2220 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2221 if (event & OHCI1394_busReset) 2222 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2223 2224 if (event & OHCI1394_selfIDComplete) { 2225 if (trace_self_id_complete_enabled()) { 2226 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2227 2228 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2229 has_be_header_quirk(ohci)); 2230 } 2231 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2232 } 2233 2234 if (event & OHCI1394_RQPkt) 2235 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2236 2237 if (event & OHCI1394_RSPkt) 2238 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2239 2240 if (event & OHCI1394_reqTxComplete) 2241 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2242 2243 if (event & OHCI1394_respTxComplete) 2244 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2245 2246 if (event & OHCI1394_isochRx) { 2247 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2248 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2249 2250 while (iso_event) { 2251 i = ffs(iso_event) - 1; 2252 tasklet_schedule( 2253 &ohci->ir_context_list[i].context.tasklet); 2254 iso_event &= ~(1 << i); 2255 } 2256 } 2257 2258 if (event & OHCI1394_isochTx) { 2259 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2260 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2261 2262 while (iso_event) { 2263 i = ffs(iso_event) - 1; 2264 tasklet_schedule( 2265 &ohci->it_context_list[i].context.tasklet); 2266 iso_event &= ~(1 << i); 2267 } 2268 } 2269 2270 if (unlikely(event & OHCI1394_regAccessFail)) 2271 ohci_err(ohci, "register access failure\n"); 2272 2273 if (unlikely(event & OHCI1394_postedWriteErr)) { 2274 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2275 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2276 reg_write(ohci, OHCI1394_IntEventClear, 2277 OHCI1394_postedWriteErr); 2278 if (printk_ratelimit()) 2279 ohci_err(ohci, "PCI posted write error\n"); 2280 } 2281 2282 if (unlikely(event & OHCI1394_cycleTooLong)) { 2283 if (printk_ratelimit()) 2284 ohci_notice(ohci, "isochronous cycle too long\n"); 2285 reg_write(ohci, OHCI1394_LinkControlSet, 2286 OHCI1394_LinkControl_cycleMaster); 2287 } 2288 2289 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2290 /* 2291 * We need to clear this event bit in order to make 2292 * cycleMatch isochronous I/O work. In theory we should 2293 * stop active cycleMatch iso contexts now and restart 2294 * them at least two cycles later. (FIXME?) 2295 */ 2296 if (printk_ratelimit()) 2297 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2298 } 2299 2300 if (unlikely(event & OHCI1394_unrecoverableError)) 2301 handle_dead_contexts(ohci); 2302 2303 if (event & OHCI1394_cycle64Seconds) { 2304 spin_lock(&ohci->lock); 2305 update_bus_time(ohci); 2306 spin_unlock(&ohci->lock); 2307 } else 2308 flush_writes(ohci); 2309 2310 return IRQ_HANDLED; 2311 } 2312 2313 static int software_reset(struct fw_ohci *ohci) 2314 { 2315 u32 val; 2316 int i; 2317 2318 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2319 for (i = 0; i < 500; i++) { 2320 val = reg_read(ohci, OHCI1394_HCControlSet); 2321 if (!~val) 2322 return -ENODEV; /* Card was ejected. */ 2323 2324 if (!(val & OHCI1394_HCControl_softReset)) 2325 return 0; 2326 2327 msleep(1); 2328 } 2329 2330 return -EBUSY; 2331 } 2332 2333 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2334 { 2335 size_t size = length * 4; 2336 2337 memcpy(dest, src, size); 2338 if (size < CONFIG_ROM_SIZE) 2339 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2340 } 2341 2342 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2343 { 2344 bool enable_1394a; 2345 int ret, clear, set, offset; 2346 2347 /* Check if the driver should configure link and PHY. */ 2348 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2349 OHCI1394_HCControl_programPhyEnable)) 2350 return 0; 2351 2352 /* Paranoia: check whether the PHY supports 1394a, too. */ 2353 enable_1394a = false; 2354 ret = read_phy_reg(ohci, 2); 2355 if (ret < 0) 2356 return ret; 2357 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2358 ret = read_paged_phy_reg(ohci, 1, 8); 2359 if (ret < 0) 2360 return ret; 2361 if (ret >= 1) 2362 enable_1394a = true; 2363 } 2364 2365 if (ohci->quirks & QUIRK_NO_1394A) 2366 enable_1394a = false; 2367 2368 /* Configure PHY and link consistently. */ 2369 if (enable_1394a) { 2370 clear = 0; 2371 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2372 } else { 2373 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2374 set = 0; 2375 } 2376 ret = update_phy_reg(ohci, 5, clear, set); 2377 if (ret < 0) 2378 return ret; 2379 2380 if (enable_1394a) 2381 offset = OHCI1394_HCControlSet; 2382 else 2383 offset = OHCI1394_HCControlClear; 2384 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2385 2386 /* Clean up: configuration has been taken care of. */ 2387 reg_write(ohci, OHCI1394_HCControlClear, 2388 OHCI1394_HCControl_programPhyEnable); 2389 2390 return 0; 2391 } 2392 2393 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2394 { 2395 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2396 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2397 int reg, i; 2398 2399 reg = read_phy_reg(ohci, 2); 2400 if (reg < 0) 2401 return reg; 2402 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2403 return 0; 2404 2405 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2406 reg = read_paged_phy_reg(ohci, 1, i + 10); 2407 if (reg < 0) 2408 return reg; 2409 if (reg != id[i]) 2410 return 0; 2411 } 2412 return 1; 2413 } 2414 2415 static int ohci_enable(struct fw_card *card, 2416 const __be32 *config_rom, size_t length) 2417 { 2418 struct fw_ohci *ohci = fw_ohci(card); 2419 u32 lps, version, irqs; 2420 int i, ret; 2421 2422 ret = software_reset(ohci); 2423 if (ret < 0) { 2424 ohci_err(ohci, "failed to reset ohci card\n"); 2425 return ret; 2426 } 2427 2428 /* 2429 * Now enable LPS, which we need in order to start accessing 2430 * most of the registers. In fact, on some cards (ALI M5251), 2431 * accessing registers in the SClk domain without LPS enabled 2432 * will lock up the machine. Wait 50msec to make sure we have 2433 * full link enabled. However, with some cards (well, at least 2434 * a JMicron PCIe card), we have to try again sometimes. 2435 * 2436 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2437 * cannot actually use the phy at that time. These need tens of 2438 * millisecods pause between LPS write and first phy access too. 2439 */ 2440 2441 reg_write(ohci, OHCI1394_HCControlSet, 2442 OHCI1394_HCControl_LPS | 2443 OHCI1394_HCControl_postedWriteEnable); 2444 flush_writes(ohci); 2445 2446 for (lps = 0, i = 0; !lps && i < 3; i++) { 2447 msleep(50); 2448 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2449 OHCI1394_HCControl_LPS; 2450 } 2451 2452 if (!lps) { 2453 ohci_err(ohci, "failed to set Link Power Status\n"); 2454 return -EIO; 2455 } 2456 2457 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2458 ret = probe_tsb41ba3d(ohci); 2459 if (ret < 0) 2460 return ret; 2461 if (ret) 2462 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2463 else 2464 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2465 } 2466 2467 reg_write(ohci, OHCI1394_HCControlClear, 2468 OHCI1394_HCControl_noByteSwapData); 2469 2470 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2471 reg_write(ohci, OHCI1394_LinkControlSet, 2472 OHCI1394_LinkControl_cycleTimerEnable | 2473 OHCI1394_LinkControl_cycleMaster); 2474 2475 reg_write(ohci, OHCI1394_ATRetries, 2476 OHCI1394_MAX_AT_REQ_RETRIES | 2477 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2478 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2479 (200 << 16)); 2480 2481 ohci->bus_time_running = false; 2482 2483 for (i = 0; i < 32; i++) 2484 if (ohci->ir_context_support & (1 << i)) 2485 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2486 IR_CONTEXT_MULTI_CHANNEL_MODE); 2487 2488 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2489 if (version >= OHCI_VERSION_1_1) { 2490 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2491 0xfffffffe); 2492 card->broadcast_channel_auto_allocated = true; 2493 } 2494 2495 /* Get implemented bits of the priority arbitration request counter. */ 2496 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2497 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2498 reg_write(ohci, OHCI1394_FairnessControl, 0); 2499 card->priority_budget_implemented = ohci->pri_req_max != 0; 2500 2501 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2502 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2503 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2504 2505 ret = configure_1394a_enhancements(ohci); 2506 if (ret < 0) 2507 return ret; 2508 2509 /* Activate link_on bit and contender bit in our self ID packets.*/ 2510 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2511 if (ret < 0) 2512 return ret; 2513 2514 /* 2515 * When the link is not yet enabled, the atomic config rom 2516 * update mechanism described below in ohci_set_config_rom() 2517 * is not active. We have to update ConfigRomHeader and 2518 * BusOptions manually, and the write to ConfigROMmap takes 2519 * effect immediately. We tie this to the enabling of the 2520 * link, so we have a valid config rom before enabling - the 2521 * OHCI requires that ConfigROMhdr and BusOptions have valid 2522 * values before enabling. 2523 * 2524 * However, when the ConfigROMmap is written, some controllers 2525 * always read back quadlets 0 and 2 from the config rom to 2526 * the ConfigRomHeader and BusOptions registers on bus reset. 2527 * They shouldn't do that in this initial case where the link 2528 * isn't enabled. This means we have to use the same 2529 * workaround here, setting the bus header to 0 and then write 2530 * the right values in the bus reset tasklet. 2531 */ 2532 2533 if (config_rom) { 2534 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2535 &ohci->next_config_rom_bus, GFP_KERNEL); 2536 if (ohci->next_config_rom == NULL) 2537 return -ENOMEM; 2538 2539 copy_config_rom(ohci->next_config_rom, config_rom, length); 2540 } else { 2541 /* 2542 * In the suspend case, config_rom is NULL, which 2543 * means that we just reuse the old config rom. 2544 */ 2545 ohci->next_config_rom = ohci->config_rom; 2546 ohci->next_config_rom_bus = ohci->config_rom_bus; 2547 } 2548 2549 ohci->next_header = ohci->next_config_rom[0]; 2550 ohci->next_config_rom[0] = 0; 2551 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2552 reg_write(ohci, OHCI1394_BusOptions, 2553 be32_to_cpu(ohci->next_config_rom[2])); 2554 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2555 2556 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2557 2558 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2559 OHCI1394_RQPkt | OHCI1394_RSPkt | 2560 OHCI1394_isochTx | OHCI1394_isochRx | 2561 OHCI1394_postedWriteErr | 2562 OHCI1394_selfIDComplete | 2563 OHCI1394_regAccessFail | 2564 OHCI1394_cycleInconsistent | 2565 OHCI1394_unrecoverableError | 2566 OHCI1394_cycleTooLong | 2567 OHCI1394_masterIntEnable | 2568 OHCI1394_busReset; 2569 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2570 2571 reg_write(ohci, OHCI1394_HCControlSet, 2572 OHCI1394_HCControl_linkEnable | 2573 OHCI1394_HCControl_BIBimageValid); 2574 2575 reg_write(ohci, OHCI1394_LinkControlSet, 2576 OHCI1394_LinkControl_rcvSelfID | 2577 OHCI1394_LinkControl_rcvPhyPkt); 2578 2579 ar_context_run(&ohci->ar_request_ctx); 2580 ar_context_run(&ohci->ar_response_ctx); 2581 2582 flush_writes(ohci); 2583 2584 /* We are ready to go, reset bus to finish initialization. */ 2585 fw_schedule_bus_reset(&ohci->card, false, true); 2586 2587 return 0; 2588 } 2589 2590 static int ohci_set_config_rom(struct fw_card *card, 2591 const __be32 *config_rom, size_t length) 2592 { 2593 struct fw_ohci *ohci; 2594 __be32 *next_config_rom; 2595 dma_addr_t next_config_rom_bus; 2596 2597 ohci = fw_ohci(card); 2598 2599 /* 2600 * When the OHCI controller is enabled, the config rom update 2601 * mechanism is a bit tricky, but easy enough to use. See 2602 * section 5.5.6 in the OHCI specification. 2603 * 2604 * The OHCI controller caches the new config rom address in a 2605 * shadow register (ConfigROMmapNext) and needs a bus reset 2606 * for the changes to take place. When the bus reset is 2607 * detected, the controller loads the new values for the 2608 * ConfigRomHeader and BusOptions registers from the specified 2609 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2610 * shadow register. All automatically and atomically. 2611 * 2612 * Now, there's a twist to this story. The automatic load of 2613 * ConfigRomHeader and BusOptions doesn't honor the 2614 * noByteSwapData bit, so with a be32 config rom, the 2615 * controller will load be32 values in to these registers 2616 * during the atomic update, even on litte endian 2617 * architectures. The workaround we use is to put a 0 in the 2618 * header quadlet; 0 is endian agnostic and means that the 2619 * config rom isn't ready yet. In the bus reset tasklet we 2620 * then set up the real values for the two registers. 2621 * 2622 * We use ohci->lock to avoid racing with the code that sets 2623 * ohci->next_config_rom to NULL (see bus_reset_work). 2624 */ 2625 2626 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2627 &next_config_rom_bus, GFP_KERNEL); 2628 if (next_config_rom == NULL) 2629 return -ENOMEM; 2630 2631 spin_lock_irq(&ohci->lock); 2632 2633 /* 2634 * If there is not an already pending config_rom update, 2635 * push our new allocation into the ohci->next_config_rom 2636 * and then mark the local variable as null so that we 2637 * won't deallocate the new buffer. 2638 * 2639 * OTOH, if there is a pending config_rom update, just 2640 * use that buffer with the new config_rom data, and 2641 * let this routine free the unused DMA allocation. 2642 */ 2643 2644 if (ohci->next_config_rom == NULL) { 2645 ohci->next_config_rom = next_config_rom; 2646 ohci->next_config_rom_bus = next_config_rom_bus; 2647 next_config_rom = NULL; 2648 } 2649 2650 copy_config_rom(ohci->next_config_rom, config_rom, length); 2651 2652 ohci->next_header = config_rom[0]; 2653 ohci->next_config_rom[0] = 0; 2654 2655 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2656 2657 spin_unlock_irq(&ohci->lock); 2658 2659 /* If we didn't use the DMA allocation, delete it. */ 2660 if (next_config_rom != NULL) { 2661 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2662 next_config_rom_bus); 2663 } 2664 2665 /* 2666 * Now initiate a bus reset to have the changes take 2667 * effect. We clean up the old config rom memory and DMA 2668 * mappings in the bus reset tasklet, since the OHCI 2669 * controller could need to access it before the bus reset 2670 * takes effect. 2671 */ 2672 2673 fw_schedule_bus_reset(&ohci->card, true, true); 2674 2675 return 0; 2676 } 2677 2678 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2679 { 2680 struct fw_ohci *ohci = fw_ohci(card); 2681 2682 at_context_transmit(&ohci->at_request_ctx, packet); 2683 } 2684 2685 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2686 { 2687 struct fw_ohci *ohci = fw_ohci(card); 2688 2689 at_context_transmit(&ohci->at_response_ctx, packet); 2690 } 2691 2692 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2693 { 2694 struct fw_ohci *ohci = fw_ohci(card); 2695 struct context *ctx = &ohci->at_request_ctx; 2696 struct driver_data *driver_data = packet->driver_data; 2697 int ret = -ENOENT; 2698 2699 tasklet_disable_in_atomic(&ctx->tasklet); 2700 2701 if (packet->ack != 0) 2702 goto out; 2703 2704 if (packet->payload_mapped) 2705 dma_unmap_single(ohci->card.device, packet->payload_bus, 2706 packet->payload_length, DMA_TO_DEVICE); 2707 2708 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2709 driver_data->packet = NULL; 2710 packet->ack = RCODE_CANCELLED; 2711 2712 // Timestamping on behalf of the hardware. 2713 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2714 2715 packet->callback(packet, &ohci->card, packet->ack); 2716 ret = 0; 2717 out: 2718 tasklet_enable(&ctx->tasklet); 2719 2720 return ret; 2721 } 2722 2723 static int ohci_enable_phys_dma(struct fw_card *card, 2724 int node_id, int generation) 2725 { 2726 struct fw_ohci *ohci = fw_ohci(card); 2727 unsigned long flags; 2728 int n, ret = 0; 2729 2730 if (param_remote_dma) 2731 return 0; 2732 2733 /* 2734 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2735 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2736 */ 2737 2738 spin_lock_irqsave(&ohci->lock, flags); 2739 2740 if (ohci->generation != generation) { 2741 ret = -ESTALE; 2742 goto out; 2743 } 2744 2745 /* 2746 * Note, if the node ID contains a non-local bus ID, physical DMA is 2747 * enabled for _all_ nodes on remote buses. 2748 */ 2749 2750 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2751 if (n < 32) 2752 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2753 else 2754 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2755 2756 flush_writes(ohci); 2757 out: 2758 spin_unlock_irqrestore(&ohci->lock, flags); 2759 2760 return ret; 2761 } 2762 2763 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2764 { 2765 struct fw_ohci *ohci = fw_ohci(card); 2766 unsigned long flags; 2767 u32 value; 2768 2769 switch (csr_offset) { 2770 case CSR_STATE_CLEAR: 2771 case CSR_STATE_SET: 2772 if (ohci->is_root && 2773 (reg_read(ohci, OHCI1394_LinkControlSet) & 2774 OHCI1394_LinkControl_cycleMaster)) 2775 value = CSR_STATE_BIT_CMSTR; 2776 else 2777 value = 0; 2778 if (ohci->csr_state_setclear_abdicate) 2779 value |= CSR_STATE_BIT_ABDICATE; 2780 2781 return value; 2782 2783 case CSR_NODE_IDS: 2784 return reg_read(ohci, OHCI1394_NodeID) << 16; 2785 2786 case CSR_CYCLE_TIME: 2787 return get_cycle_time(ohci); 2788 2789 case CSR_BUS_TIME: 2790 /* 2791 * We might be called just after the cycle timer has wrapped 2792 * around but just before the cycle64Seconds handler, so we 2793 * better check here, too, if the bus time needs to be updated. 2794 */ 2795 spin_lock_irqsave(&ohci->lock, flags); 2796 value = update_bus_time(ohci); 2797 spin_unlock_irqrestore(&ohci->lock, flags); 2798 return value; 2799 2800 case CSR_BUSY_TIMEOUT: 2801 value = reg_read(ohci, OHCI1394_ATRetries); 2802 return (value >> 4) & 0x0ffff00f; 2803 2804 case CSR_PRIORITY_BUDGET: 2805 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2806 (ohci->pri_req_max << 8); 2807 2808 default: 2809 WARN_ON(1); 2810 return 0; 2811 } 2812 } 2813 2814 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2815 { 2816 struct fw_ohci *ohci = fw_ohci(card); 2817 unsigned long flags; 2818 2819 switch (csr_offset) { 2820 case CSR_STATE_CLEAR: 2821 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2822 reg_write(ohci, OHCI1394_LinkControlClear, 2823 OHCI1394_LinkControl_cycleMaster); 2824 flush_writes(ohci); 2825 } 2826 if (value & CSR_STATE_BIT_ABDICATE) 2827 ohci->csr_state_setclear_abdicate = false; 2828 break; 2829 2830 case CSR_STATE_SET: 2831 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2832 reg_write(ohci, OHCI1394_LinkControlSet, 2833 OHCI1394_LinkControl_cycleMaster); 2834 flush_writes(ohci); 2835 } 2836 if (value & CSR_STATE_BIT_ABDICATE) 2837 ohci->csr_state_setclear_abdicate = true; 2838 break; 2839 2840 case CSR_NODE_IDS: 2841 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2842 flush_writes(ohci); 2843 break; 2844 2845 case CSR_CYCLE_TIME: 2846 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2847 reg_write(ohci, OHCI1394_IntEventSet, 2848 OHCI1394_cycleInconsistent); 2849 flush_writes(ohci); 2850 break; 2851 2852 case CSR_BUS_TIME: 2853 spin_lock_irqsave(&ohci->lock, flags); 2854 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2855 (value & ~0x7f); 2856 spin_unlock_irqrestore(&ohci->lock, flags); 2857 break; 2858 2859 case CSR_BUSY_TIMEOUT: 2860 value = (value & 0xf) | ((value & 0xf) << 4) | 2861 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2862 reg_write(ohci, OHCI1394_ATRetries, value); 2863 flush_writes(ohci); 2864 break; 2865 2866 case CSR_PRIORITY_BUDGET: 2867 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2868 flush_writes(ohci); 2869 break; 2870 2871 default: 2872 WARN_ON(1); 2873 break; 2874 } 2875 } 2876 2877 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2878 { 2879 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2880 ctx->header_length); 2881 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2882 ctx->header_length); 2883 2884 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2885 ctx->header_length, ctx->header, 2886 ctx->base.callback_data); 2887 ctx->header_length = 0; 2888 } 2889 2890 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2891 { 2892 u32 *ctx_hdr; 2893 2894 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2895 if (ctx->base.drop_overflow_headers) 2896 return; 2897 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2898 } 2899 2900 ctx_hdr = ctx->header + ctx->header_length; 2901 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2902 2903 /* 2904 * The two iso header quadlets are byteswapped to little 2905 * endian by the controller, but we want to present them 2906 * as big endian for consistency with the bus endianness. 2907 */ 2908 if (ctx->base.header_size > 0) 2909 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2910 if (ctx->base.header_size > 4) 2911 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2912 if (ctx->base.header_size > 8) 2913 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2914 ctx->header_length += ctx->base.header_size; 2915 } 2916 2917 static int handle_ir_packet_per_buffer(struct context *context, 2918 struct descriptor *d, 2919 struct descriptor *last) 2920 { 2921 struct iso_context *ctx = 2922 container_of(context, struct iso_context, context); 2923 struct descriptor *pd; 2924 u32 buffer_dma; 2925 2926 for (pd = d; pd <= last; pd++) 2927 if (pd->transfer_status) 2928 break; 2929 if (pd > last) 2930 /* Descriptor(s) not done yet, stop iteration */ 2931 return 0; 2932 2933 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2934 d++; 2935 buffer_dma = le32_to_cpu(d->data_address); 2936 dma_sync_single_range_for_cpu(context->ohci->card.device, 2937 buffer_dma & PAGE_MASK, 2938 buffer_dma & ~PAGE_MASK, 2939 le16_to_cpu(d->req_count), 2940 DMA_FROM_DEVICE); 2941 } 2942 2943 copy_iso_headers(ctx, (u32 *) (last + 1)); 2944 2945 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2946 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2947 2948 return 1; 2949 } 2950 2951 /* d == last because each descriptor block is only a single descriptor. */ 2952 static int handle_ir_buffer_fill(struct context *context, 2953 struct descriptor *d, 2954 struct descriptor *last) 2955 { 2956 struct iso_context *ctx = 2957 container_of(context, struct iso_context, context); 2958 unsigned int req_count, res_count, completed; 2959 u32 buffer_dma; 2960 2961 req_count = le16_to_cpu(last->req_count); 2962 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2963 completed = req_count - res_count; 2964 buffer_dma = le32_to_cpu(last->data_address); 2965 2966 if (completed > 0) { 2967 ctx->mc_buffer_bus = buffer_dma; 2968 ctx->mc_completed = completed; 2969 } 2970 2971 if (res_count != 0) 2972 /* Descriptor(s) not done yet, stop iteration */ 2973 return 0; 2974 2975 dma_sync_single_range_for_cpu(context->ohci->card.device, 2976 buffer_dma & PAGE_MASK, 2977 buffer_dma & ~PAGE_MASK, 2978 completed, DMA_FROM_DEVICE); 2979 2980 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2981 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2982 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2983 2984 ctx->base.callback.mc(&ctx->base, 2985 buffer_dma + completed, 2986 ctx->base.callback_data); 2987 ctx->mc_completed = 0; 2988 } 2989 2990 return 1; 2991 } 2992 2993 static void flush_ir_buffer_fill(struct iso_context *ctx) 2994 { 2995 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2996 ctx->mc_buffer_bus & PAGE_MASK, 2997 ctx->mc_buffer_bus & ~PAGE_MASK, 2998 ctx->mc_completed, DMA_FROM_DEVICE); 2999 3000 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 3001 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3002 3003 ctx->base.callback.mc(&ctx->base, 3004 ctx->mc_buffer_bus + ctx->mc_completed, 3005 ctx->base.callback_data); 3006 ctx->mc_completed = 0; 3007 } 3008 3009 static inline void sync_it_packet_for_cpu(struct context *context, 3010 struct descriptor *pd) 3011 { 3012 __le16 control; 3013 u32 buffer_dma; 3014 3015 /* only packets beginning with OUTPUT_MORE* have data buffers */ 3016 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3017 return; 3018 3019 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 3020 pd += 2; 3021 3022 /* 3023 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 3024 * data buffer is in the context program's coherent page and must not 3025 * be synced. 3026 */ 3027 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 3028 (context->current_bus & PAGE_MASK)) { 3029 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3030 return; 3031 pd++; 3032 } 3033 3034 do { 3035 buffer_dma = le32_to_cpu(pd->data_address); 3036 dma_sync_single_range_for_cpu(context->ohci->card.device, 3037 buffer_dma & PAGE_MASK, 3038 buffer_dma & ~PAGE_MASK, 3039 le16_to_cpu(pd->req_count), 3040 DMA_TO_DEVICE); 3041 control = pd->control; 3042 pd++; 3043 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3044 } 3045 3046 static int handle_it_packet(struct context *context, 3047 struct descriptor *d, 3048 struct descriptor *last) 3049 { 3050 struct iso_context *ctx = 3051 container_of(context, struct iso_context, context); 3052 struct descriptor *pd; 3053 __be32 *ctx_hdr; 3054 3055 for (pd = d; pd <= last; pd++) 3056 if (pd->transfer_status) 3057 break; 3058 if (pd > last) 3059 /* Descriptor(s) not done yet, stop iteration */ 3060 return 0; 3061 3062 sync_it_packet_for_cpu(context, d); 3063 3064 if (ctx->header_length + 4 > PAGE_SIZE) { 3065 if (ctx->base.drop_overflow_headers) 3066 return 1; 3067 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3068 } 3069 3070 ctx_hdr = ctx->header + ctx->header_length; 3071 ctx->last_timestamp = le16_to_cpu(last->res_count); 3072 /* Present this value as big-endian to match the receive code */ 3073 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3074 le16_to_cpu(pd->res_count)); 3075 ctx->header_length += 4; 3076 3077 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3078 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 3079 3080 return 1; 3081 } 3082 3083 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3084 { 3085 u32 hi = channels >> 32, lo = channels; 3086 3087 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3088 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3089 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3090 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3091 ohci->mc_channels = channels; 3092 } 3093 3094 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3095 int type, int channel, size_t header_size) 3096 { 3097 struct fw_ohci *ohci = fw_ohci(card); 3098 struct iso_context *ctx; 3099 descriptor_callback_t callback; 3100 u64 *channels; 3101 u32 *mask, regs; 3102 int index, ret = -EBUSY; 3103 3104 spin_lock_irq(&ohci->lock); 3105 3106 switch (type) { 3107 case FW_ISO_CONTEXT_TRANSMIT: 3108 mask = &ohci->it_context_mask; 3109 callback = handle_it_packet; 3110 index = ffs(*mask) - 1; 3111 if (index >= 0) { 3112 *mask &= ~(1 << index); 3113 regs = OHCI1394_IsoXmitContextBase(index); 3114 ctx = &ohci->it_context_list[index]; 3115 } 3116 break; 3117 3118 case FW_ISO_CONTEXT_RECEIVE: 3119 channels = &ohci->ir_context_channels; 3120 mask = &ohci->ir_context_mask; 3121 callback = handle_ir_packet_per_buffer; 3122 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3123 if (index >= 0) { 3124 *channels &= ~(1ULL << channel); 3125 *mask &= ~(1 << index); 3126 regs = OHCI1394_IsoRcvContextBase(index); 3127 ctx = &ohci->ir_context_list[index]; 3128 } 3129 break; 3130 3131 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3132 mask = &ohci->ir_context_mask; 3133 callback = handle_ir_buffer_fill; 3134 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3135 if (index >= 0) { 3136 ohci->mc_allocated = true; 3137 *mask &= ~(1 << index); 3138 regs = OHCI1394_IsoRcvContextBase(index); 3139 ctx = &ohci->ir_context_list[index]; 3140 } 3141 break; 3142 3143 default: 3144 index = -1; 3145 ret = -ENOSYS; 3146 } 3147 3148 spin_unlock_irq(&ohci->lock); 3149 3150 if (index < 0) 3151 return ERR_PTR(ret); 3152 3153 memset(ctx, 0, sizeof(*ctx)); 3154 ctx->header_length = 0; 3155 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3156 if (ctx->header == NULL) { 3157 ret = -ENOMEM; 3158 goto out; 3159 } 3160 ret = context_init(&ctx->context, ohci, regs, callback); 3161 if (ret < 0) 3162 goto out_with_header; 3163 3164 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3165 set_multichannel_mask(ohci, 0); 3166 ctx->mc_completed = 0; 3167 } 3168 3169 return &ctx->base; 3170 3171 out_with_header: 3172 free_page((unsigned long)ctx->header); 3173 out: 3174 spin_lock_irq(&ohci->lock); 3175 3176 switch (type) { 3177 case FW_ISO_CONTEXT_RECEIVE: 3178 *channels |= 1ULL << channel; 3179 break; 3180 3181 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3182 ohci->mc_allocated = false; 3183 break; 3184 } 3185 *mask |= 1 << index; 3186 3187 spin_unlock_irq(&ohci->lock); 3188 3189 return ERR_PTR(ret); 3190 } 3191 3192 static int ohci_start_iso(struct fw_iso_context *base, 3193 s32 cycle, u32 sync, u32 tags) 3194 { 3195 struct iso_context *ctx = container_of(base, struct iso_context, base); 3196 struct fw_ohci *ohci = ctx->context.ohci; 3197 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3198 int index; 3199 3200 /* the controller cannot start without any queued packets */ 3201 if (ctx->context.last->branch_address == 0) 3202 return -ENODATA; 3203 3204 switch (ctx->base.type) { 3205 case FW_ISO_CONTEXT_TRANSMIT: 3206 index = ctx - ohci->it_context_list; 3207 match = 0; 3208 if (cycle >= 0) 3209 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3210 (cycle & 0x7fff) << 16; 3211 3212 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3213 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3214 context_run(&ctx->context, match); 3215 break; 3216 3217 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3218 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3219 fallthrough; 3220 case FW_ISO_CONTEXT_RECEIVE: 3221 index = ctx - ohci->ir_context_list; 3222 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3223 if (cycle >= 0) { 3224 match |= (cycle & 0x07fff) << 12; 3225 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3226 } 3227 3228 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3229 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3230 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3231 context_run(&ctx->context, control); 3232 3233 ctx->sync = sync; 3234 ctx->tags = tags; 3235 3236 break; 3237 } 3238 3239 return 0; 3240 } 3241 3242 static int ohci_stop_iso(struct fw_iso_context *base) 3243 { 3244 struct fw_ohci *ohci = fw_ohci(base->card); 3245 struct iso_context *ctx = container_of(base, struct iso_context, base); 3246 int index; 3247 3248 switch (ctx->base.type) { 3249 case FW_ISO_CONTEXT_TRANSMIT: 3250 index = ctx - ohci->it_context_list; 3251 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3252 break; 3253 3254 case FW_ISO_CONTEXT_RECEIVE: 3255 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3256 index = ctx - ohci->ir_context_list; 3257 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3258 break; 3259 } 3260 flush_writes(ohci); 3261 context_stop(&ctx->context); 3262 tasklet_kill(&ctx->context.tasklet); 3263 3264 return 0; 3265 } 3266 3267 static void ohci_free_iso_context(struct fw_iso_context *base) 3268 { 3269 struct fw_ohci *ohci = fw_ohci(base->card); 3270 struct iso_context *ctx = container_of(base, struct iso_context, base); 3271 unsigned long flags; 3272 int index; 3273 3274 ohci_stop_iso(base); 3275 context_release(&ctx->context); 3276 free_page((unsigned long)ctx->header); 3277 3278 spin_lock_irqsave(&ohci->lock, flags); 3279 3280 switch (base->type) { 3281 case FW_ISO_CONTEXT_TRANSMIT: 3282 index = ctx - ohci->it_context_list; 3283 ohci->it_context_mask |= 1 << index; 3284 break; 3285 3286 case FW_ISO_CONTEXT_RECEIVE: 3287 index = ctx - ohci->ir_context_list; 3288 ohci->ir_context_mask |= 1 << index; 3289 ohci->ir_context_channels |= 1ULL << base->channel; 3290 break; 3291 3292 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3293 index = ctx - ohci->ir_context_list; 3294 ohci->ir_context_mask |= 1 << index; 3295 ohci->ir_context_channels |= ohci->mc_channels; 3296 ohci->mc_channels = 0; 3297 ohci->mc_allocated = false; 3298 break; 3299 } 3300 3301 spin_unlock_irqrestore(&ohci->lock, flags); 3302 } 3303 3304 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3305 { 3306 struct fw_ohci *ohci = fw_ohci(base->card); 3307 unsigned long flags; 3308 int ret; 3309 3310 switch (base->type) { 3311 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3312 3313 spin_lock_irqsave(&ohci->lock, flags); 3314 3315 /* Don't allow multichannel to grab other contexts' channels. */ 3316 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3317 *channels = ohci->ir_context_channels; 3318 ret = -EBUSY; 3319 } else { 3320 set_multichannel_mask(ohci, *channels); 3321 ret = 0; 3322 } 3323 3324 spin_unlock_irqrestore(&ohci->lock, flags); 3325 3326 break; 3327 default: 3328 ret = -EINVAL; 3329 } 3330 3331 return ret; 3332 } 3333 3334 #ifdef CONFIG_PM 3335 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3336 { 3337 int i; 3338 struct iso_context *ctx; 3339 3340 for (i = 0 ; i < ohci->n_ir ; i++) { 3341 ctx = &ohci->ir_context_list[i]; 3342 if (ctx->context.running) 3343 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3344 } 3345 3346 for (i = 0 ; i < ohci->n_it ; i++) { 3347 ctx = &ohci->it_context_list[i]; 3348 if (ctx->context.running) 3349 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3350 } 3351 } 3352 #endif 3353 3354 static int queue_iso_transmit(struct iso_context *ctx, 3355 struct fw_iso_packet *packet, 3356 struct fw_iso_buffer *buffer, 3357 unsigned long payload) 3358 { 3359 struct descriptor *d, *last, *pd; 3360 struct fw_iso_packet *p; 3361 __le32 *header; 3362 dma_addr_t d_bus, page_bus; 3363 u32 z, header_z, payload_z, irq; 3364 u32 payload_index, payload_end_index, next_page_index; 3365 int page, end_page, i, length, offset; 3366 3367 p = packet; 3368 payload_index = payload; 3369 3370 if (p->skip) 3371 z = 1; 3372 else 3373 z = 2; 3374 if (p->header_length > 0) 3375 z++; 3376 3377 /* Determine the first page the payload isn't contained in. */ 3378 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3379 if (p->payload_length > 0) 3380 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3381 else 3382 payload_z = 0; 3383 3384 z += payload_z; 3385 3386 /* Get header size in number of descriptors. */ 3387 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3388 3389 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3390 if (d == NULL) 3391 return -ENOMEM; 3392 3393 if (!p->skip) { 3394 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3395 d[0].req_count = cpu_to_le16(8); 3396 /* 3397 * Link the skip address to this descriptor itself. This causes 3398 * a context to skip a cycle whenever lost cycles or FIFO 3399 * overruns occur, without dropping the data. The application 3400 * should then decide whether this is an error condition or not. 3401 * FIXME: Make the context's cycle-lost behaviour configurable? 3402 */ 3403 d[0].branch_address = cpu_to_le32(d_bus | z); 3404 3405 header = (__le32 *) &d[1]; 3406 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3407 IT_HEADER_TAG(p->tag) | 3408 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3409 IT_HEADER_CHANNEL(ctx->base.channel) | 3410 IT_HEADER_SPEED(ctx->base.speed)); 3411 header[1] = 3412 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3413 p->payload_length)); 3414 } 3415 3416 if (p->header_length > 0) { 3417 d[2].req_count = cpu_to_le16(p->header_length); 3418 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3419 memcpy(&d[z], p->header, p->header_length); 3420 } 3421 3422 pd = d + z - payload_z; 3423 payload_end_index = payload_index + p->payload_length; 3424 for (i = 0; i < payload_z; i++) { 3425 page = payload_index >> PAGE_SHIFT; 3426 offset = payload_index & ~PAGE_MASK; 3427 next_page_index = (page + 1) << PAGE_SHIFT; 3428 length = 3429 min(next_page_index, payload_end_index) - payload_index; 3430 pd[i].req_count = cpu_to_le16(length); 3431 3432 page_bus = page_private(buffer->pages[page]); 3433 pd[i].data_address = cpu_to_le32(page_bus + offset); 3434 3435 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3436 page_bus, offset, length, 3437 DMA_TO_DEVICE); 3438 3439 payload_index += length; 3440 } 3441 3442 if (p->interrupt) 3443 irq = DESCRIPTOR_IRQ_ALWAYS; 3444 else 3445 irq = DESCRIPTOR_NO_IRQ; 3446 3447 last = z == 2 ? d : d + z - 1; 3448 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3449 DESCRIPTOR_STATUS | 3450 DESCRIPTOR_BRANCH_ALWAYS | 3451 irq); 3452 3453 context_append(&ctx->context, d, z, header_z); 3454 3455 return 0; 3456 } 3457 3458 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3459 struct fw_iso_packet *packet, 3460 struct fw_iso_buffer *buffer, 3461 unsigned long payload) 3462 { 3463 struct device *device = ctx->context.ohci->card.device; 3464 struct descriptor *d, *pd; 3465 dma_addr_t d_bus, page_bus; 3466 u32 z, header_z, rest; 3467 int i, j, length; 3468 int page, offset, packet_count, header_size, payload_per_buffer; 3469 3470 /* 3471 * The OHCI controller puts the isochronous header and trailer in the 3472 * buffer, so we need at least 8 bytes. 3473 */ 3474 packet_count = packet->header_length / ctx->base.header_size; 3475 header_size = max(ctx->base.header_size, (size_t)8); 3476 3477 /* Get header size in number of descriptors. */ 3478 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3479 page = payload >> PAGE_SHIFT; 3480 offset = payload & ~PAGE_MASK; 3481 payload_per_buffer = packet->payload_length / packet_count; 3482 3483 for (i = 0; i < packet_count; i++) { 3484 /* d points to the header descriptor */ 3485 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3486 d = context_get_descriptors(&ctx->context, 3487 z + header_z, &d_bus); 3488 if (d == NULL) 3489 return -ENOMEM; 3490 3491 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3492 DESCRIPTOR_INPUT_MORE); 3493 if (packet->skip && i == 0) 3494 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3495 d->req_count = cpu_to_le16(header_size); 3496 d->res_count = d->req_count; 3497 d->transfer_status = 0; 3498 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3499 3500 rest = payload_per_buffer; 3501 pd = d; 3502 for (j = 1; j < z; j++) { 3503 pd++; 3504 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3505 DESCRIPTOR_INPUT_MORE); 3506 3507 if (offset + rest < PAGE_SIZE) 3508 length = rest; 3509 else 3510 length = PAGE_SIZE - offset; 3511 pd->req_count = cpu_to_le16(length); 3512 pd->res_count = pd->req_count; 3513 pd->transfer_status = 0; 3514 3515 page_bus = page_private(buffer->pages[page]); 3516 pd->data_address = cpu_to_le32(page_bus + offset); 3517 3518 dma_sync_single_range_for_device(device, page_bus, 3519 offset, length, 3520 DMA_FROM_DEVICE); 3521 3522 offset = (offset + length) & ~PAGE_MASK; 3523 rest -= length; 3524 if (offset == 0) 3525 page++; 3526 } 3527 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3528 DESCRIPTOR_INPUT_LAST | 3529 DESCRIPTOR_BRANCH_ALWAYS); 3530 if (packet->interrupt && i == packet_count - 1) 3531 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3532 3533 context_append(&ctx->context, d, z, header_z); 3534 } 3535 3536 return 0; 3537 } 3538 3539 static int queue_iso_buffer_fill(struct iso_context *ctx, 3540 struct fw_iso_packet *packet, 3541 struct fw_iso_buffer *buffer, 3542 unsigned long payload) 3543 { 3544 struct descriptor *d; 3545 dma_addr_t d_bus, page_bus; 3546 int page, offset, rest, z, i, length; 3547 3548 page = payload >> PAGE_SHIFT; 3549 offset = payload & ~PAGE_MASK; 3550 rest = packet->payload_length; 3551 3552 /* We need one descriptor for each page in the buffer. */ 3553 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3554 3555 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3556 return -EFAULT; 3557 3558 for (i = 0; i < z; i++) { 3559 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3560 if (d == NULL) 3561 return -ENOMEM; 3562 3563 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3564 DESCRIPTOR_BRANCH_ALWAYS); 3565 if (packet->skip && i == 0) 3566 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3567 if (packet->interrupt && i == z - 1) 3568 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3569 3570 if (offset + rest < PAGE_SIZE) 3571 length = rest; 3572 else 3573 length = PAGE_SIZE - offset; 3574 d->req_count = cpu_to_le16(length); 3575 d->res_count = d->req_count; 3576 d->transfer_status = 0; 3577 3578 page_bus = page_private(buffer->pages[page]); 3579 d->data_address = cpu_to_le32(page_bus + offset); 3580 3581 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3582 page_bus, offset, length, 3583 DMA_FROM_DEVICE); 3584 3585 rest -= length; 3586 offset = 0; 3587 page++; 3588 3589 context_append(&ctx->context, d, 1, 0); 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int ohci_queue_iso(struct fw_iso_context *base, 3596 struct fw_iso_packet *packet, 3597 struct fw_iso_buffer *buffer, 3598 unsigned long payload) 3599 { 3600 struct iso_context *ctx = container_of(base, struct iso_context, base); 3601 unsigned long flags; 3602 int ret = -ENOSYS; 3603 3604 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3605 switch (base->type) { 3606 case FW_ISO_CONTEXT_TRANSMIT: 3607 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3608 break; 3609 case FW_ISO_CONTEXT_RECEIVE: 3610 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3611 break; 3612 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3613 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3614 break; 3615 } 3616 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3617 3618 return ret; 3619 } 3620 3621 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3622 { 3623 struct context *ctx = 3624 &container_of(base, struct iso_context, base)->context; 3625 3626 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3627 } 3628 3629 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3630 { 3631 struct iso_context *ctx = container_of(base, struct iso_context, base); 3632 int ret = 0; 3633 3634 tasklet_disable_in_atomic(&ctx->context.tasklet); 3635 3636 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3637 context_tasklet((unsigned long)&ctx->context); 3638 3639 switch (base->type) { 3640 case FW_ISO_CONTEXT_TRANSMIT: 3641 case FW_ISO_CONTEXT_RECEIVE: 3642 if (ctx->header_length != 0) 3643 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3644 break; 3645 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3646 if (ctx->mc_completed != 0) 3647 flush_ir_buffer_fill(ctx); 3648 break; 3649 default: 3650 ret = -ENOSYS; 3651 } 3652 3653 clear_bit_unlock(0, &ctx->flushing_completions); 3654 smp_mb__after_atomic(); 3655 } 3656 3657 tasklet_enable(&ctx->context.tasklet); 3658 3659 return ret; 3660 } 3661 3662 static const struct fw_card_driver ohci_driver = { 3663 .enable = ohci_enable, 3664 .read_phy_reg = ohci_read_phy_reg, 3665 .update_phy_reg = ohci_update_phy_reg, 3666 .set_config_rom = ohci_set_config_rom, 3667 .send_request = ohci_send_request, 3668 .send_response = ohci_send_response, 3669 .cancel_packet = ohci_cancel_packet, 3670 .enable_phys_dma = ohci_enable_phys_dma, 3671 .read_csr = ohci_read_csr, 3672 .write_csr = ohci_write_csr, 3673 3674 .allocate_iso_context = ohci_allocate_iso_context, 3675 .free_iso_context = ohci_free_iso_context, 3676 .set_iso_channels = ohci_set_iso_channels, 3677 .queue_iso = ohci_queue_iso, 3678 .flush_queue_iso = ohci_flush_queue_iso, 3679 .flush_iso_completions = ohci_flush_iso_completions, 3680 .start_iso = ohci_start_iso, 3681 .stop_iso = ohci_stop_iso, 3682 }; 3683 3684 #ifdef CONFIG_PPC_PMAC 3685 static void pmac_ohci_on(struct pci_dev *dev) 3686 { 3687 if (machine_is(powermac)) { 3688 struct device_node *ofn = pci_device_to_OF_node(dev); 3689 3690 if (ofn) { 3691 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3692 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3693 } 3694 } 3695 } 3696 3697 static void pmac_ohci_off(struct pci_dev *dev) 3698 { 3699 if (machine_is(powermac)) { 3700 struct device_node *ofn = pci_device_to_OF_node(dev); 3701 3702 if (ofn) { 3703 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3704 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3705 } 3706 } 3707 } 3708 #else 3709 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3710 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3711 #endif /* CONFIG_PPC_PMAC */ 3712 3713 static void release_ohci(struct device *dev, void *data) 3714 { 3715 struct pci_dev *pdev = to_pci_dev(dev); 3716 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3717 3718 pmac_ohci_off(pdev); 3719 3720 ar_context_release(&ohci->ar_response_ctx); 3721 ar_context_release(&ohci->ar_request_ctx); 3722 3723 dev_notice(dev, "removed fw-ohci device\n"); 3724 } 3725 3726 static int pci_probe(struct pci_dev *dev, 3727 const struct pci_device_id *ent) 3728 { 3729 struct fw_ohci *ohci; 3730 u32 bus_options, max_receive, link_speed, version; 3731 u64 guid; 3732 int i, flags, irq, err; 3733 size_t size; 3734 3735 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3736 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3737 return -ENOSYS; 3738 } 3739 3740 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3741 if (ohci == NULL) 3742 return -ENOMEM; 3743 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3744 pci_set_drvdata(dev, ohci); 3745 pmac_ohci_on(dev); 3746 devres_add(&dev->dev, ohci); 3747 3748 err = pcim_enable_device(dev); 3749 if (err) { 3750 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3751 return err; 3752 } 3753 3754 pci_set_master(dev); 3755 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3756 3757 spin_lock_init(&ohci->lock); 3758 mutex_init(&ohci->phy_reg_mutex); 3759 3760 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3761 3762 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3763 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3764 ohci_err(ohci, "invalid MMIO resource\n"); 3765 return -ENXIO; 3766 } 3767 3768 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3769 if (err) { 3770 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3771 return -ENXIO; 3772 } 3773 ohci->registers = pcim_iomap_table(dev)[0]; 3774 3775 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3776 if ((ohci_quirks[i].vendor == dev->vendor) && 3777 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3778 ohci_quirks[i].device == dev->device) && 3779 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3780 ohci_quirks[i].revision >= dev->revision)) { 3781 ohci->quirks = ohci_quirks[i].flags; 3782 break; 3783 } 3784 if (param_quirks) 3785 ohci->quirks = param_quirks; 3786 3787 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3788 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3789 3790 /* 3791 * Because dma_alloc_coherent() allocates at least one page, 3792 * we save space by using a common buffer for the AR request/ 3793 * response descriptors and the self IDs buffer. 3794 */ 3795 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3796 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3797 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3798 GFP_KERNEL); 3799 if (!ohci->misc_buffer) 3800 return -ENOMEM; 3801 3802 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3803 OHCI1394_AsReqRcvContextControlSet); 3804 if (err < 0) 3805 return err; 3806 3807 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3808 OHCI1394_AsRspRcvContextControlSet); 3809 if (err < 0) 3810 return err; 3811 3812 err = context_init(&ohci->at_request_ctx, ohci, 3813 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3814 if (err < 0) 3815 return err; 3816 3817 err = context_init(&ohci->at_response_ctx, ohci, 3818 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3819 if (err < 0) 3820 return err; 3821 3822 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3823 ohci->ir_context_channels = ~0ULL; 3824 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3825 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3826 ohci->ir_context_mask = ohci->ir_context_support; 3827 ohci->n_ir = hweight32(ohci->ir_context_mask); 3828 size = sizeof(struct iso_context) * ohci->n_ir; 3829 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3830 if (!ohci->ir_context_list) 3831 return -ENOMEM; 3832 3833 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3834 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3835 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3836 if (!ohci->it_context_support) { 3837 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3838 ohci->it_context_support = 0xf; 3839 } 3840 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3841 ohci->it_context_mask = ohci->it_context_support; 3842 ohci->n_it = hweight32(ohci->it_context_mask); 3843 size = sizeof(struct iso_context) * ohci->n_it; 3844 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3845 if (!ohci->it_context_list) 3846 return -ENOMEM; 3847 3848 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3849 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3850 3851 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3852 max_receive = (bus_options >> 12) & 0xf; 3853 link_speed = bus_options & 0x7; 3854 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3855 reg_read(ohci, OHCI1394_GUIDLo); 3856 3857 flags = PCI_IRQ_INTX; 3858 if (!(ohci->quirks & QUIRK_NO_MSI)) 3859 flags |= PCI_IRQ_MSI; 3860 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3861 if (err < 0) 3862 return err; 3863 irq = pci_irq_vector(dev, 0); 3864 if (irq < 0) { 3865 err = irq; 3866 goto fail_msi; 3867 } 3868 3869 err = request_threaded_irq(irq, irq_handler, NULL, 3870 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3871 ohci); 3872 if (err < 0) { 3873 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3874 goto fail_msi; 3875 } 3876 3877 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3878 if (err) 3879 goto fail_irq; 3880 3881 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3882 ohci_notice(ohci, 3883 "added OHCI v%x.%x device as card %d, " 3884 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3885 version >> 16, version & 0xff, ohci->card.index, 3886 ohci->n_ir, ohci->n_it, ohci->quirks, 3887 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3888 ", physUB" : ""); 3889 3890 return 0; 3891 3892 fail_irq: 3893 free_irq(irq, ohci); 3894 fail_msi: 3895 pci_free_irq_vectors(dev); 3896 3897 return err; 3898 } 3899 3900 static void pci_remove(struct pci_dev *dev) 3901 { 3902 struct fw_ohci *ohci = pci_get_drvdata(dev); 3903 int irq; 3904 3905 /* 3906 * If the removal is happening from the suspend state, LPS won't be 3907 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3908 */ 3909 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3910 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3911 flush_writes(ohci); 3912 } 3913 cancel_work_sync(&ohci->bus_reset_work); 3914 fw_core_remove_card(&ohci->card); 3915 3916 /* 3917 * FIXME: Fail all pending packets here, now that the upper 3918 * layers can't queue any more. 3919 */ 3920 3921 software_reset(ohci); 3922 3923 irq = pci_irq_vector(dev, 0); 3924 if (irq >= 0) 3925 free_irq(irq, ohci); 3926 pci_free_irq_vectors(dev); 3927 3928 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3929 } 3930 3931 #ifdef CONFIG_PM 3932 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3933 { 3934 struct fw_ohci *ohci = pci_get_drvdata(dev); 3935 int err; 3936 3937 software_reset(ohci); 3938 err = pci_save_state(dev); 3939 if (err) { 3940 ohci_err(ohci, "pci_save_state failed\n"); 3941 return err; 3942 } 3943 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3944 if (err) 3945 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3946 pmac_ohci_off(dev); 3947 3948 return 0; 3949 } 3950 3951 static int pci_resume(struct pci_dev *dev) 3952 { 3953 struct fw_ohci *ohci = pci_get_drvdata(dev); 3954 int err; 3955 3956 pmac_ohci_on(dev); 3957 pci_set_power_state(dev, PCI_D0); 3958 pci_restore_state(dev); 3959 err = pci_enable_device(dev); 3960 if (err) { 3961 ohci_err(ohci, "pci_enable_device failed\n"); 3962 return err; 3963 } 3964 3965 /* Some systems don't setup GUID register on resume from ram */ 3966 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3967 !reg_read(ohci, OHCI1394_GUIDHi)) { 3968 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3969 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3970 } 3971 3972 err = ohci_enable(&ohci->card, NULL, 0); 3973 if (err) 3974 return err; 3975 3976 ohci_resume_iso_dma(ohci); 3977 3978 return 0; 3979 } 3980 #endif 3981 3982 static const struct pci_device_id pci_table[] = { 3983 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3984 { } 3985 }; 3986 3987 MODULE_DEVICE_TABLE(pci, pci_table); 3988 3989 static struct pci_driver fw_ohci_pci_driver = { 3990 .name = ohci_driver_name, 3991 .id_table = pci_table, 3992 .probe = pci_probe, 3993 .remove = pci_remove, 3994 #ifdef CONFIG_PM 3995 .resume = pci_resume, 3996 .suspend = pci_suspend, 3997 #endif 3998 }; 3999 4000 static int __init fw_ohci_init(void) 4001 { 4002 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 4003 if (!selfid_workqueue) 4004 return -ENOMEM; 4005 4006 return pci_register_driver(&fw_ohci_pci_driver); 4007 } 4008 4009 static void __exit fw_ohci_cleanup(void) 4010 { 4011 pci_unregister_driver(&fw_ohci_pci_driver); 4012 destroy_workqueue(selfid_workqueue); 4013 } 4014 4015 module_init(fw_ohci_init); 4016 module_exit(fw_ohci_cleanup); 4017 4018 MODULE_AUTHOR("Kristian Hoegsberg <[email protected]>"); 4019 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 4020 MODULE_LICENSE("GPL"); 4021 4022 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 4023 MODULE_ALIAS("ohci1394"); 4024