1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <[email protected]> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 54 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 55 56 #define DESCRIPTOR_OUTPUT_MORE 0 57 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 58 #define DESCRIPTOR_INPUT_MORE (2 << 12) 59 #define DESCRIPTOR_INPUT_LAST (3 << 12) 60 #define DESCRIPTOR_STATUS (1 << 11) 61 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 62 #define DESCRIPTOR_PING (1 << 7) 63 #define DESCRIPTOR_YY (1 << 6) 64 #define DESCRIPTOR_NO_IRQ (0 << 4) 65 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 66 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 67 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 68 #define DESCRIPTOR_WAIT (3 << 0) 69 70 #define DESCRIPTOR_CMD (0xf << 12) 71 72 struct descriptor { 73 __le16 req_count; 74 __le16 control; 75 __le32 data_address; 76 __le32 branch_address; 77 __le16 res_count; 78 __le16 transfer_status; 79 } __aligned(16); 80 81 #define CONTROL_SET(regs) (regs) 82 #define CONTROL_CLEAR(regs) ((regs) + 4) 83 #define COMMAND_PTR(regs) ((regs) + 12) 84 #define CONTEXT_MATCH(regs) ((regs) + 16) 85 86 #define AR_BUFFER_SIZE (32*1024) 87 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 88 /* we need at least two pages for proper list management */ 89 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 90 91 #define MAX_ASYNC_PAYLOAD 4096 92 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 93 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 94 95 struct ar_context { 96 struct fw_ohci *ohci; 97 struct page *pages[AR_BUFFERS]; 98 void *buffer; 99 struct descriptor *descriptors; 100 dma_addr_t descriptors_bus; 101 void *pointer; 102 unsigned int last_buffer_index; 103 u32 regs; 104 struct tasklet_struct tasklet; 105 }; 106 107 struct context; 108 109 typedef int (*descriptor_callback_t)(struct context *ctx, 110 struct descriptor *d, 111 struct descriptor *last); 112 113 /* 114 * A buffer that contains a block of DMA-able coherent memory used for 115 * storing a portion of a DMA descriptor program. 116 */ 117 struct descriptor_buffer { 118 struct list_head list; 119 dma_addr_t buffer_bus; 120 size_t buffer_size; 121 size_t used; 122 struct descriptor buffer[]; 123 }; 124 125 struct context { 126 struct fw_ohci *ohci; 127 u32 regs; 128 int total_allocation; 129 u32 current_bus; 130 bool running; 131 bool flushing; 132 133 /* 134 * List of page-sized buffers for storing DMA descriptors. 135 * Head of list contains buffers in use and tail of list contains 136 * free buffers. 137 */ 138 struct list_head buffer_list; 139 140 /* 141 * Pointer to a buffer inside buffer_list that contains the tail 142 * end of the current DMA program. 143 */ 144 struct descriptor_buffer *buffer_tail; 145 146 /* 147 * The descriptor containing the branch address of the first 148 * descriptor that has not yet been filled by the device. 149 */ 150 struct descriptor *last; 151 152 /* 153 * The last descriptor block in the DMA program. It contains the branch 154 * address that must be updated upon appending a new descriptor. 155 */ 156 struct descriptor *prev; 157 int prev_z; 158 159 descriptor_callback_t callback; 160 161 struct tasklet_struct tasklet; 162 }; 163 164 struct iso_context { 165 struct fw_iso_context base; 166 struct context context; 167 void *header; 168 size_t header_length; 169 unsigned long flushing_completions; 170 u32 mc_buffer_bus; 171 u16 mc_completed; 172 u16 last_timestamp; 173 u8 sync; 174 u8 tags; 175 }; 176 177 #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) 178 179 struct fw_ohci { 180 struct fw_card card; 181 182 __iomem char *registers; 183 int node_id; 184 int generation; 185 int request_generation; /* for timestamping incoming requests */ 186 unsigned quirks; 187 unsigned int pri_req_max; 188 u32 bus_time; 189 bool bus_time_running; 190 bool is_root; 191 bool csr_state_setclear_abdicate; 192 int n_ir; 193 int n_it; 194 /* 195 * Spinlock for accessing fw_ohci data. Never call out of 196 * this driver with this lock held. 197 */ 198 spinlock_t lock; 199 200 struct mutex phy_reg_mutex; 201 202 void *misc_buffer; 203 dma_addr_t misc_buffer_bus; 204 205 struct ar_context ar_request_ctx; 206 struct ar_context ar_response_ctx; 207 struct context at_request_ctx; 208 struct context at_response_ctx; 209 210 u32 it_context_support; 211 u32 it_context_mask; /* unoccupied IT contexts */ 212 struct iso_context *it_context_list; 213 u64 ir_context_channels; /* unoccupied channels */ 214 u32 ir_context_support; 215 u32 ir_context_mask; /* unoccupied IR contexts */ 216 struct iso_context *ir_context_list; 217 u64 mc_channels; /* channels in use by the multichannel IR context */ 218 bool mc_allocated; 219 220 __be32 *config_rom; 221 dma_addr_t config_rom_bus; 222 __be32 *next_config_rom; 223 dma_addr_t next_config_rom_bus; 224 __be32 next_header; 225 226 __le32 *self_id; 227 dma_addr_t self_id_bus; 228 struct work_struct bus_reset_work; 229 230 u32 self_id_buffer[512]; 231 }; 232 233 static struct workqueue_struct *selfid_workqueue; 234 235 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 236 { 237 return container_of(card, struct fw_ohci, card); 238 } 239 240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 241 #define IR_CONTEXT_BUFFER_FILL 0x80000000 242 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 244 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 245 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 246 247 #define CONTEXT_RUN 0x8000 248 #define CONTEXT_WAKE 0x1000 249 #define CONTEXT_DEAD 0x0800 250 #define CONTEXT_ACTIVE 0x0400 251 252 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 253 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 254 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 255 256 #define OHCI1394_REGISTER_SIZE 0x800 257 #define OHCI1394_PCI_HCI_Control 0x40 258 #define SELF_ID_BUF_SIZE 0x800 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 271 #define PCI_REV_ID_VIA_VT6306 0x46 272 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274 #define QUIRK_CYCLE_TIMER 0x1 275 #define QUIRK_RESET_PACKET 0x2 276 #define QUIRK_BE_HEADERS 0x4 277 #define QUIRK_NO_1394A 0x8 278 #define QUIRK_NO_MSI 0x10 279 #define QUIRK_TI_SLLZ059 0x20 280 #define QUIRK_IR_WAKE 0x40 281 282 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 283 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 284 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 285 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 286 // while it is probable due to detection of any type of PCIe error. 287 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 288 289 #if IS_ENABLED(CONFIG_X86) 290 291 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 292 { 293 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 294 } 295 296 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 297 298 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 299 { 300 const struct pci_dev *pcie_to_pci_bridge; 301 302 // Detect any type of AMD Ryzen machine. 303 if (!static_cpu_has(X86_FEATURE_ZEN)) 304 return false; 305 306 // Detect VIA VT6306/6307/6308. 307 if (pdev->vendor != PCI_VENDOR_ID_VIA) 308 return false; 309 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 310 return false; 311 312 // Detect Asmedia ASM1083/1085. 313 pcie_to_pci_bridge = pdev->bus->self; 314 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 315 return false; 316 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 317 return false; 318 319 return true; 320 } 321 322 #else 323 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 324 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 325 #endif 326 327 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 328 static const struct { 329 unsigned short vendor, device, revision, flags; 330 } ohci_quirks[] = { 331 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER}, 333 334 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 335 QUIRK_BE_HEADERS}, 336 337 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 338 QUIRK_NO_MSI}, 339 340 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 341 QUIRK_RESET_PACKET}, 342 343 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 344 QUIRK_NO_MSI}, 345 346 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 347 QUIRK_CYCLE_TIMER}, 348 349 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 350 QUIRK_NO_MSI}, 351 352 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 353 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 354 355 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 356 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 357 358 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 359 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 360 361 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 362 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 363 364 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 365 QUIRK_RESET_PACKET}, 366 367 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 368 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 369 370 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 371 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 372 373 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 374 QUIRK_NO_MSI}, 375 376 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 377 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 378 }; 379 380 /* This overrides anything that was found in ohci_quirks[]. */ 381 static int param_quirks; 382 module_param_named(quirks, param_quirks, int, 0644); 383 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 384 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 385 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 386 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 387 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 388 ", disable MSI = " __stringify(QUIRK_NO_MSI) 389 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 390 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 391 ")"); 392 393 #define OHCI_PARAM_DEBUG_AT_AR 1 394 #define OHCI_PARAM_DEBUG_SELFIDS 2 395 #define OHCI_PARAM_DEBUG_IRQS 4 396 397 static int param_debug; 398 module_param_named(debug, param_debug, int, 0644); 399 MODULE_PARM_DESC(debug, "Verbose logging, deprecated in v6.11 kernel or later. (default = 0" 400 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 401 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 402 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 403 ", or a combination, or all = -1)"); 404 405 static bool param_remote_dma; 406 module_param_named(remote_dma, param_remote_dma, bool, 0444); 407 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 408 409 static void log_irqs(struct fw_ohci *ohci, u32 evt) 410 { 411 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 412 return; 413 414 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 415 evt & OHCI1394_selfIDComplete ? " selfID" : "", 416 evt & OHCI1394_RQPkt ? " AR_req" : "", 417 evt & OHCI1394_RSPkt ? " AR_resp" : "", 418 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 419 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 420 evt & OHCI1394_isochRx ? " IR" : "", 421 evt & OHCI1394_isochTx ? " IT" : "", 422 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 423 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 424 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 425 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 426 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 427 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 428 evt & OHCI1394_busReset ? " busReset" : "", 429 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 430 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 431 OHCI1394_respTxComplete | OHCI1394_isochRx | 432 OHCI1394_isochTx | OHCI1394_postedWriteErr | 433 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 434 OHCI1394_cycleInconsistent | 435 OHCI1394_regAccessFail | OHCI1394_busReset) 436 ? " ?" : ""); 437 } 438 439 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 440 { 441 static const char *const speed[] = { 442 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 443 }; 444 static const char *const power[] = { 445 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 446 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 447 }; 448 static const char port[] = { 449 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 450 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 451 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 452 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 453 }; 454 struct self_id_sequence_enumerator enumerator = { 455 .cursor = ohci->self_id_buffer, 456 .quadlet_count = self_id_count, 457 }; 458 459 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 460 return; 461 462 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 463 self_id_count, generation, ohci->node_id); 464 465 while (enumerator.quadlet_count > 0) { 466 unsigned int quadlet_count; 467 unsigned int port_index; 468 const u32 *s; 469 int i; 470 471 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 472 if (IS_ERR(s)) 473 break; 474 475 ohci_notice(ohci, 476 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 477 *s, 478 phy_packet_self_id_get_phy_id(*s), 479 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 480 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 481 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 482 speed[*s >> 14 & 3], *s >> 16 & 63, 483 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 484 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 485 486 port_index = 3; 487 for (i = 1; i < quadlet_count; ++i) { 488 ohci_notice(ohci, 489 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 490 s[i], 491 phy_packet_self_id_get_phy_id(s[i]), 492 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 493 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 494 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 495 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 496 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 497 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 498 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 499 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 500 ); 501 502 port_index += 8; 503 } 504 } 505 } 506 507 static const char *evts[] = { 508 [0x00] = "evt_no_status", [0x01] = "-reserved-", 509 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 510 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 511 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 512 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 513 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 514 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 515 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 516 [0x10] = "-reserved-", [0x11] = "ack_complete", 517 [0x12] = "ack_pending ", [0x13] = "-reserved-", 518 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 519 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 520 [0x18] = "-reserved-", [0x19] = "-reserved-", 521 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 522 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 523 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 524 [0x20] = "pending/cancelled", 525 }; 526 527 static void log_ar_at_event(struct fw_ohci *ohci, 528 char dir, int speed, u32 *header, int evt) 529 { 530 static const char *const tcodes[] = { 531 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 532 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 533 [TCODE_WRITE_RESPONSE] = "W resp", 534 [0x3] = "-reserved-", 535 [TCODE_READ_QUADLET_REQUEST] = "QR req", 536 [TCODE_READ_BLOCK_REQUEST] = "BR req", 537 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 538 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 539 [TCODE_CYCLE_START] = "cycle start", 540 [TCODE_LOCK_REQUEST] = "Lk req", 541 [TCODE_STREAM_DATA] = "async stream packet", 542 [TCODE_LOCK_RESPONSE] = "Lk resp", 543 [0xc] = "-reserved-", 544 [0xd] = "-reserved-", 545 [TCODE_LINK_INTERNAL] = "link internal", 546 [0xf] = "-reserved-", 547 }; 548 int tcode = async_header_get_tcode(header); 549 char specific[12]; 550 551 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 552 return; 553 554 if (unlikely(evt >= ARRAY_SIZE(evts))) 555 evt = 0x1f; 556 557 if (evt == OHCI1394_evt_bus_reset) { 558 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 559 dir, (header[2] >> 16) & 0xff); 560 return; 561 } 562 563 switch (tcode) { 564 case TCODE_WRITE_QUADLET_REQUEST: 565 case TCODE_READ_QUADLET_RESPONSE: 566 case TCODE_CYCLE_START: 567 snprintf(specific, sizeof(specific), " = %08x", 568 be32_to_cpu((__force __be32)header[3])); 569 break; 570 case TCODE_WRITE_BLOCK_REQUEST: 571 case TCODE_READ_BLOCK_REQUEST: 572 case TCODE_READ_BLOCK_RESPONSE: 573 case TCODE_LOCK_REQUEST: 574 case TCODE_LOCK_RESPONSE: 575 snprintf(specific, sizeof(specific), " %x,%x", 576 async_header_get_data_length(header), 577 async_header_get_extended_tcode(header)); 578 break; 579 default: 580 specific[0] = '\0'; 581 } 582 583 switch (tcode) { 584 case TCODE_STREAM_DATA: 585 ohci_notice(ohci, "A%c %s, %s\n", 586 dir, evts[evt], tcodes[tcode]); 587 break; 588 case TCODE_LINK_INTERNAL: 589 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 590 dir, evts[evt], header[1], header[2]); 591 break; 592 case TCODE_WRITE_QUADLET_REQUEST: 593 case TCODE_WRITE_BLOCK_REQUEST: 594 case TCODE_READ_QUADLET_REQUEST: 595 case TCODE_READ_BLOCK_REQUEST: 596 case TCODE_LOCK_REQUEST: 597 ohci_notice(ohci, 598 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 599 dir, speed, async_header_get_tlabel(header), 600 async_header_get_source(header), async_header_get_destination(header), 601 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 602 break; 603 default: 604 ohci_notice(ohci, 605 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 606 dir, speed, async_header_get_tlabel(header), 607 async_header_get_source(header), async_header_get_destination(header), 608 evts[evt], tcodes[tcode], specific); 609 } 610 } 611 612 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 613 { 614 writel(data, ohci->registers + offset); 615 } 616 617 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 618 { 619 return readl(ohci->registers + offset); 620 } 621 622 static inline void flush_writes(const struct fw_ohci *ohci) 623 { 624 /* Do a dummy read to flush writes. */ 625 reg_read(ohci, OHCI1394_Version); 626 } 627 628 /* 629 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 630 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 631 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 632 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 633 */ 634 static int read_phy_reg(struct fw_ohci *ohci, int addr) 635 { 636 u32 val; 637 int i; 638 639 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 640 for (i = 0; i < 3 + 100; i++) { 641 val = reg_read(ohci, OHCI1394_PhyControl); 642 if (!~val) 643 return -ENODEV; /* Card was ejected. */ 644 645 if (val & OHCI1394_PhyControl_ReadDone) 646 return OHCI1394_PhyControl_ReadData(val); 647 648 /* 649 * Try a few times without waiting. Sleeping is necessary 650 * only when the link/PHY interface is busy. 651 */ 652 if (i >= 3) 653 msleep(1); 654 } 655 ohci_err(ohci, "failed to read phy reg %d\n", addr); 656 dump_stack(); 657 658 return -EBUSY; 659 } 660 661 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 662 { 663 int i; 664 665 reg_write(ohci, OHCI1394_PhyControl, 666 OHCI1394_PhyControl_Write(addr, val)); 667 for (i = 0; i < 3 + 100; i++) { 668 val = reg_read(ohci, OHCI1394_PhyControl); 669 if (!~val) 670 return -ENODEV; /* Card was ejected. */ 671 672 if (!(val & OHCI1394_PhyControl_WritePending)) 673 return 0; 674 675 if (i >= 3) 676 msleep(1); 677 } 678 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 679 dump_stack(); 680 681 return -EBUSY; 682 } 683 684 static int update_phy_reg(struct fw_ohci *ohci, int addr, 685 int clear_bits, int set_bits) 686 { 687 int ret = read_phy_reg(ohci, addr); 688 if (ret < 0) 689 return ret; 690 691 /* 692 * The interrupt status bits are cleared by writing a one bit. 693 * Avoid clearing them unless explicitly requested in set_bits. 694 */ 695 if (addr == 5) 696 clear_bits |= PHY_INT_STATUS_BITS; 697 698 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 699 } 700 701 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 702 { 703 int ret; 704 705 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 706 if (ret < 0) 707 return ret; 708 709 return read_phy_reg(ohci, addr); 710 } 711 712 static int ohci_read_phy_reg(struct fw_card *card, int addr) 713 { 714 struct fw_ohci *ohci = fw_ohci(card); 715 716 guard(mutex)(&ohci->phy_reg_mutex); 717 718 return read_phy_reg(ohci, addr); 719 } 720 721 static int ohci_update_phy_reg(struct fw_card *card, int addr, 722 int clear_bits, int set_bits) 723 { 724 struct fw_ohci *ohci = fw_ohci(card); 725 726 guard(mutex)(&ohci->phy_reg_mutex); 727 728 return update_phy_reg(ohci, addr, clear_bits, set_bits); 729 } 730 731 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 732 { 733 return page_private(ctx->pages[i]); 734 } 735 736 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 737 { 738 struct descriptor *d; 739 740 d = &ctx->descriptors[index]; 741 d->branch_address &= cpu_to_le32(~0xf); 742 d->res_count = cpu_to_le16(PAGE_SIZE); 743 d->transfer_status = 0; 744 745 wmb(); /* finish init of new descriptors before branch_address update */ 746 d = &ctx->descriptors[ctx->last_buffer_index]; 747 d->branch_address |= cpu_to_le32(1); 748 749 ctx->last_buffer_index = index; 750 751 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 752 } 753 754 static void ar_context_release(struct ar_context *ctx) 755 { 756 struct device *dev = ctx->ohci->card.device; 757 unsigned int i; 758 759 if (!ctx->buffer) 760 return; 761 762 vunmap(ctx->buffer); 763 764 for (i = 0; i < AR_BUFFERS; i++) { 765 if (ctx->pages[i]) 766 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 767 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 768 } 769 } 770 771 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 772 { 773 struct fw_ohci *ohci = ctx->ohci; 774 775 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 776 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 777 flush_writes(ohci); 778 779 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 780 } 781 /* FIXME: restart? */ 782 } 783 784 static inline unsigned int ar_next_buffer_index(unsigned int index) 785 { 786 return (index + 1) % AR_BUFFERS; 787 } 788 789 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 790 { 791 return ar_next_buffer_index(ctx->last_buffer_index); 792 } 793 794 /* 795 * We search for the buffer that contains the last AR packet DMA data written 796 * by the controller. 797 */ 798 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 799 unsigned int *buffer_offset) 800 { 801 unsigned int i, next_i, last = ctx->last_buffer_index; 802 __le16 res_count, next_res_count; 803 804 i = ar_first_buffer_index(ctx); 805 res_count = READ_ONCE(ctx->descriptors[i].res_count); 806 807 /* A buffer that is not yet completely filled must be the last one. */ 808 while (i != last && res_count == 0) { 809 810 /* Peek at the next descriptor. */ 811 next_i = ar_next_buffer_index(i); 812 rmb(); /* read descriptors in order */ 813 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 814 /* 815 * If the next descriptor is still empty, we must stop at this 816 * descriptor. 817 */ 818 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 819 /* 820 * The exception is when the DMA data for one packet is 821 * split over three buffers; in this case, the middle 822 * buffer's descriptor might be never updated by the 823 * controller and look still empty, and we have to peek 824 * at the third one. 825 */ 826 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 827 next_i = ar_next_buffer_index(next_i); 828 rmb(); 829 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 830 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 831 goto next_buffer_is_active; 832 } 833 834 break; 835 } 836 837 next_buffer_is_active: 838 i = next_i; 839 res_count = next_res_count; 840 } 841 842 rmb(); /* read res_count before the DMA data */ 843 844 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 845 if (*buffer_offset > PAGE_SIZE) { 846 *buffer_offset = 0; 847 ar_context_abort(ctx, "corrupted descriptor"); 848 } 849 850 return i; 851 } 852 853 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 854 unsigned int end_buffer_index, 855 unsigned int end_buffer_offset) 856 { 857 unsigned int i; 858 859 i = ar_first_buffer_index(ctx); 860 while (i != end_buffer_index) { 861 dma_sync_single_for_cpu(ctx->ohci->card.device, 862 ar_buffer_bus(ctx, i), 863 PAGE_SIZE, DMA_FROM_DEVICE); 864 i = ar_next_buffer_index(i); 865 } 866 if (end_buffer_offset > 0) 867 dma_sync_single_for_cpu(ctx->ohci->card.device, 868 ar_buffer_bus(ctx, i), 869 end_buffer_offset, DMA_FROM_DEVICE); 870 } 871 872 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 873 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 874 { 875 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 876 } 877 878 static bool has_be_header_quirk(const struct fw_ohci *ohci) 879 { 880 return !!(ohci->quirks & QUIRK_BE_HEADERS); 881 } 882 #else 883 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 884 { 885 return le32_to_cpu(value); 886 } 887 888 static bool has_be_header_quirk(const struct fw_ohci *ohci) 889 { 890 return false; 891 } 892 #endif 893 894 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 895 { 896 struct fw_ohci *ohci = ctx->ohci; 897 struct fw_packet p; 898 u32 status, length, tcode; 899 int evt; 900 901 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 902 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 903 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 904 905 tcode = async_header_get_tcode(p.header); 906 switch (tcode) { 907 case TCODE_WRITE_QUADLET_REQUEST: 908 case TCODE_READ_QUADLET_RESPONSE: 909 p.header[3] = (__force __u32) buffer[3]; 910 p.header_length = 16; 911 p.payload_length = 0; 912 break; 913 914 case TCODE_READ_BLOCK_REQUEST : 915 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 916 p.header_length = 16; 917 p.payload_length = 0; 918 break; 919 920 case TCODE_WRITE_BLOCK_REQUEST: 921 case TCODE_READ_BLOCK_RESPONSE: 922 case TCODE_LOCK_REQUEST: 923 case TCODE_LOCK_RESPONSE: 924 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 925 p.header_length = 16; 926 p.payload_length = async_header_get_data_length(p.header); 927 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 928 ar_context_abort(ctx, "invalid packet length"); 929 return NULL; 930 } 931 break; 932 933 case TCODE_WRITE_RESPONSE: 934 case TCODE_READ_QUADLET_REQUEST: 935 case TCODE_LINK_INTERNAL: 936 p.header_length = 12; 937 p.payload_length = 0; 938 break; 939 940 default: 941 ar_context_abort(ctx, "invalid tcode"); 942 return NULL; 943 } 944 945 p.payload = (void *) buffer + p.header_length; 946 947 /* FIXME: What to do about evt_* errors? */ 948 length = (p.header_length + p.payload_length + 3) / 4; 949 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 950 evt = (status >> 16) & 0x1f; 951 952 p.ack = evt - 16; 953 p.speed = (status >> 21) & 0x7; 954 p.timestamp = status & 0xffff; 955 p.generation = ohci->request_generation; 956 957 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 958 959 /* 960 * Several controllers, notably from NEC and VIA, forget to 961 * write ack_complete status at PHY packet reception. 962 */ 963 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 964 p.ack = ACK_COMPLETE; 965 966 /* 967 * The OHCI bus reset handler synthesizes a PHY packet with 968 * the new generation number when a bus reset happens (see 969 * section 8.4.2.3). This helps us determine when a request 970 * was received and make sure we send the response in the same 971 * generation. We only need this for requests; for responses 972 * we use the unique tlabel for finding the matching 973 * request. 974 * 975 * Alas some chips sometimes emit bus reset packets with a 976 * wrong generation. We set the correct generation for these 977 * at a slightly incorrect time (in bus_reset_work). 978 */ 979 if (evt == OHCI1394_evt_bus_reset) { 980 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 981 ohci->request_generation = (p.header[2] >> 16) & 0xff; 982 } else if (ctx == &ohci->ar_request_ctx) { 983 fw_core_handle_request(&ohci->card, &p); 984 } else { 985 fw_core_handle_response(&ohci->card, &p); 986 } 987 988 return buffer + length + 1; 989 } 990 991 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 992 { 993 void *next; 994 995 while (p < end) { 996 next = handle_ar_packet(ctx, p); 997 if (!next) 998 return p; 999 p = next; 1000 } 1001 1002 return p; 1003 } 1004 1005 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1006 { 1007 unsigned int i; 1008 1009 i = ar_first_buffer_index(ctx); 1010 while (i != end_buffer) { 1011 dma_sync_single_for_device(ctx->ohci->card.device, 1012 ar_buffer_bus(ctx, i), 1013 PAGE_SIZE, DMA_FROM_DEVICE); 1014 ar_context_link_page(ctx, i); 1015 i = ar_next_buffer_index(i); 1016 } 1017 } 1018 1019 static void ar_context_tasklet(unsigned long data) 1020 { 1021 struct ar_context *ctx = (struct ar_context *)data; 1022 unsigned int end_buffer_index, end_buffer_offset; 1023 void *p, *end; 1024 1025 p = ctx->pointer; 1026 if (!p) 1027 return; 1028 1029 end_buffer_index = ar_search_last_active_buffer(ctx, 1030 &end_buffer_offset); 1031 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1032 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1033 1034 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1035 /* 1036 * The filled part of the overall buffer wraps around; handle 1037 * all packets up to the buffer end here. If the last packet 1038 * wraps around, its tail will be visible after the buffer end 1039 * because the buffer start pages are mapped there again. 1040 */ 1041 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1042 p = handle_ar_packets(ctx, p, buffer_end); 1043 if (p < buffer_end) 1044 goto error; 1045 /* adjust p to point back into the actual buffer */ 1046 p -= AR_BUFFERS * PAGE_SIZE; 1047 } 1048 1049 p = handle_ar_packets(ctx, p, end); 1050 if (p != end) { 1051 if (p > end) 1052 ar_context_abort(ctx, "inconsistent descriptor"); 1053 goto error; 1054 } 1055 1056 ctx->pointer = p; 1057 ar_recycle_buffers(ctx, end_buffer_index); 1058 1059 return; 1060 1061 error: 1062 ctx->pointer = NULL; 1063 } 1064 1065 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1066 unsigned int descriptors_offset, u32 regs) 1067 { 1068 struct device *dev = ohci->card.device; 1069 unsigned int i; 1070 dma_addr_t dma_addr; 1071 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1072 struct descriptor *d; 1073 1074 ctx->regs = regs; 1075 ctx->ohci = ohci; 1076 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1077 1078 for (i = 0; i < AR_BUFFERS; i++) { 1079 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1080 DMA_FROM_DEVICE, GFP_KERNEL); 1081 if (!ctx->pages[i]) 1082 goto out_of_memory; 1083 set_page_private(ctx->pages[i], dma_addr); 1084 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1085 DMA_FROM_DEVICE); 1086 } 1087 1088 for (i = 0; i < AR_BUFFERS; i++) 1089 pages[i] = ctx->pages[i]; 1090 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1091 pages[AR_BUFFERS + i] = ctx->pages[i]; 1092 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1093 if (!ctx->buffer) 1094 goto out_of_memory; 1095 1096 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1097 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1098 1099 for (i = 0; i < AR_BUFFERS; i++) { 1100 d = &ctx->descriptors[i]; 1101 d->req_count = cpu_to_le16(PAGE_SIZE); 1102 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1103 DESCRIPTOR_STATUS | 1104 DESCRIPTOR_BRANCH_ALWAYS); 1105 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1106 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1107 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1108 } 1109 1110 return 0; 1111 1112 out_of_memory: 1113 ar_context_release(ctx); 1114 1115 return -ENOMEM; 1116 } 1117 1118 static void ar_context_run(struct ar_context *ctx) 1119 { 1120 unsigned int i; 1121 1122 for (i = 0; i < AR_BUFFERS; i++) 1123 ar_context_link_page(ctx, i); 1124 1125 ctx->pointer = ctx->buffer; 1126 1127 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1128 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1129 } 1130 1131 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1132 { 1133 __le16 branch; 1134 1135 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1136 1137 /* figure out which descriptor the branch address goes in */ 1138 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1139 return d; 1140 else 1141 return d + z - 1; 1142 } 1143 1144 static void context_tasklet(unsigned long data) 1145 { 1146 struct context *ctx = (struct context *) data; 1147 struct descriptor *d, *last; 1148 u32 address; 1149 int z; 1150 struct descriptor_buffer *desc; 1151 1152 desc = list_entry(ctx->buffer_list.next, 1153 struct descriptor_buffer, list); 1154 last = ctx->last; 1155 while (last->branch_address != 0) { 1156 struct descriptor_buffer *old_desc = desc; 1157 address = le32_to_cpu(last->branch_address); 1158 z = address & 0xf; 1159 address &= ~0xf; 1160 ctx->current_bus = address; 1161 1162 /* If the branch address points to a buffer outside of the 1163 * current buffer, advance to the next buffer. */ 1164 if (address < desc->buffer_bus || 1165 address >= desc->buffer_bus + desc->used) 1166 desc = list_entry(desc->list.next, 1167 struct descriptor_buffer, list); 1168 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1169 last = find_branch_descriptor(d, z); 1170 1171 if (!ctx->callback(ctx, d, last)) 1172 break; 1173 1174 if (old_desc != desc) { 1175 // If we've advanced to the next buffer, move the previous buffer to the 1176 // free list. 1177 old_desc->used = 0; 1178 guard(spinlock_irqsave)(&ctx->ohci->lock); 1179 list_move_tail(&old_desc->list, &ctx->buffer_list); 1180 } 1181 ctx->last = last; 1182 } 1183 } 1184 1185 /* 1186 * Allocate a new buffer and add it to the list of free buffers for this 1187 * context. Must be called with ohci->lock held. 1188 */ 1189 static int context_add_buffer(struct context *ctx) 1190 { 1191 struct descriptor_buffer *desc; 1192 dma_addr_t bus_addr; 1193 int offset; 1194 1195 /* 1196 * 16MB of descriptors should be far more than enough for any DMA 1197 * program. This will catch run-away userspace or DoS attacks. 1198 */ 1199 if (ctx->total_allocation >= 16*1024*1024) 1200 return -ENOMEM; 1201 1202 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1203 if (!desc) 1204 return -ENOMEM; 1205 1206 offset = (void *)&desc->buffer - (void *)desc; 1207 /* 1208 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1209 * for descriptors, even 0x10-byte ones. This can cause page faults when 1210 * an IOMMU is in use and the oversized read crosses a page boundary. 1211 * Work around this by always leaving at least 0x10 bytes of padding. 1212 */ 1213 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1214 desc->buffer_bus = bus_addr + offset; 1215 desc->used = 0; 1216 1217 list_add_tail(&desc->list, &ctx->buffer_list); 1218 ctx->total_allocation += PAGE_SIZE; 1219 1220 return 0; 1221 } 1222 1223 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1224 u32 regs, descriptor_callback_t callback) 1225 { 1226 ctx->ohci = ohci; 1227 ctx->regs = regs; 1228 ctx->total_allocation = 0; 1229 1230 INIT_LIST_HEAD(&ctx->buffer_list); 1231 if (context_add_buffer(ctx) < 0) 1232 return -ENOMEM; 1233 1234 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1235 struct descriptor_buffer, list); 1236 1237 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1238 ctx->callback = callback; 1239 1240 /* 1241 * We put a dummy descriptor in the buffer that has a NULL 1242 * branch address and looks like it's been sent. That way we 1243 * have a descriptor to append DMA programs to. 1244 */ 1245 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1246 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1247 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1248 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1249 ctx->last = ctx->buffer_tail->buffer; 1250 ctx->prev = ctx->buffer_tail->buffer; 1251 ctx->prev_z = 1; 1252 1253 return 0; 1254 } 1255 1256 static void context_release(struct context *ctx) 1257 { 1258 struct fw_card *card = &ctx->ohci->card; 1259 struct descriptor_buffer *desc, *tmp; 1260 1261 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1262 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1263 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1264 } 1265 } 1266 1267 /* Must be called with ohci->lock held */ 1268 static struct descriptor *context_get_descriptors(struct context *ctx, 1269 int z, dma_addr_t *d_bus) 1270 { 1271 struct descriptor *d = NULL; 1272 struct descriptor_buffer *desc = ctx->buffer_tail; 1273 1274 if (z * sizeof(*d) > desc->buffer_size) 1275 return NULL; 1276 1277 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1278 /* No room for the descriptor in this buffer, so advance to the 1279 * next one. */ 1280 1281 if (desc->list.next == &ctx->buffer_list) { 1282 /* If there is no free buffer next in the list, 1283 * allocate one. */ 1284 if (context_add_buffer(ctx) < 0) 1285 return NULL; 1286 } 1287 desc = list_entry(desc->list.next, 1288 struct descriptor_buffer, list); 1289 ctx->buffer_tail = desc; 1290 } 1291 1292 d = desc->buffer + desc->used / sizeof(*d); 1293 memset(d, 0, z * sizeof(*d)); 1294 *d_bus = desc->buffer_bus + desc->used; 1295 1296 return d; 1297 } 1298 1299 static void context_run(struct context *ctx, u32 extra) 1300 { 1301 struct fw_ohci *ohci = ctx->ohci; 1302 1303 reg_write(ohci, COMMAND_PTR(ctx->regs), 1304 le32_to_cpu(ctx->last->branch_address)); 1305 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1306 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1307 ctx->running = true; 1308 flush_writes(ohci); 1309 } 1310 1311 static void context_append(struct context *ctx, 1312 struct descriptor *d, int z, int extra) 1313 { 1314 dma_addr_t d_bus; 1315 struct descriptor_buffer *desc = ctx->buffer_tail; 1316 struct descriptor *d_branch; 1317 1318 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1319 1320 desc->used += (z + extra) * sizeof(*d); 1321 1322 wmb(); /* finish init of new descriptors before branch_address update */ 1323 1324 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1325 d_branch->branch_address = cpu_to_le32(d_bus | z); 1326 1327 /* 1328 * VT6306 incorrectly checks only the single descriptor at the 1329 * CommandPtr when the wake bit is written, so if it's a 1330 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1331 * the branch address in the first descriptor. 1332 * 1333 * Not doing this for transmit contexts since not sure how it interacts 1334 * with skip addresses. 1335 */ 1336 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1337 d_branch != ctx->prev && 1338 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1339 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1340 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1341 } 1342 1343 ctx->prev = d; 1344 ctx->prev_z = z; 1345 } 1346 1347 static void context_stop(struct context *ctx) 1348 { 1349 struct fw_ohci *ohci = ctx->ohci; 1350 u32 reg; 1351 int i; 1352 1353 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1354 ctx->running = false; 1355 1356 for (i = 0; i < 1000; i++) { 1357 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1358 if ((reg & CONTEXT_ACTIVE) == 0) 1359 return; 1360 1361 if (i) 1362 udelay(10); 1363 } 1364 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1365 } 1366 1367 struct driver_data { 1368 u8 inline_data[8]; 1369 struct fw_packet *packet; 1370 }; 1371 1372 /* 1373 * This function apppends a packet to the DMA queue for transmission. 1374 * Must always be called with the ochi->lock held to ensure proper 1375 * generation handling and locking around packet queue manipulation. 1376 */ 1377 static int at_context_queue_packet(struct context *ctx, 1378 struct fw_packet *packet) 1379 { 1380 struct fw_ohci *ohci = ctx->ohci; 1381 dma_addr_t d_bus, payload_bus; 1382 struct driver_data *driver_data; 1383 struct descriptor *d, *last; 1384 __le32 *header; 1385 int z, tcode; 1386 1387 d = context_get_descriptors(ctx, 4, &d_bus); 1388 if (d == NULL) { 1389 packet->ack = RCODE_SEND_ERROR; 1390 return -1; 1391 } 1392 1393 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1394 d[0].res_count = cpu_to_le16(packet->timestamp); 1395 1396 tcode = async_header_get_tcode(packet->header); 1397 header = (__le32 *) &d[1]; 1398 switch (tcode) { 1399 case TCODE_WRITE_QUADLET_REQUEST: 1400 case TCODE_WRITE_BLOCK_REQUEST: 1401 case TCODE_WRITE_RESPONSE: 1402 case TCODE_READ_QUADLET_REQUEST: 1403 case TCODE_READ_BLOCK_REQUEST: 1404 case TCODE_READ_QUADLET_RESPONSE: 1405 case TCODE_READ_BLOCK_RESPONSE: 1406 case TCODE_LOCK_REQUEST: 1407 case TCODE_LOCK_RESPONSE: 1408 ohci1394_at_data_set_src_bus_id(header, false); 1409 ohci1394_at_data_set_speed(header, packet->speed); 1410 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1411 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1412 ohci1394_at_data_set_tcode(header, tcode); 1413 1414 ohci1394_at_data_set_destination_id(header, 1415 async_header_get_destination(packet->header)); 1416 1417 if (ctx == &ctx->ohci->at_response_ctx) { 1418 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1419 } else { 1420 ohci1394_at_data_set_destination_offset(header, 1421 async_header_get_offset(packet->header)); 1422 } 1423 1424 if (tcode_is_block_packet(tcode)) 1425 header[3] = cpu_to_le32(packet->header[3]); 1426 else 1427 header[3] = (__force __le32) packet->header[3]; 1428 1429 d[0].req_count = cpu_to_le16(packet->header_length); 1430 break; 1431 case TCODE_LINK_INTERNAL: 1432 ohci1394_at_data_set_speed(header, packet->speed); 1433 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1434 1435 header[1] = cpu_to_le32(packet->header[1]); 1436 header[2] = cpu_to_le32(packet->header[2]); 1437 d[0].req_count = cpu_to_le16(12); 1438 1439 if (is_ping_packet(&packet->header[1])) 1440 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1441 break; 1442 1443 case TCODE_STREAM_DATA: 1444 ohci1394_it_data_set_speed(header, packet->speed); 1445 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0])); 1446 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0])); 1447 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 1448 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0])); 1449 1450 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0])); 1451 1452 d[0].req_count = cpu_to_le16(8); 1453 break; 1454 1455 default: 1456 /* BUG(); */ 1457 packet->ack = RCODE_SEND_ERROR; 1458 return -1; 1459 } 1460 1461 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1462 driver_data = (struct driver_data *) &d[3]; 1463 driver_data->packet = packet; 1464 packet->driver_data = driver_data; 1465 1466 if (packet->payload_length > 0) { 1467 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1468 payload_bus = dma_map_single(ohci->card.device, 1469 packet->payload, 1470 packet->payload_length, 1471 DMA_TO_DEVICE); 1472 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1473 packet->ack = RCODE_SEND_ERROR; 1474 return -1; 1475 } 1476 packet->payload_bus = payload_bus; 1477 packet->payload_mapped = true; 1478 } else { 1479 memcpy(driver_data->inline_data, packet->payload, 1480 packet->payload_length); 1481 payload_bus = d_bus + 3 * sizeof(*d); 1482 } 1483 1484 d[2].req_count = cpu_to_le16(packet->payload_length); 1485 d[2].data_address = cpu_to_le32(payload_bus); 1486 last = &d[2]; 1487 z = 3; 1488 } else { 1489 last = &d[0]; 1490 z = 2; 1491 } 1492 1493 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1494 DESCRIPTOR_IRQ_ALWAYS | 1495 DESCRIPTOR_BRANCH_ALWAYS); 1496 1497 /* FIXME: Document how the locking works. */ 1498 if (ohci->generation != packet->generation) { 1499 if (packet->payload_mapped) 1500 dma_unmap_single(ohci->card.device, payload_bus, 1501 packet->payload_length, DMA_TO_DEVICE); 1502 packet->ack = RCODE_GENERATION; 1503 return -1; 1504 } 1505 1506 context_append(ctx, d, z, 4 - z); 1507 1508 if (ctx->running) 1509 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1510 else 1511 context_run(ctx, 0); 1512 1513 return 0; 1514 } 1515 1516 static void at_context_flush(struct context *ctx) 1517 { 1518 tasklet_disable(&ctx->tasklet); 1519 1520 ctx->flushing = true; 1521 context_tasklet((unsigned long)ctx); 1522 ctx->flushing = false; 1523 1524 tasklet_enable(&ctx->tasklet); 1525 } 1526 1527 static int handle_at_packet(struct context *context, 1528 struct descriptor *d, 1529 struct descriptor *last) 1530 { 1531 struct driver_data *driver_data; 1532 struct fw_packet *packet; 1533 struct fw_ohci *ohci = context->ohci; 1534 int evt; 1535 1536 if (last->transfer_status == 0 && !context->flushing) 1537 /* This descriptor isn't done yet, stop iteration. */ 1538 return 0; 1539 1540 driver_data = (struct driver_data *) &d[3]; 1541 packet = driver_data->packet; 1542 if (packet == NULL) 1543 /* This packet was cancelled, just continue. */ 1544 return 1; 1545 1546 if (packet->payload_mapped) 1547 dma_unmap_single(ohci->card.device, packet->payload_bus, 1548 packet->payload_length, DMA_TO_DEVICE); 1549 1550 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1551 packet->timestamp = le16_to_cpu(last->res_count); 1552 1553 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1554 1555 switch (evt) { 1556 case OHCI1394_evt_timeout: 1557 /* Async response transmit timed out. */ 1558 packet->ack = RCODE_CANCELLED; 1559 break; 1560 1561 case OHCI1394_evt_flushed: 1562 /* 1563 * The packet was flushed should give same error as 1564 * when we try to use a stale generation count. 1565 */ 1566 packet->ack = RCODE_GENERATION; 1567 break; 1568 1569 case OHCI1394_evt_missing_ack: 1570 if (context->flushing) 1571 packet->ack = RCODE_GENERATION; 1572 else { 1573 /* 1574 * Using a valid (current) generation count, but the 1575 * node is not on the bus or not sending acks. 1576 */ 1577 packet->ack = RCODE_NO_ACK; 1578 } 1579 break; 1580 1581 case ACK_COMPLETE + 0x10: 1582 case ACK_PENDING + 0x10: 1583 case ACK_BUSY_X + 0x10: 1584 case ACK_BUSY_A + 0x10: 1585 case ACK_BUSY_B + 0x10: 1586 case ACK_DATA_ERROR + 0x10: 1587 case ACK_TYPE_ERROR + 0x10: 1588 packet->ack = evt - 0x10; 1589 break; 1590 1591 case OHCI1394_evt_no_status: 1592 if (context->flushing) { 1593 packet->ack = RCODE_GENERATION; 1594 break; 1595 } 1596 fallthrough; 1597 1598 default: 1599 packet->ack = RCODE_SEND_ERROR; 1600 break; 1601 } 1602 1603 packet->callback(packet, &ohci->card, packet->ack); 1604 1605 return 1; 1606 } 1607 1608 static u32 get_cycle_time(struct fw_ohci *ohci); 1609 1610 static void handle_local_rom(struct fw_ohci *ohci, 1611 struct fw_packet *packet, u32 csr) 1612 { 1613 struct fw_packet response; 1614 int tcode, length, i; 1615 1616 tcode = async_header_get_tcode(packet->header); 1617 if (tcode_is_block_packet(tcode)) 1618 length = async_header_get_data_length(packet->header); 1619 else 1620 length = 4; 1621 1622 i = csr - CSR_CONFIG_ROM; 1623 if (i + length > CONFIG_ROM_SIZE) { 1624 fw_fill_response(&response, packet->header, 1625 RCODE_ADDRESS_ERROR, NULL, 0); 1626 } else if (!tcode_is_read_request(tcode)) { 1627 fw_fill_response(&response, packet->header, 1628 RCODE_TYPE_ERROR, NULL, 0); 1629 } else { 1630 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1631 (void *) ohci->config_rom + i, length); 1632 } 1633 1634 // Timestamping on behalf of the hardware. 1635 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1636 fw_core_handle_response(&ohci->card, &response); 1637 } 1638 1639 static void handle_local_lock(struct fw_ohci *ohci, 1640 struct fw_packet *packet, u32 csr) 1641 { 1642 struct fw_packet response; 1643 int tcode, length, ext_tcode, sel, try; 1644 __be32 *payload, lock_old; 1645 u32 lock_arg, lock_data; 1646 1647 tcode = async_header_get_tcode(packet->header); 1648 length = async_header_get_data_length(packet->header); 1649 payload = packet->payload; 1650 ext_tcode = async_header_get_extended_tcode(packet->header); 1651 1652 if (tcode == TCODE_LOCK_REQUEST && 1653 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1654 lock_arg = be32_to_cpu(payload[0]); 1655 lock_data = be32_to_cpu(payload[1]); 1656 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1657 lock_arg = 0; 1658 lock_data = 0; 1659 } else { 1660 fw_fill_response(&response, packet->header, 1661 RCODE_TYPE_ERROR, NULL, 0); 1662 goto out; 1663 } 1664 1665 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1666 reg_write(ohci, OHCI1394_CSRData, lock_data); 1667 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1668 reg_write(ohci, OHCI1394_CSRControl, sel); 1669 1670 for (try = 0; try < 20; try++) 1671 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1672 lock_old = cpu_to_be32(reg_read(ohci, 1673 OHCI1394_CSRData)); 1674 fw_fill_response(&response, packet->header, 1675 RCODE_COMPLETE, 1676 &lock_old, sizeof(lock_old)); 1677 goto out; 1678 } 1679 1680 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1681 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1682 1683 out: 1684 // Timestamping on behalf of the hardware. 1685 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1686 fw_core_handle_response(&ohci->card, &response); 1687 } 1688 1689 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1690 { 1691 u64 offset, csr; 1692 1693 if (ctx == &ctx->ohci->at_request_ctx) { 1694 packet->ack = ACK_PENDING; 1695 packet->callback(packet, &ctx->ohci->card, packet->ack); 1696 } 1697 1698 offset = async_header_get_offset(packet->header); 1699 csr = offset - CSR_REGISTER_BASE; 1700 1701 /* Handle config rom reads. */ 1702 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1703 handle_local_rom(ctx->ohci, packet, csr); 1704 else switch (csr) { 1705 case CSR_BUS_MANAGER_ID: 1706 case CSR_BANDWIDTH_AVAILABLE: 1707 case CSR_CHANNELS_AVAILABLE_HI: 1708 case CSR_CHANNELS_AVAILABLE_LO: 1709 handle_local_lock(ctx->ohci, packet, csr); 1710 break; 1711 default: 1712 if (ctx == &ctx->ohci->at_request_ctx) 1713 fw_core_handle_request(&ctx->ohci->card, packet); 1714 else 1715 fw_core_handle_response(&ctx->ohci->card, packet); 1716 break; 1717 } 1718 1719 if (ctx == &ctx->ohci->at_response_ctx) { 1720 packet->ack = ACK_COMPLETE; 1721 packet->callback(packet, &ctx->ohci->card, packet->ack); 1722 } 1723 } 1724 1725 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1726 { 1727 unsigned long flags; 1728 int ret; 1729 1730 spin_lock_irqsave(&ctx->ohci->lock, flags); 1731 1732 if (async_header_get_destination(packet->header) == ctx->ohci->node_id && 1733 ctx->ohci->generation == packet->generation) { 1734 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1735 1736 // Timestamping on behalf of the hardware. 1737 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1738 1739 handle_local_request(ctx, packet); 1740 return; 1741 } 1742 1743 ret = at_context_queue_packet(ctx, packet); 1744 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1745 1746 if (ret < 0) { 1747 // Timestamping on behalf of the hardware. 1748 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1749 1750 packet->callback(packet, &ctx->ohci->card, packet->ack); 1751 } 1752 } 1753 1754 static void detect_dead_context(struct fw_ohci *ohci, 1755 const char *name, unsigned int regs) 1756 { 1757 u32 ctl; 1758 1759 ctl = reg_read(ohci, CONTROL_SET(regs)); 1760 if (ctl & CONTEXT_DEAD) 1761 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1762 name, evts[ctl & 0x1f]); 1763 } 1764 1765 static void handle_dead_contexts(struct fw_ohci *ohci) 1766 { 1767 unsigned int i; 1768 char name[8]; 1769 1770 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1771 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1772 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1773 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1774 for (i = 0; i < 32; ++i) { 1775 if (!(ohci->it_context_support & (1 << i))) 1776 continue; 1777 sprintf(name, "IT%u", i); 1778 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1779 } 1780 for (i = 0; i < 32; ++i) { 1781 if (!(ohci->ir_context_support & (1 << i))) 1782 continue; 1783 sprintf(name, "IR%u", i); 1784 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1785 } 1786 /* TODO: maybe try to flush and restart the dead contexts */ 1787 } 1788 1789 static u32 cycle_timer_ticks(u32 cycle_timer) 1790 { 1791 u32 ticks; 1792 1793 ticks = cycle_timer & 0xfff; 1794 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1795 ticks += (3072 * 8000) * (cycle_timer >> 25); 1796 1797 return ticks; 1798 } 1799 1800 /* 1801 * Some controllers exhibit one or more of the following bugs when updating the 1802 * iso cycle timer register: 1803 * - When the lowest six bits are wrapping around to zero, a read that happens 1804 * at the same time will return garbage in the lowest ten bits. 1805 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1806 * not incremented for about 60 ns. 1807 * - Occasionally, the entire register reads zero. 1808 * 1809 * To catch these, we read the register three times and ensure that the 1810 * difference between each two consecutive reads is approximately the same, i.e. 1811 * less than twice the other. Furthermore, any negative difference indicates an 1812 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1813 * execute, so we have enough precision to compute the ratio of the differences.) 1814 */ 1815 static u32 get_cycle_time(struct fw_ohci *ohci) 1816 { 1817 u32 c0, c1, c2; 1818 u32 t0, t1, t2; 1819 s32 diff01, diff12; 1820 int i; 1821 1822 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1823 return 0; 1824 1825 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1826 1827 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1828 i = 0; 1829 c1 = c2; 1830 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1831 do { 1832 c0 = c1; 1833 c1 = c2; 1834 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1835 t0 = cycle_timer_ticks(c0); 1836 t1 = cycle_timer_ticks(c1); 1837 t2 = cycle_timer_ticks(c2); 1838 diff01 = t1 - t0; 1839 diff12 = t2 - t1; 1840 } while ((diff01 <= 0 || diff12 <= 0 || 1841 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1842 && i++ < 20); 1843 } 1844 1845 return c2; 1846 } 1847 1848 /* 1849 * This function has to be called at least every 64 seconds. The bus_time 1850 * field stores not only the upper 25 bits of the BUS_TIME register but also 1851 * the most significant bit of the cycle timer in bit 6 so that we can detect 1852 * changes in this bit. 1853 */ 1854 static u32 update_bus_time(struct fw_ohci *ohci) 1855 { 1856 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1857 1858 if (unlikely(!ohci->bus_time_running)) { 1859 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1860 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1861 (cycle_time_seconds & 0x40); 1862 ohci->bus_time_running = true; 1863 } 1864 1865 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1866 ohci->bus_time += 0x40; 1867 1868 return ohci->bus_time | cycle_time_seconds; 1869 } 1870 1871 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1872 enum phy_packet_self_id_port_status *status) 1873 { 1874 int reg; 1875 1876 scoped_guard(mutex, &ohci->phy_reg_mutex) { 1877 reg = write_phy_reg(ohci, 7, port_index); 1878 if (reg < 0) 1879 return reg; 1880 1881 reg = read_phy_reg(ohci, 8); 1882 if (reg < 0) 1883 return reg; 1884 } 1885 1886 switch (reg & 0x0f) { 1887 case 0x06: 1888 // is child node (connected to parent node) 1889 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1890 break; 1891 case 0x0e: 1892 // is parent node (connected to child node) 1893 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1894 break; 1895 default: 1896 // not connected 1897 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1898 break; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1905 int self_id_count) 1906 { 1907 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1908 int i; 1909 1910 for (i = 0; i < self_id_count; i++) { 1911 u32 entry = ohci->self_id_buffer[i]; 1912 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1913 1914 if (left_phy_id == right_phy_id) 1915 return -1; 1916 if (left_phy_id < right_phy_id) 1917 return i; 1918 } 1919 return i; 1920 } 1921 1922 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset) 1923 { 1924 int reg; 1925 1926 guard(mutex)(&ohci->phy_reg_mutex); 1927 1928 // Select page 7 1929 reg = write_phy_reg(ohci, 7, 0xe0); 1930 if (reg < 0) 1931 return reg; 1932 1933 reg = read_phy_reg(ohci, 8); 1934 if (reg < 0) 1935 return reg; 1936 1937 // set PMODE bit 1938 reg |= 0x40; 1939 reg = write_phy_reg(ohci, 8, reg); 1940 if (reg < 0) 1941 return reg; 1942 1943 // read register 12 1944 reg = read_phy_reg(ohci, 12); 1945 if (reg < 0) 1946 return reg; 1947 1948 // bit 3 indicates "initiated reset" 1949 *is_initiated_reset = !!((reg & 0x08) == 0x08); 1950 1951 return 0; 1952 } 1953 1954 /* 1955 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1956 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1957 * Construct the selfID from phy register contents. 1958 */ 1959 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1960 { 1961 int reg, i, pos, err; 1962 bool is_initiated_reset; 1963 u32 self_id = 0; 1964 1965 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 1966 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 1967 phy_packet_self_id_zero_set_link_active(&self_id, true); 1968 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 1969 phy_packet_self_id_zero_set_contender(&self_id, true); 1970 1971 reg = reg_read(ohci, OHCI1394_NodeID); 1972 if (!(reg & OHCI1394_NodeID_idValid)) { 1973 ohci_notice(ohci, 1974 "node ID not valid, new bus reset in progress\n"); 1975 return -EBUSY; 1976 } 1977 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 1978 1979 reg = ohci_read_phy_reg(&ohci->card, 4); 1980 if (reg < 0) 1981 return reg; 1982 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 1983 1984 reg = ohci_read_phy_reg(&ohci->card, 1); 1985 if (reg < 0) 1986 return reg; 1987 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 1988 1989 for (i = 0; i < 3; i++) { 1990 enum phy_packet_self_id_port_status status; 1991 1992 err = get_status_for_port(ohci, i, &status); 1993 if (err < 0) 1994 return err; 1995 1996 self_id_sequence_set_port_status(&self_id, 1, i, status); 1997 } 1998 1999 err = detect_initiated_reset(ohci, &is_initiated_reset); 2000 if (err < 0) 2001 return err; 2002 phy_packet_self_id_zero_set_initiated_reset(&self_id, is_initiated_reset); 2003 2004 pos = get_self_id_pos(ohci, self_id, self_id_count); 2005 if (pos >= 0) { 2006 memmove(&(ohci->self_id_buffer[pos+1]), 2007 &(ohci->self_id_buffer[pos]), 2008 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2009 ohci->self_id_buffer[pos] = self_id; 2010 self_id_count++; 2011 } 2012 return self_id_count; 2013 } 2014 2015 static void bus_reset_work(struct work_struct *work) 2016 { 2017 struct fw_ohci *ohci = 2018 container_of(work, struct fw_ohci, bus_reset_work); 2019 int self_id_count, generation, new_generation, i, j; 2020 u32 reg, quadlet; 2021 void *free_rom = NULL; 2022 dma_addr_t free_rom_bus = 0; 2023 bool is_new_root; 2024 2025 reg = reg_read(ohci, OHCI1394_NodeID); 2026 if (!(reg & OHCI1394_NodeID_idValid)) { 2027 ohci_notice(ohci, 2028 "node ID not valid, new bus reset in progress\n"); 2029 return; 2030 } 2031 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2032 ohci_notice(ohci, "malconfigured bus\n"); 2033 return; 2034 } 2035 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2036 OHCI1394_NodeID_nodeNumber); 2037 2038 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2039 if (!(ohci->is_root && is_new_root)) 2040 reg_write(ohci, OHCI1394_LinkControlSet, 2041 OHCI1394_LinkControl_cycleMaster); 2042 ohci->is_root = is_new_root; 2043 2044 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2045 if (ohci1394_self_id_count_is_error(reg)) { 2046 ohci_notice(ohci, "self ID receive error\n"); 2047 return; 2048 } 2049 /* 2050 * The count in the SelfIDCount register is the number of 2051 * bytes in the self ID receive buffer. Since we also receive 2052 * the inverted quadlets and a header quadlet, we shift one 2053 * bit extra to get the actual number of self IDs. 2054 */ 2055 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2056 2057 if (self_id_count > 252) { 2058 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2059 return; 2060 } 2061 2062 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2063 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2064 rmb(); 2065 2066 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2067 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2068 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2069 2070 if (id != ~id2) { 2071 /* 2072 * If the invalid data looks like a cycle start packet, 2073 * it's likely to be the result of the cycle master 2074 * having a wrong gap count. In this case, the self IDs 2075 * so far are valid and should be processed so that the 2076 * bus manager can then correct the gap count. 2077 */ 2078 if (id == 0xffff008f) { 2079 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2080 self_id_count = j; 2081 break; 2082 } 2083 2084 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2085 j, self_id_count, id, id2); 2086 return; 2087 } 2088 ohci->self_id_buffer[j] = id; 2089 } 2090 2091 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2092 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2093 if (self_id_count < 0) { 2094 ohci_notice(ohci, 2095 "could not construct local self ID\n"); 2096 return; 2097 } 2098 } 2099 2100 if (self_id_count == 0) { 2101 ohci_notice(ohci, "no self IDs\n"); 2102 return; 2103 } 2104 rmb(); 2105 2106 /* 2107 * Check the consistency of the self IDs we just read. The 2108 * problem we face is that a new bus reset can start while we 2109 * read out the self IDs from the DMA buffer. If this happens, 2110 * the DMA buffer will be overwritten with new self IDs and we 2111 * will read out inconsistent data. The OHCI specification 2112 * (section 11.2) recommends a technique similar to 2113 * linux/seqlock.h, where we remember the generation of the 2114 * self IDs in the buffer before reading them out and compare 2115 * it to the current generation after reading them out. If 2116 * the two generations match we know we have a consistent set 2117 * of self IDs. 2118 */ 2119 2120 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2121 new_generation = ohci1394_self_id_count_get_generation(reg); 2122 if (new_generation != generation) { 2123 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2124 return; 2125 } 2126 2127 // FIXME: Document how the locking works. 2128 scoped_guard(spinlock_irq, &ohci->lock) { 2129 ohci->generation = -1; // prevent AT packet queueing 2130 context_stop(&ohci->at_request_ctx); 2131 context_stop(&ohci->at_response_ctx); 2132 } 2133 2134 /* 2135 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2136 * packets in the AT queues and software needs to drain them. 2137 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2138 */ 2139 at_context_flush(&ohci->at_request_ctx); 2140 at_context_flush(&ohci->at_response_ctx); 2141 2142 scoped_guard(spinlock_irq, &ohci->lock) { 2143 ohci->generation = generation; 2144 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2145 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2146 2147 if (ohci->quirks & QUIRK_RESET_PACKET) 2148 ohci->request_generation = generation; 2149 2150 // This next bit is unrelated to the AT context stuff but we have to do it under the 2151 // spinlock also. If a new config rom was set up before this reset, the old one is 2152 // now no longer in use and we can free it. Update the config rom pointers to point 2153 // to the current config rom and clear the next_config_rom pointer so a new update 2154 // can take place. 2155 if (ohci->next_config_rom != NULL) { 2156 if (ohci->next_config_rom != ohci->config_rom) { 2157 free_rom = ohci->config_rom; 2158 free_rom_bus = ohci->config_rom_bus; 2159 } 2160 ohci->config_rom = ohci->next_config_rom; 2161 ohci->config_rom_bus = ohci->next_config_rom_bus; 2162 ohci->next_config_rom = NULL; 2163 2164 // Restore config_rom image and manually update config_rom registers. 2165 // Writing the header quadlet will indicate that the config rom is ready, 2166 // so we do that last. 2167 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); 2168 ohci->config_rom[0] = ohci->next_header; 2169 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header)); 2170 } 2171 2172 if (param_remote_dma) { 2173 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2174 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2175 } 2176 } 2177 2178 if (free_rom) 2179 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2180 2181 log_selfids(ohci, generation, self_id_count); 2182 2183 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2184 self_id_count, ohci->self_id_buffer, 2185 ohci->csr_state_setclear_abdicate); 2186 ohci->csr_state_setclear_abdicate = false; 2187 } 2188 2189 static irqreturn_t irq_handler(int irq, void *data) 2190 { 2191 struct fw_ohci *ohci = data; 2192 u32 event, iso_event; 2193 int i; 2194 2195 event = reg_read(ohci, OHCI1394_IntEventClear); 2196 2197 if (!event || !~event) 2198 return IRQ_NONE; 2199 2200 if (unlikely(param_debug > 0)) { 2201 dev_notice_ratelimited(ohci->card.device, 2202 "The debug parameter is superceded by tracepoints events, and deprecated."); 2203 } 2204 2205 /* 2206 * busReset and postedWriteErr events must not be cleared yet 2207 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2208 */ 2209 reg_write(ohci, OHCI1394_IntEventClear, 2210 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2211 trace_irqs(ohci->card.index, event); 2212 log_irqs(ohci, event); 2213 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2214 if (event & OHCI1394_busReset) 2215 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2216 2217 if (event & OHCI1394_selfIDComplete) { 2218 if (trace_self_id_complete_enabled()) { 2219 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2220 2221 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2222 has_be_header_quirk(ohci)); 2223 } 2224 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2225 } 2226 2227 if (event & OHCI1394_RQPkt) 2228 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2229 2230 if (event & OHCI1394_RSPkt) 2231 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2232 2233 if (event & OHCI1394_reqTxComplete) 2234 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2235 2236 if (event & OHCI1394_respTxComplete) 2237 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2238 2239 if (event & OHCI1394_isochRx) { 2240 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2241 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2242 2243 while (iso_event) { 2244 i = ffs(iso_event) - 1; 2245 tasklet_schedule( 2246 &ohci->ir_context_list[i].context.tasklet); 2247 iso_event &= ~(1 << i); 2248 } 2249 } 2250 2251 if (event & OHCI1394_isochTx) { 2252 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2253 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2254 2255 while (iso_event) { 2256 i = ffs(iso_event) - 1; 2257 tasklet_schedule( 2258 &ohci->it_context_list[i].context.tasklet); 2259 iso_event &= ~(1 << i); 2260 } 2261 } 2262 2263 if (unlikely(event & OHCI1394_regAccessFail)) 2264 ohci_err(ohci, "register access failure\n"); 2265 2266 if (unlikely(event & OHCI1394_postedWriteErr)) { 2267 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2268 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2269 reg_write(ohci, OHCI1394_IntEventClear, 2270 OHCI1394_postedWriteErr); 2271 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n"); 2272 } 2273 2274 if (unlikely(event & OHCI1394_cycleTooLong)) { 2275 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n"); 2276 reg_write(ohci, OHCI1394_LinkControlSet, 2277 OHCI1394_LinkControl_cycleMaster); 2278 } 2279 2280 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2281 /* 2282 * We need to clear this event bit in order to make 2283 * cycleMatch isochronous I/O work. In theory we should 2284 * stop active cycleMatch iso contexts now and restart 2285 * them at least two cycles later. (FIXME?) 2286 */ 2287 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n"); 2288 } 2289 2290 if (unlikely(event & OHCI1394_unrecoverableError)) 2291 handle_dead_contexts(ohci); 2292 2293 if (event & OHCI1394_cycle64Seconds) { 2294 guard(spinlock)(&ohci->lock); 2295 update_bus_time(ohci); 2296 } else 2297 flush_writes(ohci); 2298 2299 return IRQ_HANDLED; 2300 } 2301 2302 static int software_reset(struct fw_ohci *ohci) 2303 { 2304 u32 val; 2305 int i; 2306 2307 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2308 for (i = 0; i < 500; i++) { 2309 val = reg_read(ohci, OHCI1394_HCControlSet); 2310 if (!~val) 2311 return -ENODEV; /* Card was ejected. */ 2312 2313 if (!(val & OHCI1394_HCControl_softReset)) 2314 return 0; 2315 2316 msleep(1); 2317 } 2318 2319 return -EBUSY; 2320 } 2321 2322 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2323 { 2324 size_t size = length * 4; 2325 2326 memcpy(dest, src, size); 2327 if (size < CONFIG_ROM_SIZE) 2328 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2329 } 2330 2331 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2332 { 2333 bool enable_1394a; 2334 int ret, clear, set, offset; 2335 2336 /* Check if the driver should configure link and PHY. */ 2337 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2338 OHCI1394_HCControl_programPhyEnable)) 2339 return 0; 2340 2341 /* Paranoia: check whether the PHY supports 1394a, too. */ 2342 enable_1394a = false; 2343 ret = read_phy_reg(ohci, 2); 2344 if (ret < 0) 2345 return ret; 2346 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2347 ret = read_paged_phy_reg(ohci, 1, 8); 2348 if (ret < 0) 2349 return ret; 2350 if (ret >= 1) 2351 enable_1394a = true; 2352 } 2353 2354 if (ohci->quirks & QUIRK_NO_1394A) 2355 enable_1394a = false; 2356 2357 /* Configure PHY and link consistently. */ 2358 if (enable_1394a) { 2359 clear = 0; 2360 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2361 } else { 2362 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2363 set = 0; 2364 } 2365 ret = update_phy_reg(ohci, 5, clear, set); 2366 if (ret < 0) 2367 return ret; 2368 2369 if (enable_1394a) 2370 offset = OHCI1394_HCControlSet; 2371 else 2372 offset = OHCI1394_HCControlClear; 2373 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2374 2375 /* Clean up: configuration has been taken care of. */ 2376 reg_write(ohci, OHCI1394_HCControlClear, 2377 OHCI1394_HCControl_programPhyEnable); 2378 2379 return 0; 2380 } 2381 2382 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2383 { 2384 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2385 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2386 int reg, i; 2387 2388 reg = read_phy_reg(ohci, 2); 2389 if (reg < 0) 2390 return reg; 2391 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2392 return 0; 2393 2394 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2395 reg = read_paged_phy_reg(ohci, 1, i + 10); 2396 if (reg < 0) 2397 return reg; 2398 if (reg != id[i]) 2399 return 0; 2400 } 2401 return 1; 2402 } 2403 2404 static int ohci_enable(struct fw_card *card, 2405 const __be32 *config_rom, size_t length) 2406 { 2407 struct fw_ohci *ohci = fw_ohci(card); 2408 u32 lps, version, irqs; 2409 int i, ret; 2410 2411 ret = software_reset(ohci); 2412 if (ret < 0) { 2413 ohci_err(ohci, "failed to reset ohci card\n"); 2414 return ret; 2415 } 2416 2417 /* 2418 * Now enable LPS, which we need in order to start accessing 2419 * most of the registers. In fact, on some cards (ALI M5251), 2420 * accessing registers in the SClk domain without LPS enabled 2421 * will lock up the machine. Wait 50msec to make sure we have 2422 * full link enabled. However, with some cards (well, at least 2423 * a JMicron PCIe card), we have to try again sometimes. 2424 * 2425 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2426 * cannot actually use the phy at that time. These need tens of 2427 * millisecods pause between LPS write and first phy access too. 2428 */ 2429 2430 reg_write(ohci, OHCI1394_HCControlSet, 2431 OHCI1394_HCControl_LPS | 2432 OHCI1394_HCControl_postedWriteEnable); 2433 flush_writes(ohci); 2434 2435 for (lps = 0, i = 0; !lps && i < 3; i++) { 2436 msleep(50); 2437 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2438 OHCI1394_HCControl_LPS; 2439 } 2440 2441 if (!lps) { 2442 ohci_err(ohci, "failed to set Link Power Status\n"); 2443 return -EIO; 2444 } 2445 2446 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2447 ret = probe_tsb41ba3d(ohci); 2448 if (ret < 0) 2449 return ret; 2450 if (ret) 2451 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2452 else 2453 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2454 } 2455 2456 reg_write(ohci, OHCI1394_HCControlClear, 2457 OHCI1394_HCControl_noByteSwapData); 2458 2459 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2460 reg_write(ohci, OHCI1394_LinkControlSet, 2461 OHCI1394_LinkControl_cycleTimerEnable | 2462 OHCI1394_LinkControl_cycleMaster); 2463 2464 reg_write(ohci, OHCI1394_ATRetries, 2465 OHCI1394_MAX_AT_REQ_RETRIES | 2466 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2467 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2468 (200 << 16)); 2469 2470 ohci->bus_time_running = false; 2471 2472 for (i = 0; i < 32; i++) 2473 if (ohci->ir_context_support & (1 << i)) 2474 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2475 IR_CONTEXT_MULTI_CHANNEL_MODE); 2476 2477 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2478 if (version >= OHCI_VERSION_1_1) { 2479 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2480 0xfffffffe); 2481 card->broadcast_channel_auto_allocated = true; 2482 } 2483 2484 /* Get implemented bits of the priority arbitration request counter. */ 2485 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2486 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2487 reg_write(ohci, OHCI1394_FairnessControl, 0); 2488 card->priority_budget_implemented = ohci->pri_req_max != 0; 2489 2490 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2491 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2492 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2493 2494 ret = configure_1394a_enhancements(ohci); 2495 if (ret < 0) 2496 return ret; 2497 2498 /* Activate link_on bit and contender bit in our self ID packets.*/ 2499 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2500 if (ret < 0) 2501 return ret; 2502 2503 /* 2504 * When the link is not yet enabled, the atomic config rom 2505 * update mechanism described below in ohci_set_config_rom() 2506 * is not active. We have to update ConfigRomHeader and 2507 * BusOptions manually, and the write to ConfigROMmap takes 2508 * effect immediately. We tie this to the enabling of the 2509 * link, so we have a valid config rom before enabling - the 2510 * OHCI requires that ConfigROMhdr and BusOptions have valid 2511 * values before enabling. 2512 * 2513 * However, when the ConfigROMmap is written, some controllers 2514 * always read back quadlets 0 and 2 from the config rom to 2515 * the ConfigRomHeader and BusOptions registers on bus reset. 2516 * They shouldn't do that in this initial case where the link 2517 * isn't enabled. This means we have to use the same 2518 * workaround here, setting the bus header to 0 and then write 2519 * the right values in the bus reset tasklet. 2520 */ 2521 2522 if (config_rom) { 2523 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2524 &ohci->next_config_rom_bus, GFP_KERNEL); 2525 if (ohci->next_config_rom == NULL) 2526 return -ENOMEM; 2527 2528 copy_config_rom(ohci->next_config_rom, config_rom, length); 2529 } else { 2530 /* 2531 * In the suspend case, config_rom is NULL, which 2532 * means that we just reuse the old config rom. 2533 */ 2534 ohci->next_config_rom = ohci->config_rom; 2535 ohci->next_config_rom_bus = ohci->config_rom_bus; 2536 } 2537 2538 ohci->next_header = ohci->next_config_rom[0]; 2539 ohci->next_config_rom[0] = 0; 2540 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2541 reg_write(ohci, OHCI1394_BusOptions, 2542 be32_to_cpu(ohci->next_config_rom[2])); 2543 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2544 2545 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2546 2547 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2548 OHCI1394_RQPkt | OHCI1394_RSPkt | 2549 OHCI1394_isochTx | OHCI1394_isochRx | 2550 OHCI1394_postedWriteErr | 2551 OHCI1394_selfIDComplete | 2552 OHCI1394_regAccessFail | 2553 OHCI1394_cycleInconsistent | 2554 OHCI1394_unrecoverableError | 2555 OHCI1394_cycleTooLong | 2556 OHCI1394_masterIntEnable | 2557 OHCI1394_busReset; 2558 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2559 2560 reg_write(ohci, OHCI1394_HCControlSet, 2561 OHCI1394_HCControl_linkEnable | 2562 OHCI1394_HCControl_BIBimageValid); 2563 2564 reg_write(ohci, OHCI1394_LinkControlSet, 2565 OHCI1394_LinkControl_rcvSelfID | 2566 OHCI1394_LinkControl_rcvPhyPkt); 2567 2568 ar_context_run(&ohci->ar_request_ctx); 2569 ar_context_run(&ohci->ar_response_ctx); 2570 2571 flush_writes(ohci); 2572 2573 /* We are ready to go, reset bus to finish initialization. */ 2574 fw_schedule_bus_reset(&ohci->card, false, true); 2575 2576 return 0; 2577 } 2578 2579 static int ohci_set_config_rom(struct fw_card *card, 2580 const __be32 *config_rom, size_t length) 2581 { 2582 struct fw_ohci *ohci; 2583 __be32 *next_config_rom; 2584 dma_addr_t next_config_rom_bus; 2585 2586 ohci = fw_ohci(card); 2587 2588 /* 2589 * When the OHCI controller is enabled, the config rom update 2590 * mechanism is a bit tricky, but easy enough to use. See 2591 * section 5.5.6 in the OHCI specification. 2592 * 2593 * The OHCI controller caches the new config rom address in a 2594 * shadow register (ConfigROMmapNext) and needs a bus reset 2595 * for the changes to take place. When the bus reset is 2596 * detected, the controller loads the new values for the 2597 * ConfigRomHeader and BusOptions registers from the specified 2598 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2599 * shadow register. All automatically and atomically. 2600 * 2601 * Now, there's a twist to this story. The automatic load of 2602 * ConfigRomHeader and BusOptions doesn't honor the 2603 * noByteSwapData bit, so with a be32 config rom, the 2604 * controller will load be32 values in to these registers 2605 * during the atomic update, even on litte endian 2606 * architectures. The workaround we use is to put a 0 in the 2607 * header quadlet; 0 is endian agnostic and means that the 2608 * config rom isn't ready yet. In the bus reset tasklet we 2609 * then set up the real values for the two registers. 2610 * 2611 * We use ohci->lock to avoid racing with the code that sets 2612 * ohci->next_config_rom to NULL (see bus_reset_work). 2613 */ 2614 2615 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2616 &next_config_rom_bus, GFP_KERNEL); 2617 if (next_config_rom == NULL) 2618 return -ENOMEM; 2619 2620 scoped_guard(spinlock_irq, &ohci->lock) { 2621 // If there is not an already pending config_rom update, push our new allocation 2622 // into the ohci->next_config_rom and then mark the local variable as null so that 2623 // we won't deallocate the new buffer. 2624 // 2625 // OTOH, if there is a pending config_rom update, just use that buffer with the new 2626 // config_rom data, and let this routine free the unused DMA allocation. 2627 if (ohci->next_config_rom == NULL) { 2628 ohci->next_config_rom = next_config_rom; 2629 ohci->next_config_rom_bus = next_config_rom_bus; 2630 next_config_rom = NULL; 2631 } 2632 2633 copy_config_rom(ohci->next_config_rom, config_rom, length); 2634 2635 ohci->next_header = config_rom[0]; 2636 ohci->next_config_rom[0] = 0; 2637 2638 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2639 } 2640 2641 /* If we didn't use the DMA allocation, delete it. */ 2642 if (next_config_rom != NULL) { 2643 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2644 next_config_rom_bus); 2645 } 2646 2647 /* 2648 * Now initiate a bus reset to have the changes take 2649 * effect. We clean up the old config rom memory and DMA 2650 * mappings in the bus reset tasklet, since the OHCI 2651 * controller could need to access it before the bus reset 2652 * takes effect. 2653 */ 2654 2655 fw_schedule_bus_reset(&ohci->card, true, true); 2656 2657 return 0; 2658 } 2659 2660 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2661 { 2662 struct fw_ohci *ohci = fw_ohci(card); 2663 2664 at_context_transmit(&ohci->at_request_ctx, packet); 2665 } 2666 2667 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2668 { 2669 struct fw_ohci *ohci = fw_ohci(card); 2670 2671 at_context_transmit(&ohci->at_response_ctx, packet); 2672 } 2673 2674 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2675 { 2676 struct fw_ohci *ohci = fw_ohci(card); 2677 struct context *ctx = &ohci->at_request_ctx; 2678 struct driver_data *driver_data = packet->driver_data; 2679 int ret = -ENOENT; 2680 2681 tasklet_disable_in_atomic(&ctx->tasklet); 2682 2683 if (packet->ack != 0) 2684 goto out; 2685 2686 if (packet->payload_mapped) 2687 dma_unmap_single(ohci->card.device, packet->payload_bus, 2688 packet->payload_length, DMA_TO_DEVICE); 2689 2690 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2691 driver_data->packet = NULL; 2692 packet->ack = RCODE_CANCELLED; 2693 2694 // Timestamping on behalf of the hardware. 2695 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2696 2697 packet->callback(packet, &ohci->card, packet->ack); 2698 ret = 0; 2699 out: 2700 tasklet_enable(&ctx->tasklet); 2701 2702 return ret; 2703 } 2704 2705 static int ohci_enable_phys_dma(struct fw_card *card, 2706 int node_id, int generation) 2707 { 2708 struct fw_ohci *ohci = fw_ohci(card); 2709 int n, ret = 0; 2710 2711 if (param_remote_dma) 2712 return 0; 2713 2714 /* 2715 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2716 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2717 */ 2718 2719 guard(spinlock_irqsave)(&ohci->lock); 2720 2721 if (ohci->generation != generation) 2722 return -ESTALE; 2723 2724 /* 2725 * Note, if the node ID contains a non-local bus ID, physical DMA is 2726 * enabled for _all_ nodes on remote buses. 2727 */ 2728 2729 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2730 if (n < 32) 2731 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2732 else 2733 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2734 2735 flush_writes(ohci); 2736 2737 return ret; 2738 } 2739 2740 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2741 { 2742 struct fw_ohci *ohci = fw_ohci(card); 2743 u32 value; 2744 2745 switch (csr_offset) { 2746 case CSR_STATE_CLEAR: 2747 case CSR_STATE_SET: 2748 if (ohci->is_root && 2749 (reg_read(ohci, OHCI1394_LinkControlSet) & 2750 OHCI1394_LinkControl_cycleMaster)) 2751 value = CSR_STATE_BIT_CMSTR; 2752 else 2753 value = 0; 2754 if (ohci->csr_state_setclear_abdicate) 2755 value |= CSR_STATE_BIT_ABDICATE; 2756 2757 return value; 2758 2759 case CSR_NODE_IDS: 2760 return reg_read(ohci, OHCI1394_NodeID) << 16; 2761 2762 case CSR_CYCLE_TIME: 2763 return get_cycle_time(ohci); 2764 2765 case CSR_BUS_TIME: 2766 { 2767 // We might be called just after the cycle timer has wrapped around but just before 2768 // the cycle64Seconds handler, so we better check here, too, if the bus time needs 2769 // to be updated. 2770 2771 guard(spinlock_irqsave)(&ohci->lock); 2772 return update_bus_time(ohci); 2773 } 2774 case CSR_BUSY_TIMEOUT: 2775 value = reg_read(ohci, OHCI1394_ATRetries); 2776 return (value >> 4) & 0x0ffff00f; 2777 2778 case CSR_PRIORITY_BUDGET: 2779 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2780 (ohci->pri_req_max << 8); 2781 2782 default: 2783 WARN_ON(1); 2784 return 0; 2785 } 2786 } 2787 2788 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2789 { 2790 struct fw_ohci *ohci = fw_ohci(card); 2791 2792 switch (csr_offset) { 2793 case CSR_STATE_CLEAR: 2794 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2795 reg_write(ohci, OHCI1394_LinkControlClear, 2796 OHCI1394_LinkControl_cycleMaster); 2797 flush_writes(ohci); 2798 } 2799 if (value & CSR_STATE_BIT_ABDICATE) 2800 ohci->csr_state_setclear_abdicate = false; 2801 break; 2802 2803 case CSR_STATE_SET: 2804 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2805 reg_write(ohci, OHCI1394_LinkControlSet, 2806 OHCI1394_LinkControl_cycleMaster); 2807 flush_writes(ohci); 2808 } 2809 if (value & CSR_STATE_BIT_ABDICATE) 2810 ohci->csr_state_setclear_abdicate = true; 2811 break; 2812 2813 case CSR_NODE_IDS: 2814 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2815 flush_writes(ohci); 2816 break; 2817 2818 case CSR_CYCLE_TIME: 2819 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2820 reg_write(ohci, OHCI1394_IntEventSet, 2821 OHCI1394_cycleInconsistent); 2822 flush_writes(ohci); 2823 break; 2824 2825 case CSR_BUS_TIME: 2826 { 2827 guard(spinlock_irqsave)(&ohci->lock); 2828 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); 2829 break; 2830 } 2831 case CSR_BUSY_TIMEOUT: 2832 value = (value & 0xf) | ((value & 0xf) << 4) | 2833 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2834 reg_write(ohci, OHCI1394_ATRetries, value); 2835 flush_writes(ohci); 2836 break; 2837 2838 case CSR_PRIORITY_BUDGET: 2839 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2840 flush_writes(ohci); 2841 break; 2842 2843 default: 2844 WARN_ON(1); 2845 break; 2846 } 2847 } 2848 2849 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2850 { 2851 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2852 ctx->header_length); 2853 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2854 ctx->header_length); 2855 2856 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2857 ctx->header_length, ctx->header, 2858 ctx->base.callback_data); 2859 ctx->header_length = 0; 2860 } 2861 2862 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2863 { 2864 u32 *ctx_hdr; 2865 2866 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2867 if (ctx->base.drop_overflow_headers) 2868 return; 2869 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2870 } 2871 2872 ctx_hdr = ctx->header + ctx->header_length; 2873 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2874 2875 /* 2876 * The two iso header quadlets are byteswapped to little 2877 * endian by the controller, but we want to present them 2878 * as big endian for consistency with the bus endianness. 2879 */ 2880 if (ctx->base.header_size > 0) 2881 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2882 if (ctx->base.header_size > 4) 2883 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2884 if (ctx->base.header_size > 8) 2885 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2886 ctx->header_length += ctx->base.header_size; 2887 } 2888 2889 static int handle_ir_packet_per_buffer(struct context *context, 2890 struct descriptor *d, 2891 struct descriptor *last) 2892 { 2893 struct iso_context *ctx = 2894 container_of(context, struct iso_context, context); 2895 struct descriptor *pd; 2896 u32 buffer_dma; 2897 2898 for (pd = d; pd <= last; pd++) 2899 if (pd->transfer_status) 2900 break; 2901 if (pd > last) 2902 /* Descriptor(s) not done yet, stop iteration */ 2903 return 0; 2904 2905 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2906 d++; 2907 buffer_dma = le32_to_cpu(d->data_address); 2908 dma_sync_single_range_for_cpu(context->ohci->card.device, 2909 buffer_dma & PAGE_MASK, 2910 buffer_dma & ~PAGE_MASK, 2911 le16_to_cpu(d->req_count), 2912 DMA_FROM_DEVICE); 2913 } 2914 2915 copy_iso_headers(ctx, (u32 *) (last + 1)); 2916 2917 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2918 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2919 2920 return 1; 2921 } 2922 2923 /* d == last because each descriptor block is only a single descriptor. */ 2924 static int handle_ir_buffer_fill(struct context *context, 2925 struct descriptor *d, 2926 struct descriptor *last) 2927 { 2928 struct iso_context *ctx = 2929 container_of(context, struct iso_context, context); 2930 unsigned int req_count, res_count, completed; 2931 u32 buffer_dma; 2932 2933 req_count = le16_to_cpu(last->req_count); 2934 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2935 completed = req_count - res_count; 2936 buffer_dma = le32_to_cpu(last->data_address); 2937 2938 if (completed > 0) { 2939 ctx->mc_buffer_bus = buffer_dma; 2940 ctx->mc_completed = completed; 2941 } 2942 2943 if (res_count != 0) 2944 /* Descriptor(s) not done yet, stop iteration */ 2945 return 0; 2946 2947 dma_sync_single_range_for_cpu(context->ohci->card.device, 2948 buffer_dma & PAGE_MASK, 2949 buffer_dma & ~PAGE_MASK, 2950 completed, DMA_FROM_DEVICE); 2951 2952 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2953 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2954 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2955 2956 ctx->base.callback.mc(&ctx->base, 2957 buffer_dma + completed, 2958 ctx->base.callback_data); 2959 ctx->mc_completed = 0; 2960 } 2961 2962 return 1; 2963 } 2964 2965 static void flush_ir_buffer_fill(struct iso_context *ctx) 2966 { 2967 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2968 ctx->mc_buffer_bus & PAGE_MASK, 2969 ctx->mc_buffer_bus & ~PAGE_MASK, 2970 ctx->mc_completed, DMA_FROM_DEVICE); 2971 2972 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 2973 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 2974 2975 ctx->base.callback.mc(&ctx->base, 2976 ctx->mc_buffer_bus + ctx->mc_completed, 2977 ctx->base.callback_data); 2978 ctx->mc_completed = 0; 2979 } 2980 2981 static inline void sync_it_packet_for_cpu(struct context *context, 2982 struct descriptor *pd) 2983 { 2984 __le16 control; 2985 u32 buffer_dma; 2986 2987 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2988 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2989 return; 2990 2991 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2992 pd += 2; 2993 2994 /* 2995 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2996 * data buffer is in the context program's coherent page and must not 2997 * be synced. 2998 */ 2999 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 3000 (context->current_bus & PAGE_MASK)) { 3001 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3002 return; 3003 pd++; 3004 } 3005 3006 do { 3007 buffer_dma = le32_to_cpu(pd->data_address); 3008 dma_sync_single_range_for_cpu(context->ohci->card.device, 3009 buffer_dma & PAGE_MASK, 3010 buffer_dma & ~PAGE_MASK, 3011 le16_to_cpu(pd->req_count), 3012 DMA_TO_DEVICE); 3013 control = pd->control; 3014 pd++; 3015 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3016 } 3017 3018 static int handle_it_packet(struct context *context, 3019 struct descriptor *d, 3020 struct descriptor *last) 3021 { 3022 struct iso_context *ctx = 3023 container_of(context, struct iso_context, context); 3024 struct descriptor *pd; 3025 __be32 *ctx_hdr; 3026 3027 for (pd = d; pd <= last; pd++) 3028 if (pd->transfer_status) 3029 break; 3030 if (pd > last) 3031 /* Descriptor(s) not done yet, stop iteration */ 3032 return 0; 3033 3034 sync_it_packet_for_cpu(context, d); 3035 3036 if (ctx->header_length + 4 > PAGE_SIZE) { 3037 if (ctx->base.drop_overflow_headers) 3038 return 1; 3039 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3040 } 3041 3042 ctx_hdr = ctx->header + ctx->header_length; 3043 ctx->last_timestamp = le16_to_cpu(last->res_count); 3044 /* Present this value as big-endian to match the receive code */ 3045 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3046 le16_to_cpu(pd->res_count)); 3047 ctx->header_length += 4; 3048 3049 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3050 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 3051 3052 return 1; 3053 } 3054 3055 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3056 { 3057 u32 hi = channels >> 32, lo = channels; 3058 3059 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3060 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3061 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3062 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3063 ohci->mc_channels = channels; 3064 } 3065 3066 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3067 int type, int channel, size_t header_size) 3068 { 3069 struct fw_ohci *ohci = fw_ohci(card); 3070 struct iso_context *ctx; 3071 descriptor_callback_t callback; 3072 u64 *channels; 3073 u32 *mask, regs; 3074 int index, ret = -EBUSY; 3075 3076 scoped_guard(spinlock_irq, &ohci->lock) { 3077 switch (type) { 3078 case FW_ISO_CONTEXT_TRANSMIT: 3079 mask = &ohci->it_context_mask; 3080 callback = handle_it_packet; 3081 index = ffs(*mask) - 1; 3082 if (index >= 0) { 3083 *mask &= ~(1 << index); 3084 regs = OHCI1394_IsoXmitContextBase(index); 3085 ctx = &ohci->it_context_list[index]; 3086 } 3087 break; 3088 3089 case FW_ISO_CONTEXT_RECEIVE: 3090 channels = &ohci->ir_context_channels; 3091 mask = &ohci->ir_context_mask; 3092 callback = handle_ir_packet_per_buffer; 3093 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3094 if (index >= 0) { 3095 *channels &= ~(1ULL << channel); 3096 *mask &= ~(1 << index); 3097 regs = OHCI1394_IsoRcvContextBase(index); 3098 ctx = &ohci->ir_context_list[index]; 3099 } 3100 break; 3101 3102 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3103 mask = &ohci->ir_context_mask; 3104 callback = handle_ir_buffer_fill; 3105 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3106 if (index >= 0) { 3107 ohci->mc_allocated = true; 3108 *mask &= ~(1 << index); 3109 regs = OHCI1394_IsoRcvContextBase(index); 3110 ctx = &ohci->ir_context_list[index]; 3111 } 3112 break; 3113 3114 default: 3115 index = -1; 3116 ret = -ENOSYS; 3117 } 3118 3119 if (index < 0) 3120 return ERR_PTR(ret); 3121 } 3122 3123 memset(ctx, 0, sizeof(*ctx)); 3124 ctx->header_length = 0; 3125 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3126 if (ctx->header == NULL) { 3127 ret = -ENOMEM; 3128 goto out; 3129 } 3130 ret = context_init(&ctx->context, ohci, regs, callback); 3131 if (ret < 0) 3132 goto out_with_header; 3133 3134 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3135 set_multichannel_mask(ohci, 0); 3136 ctx->mc_completed = 0; 3137 } 3138 3139 return &ctx->base; 3140 3141 out_with_header: 3142 free_page((unsigned long)ctx->header); 3143 out: 3144 scoped_guard(spinlock_irq, &ohci->lock) { 3145 switch (type) { 3146 case FW_ISO_CONTEXT_RECEIVE: 3147 *channels |= 1ULL << channel; 3148 break; 3149 3150 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3151 ohci->mc_allocated = false; 3152 break; 3153 } 3154 *mask |= 1 << index; 3155 } 3156 3157 return ERR_PTR(ret); 3158 } 3159 3160 static int ohci_start_iso(struct fw_iso_context *base, 3161 s32 cycle, u32 sync, u32 tags) 3162 { 3163 struct iso_context *ctx = container_of(base, struct iso_context, base); 3164 struct fw_ohci *ohci = ctx->context.ohci; 3165 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3166 int index; 3167 3168 /* the controller cannot start without any queued packets */ 3169 if (ctx->context.last->branch_address == 0) 3170 return -ENODATA; 3171 3172 switch (ctx->base.type) { 3173 case FW_ISO_CONTEXT_TRANSMIT: 3174 index = ctx - ohci->it_context_list; 3175 match = 0; 3176 if (cycle >= 0) 3177 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3178 (cycle & 0x7fff) << 16; 3179 3180 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3181 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3182 context_run(&ctx->context, match); 3183 break; 3184 3185 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3186 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3187 fallthrough; 3188 case FW_ISO_CONTEXT_RECEIVE: 3189 index = ctx - ohci->ir_context_list; 3190 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3191 if (cycle >= 0) { 3192 match |= (cycle & 0x07fff) << 12; 3193 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3194 } 3195 3196 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3197 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3198 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3199 context_run(&ctx->context, control); 3200 3201 ctx->sync = sync; 3202 ctx->tags = tags; 3203 3204 break; 3205 } 3206 3207 return 0; 3208 } 3209 3210 static int ohci_stop_iso(struct fw_iso_context *base) 3211 { 3212 struct fw_ohci *ohci = fw_ohci(base->card); 3213 struct iso_context *ctx = container_of(base, struct iso_context, base); 3214 int index; 3215 3216 switch (ctx->base.type) { 3217 case FW_ISO_CONTEXT_TRANSMIT: 3218 index = ctx - ohci->it_context_list; 3219 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3220 break; 3221 3222 case FW_ISO_CONTEXT_RECEIVE: 3223 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3224 index = ctx - ohci->ir_context_list; 3225 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3226 break; 3227 } 3228 flush_writes(ohci); 3229 context_stop(&ctx->context); 3230 tasklet_kill(&ctx->context.tasklet); 3231 3232 return 0; 3233 } 3234 3235 static void ohci_free_iso_context(struct fw_iso_context *base) 3236 { 3237 struct fw_ohci *ohci = fw_ohci(base->card); 3238 struct iso_context *ctx = container_of(base, struct iso_context, base); 3239 int index; 3240 3241 ohci_stop_iso(base); 3242 context_release(&ctx->context); 3243 free_page((unsigned long)ctx->header); 3244 3245 guard(spinlock_irqsave)(&ohci->lock); 3246 3247 switch (base->type) { 3248 case FW_ISO_CONTEXT_TRANSMIT: 3249 index = ctx - ohci->it_context_list; 3250 ohci->it_context_mask |= 1 << index; 3251 break; 3252 3253 case FW_ISO_CONTEXT_RECEIVE: 3254 index = ctx - ohci->ir_context_list; 3255 ohci->ir_context_mask |= 1 << index; 3256 ohci->ir_context_channels |= 1ULL << base->channel; 3257 break; 3258 3259 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3260 index = ctx - ohci->ir_context_list; 3261 ohci->ir_context_mask |= 1 << index; 3262 ohci->ir_context_channels |= ohci->mc_channels; 3263 ohci->mc_channels = 0; 3264 ohci->mc_allocated = false; 3265 break; 3266 } 3267 } 3268 3269 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3270 { 3271 struct fw_ohci *ohci = fw_ohci(base->card); 3272 3273 switch (base->type) { 3274 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3275 { 3276 guard(spinlock_irqsave)(&ohci->lock); 3277 3278 // Don't allow multichannel to grab other contexts' channels. 3279 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3280 *channels = ohci->ir_context_channels; 3281 return -EBUSY; 3282 } else { 3283 set_multichannel_mask(ohci, *channels); 3284 return 0; 3285 } 3286 } 3287 default: 3288 return -EINVAL; 3289 } 3290 } 3291 3292 #ifdef CONFIG_PM 3293 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3294 { 3295 int i; 3296 struct iso_context *ctx; 3297 3298 for (i = 0 ; i < ohci->n_ir ; i++) { 3299 ctx = &ohci->ir_context_list[i]; 3300 if (ctx->context.running) 3301 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3302 } 3303 3304 for (i = 0 ; i < ohci->n_it ; i++) { 3305 ctx = &ohci->it_context_list[i]; 3306 if (ctx->context.running) 3307 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3308 } 3309 } 3310 #endif 3311 3312 static int queue_iso_transmit(struct iso_context *ctx, 3313 struct fw_iso_packet *packet, 3314 struct fw_iso_buffer *buffer, 3315 unsigned long payload) 3316 { 3317 struct descriptor *d, *last, *pd; 3318 struct fw_iso_packet *p; 3319 __le32 *header; 3320 dma_addr_t d_bus, page_bus; 3321 u32 z, header_z, payload_z, irq; 3322 u32 payload_index, payload_end_index, next_page_index; 3323 int page, end_page, i, length, offset; 3324 3325 p = packet; 3326 payload_index = payload; 3327 3328 if (p->skip) 3329 z = 1; 3330 else 3331 z = 2; 3332 if (p->header_length > 0) 3333 z++; 3334 3335 /* Determine the first page the payload isn't contained in. */ 3336 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3337 if (p->payload_length > 0) 3338 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3339 else 3340 payload_z = 0; 3341 3342 z += payload_z; 3343 3344 /* Get header size in number of descriptors. */ 3345 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3346 3347 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3348 if (d == NULL) 3349 return -ENOMEM; 3350 3351 if (!p->skip) { 3352 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3353 d[0].req_count = cpu_to_le16(8); 3354 /* 3355 * Link the skip address to this descriptor itself. This causes 3356 * a context to skip a cycle whenever lost cycles or FIFO 3357 * overruns occur, without dropping the data. The application 3358 * should then decide whether this is an error condition or not. 3359 * FIXME: Make the context's cycle-lost behaviour configurable? 3360 */ 3361 d[0].branch_address = cpu_to_le32(d_bus | z); 3362 3363 header = (__le32 *) &d[1]; 3364 3365 ohci1394_it_data_set_speed(header, ctx->base.speed); 3366 ohci1394_it_data_set_tag(header, p->tag); 3367 ohci1394_it_data_set_channel(header, ctx->base.channel); 3368 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 3369 ohci1394_it_data_set_sync(header, p->sy); 3370 3371 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length); 3372 } 3373 3374 if (p->header_length > 0) { 3375 d[2].req_count = cpu_to_le16(p->header_length); 3376 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3377 memcpy(&d[z], p->header, p->header_length); 3378 } 3379 3380 pd = d + z - payload_z; 3381 payload_end_index = payload_index + p->payload_length; 3382 for (i = 0; i < payload_z; i++) { 3383 page = payload_index >> PAGE_SHIFT; 3384 offset = payload_index & ~PAGE_MASK; 3385 next_page_index = (page + 1) << PAGE_SHIFT; 3386 length = 3387 min(next_page_index, payload_end_index) - payload_index; 3388 pd[i].req_count = cpu_to_le16(length); 3389 3390 page_bus = page_private(buffer->pages[page]); 3391 pd[i].data_address = cpu_to_le32(page_bus + offset); 3392 3393 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3394 page_bus, offset, length, 3395 DMA_TO_DEVICE); 3396 3397 payload_index += length; 3398 } 3399 3400 if (p->interrupt) 3401 irq = DESCRIPTOR_IRQ_ALWAYS; 3402 else 3403 irq = DESCRIPTOR_NO_IRQ; 3404 3405 last = z == 2 ? d : d + z - 1; 3406 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3407 DESCRIPTOR_STATUS | 3408 DESCRIPTOR_BRANCH_ALWAYS | 3409 irq); 3410 3411 context_append(&ctx->context, d, z, header_z); 3412 3413 return 0; 3414 } 3415 3416 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3417 struct fw_iso_packet *packet, 3418 struct fw_iso_buffer *buffer, 3419 unsigned long payload) 3420 { 3421 struct device *device = ctx->context.ohci->card.device; 3422 struct descriptor *d, *pd; 3423 dma_addr_t d_bus, page_bus; 3424 u32 z, header_z, rest; 3425 int i, j, length; 3426 int page, offset, packet_count, header_size, payload_per_buffer; 3427 3428 /* 3429 * The OHCI controller puts the isochronous header and trailer in the 3430 * buffer, so we need at least 8 bytes. 3431 */ 3432 packet_count = packet->header_length / ctx->base.header_size; 3433 header_size = max(ctx->base.header_size, (size_t)8); 3434 3435 /* Get header size in number of descriptors. */ 3436 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3437 page = payload >> PAGE_SHIFT; 3438 offset = payload & ~PAGE_MASK; 3439 payload_per_buffer = packet->payload_length / packet_count; 3440 3441 for (i = 0; i < packet_count; i++) { 3442 /* d points to the header descriptor */ 3443 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3444 d = context_get_descriptors(&ctx->context, 3445 z + header_z, &d_bus); 3446 if (d == NULL) 3447 return -ENOMEM; 3448 3449 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3450 DESCRIPTOR_INPUT_MORE); 3451 if (packet->skip && i == 0) 3452 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3453 d->req_count = cpu_to_le16(header_size); 3454 d->res_count = d->req_count; 3455 d->transfer_status = 0; 3456 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3457 3458 rest = payload_per_buffer; 3459 pd = d; 3460 for (j = 1; j < z; j++) { 3461 pd++; 3462 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3463 DESCRIPTOR_INPUT_MORE); 3464 3465 if (offset + rest < PAGE_SIZE) 3466 length = rest; 3467 else 3468 length = PAGE_SIZE - offset; 3469 pd->req_count = cpu_to_le16(length); 3470 pd->res_count = pd->req_count; 3471 pd->transfer_status = 0; 3472 3473 page_bus = page_private(buffer->pages[page]); 3474 pd->data_address = cpu_to_le32(page_bus + offset); 3475 3476 dma_sync_single_range_for_device(device, page_bus, 3477 offset, length, 3478 DMA_FROM_DEVICE); 3479 3480 offset = (offset + length) & ~PAGE_MASK; 3481 rest -= length; 3482 if (offset == 0) 3483 page++; 3484 } 3485 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3486 DESCRIPTOR_INPUT_LAST | 3487 DESCRIPTOR_BRANCH_ALWAYS); 3488 if (packet->interrupt && i == packet_count - 1) 3489 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3490 3491 context_append(&ctx->context, d, z, header_z); 3492 } 3493 3494 return 0; 3495 } 3496 3497 static int queue_iso_buffer_fill(struct iso_context *ctx, 3498 struct fw_iso_packet *packet, 3499 struct fw_iso_buffer *buffer, 3500 unsigned long payload) 3501 { 3502 struct descriptor *d; 3503 dma_addr_t d_bus, page_bus; 3504 int page, offset, rest, z, i, length; 3505 3506 page = payload >> PAGE_SHIFT; 3507 offset = payload & ~PAGE_MASK; 3508 rest = packet->payload_length; 3509 3510 /* We need one descriptor for each page in the buffer. */ 3511 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3512 3513 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3514 return -EFAULT; 3515 3516 for (i = 0; i < z; i++) { 3517 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3518 if (d == NULL) 3519 return -ENOMEM; 3520 3521 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3522 DESCRIPTOR_BRANCH_ALWAYS); 3523 if (packet->skip && i == 0) 3524 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3525 if (packet->interrupt && i == z - 1) 3526 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3527 3528 if (offset + rest < PAGE_SIZE) 3529 length = rest; 3530 else 3531 length = PAGE_SIZE - offset; 3532 d->req_count = cpu_to_le16(length); 3533 d->res_count = d->req_count; 3534 d->transfer_status = 0; 3535 3536 page_bus = page_private(buffer->pages[page]); 3537 d->data_address = cpu_to_le32(page_bus + offset); 3538 3539 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3540 page_bus, offset, length, 3541 DMA_FROM_DEVICE); 3542 3543 rest -= length; 3544 offset = 0; 3545 page++; 3546 3547 context_append(&ctx->context, d, 1, 0); 3548 } 3549 3550 return 0; 3551 } 3552 3553 static int ohci_queue_iso(struct fw_iso_context *base, 3554 struct fw_iso_packet *packet, 3555 struct fw_iso_buffer *buffer, 3556 unsigned long payload) 3557 { 3558 struct iso_context *ctx = container_of(base, struct iso_context, base); 3559 3560 guard(spinlock_irqsave)(&ctx->context.ohci->lock); 3561 3562 switch (base->type) { 3563 case FW_ISO_CONTEXT_TRANSMIT: 3564 return queue_iso_transmit(ctx, packet, buffer, payload); 3565 case FW_ISO_CONTEXT_RECEIVE: 3566 return queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3567 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3568 return queue_iso_buffer_fill(ctx, packet, buffer, payload); 3569 default: 3570 return -ENOSYS; 3571 } 3572 } 3573 3574 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3575 { 3576 struct context *ctx = 3577 &container_of(base, struct iso_context, base)->context; 3578 3579 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3580 } 3581 3582 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3583 { 3584 struct iso_context *ctx = container_of(base, struct iso_context, base); 3585 int ret = 0; 3586 3587 tasklet_disable_in_atomic(&ctx->context.tasklet); 3588 3589 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3590 context_tasklet((unsigned long)&ctx->context); 3591 3592 switch (base->type) { 3593 case FW_ISO_CONTEXT_TRANSMIT: 3594 case FW_ISO_CONTEXT_RECEIVE: 3595 if (ctx->header_length != 0) 3596 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3597 break; 3598 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3599 if (ctx->mc_completed != 0) 3600 flush_ir_buffer_fill(ctx); 3601 break; 3602 default: 3603 ret = -ENOSYS; 3604 } 3605 3606 clear_bit_unlock(0, &ctx->flushing_completions); 3607 smp_mb__after_atomic(); 3608 } 3609 3610 tasklet_enable(&ctx->context.tasklet); 3611 3612 return ret; 3613 } 3614 3615 static const struct fw_card_driver ohci_driver = { 3616 .enable = ohci_enable, 3617 .read_phy_reg = ohci_read_phy_reg, 3618 .update_phy_reg = ohci_update_phy_reg, 3619 .set_config_rom = ohci_set_config_rom, 3620 .send_request = ohci_send_request, 3621 .send_response = ohci_send_response, 3622 .cancel_packet = ohci_cancel_packet, 3623 .enable_phys_dma = ohci_enable_phys_dma, 3624 .read_csr = ohci_read_csr, 3625 .write_csr = ohci_write_csr, 3626 3627 .allocate_iso_context = ohci_allocate_iso_context, 3628 .free_iso_context = ohci_free_iso_context, 3629 .set_iso_channels = ohci_set_iso_channels, 3630 .queue_iso = ohci_queue_iso, 3631 .flush_queue_iso = ohci_flush_queue_iso, 3632 .flush_iso_completions = ohci_flush_iso_completions, 3633 .start_iso = ohci_start_iso, 3634 .stop_iso = ohci_stop_iso, 3635 }; 3636 3637 #ifdef CONFIG_PPC_PMAC 3638 static void pmac_ohci_on(struct pci_dev *dev) 3639 { 3640 if (machine_is(powermac)) { 3641 struct device_node *ofn = pci_device_to_OF_node(dev); 3642 3643 if (ofn) { 3644 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3645 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3646 } 3647 } 3648 } 3649 3650 static void pmac_ohci_off(struct pci_dev *dev) 3651 { 3652 if (machine_is(powermac)) { 3653 struct device_node *ofn = pci_device_to_OF_node(dev); 3654 3655 if (ofn) { 3656 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3657 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3658 } 3659 } 3660 } 3661 #else 3662 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3663 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3664 #endif /* CONFIG_PPC_PMAC */ 3665 3666 static void release_ohci(struct device *dev, void *data) 3667 { 3668 struct pci_dev *pdev = to_pci_dev(dev); 3669 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3670 3671 pmac_ohci_off(pdev); 3672 3673 ar_context_release(&ohci->ar_response_ctx); 3674 ar_context_release(&ohci->ar_request_ctx); 3675 3676 dev_notice(dev, "removed fw-ohci device\n"); 3677 } 3678 3679 static int pci_probe(struct pci_dev *dev, 3680 const struct pci_device_id *ent) 3681 { 3682 struct fw_ohci *ohci; 3683 u32 bus_options, max_receive, link_speed, version; 3684 u64 guid; 3685 int i, flags, irq, err; 3686 size_t size; 3687 3688 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3689 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3690 return -ENOSYS; 3691 } 3692 3693 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3694 if (ohci == NULL) 3695 return -ENOMEM; 3696 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3697 pci_set_drvdata(dev, ohci); 3698 pmac_ohci_on(dev); 3699 devres_add(&dev->dev, ohci); 3700 3701 err = pcim_enable_device(dev); 3702 if (err) { 3703 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3704 return err; 3705 } 3706 3707 pci_set_master(dev); 3708 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3709 3710 spin_lock_init(&ohci->lock); 3711 mutex_init(&ohci->phy_reg_mutex); 3712 3713 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3714 3715 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3716 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3717 ohci_err(ohci, "invalid MMIO resource\n"); 3718 return -ENXIO; 3719 } 3720 3721 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3722 if (err) { 3723 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3724 return -ENXIO; 3725 } 3726 ohci->registers = pcim_iomap_table(dev)[0]; 3727 3728 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3729 if ((ohci_quirks[i].vendor == dev->vendor) && 3730 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3731 ohci_quirks[i].device == dev->device) && 3732 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3733 ohci_quirks[i].revision >= dev->revision)) { 3734 ohci->quirks = ohci_quirks[i].flags; 3735 break; 3736 } 3737 if (param_quirks) 3738 ohci->quirks = param_quirks; 3739 3740 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3741 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3742 3743 /* 3744 * Because dma_alloc_coherent() allocates at least one page, 3745 * we save space by using a common buffer for the AR request/ 3746 * response descriptors and the self IDs buffer. 3747 */ 3748 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3749 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3750 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3751 GFP_KERNEL); 3752 if (!ohci->misc_buffer) 3753 return -ENOMEM; 3754 3755 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3756 OHCI1394_AsReqRcvContextControlSet); 3757 if (err < 0) 3758 return err; 3759 3760 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3761 OHCI1394_AsRspRcvContextControlSet); 3762 if (err < 0) 3763 return err; 3764 3765 err = context_init(&ohci->at_request_ctx, ohci, 3766 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3767 if (err < 0) 3768 return err; 3769 3770 err = context_init(&ohci->at_response_ctx, ohci, 3771 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3772 if (err < 0) 3773 return err; 3774 3775 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3776 ohci->ir_context_channels = ~0ULL; 3777 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3778 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3779 ohci->ir_context_mask = ohci->ir_context_support; 3780 ohci->n_ir = hweight32(ohci->ir_context_mask); 3781 size = sizeof(struct iso_context) * ohci->n_ir; 3782 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3783 if (!ohci->ir_context_list) 3784 return -ENOMEM; 3785 3786 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3787 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3788 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3789 if (!ohci->it_context_support) { 3790 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3791 ohci->it_context_support = 0xf; 3792 } 3793 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3794 ohci->it_context_mask = ohci->it_context_support; 3795 ohci->n_it = hweight32(ohci->it_context_mask); 3796 size = sizeof(struct iso_context) * ohci->n_it; 3797 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3798 if (!ohci->it_context_list) 3799 return -ENOMEM; 3800 3801 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3802 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3803 3804 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3805 max_receive = (bus_options >> 12) & 0xf; 3806 link_speed = bus_options & 0x7; 3807 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3808 reg_read(ohci, OHCI1394_GUIDLo); 3809 3810 flags = PCI_IRQ_INTX; 3811 if (!(ohci->quirks & QUIRK_NO_MSI)) 3812 flags |= PCI_IRQ_MSI; 3813 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3814 if (err < 0) 3815 return err; 3816 irq = pci_irq_vector(dev, 0); 3817 if (irq < 0) { 3818 err = irq; 3819 goto fail_msi; 3820 } 3821 3822 err = request_threaded_irq(irq, irq_handler, NULL, 3823 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3824 ohci); 3825 if (err < 0) { 3826 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3827 goto fail_msi; 3828 } 3829 3830 err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir); 3831 if (err) 3832 goto fail_irq; 3833 3834 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3835 ohci_notice(ohci, 3836 "added OHCI v%x.%x device as card %d, " 3837 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3838 version >> 16, version & 0xff, ohci->card.index, 3839 ohci->n_ir, ohci->n_it, ohci->quirks, 3840 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3841 ", physUB" : ""); 3842 3843 return 0; 3844 3845 fail_irq: 3846 free_irq(irq, ohci); 3847 fail_msi: 3848 pci_free_irq_vectors(dev); 3849 3850 return err; 3851 } 3852 3853 static void pci_remove(struct pci_dev *dev) 3854 { 3855 struct fw_ohci *ohci = pci_get_drvdata(dev); 3856 int irq; 3857 3858 /* 3859 * If the removal is happening from the suspend state, LPS won't be 3860 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3861 */ 3862 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3863 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3864 flush_writes(ohci); 3865 } 3866 cancel_work_sync(&ohci->bus_reset_work); 3867 fw_core_remove_card(&ohci->card); 3868 3869 /* 3870 * FIXME: Fail all pending packets here, now that the upper 3871 * layers can't queue any more. 3872 */ 3873 3874 software_reset(ohci); 3875 3876 irq = pci_irq_vector(dev, 0); 3877 if (irq >= 0) 3878 free_irq(irq, ohci); 3879 pci_free_irq_vectors(dev); 3880 3881 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3882 } 3883 3884 #ifdef CONFIG_PM 3885 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3886 { 3887 struct fw_ohci *ohci = pci_get_drvdata(dev); 3888 int err; 3889 3890 software_reset(ohci); 3891 err = pci_save_state(dev); 3892 if (err) { 3893 ohci_err(ohci, "pci_save_state failed\n"); 3894 return err; 3895 } 3896 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3897 if (err) 3898 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3899 pmac_ohci_off(dev); 3900 3901 return 0; 3902 } 3903 3904 static int pci_resume(struct pci_dev *dev) 3905 { 3906 struct fw_ohci *ohci = pci_get_drvdata(dev); 3907 int err; 3908 3909 pmac_ohci_on(dev); 3910 pci_set_power_state(dev, PCI_D0); 3911 pci_restore_state(dev); 3912 err = pci_enable_device(dev); 3913 if (err) { 3914 ohci_err(ohci, "pci_enable_device failed\n"); 3915 return err; 3916 } 3917 3918 /* Some systems don't setup GUID register on resume from ram */ 3919 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3920 !reg_read(ohci, OHCI1394_GUIDHi)) { 3921 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3922 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3923 } 3924 3925 err = ohci_enable(&ohci->card, NULL, 0); 3926 if (err) 3927 return err; 3928 3929 ohci_resume_iso_dma(ohci); 3930 3931 return 0; 3932 } 3933 #endif 3934 3935 static const struct pci_device_id pci_table[] = { 3936 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3937 { } 3938 }; 3939 3940 MODULE_DEVICE_TABLE(pci, pci_table); 3941 3942 static struct pci_driver fw_ohci_pci_driver = { 3943 .name = ohci_driver_name, 3944 .id_table = pci_table, 3945 .probe = pci_probe, 3946 .remove = pci_remove, 3947 #ifdef CONFIG_PM 3948 .resume = pci_resume, 3949 .suspend = pci_suspend, 3950 #endif 3951 }; 3952 3953 static int __init fw_ohci_init(void) 3954 { 3955 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3956 if (!selfid_workqueue) 3957 return -ENOMEM; 3958 3959 return pci_register_driver(&fw_ohci_pci_driver); 3960 } 3961 3962 static void __exit fw_ohci_cleanup(void) 3963 { 3964 pci_unregister_driver(&fw_ohci_pci_driver); 3965 destroy_workqueue(selfid_workqueue); 3966 } 3967 3968 module_init(fw_ohci_init); 3969 module_exit(fw_ohci_cleanup); 3970 3971 MODULE_AUTHOR("Kristian Hoegsberg <[email protected]>"); 3972 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3973 MODULE_LICENSE("GPL"); 3974 3975 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3976 MODULE_ALIAS("ohci1394"); 3977