1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <[email protected]> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 #include "packet-header-definitions.h" 44 #include "phy-packet-definitions.h" 45 46 #include <trace/events/firewire.h> 47 48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/firewire_ohci.h> 52 53 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 54 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 55 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 #define DESCRIPTOR_CMD (0xf << 12) 72 73 struct descriptor { 74 __le16 req_count; 75 __le16 control; 76 __le32 data_address; 77 __le32 branch_address; 78 __le16 res_count; 79 __le16 transfer_status; 80 } __attribute__((aligned(16))); 81 82 #define CONTROL_SET(regs) (regs) 83 #define CONTROL_CLEAR(regs) ((regs) + 4) 84 #define COMMAND_PTR(regs) ((regs) + 12) 85 #define CONTEXT_MATCH(regs) ((regs) + 16) 86 87 #define AR_BUFFER_SIZE (32*1024) 88 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 89 /* we need at least two pages for proper list management */ 90 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 91 92 #define MAX_ASYNC_PAYLOAD 4096 93 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 94 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 95 96 struct ar_context { 97 struct fw_ohci *ohci; 98 struct page *pages[AR_BUFFERS]; 99 void *buffer; 100 struct descriptor *descriptors; 101 dma_addr_t descriptors_bus; 102 void *pointer; 103 unsigned int last_buffer_index; 104 u32 regs; 105 struct tasklet_struct tasklet; 106 }; 107 108 struct context; 109 110 typedef int (*descriptor_callback_t)(struct context *ctx, 111 struct descriptor *d, 112 struct descriptor *last); 113 114 /* 115 * A buffer that contains a block of DMA-able coherent memory used for 116 * storing a portion of a DMA descriptor program. 117 */ 118 struct descriptor_buffer { 119 struct list_head list; 120 dma_addr_t buffer_bus; 121 size_t buffer_size; 122 size_t used; 123 struct descriptor buffer[]; 124 }; 125 126 struct context { 127 struct fw_ohci *ohci; 128 u32 regs; 129 int total_allocation; 130 u32 current_bus; 131 bool running; 132 bool flushing; 133 134 /* 135 * List of page-sized buffers for storing DMA descriptors. 136 * Head of list contains buffers in use and tail of list contains 137 * free buffers. 138 */ 139 struct list_head buffer_list; 140 141 /* 142 * Pointer to a buffer inside buffer_list that contains the tail 143 * end of the current DMA program. 144 */ 145 struct descriptor_buffer *buffer_tail; 146 147 /* 148 * The descriptor containing the branch address of the first 149 * descriptor that has not yet been filled by the device. 150 */ 151 struct descriptor *last; 152 153 /* 154 * The last descriptor block in the DMA program. It contains the branch 155 * address that must be updated upon appending a new descriptor. 156 */ 157 struct descriptor *prev; 158 int prev_z; 159 160 descriptor_callback_t callback; 161 162 struct tasklet_struct tasklet; 163 }; 164 165 struct iso_context { 166 struct fw_iso_context base; 167 struct context context; 168 void *header; 169 size_t header_length; 170 unsigned long flushing_completions; 171 u32 mc_buffer_bus; 172 u16 mc_completed; 173 u16 last_timestamp; 174 u8 sync; 175 u8 tags; 176 }; 177 178 #define CONFIG_ROM_SIZE 1024 179 180 struct fw_ohci { 181 struct fw_card card; 182 183 __iomem char *registers; 184 int node_id; 185 int generation; 186 int request_generation; /* for timestamping incoming requests */ 187 unsigned quirks; 188 unsigned int pri_req_max; 189 u32 bus_time; 190 bool bus_time_running; 191 bool is_root; 192 bool csr_state_setclear_abdicate; 193 int n_ir; 194 int n_it; 195 /* 196 * Spinlock for accessing fw_ohci data. Never call out of 197 * this driver with this lock held. 198 */ 199 spinlock_t lock; 200 201 struct mutex phy_reg_mutex; 202 203 void *misc_buffer; 204 dma_addr_t misc_buffer_bus; 205 206 struct ar_context ar_request_ctx; 207 struct ar_context ar_response_ctx; 208 struct context at_request_ctx; 209 struct context at_response_ctx; 210 211 u32 it_context_support; 212 u32 it_context_mask; /* unoccupied IT contexts */ 213 struct iso_context *it_context_list; 214 u64 ir_context_channels; /* unoccupied channels */ 215 u32 ir_context_support; 216 u32 ir_context_mask; /* unoccupied IR contexts */ 217 struct iso_context *ir_context_list; 218 u64 mc_channels; /* channels in use by the multichannel IR context */ 219 bool mc_allocated; 220 221 __be32 *config_rom; 222 dma_addr_t config_rom_bus; 223 __be32 *next_config_rom; 224 dma_addr_t next_config_rom_bus; 225 __be32 next_header; 226 227 __le32 *self_id; 228 dma_addr_t self_id_bus; 229 struct work_struct bus_reset_work; 230 231 u32 self_id_buffer[512]; 232 }; 233 234 static struct workqueue_struct *selfid_workqueue; 235 236 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 237 { 238 return container_of(card, struct fw_ohci, card); 239 } 240 241 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 242 #define IR_CONTEXT_BUFFER_FILL 0x80000000 243 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 244 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 245 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 246 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 247 248 #define CONTEXT_RUN 0x8000 249 #define CONTEXT_WAKE 0x1000 250 #define CONTEXT_DEAD 0x0800 251 #define CONTEXT_ACTIVE 0x0400 252 253 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 254 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 255 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 256 257 #define OHCI1394_REGISTER_SIZE 0x800 258 #define OHCI1394_PCI_HCI_Control 0x40 259 #define SELF_ID_BUF_SIZE 0x800 260 #define OHCI_VERSION_1_1 0x010010 261 262 static char ohci_driver_name[] = KBUILD_MODNAME; 263 264 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 265 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 266 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 267 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 268 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 269 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 270 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 271 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 272 #define PCI_REV_ID_VIA_VT6306 0x46 273 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 274 275 #define QUIRK_CYCLE_TIMER 0x1 276 #define QUIRK_RESET_PACKET 0x2 277 #define QUIRK_BE_HEADERS 0x4 278 #define QUIRK_NO_1394A 0x8 279 #define QUIRK_NO_MSI 0x10 280 #define QUIRK_TI_SLLZ059 0x20 281 #define QUIRK_IR_WAKE 0x40 282 283 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 284 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 285 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 286 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 287 // while it is probable due to detection of any type of PCIe error. 288 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 289 290 #if IS_ENABLED(CONFIG_X86) 291 292 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 293 { 294 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 295 } 296 297 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 298 299 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 300 { 301 const struct pci_dev *pcie_to_pci_bridge; 302 303 // Detect any type of AMD Ryzen machine. 304 if (!static_cpu_has(X86_FEATURE_ZEN)) 305 return false; 306 307 // Detect VIA VT6306/6307/6308. 308 if (pdev->vendor != PCI_VENDOR_ID_VIA) 309 return false; 310 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 311 return false; 312 313 // Detect Asmedia ASM1083/1085. 314 pcie_to_pci_bridge = pdev->bus->self; 315 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 316 return false; 317 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 318 return false; 319 320 return true; 321 } 322 323 #else 324 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 325 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 326 #endif 327 328 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 329 static const struct { 330 unsigned short vendor, device, revision, flags; 331 } ohci_quirks[] = { 332 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 333 QUIRK_CYCLE_TIMER}, 334 335 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 336 QUIRK_BE_HEADERS}, 337 338 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 339 QUIRK_NO_MSI}, 340 341 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 342 QUIRK_RESET_PACKET}, 343 344 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 345 QUIRK_NO_MSI}, 346 347 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 348 QUIRK_CYCLE_TIMER}, 349 350 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 351 QUIRK_NO_MSI}, 352 353 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 354 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 355 356 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 357 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 358 359 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 360 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 361 362 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 363 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 364 365 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 366 QUIRK_RESET_PACKET}, 367 368 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 369 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 370 371 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 372 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 373 374 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 375 QUIRK_NO_MSI}, 376 377 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 378 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 379 }; 380 381 /* This overrides anything that was found in ohci_quirks[]. */ 382 static int param_quirks; 383 module_param_named(quirks, param_quirks, int, 0644); 384 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 385 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 386 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 387 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 388 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 389 ", disable MSI = " __stringify(QUIRK_NO_MSI) 390 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 391 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 392 ")"); 393 394 #define OHCI_PARAM_DEBUG_AT_AR 1 395 #define OHCI_PARAM_DEBUG_SELFIDS 2 396 #define OHCI_PARAM_DEBUG_IRQS 4 397 398 static int param_debug; 399 module_param_named(debug, param_debug, int, 0644); 400 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 401 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 402 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 403 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 404 ", or a combination, or all = -1)"); 405 406 static bool param_remote_dma; 407 module_param_named(remote_dma, param_remote_dma, bool, 0444); 408 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 409 410 static void log_irqs(struct fw_ohci *ohci, u32 evt) 411 { 412 if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) 413 return; 414 415 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 416 evt & OHCI1394_selfIDComplete ? " selfID" : "", 417 evt & OHCI1394_RQPkt ? " AR_req" : "", 418 evt & OHCI1394_RSPkt ? " AR_resp" : "", 419 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 420 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 421 evt & OHCI1394_isochRx ? " IR" : "", 422 evt & OHCI1394_isochTx ? " IT" : "", 423 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 424 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 425 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 426 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 427 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 428 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 429 evt & OHCI1394_busReset ? " busReset" : "", 430 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 431 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 432 OHCI1394_respTxComplete | OHCI1394_isochRx | 433 OHCI1394_isochTx | OHCI1394_postedWriteErr | 434 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 435 OHCI1394_cycleInconsistent | 436 OHCI1394_regAccessFail | OHCI1394_busReset) 437 ? " ?" : ""); 438 } 439 440 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 441 { 442 static const char *const speed[] = { 443 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 444 }; 445 static const char *const power[] = { 446 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 447 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 448 }; 449 static const char port[] = { 450 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.', 451 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-', 452 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p', 453 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c', 454 }; 455 struct self_id_sequence_enumerator enumerator = { 456 .cursor = ohci->self_id_buffer, 457 .quadlet_count = self_id_count, 458 }; 459 460 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 461 return; 462 463 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 464 self_id_count, generation, ohci->node_id); 465 466 while (enumerator.quadlet_count > 0) { 467 unsigned int quadlet_count; 468 unsigned int port_index; 469 const u32 *s; 470 int i; 471 472 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count); 473 if (IS_ERR(s)) 474 break; 475 476 ohci_notice(ohci, 477 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 478 *s, 479 phy_packet_self_id_get_phy_id(*s), 480 port[self_id_sequence_get_port_status(s, quadlet_count, 0)], 481 port[self_id_sequence_get_port_status(s, quadlet_count, 1)], 482 port[self_id_sequence_get_port_status(s, quadlet_count, 2)], 483 speed[*s >> 14 & 3], *s >> 16 & 63, 484 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 485 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 486 487 port_index = 3; 488 for (i = 1; i < quadlet_count; ++i) { 489 ohci_notice(ohci, 490 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 491 s[i], 492 phy_packet_self_id_get_phy_id(s[i]), 493 port[self_id_sequence_get_port_status(s, quadlet_count, port_index)], 494 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)], 495 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)], 496 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)], 497 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)], 498 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)], 499 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)], 500 port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)] 501 ); 502 503 port_index += 8; 504 } 505 } 506 } 507 508 static const char *evts[] = { 509 [0x00] = "evt_no_status", [0x01] = "-reserved-", 510 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 511 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 512 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 513 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 514 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 515 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 516 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 517 [0x10] = "-reserved-", [0x11] = "ack_complete", 518 [0x12] = "ack_pending ", [0x13] = "-reserved-", 519 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 520 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 521 [0x18] = "-reserved-", [0x19] = "-reserved-", 522 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 523 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 524 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 525 [0x20] = "pending/cancelled", 526 }; 527 528 static void log_ar_at_event(struct fw_ohci *ohci, 529 char dir, int speed, u32 *header, int evt) 530 { 531 static const char *const tcodes[] = { 532 [TCODE_WRITE_QUADLET_REQUEST] = "QW req", 533 [TCODE_WRITE_BLOCK_REQUEST] = "BW req", 534 [TCODE_WRITE_RESPONSE] = "W resp", 535 [0x3] = "-reserved-", 536 [TCODE_READ_QUADLET_REQUEST] = "QR req", 537 [TCODE_READ_BLOCK_REQUEST] = "BR req", 538 [TCODE_READ_QUADLET_RESPONSE] = "QR resp", 539 [TCODE_READ_BLOCK_RESPONSE] = "BR resp", 540 [TCODE_CYCLE_START] = "cycle start", 541 [TCODE_LOCK_REQUEST] = "Lk req", 542 [TCODE_STREAM_DATA] = "async stream packet", 543 [TCODE_LOCK_RESPONSE] = "Lk resp", 544 [0xc] = "-reserved-", 545 [0xd] = "-reserved-", 546 [TCODE_LINK_INTERNAL] = "link internal", 547 [0xf] = "-reserved-", 548 }; 549 int tcode = async_header_get_tcode(header); 550 char specific[12]; 551 552 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 553 return; 554 555 if (unlikely(evt >= ARRAY_SIZE(evts))) 556 evt = 0x1f; 557 558 if (evt == OHCI1394_evt_bus_reset) { 559 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 560 dir, (header[2] >> 16) & 0xff); 561 return; 562 } 563 564 switch (tcode) { 565 case TCODE_WRITE_QUADLET_REQUEST: 566 case TCODE_READ_QUADLET_RESPONSE: 567 case TCODE_CYCLE_START: 568 snprintf(specific, sizeof(specific), " = %08x", 569 be32_to_cpu((__force __be32)header[3])); 570 break; 571 case TCODE_WRITE_BLOCK_REQUEST: 572 case TCODE_READ_BLOCK_REQUEST: 573 case TCODE_READ_BLOCK_RESPONSE: 574 case TCODE_LOCK_REQUEST: 575 case TCODE_LOCK_RESPONSE: 576 snprintf(specific, sizeof(specific), " %x,%x", 577 async_header_get_data_length(header), 578 async_header_get_extended_tcode(header)); 579 break; 580 default: 581 specific[0] = '\0'; 582 } 583 584 switch (tcode) { 585 case TCODE_STREAM_DATA: 586 ohci_notice(ohci, "A%c %s, %s\n", 587 dir, evts[evt], tcodes[tcode]); 588 break; 589 case TCODE_LINK_INTERNAL: 590 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 591 dir, evts[evt], header[1], header[2]); 592 break; 593 case TCODE_WRITE_QUADLET_REQUEST: 594 case TCODE_WRITE_BLOCK_REQUEST: 595 case TCODE_READ_QUADLET_REQUEST: 596 case TCODE_READ_BLOCK_REQUEST: 597 case TCODE_LOCK_REQUEST: 598 ohci_notice(ohci, 599 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n", 600 dir, speed, async_header_get_tlabel(header), 601 async_header_get_source(header), async_header_get_destination(header), 602 evts[evt], tcodes[tcode], async_header_get_offset(header), specific); 603 break; 604 default: 605 ohci_notice(ohci, 606 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 607 dir, speed, async_header_get_tlabel(header), 608 async_header_get_source(header), async_header_get_destination(header), 609 evts[evt], tcodes[tcode], specific); 610 } 611 } 612 613 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 614 { 615 writel(data, ohci->registers + offset); 616 } 617 618 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 619 { 620 return readl(ohci->registers + offset); 621 } 622 623 static inline void flush_writes(const struct fw_ohci *ohci) 624 { 625 /* Do a dummy read to flush writes. */ 626 reg_read(ohci, OHCI1394_Version); 627 } 628 629 /* 630 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 631 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 632 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 633 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 634 */ 635 static int read_phy_reg(struct fw_ohci *ohci, int addr) 636 { 637 u32 val; 638 int i; 639 640 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 641 for (i = 0; i < 3 + 100; i++) { 642 val = reg_read(ohci, OHCI1394_PhyControl); 643 if (!~val) 644 return -ENODEV; /* Card was ejected. */ 645 646 if (val & OHCI1394_PhyControl_ReadDone) 647 return OHCI1394_PhyControl_ReadData(val); 648 649 /* 650 * Try a few times without waiting. Sleeping is necessary 651 * only when the link/PHY interface is busy. 652 */ 653 if (i >= 3) 654 msleep(1); 655 } 656 ohci_err(ohci, "failed to read phy reg %d\n", addr); 657 dump_stack(); 658 659 return -EBUSY; 660 } 661 662 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 663 { 664 int i; 665 666 reg_write(ohci, OHCI1394_PhyControl, 667 OHCI1394_PhyControl_Write(addr, val)); 668 for (i = 0; i < 3 + 100; i++) { 669 val = reg_read(ohci, OHCI1394_PhyControl); 670 if (!~val) 671 return -ENODEV; /* Card was ejected. */ 672 673 if (!(val & OHCI1394_PhyControl_WritePending)) 674 return 0; 675 676 if (i >= 3) 677 msleep(1); 678 } 679 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 680 dump_stack(); 681 682 return -EBUSY; 683 } 684 685 static int update_phy_reg(struct fw_ohci *ohci, int addr, 686 int clear_bits, int set_bits) 687 { 688 int ret = read_phy_reg(ohci, addr); 689 if (ret < 0) 690 return ret; 691 692 /* 693 * The interrupt status bits are cleared by writing a one bit. 694 * Avoid clearing them unless explicitly requested in set_bits. 695 */ 696 if (addr == 5) 697 clear_bits |= PHY_INT_STATUS_BITS; 698 699 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 700 } 701 702 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 703 { 704 int ret; 705 706 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 707 if (ret < 0) 708 return ret; 709 710 return read_phy_reg(ohci, addr); 711 } 712 713 static int ohci_read_phy_reg(struct fw_card *card, int addr) 714 { 715 struct fw_ohci *ohci = fw_ohci(card); 716 717 guard(mutex)(&ohci->phy_reg_mutex); 718 719 return read_phy_reg(ohci, addr); 720 } 721 722 static int ohci_update_phy_reg(struct fw_card *card, int addr, 723 int clear_bits, int set_bits) 724 { 725 struct fw_ohci *ohci = fw_ohci(card); 726 727 guard(mutex)(&ohci->phy_reg_mutex); 728 729 return update_phy_reg(ohci, addr, clear_bits, set_bits); 730 } 731 732 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 733 { 734 return page_private(ctx->pages[i]); 735 } 736 737 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 738 { 739 struct descriptor *d; 740 741 d = &ctx->descriptors[index]; 742 d->branch_address &= cpu_to_le32(~0xf); 743 d->res_count = cpu_to_le16(PAGE_SIZE); 744 d->transfer_status = 0; 745 746 wmb(); /* finish init of new descriptors before branch_address update */ 747 d = &ctx->descriptors[ctx->last_buffer_index]; 748 d->branch_address |= cpu_to_le32(1); 749 750 ctx->last_buffer_index = index; 751 752 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 753 } 754 755 static void ar_context_release(struct ar_context *ctx) 756 { 757 struct device *dev = ctx->ohci->card.device; 758 unsigned int i; 759 760 if (!ctx->buffer) 761 return; 762 763 vunmap(ctx->buffer); 764 765 for (i = 0; i < AR_BUFFERS; i++) { 766 if (ctx->pages[i]) 767 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 768 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 769 } 770 } 771 772 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 773 { 774 struct fw_ohci *ohci = ctx->ohci; 775 776 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 777 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 778 flush_writes(ohci); 779 780 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 781 } 782 /* FIXME: restart? */ 783 } 784 785 static inline unsigned int ar_next_buffer_index(unsigned int index) 786 { 787 return (index + 1) % AR_BUFFERS; 788 } 789 790 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 791 { 792 return ar_next_buffer_index(ctx->last_buffer_index); 793 } 794 795 /* 796 * We search for the buffer that contains the last AR packet DMA data written 797 * by the controller. 798 */ 799 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 800 unsigned int *buffer_offset) 801 { 802 unsigned int i, next_i, last = ctx->last_buffer_index; 803 __le16 res_count, next_res_count; 804 805 i = ar_first_buffer_index(ctx); 806 res_count = READ_ONCE(ctx->descriptors[i].res_count); 807 808 /* A buffer that is not yet completely filled must be the last one. */ 809 while (i != last && res_count == 0) { 810 811 /* Peek at the next descriptor. */ 812 next_i = ar_next_buffer_index(i); 813 rmb(); /* read descriptors in order */ 814 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 815 /* 816 * If the next descriptor is still empty, we must stop at this 817 * descriptor. 818 */ 819 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 820 /* 821 * The exception is when the DMA data for one packet is 822 * split over three buffers; in this case, the middle 823 * buffer's descriptor might be never updated by the 824 * controller and look still empty, and we have to peek 825 * at the third one. 826 */ 827 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 828 next_i = ar_next_buffer_index(next_i); 829 rmb(); 830 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 831 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 832 goto next_buffer_is_active; 833 } 834 835 break; 836 } 837 838 next_buffer_is_active: 839 i = next_i; 840 res_count = next_res_count; 841 } 842 843 rmb(); /* read res_count before the DMA data */ 844 845 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 846 if (*buffer_offset > PAGE_SIZE) { 847 *buffer_offset = 0; 848 ar_context_abort(ctx, "corrupted descriptor"); 849 } 850 851 return i; 852 } 853 854 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 855 unsigned int end_buffer_index, 856 unsigned int end_buffer_offset) 857 { 858 unsigned int i; 859 860 i = ar_first_buffer_index(ctx); 861 while (i != end_buffer_index) { 862 dma_sync_single_for_cpu(ctx->ohci->card.device, 863 ar_buffer_bus(ctx, i), 864 PAGE_SIZE, DMA_FROM_DEVICE); 865 i = ar_next_buffer_index(i); 866 } 867 if (end_buffer_offset > 0) 868 dma_sync_single_for_cpu(ctx->ohci->card.device, 869 ar_buffer_bus(ctx, i), 870 end_buffer_offset, DMA_FROM_DEVICE); 871 } 872 873 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 874 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk) 875 { 876 return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value); 877 } 878 879 static bool has_be_header_quirk(const struct fw_ohci *ohci) 880 { 881 return !!(ohci->quirks & QUIRK_BE_HEADERS); 882 } 883 #else 884 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused) 885 { 886 return le32_to_cpu(value); 887 } 888 889 static bool has_be_header_quirk(const struct fw_ohci *ohci) 890 { 891 return false; 892 } 893 #endif 894 895 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 896 { 897 struct fw_ohci *ohci = ctx->ohci; 898 struct fw_packet p; 899 u32 status, length, tcode; 900 int evt; 901 902 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); 903 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); 904 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); 905 906 tcode = async_header_get_tcode(p.header); 907 switch (tcode) { 908 case TCODE_WRITE_QUADLET_REQUEST: 909 case TCODE_READ_QUADLET_RESPONSE: 910 p.header[3] = (__force __u32) buffer[3]; 911 p.header_length = 16; 912 p.payload_length = 0; 913 break; 914 915 case TCODE_READ_BLOCK_REQUEST : 916 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 917 p.header_length = 16; 918 p.payload_length = 0; 919 break; 920 921 case TCODE_WRITE_BLOCK_REQUEST: 922 case TCODE_READ_BLOCK_RESPONSE: 923 case TCODE_LOCK_REQUEST: 924 case TCODE_LOCK_RESPONSE: 925 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); 926 p.header_length = 16; 927 p.payload_length = async_header_get_data_length(p.header); 928 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 929 ar_context_abort(ctx, "invalid packet length"); 930 return NULL; 931 } 932 break; 933 934 case TCODE_WRITE_RESPONSE: 935 case TCODE_READ_QUADLET_REQUEST: 936 case TCODE_LINK_INTERNAL: 937 p.header_length = 12; 938 p.payload_length = 0; 939 break; 940 941 default: 942 ar_context_abort(ctx, "invalid tcode"); 943 return NULL; 944 } 945 946 p.payload = (void *) buffer + p.header_length; 947 948 /* FIXME: What to do about evt_* errors? */ 949 length = (p.header_length + p.payload_length + 3) / 4; 950 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); 951 evt = (status >> 16) & 0x1f; 952 953 p.ack = evt - 16; 954 p.speed = (status >> 21) & 0x7; 955 p.timestamp = status & 0xffff; 956 p.generation = ohci->request_generation; 957 958 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 959 960 /* 961 * Several controllers, notably from NEC and VIA, forget to 962 * write ack_complete status at PHY packet reception. 963 */ 964 if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL) 965 p.ack = ACK_COMPLETE; 966 967 /* 968 * The OHCI bus reset handler synthesizes a PHY packet with 969 * the new generation number when a bus reset happens (see 970 * section 8.4.2.3). This helps us determine when a request 971 * was received and make sure we send the response in the same 972 * generation. We only need this for requests; for responses 973 * we use the unique tlabel for finding the matching 974 * request. 975 * 976 * Alas some chips sometimes emit bus reset packets with a 977 * wrong generation. We set the correct generation for these 978 * at a slightly incorrect time (in bus_reset_work). 979 */ 980 if (evt == OHCI1394_evt_bus_reset) { 981 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 982 ohci->request_generation = (p.header[2] >> 16) & 0xff; 983 } else if (ctx == &ohci->ar_request_ctx) { 984 fw_core_handle_request(&ohci->card, &p); 985 } else { 986 fw_core_handle_response(&ohci->card, &p); 987 } 988 989 return buffer + length + 1; 990 } 991 992 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 993 { 994 void *next; 995 996 while (p < end) { 997 next = handle_ar_packet(ctx, p); 998 if (!next) 999 return p; 1000 p = next; 1001 } 1002 1003 return p; 1004 } 1005 1006 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 1007 { 1008 unsigned int i; 1009 1010 i = ar_first_buffer_index(ctx); 1011 while (i != end_buffer) { 1012 dma_sync_single_for_device(ctx->ohci->card.device, 1013 ar_buffer_bus(ctx, i), 1014 PAGE_SIZE, DMA_FROM_DEVICE); 1015 ar_context_link_page(ctx, i); 1016 i = ar_next_buffer_index(i); 1017 } 1018 } 1019 1020 static void ar_context_tasklet(unsigned long data) 1021 { 1022 struct ar_context *ctx = (struct ar_context *)data; 1023 unsigned int end_buffer_index, end_buffer_offset; 1024 void *p, *end; 1025 1026 p = ctx->pointer; 1027 if (!p) 1028 return; 1029 1030 end_buffer_index = ar_search_last_active_buffer(ctx, 1031 &end_buffer_offset); 1032 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 1033 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 1034 1035 if (end_buffer_index < ar_first_buffer_index(ctx)) { 1036 /* 1037 * The filled part of the overall buffer wraps around; handle 1038 * all packets up to the buffer end here. If the last packet 1039 * wraps around, its tail will be visible after the buffer end 1040 * because the buffer start pages are mapped there again. 1041 */ 1042 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 1043 p = handle_ar_packets(ctx, p, buffer_end); 1044 if (p < buffer_end) 1045 goto error; 1046 /* adjust p to point back into the actual buffer */ 1047 p -= AR_BUFFERS * PAGE_SIZE; 1048 } 1049 1050 p = handle_ar_packets(ctx, p, end); 1051 if (p != end) { 1052 if (p > end) 1053 ar_context_abort(ctx, "inconsistent descriptor"); 1054 goto error; 1055 } 1056 1057 ctx->pointer = p; 1058 ar_recycle_buffers(ctx, end_buffer_index); 1059 1060 return; 1061 1062 error: 1063 ctx->pointer = NULL; 1064 } 1065 1066 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1067 unsigned int descriptors_offset, u32 regs) 1068 { 1069 struct device *dev = ohci->card.device; 1070 unsigned int i; 1071 dma_addr_t dma_addr; 1072 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1073 struct descriptor *d; 1074 1075 ctx->regs = regs; 1076 ctx->ohci = ohci; 1077 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1078 1079 for (i = 0; i < AR_BUFFERS; i++) { 1080 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1081 DMA_FROM_DEVICE, GFP_KERNEL); 1082 if (!ctx->pages[i]) 1083 goto out_of_memory; 1084 set_page_private(ctx->pages[i], dma_addr); 1085 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1086 DMA_FROM_DEVICE); 1087 } 1088 1089 for (i = 0; i < AR_BUFFERS; i++) 1090 pages[i] = ctx->pages[i]; 1091 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1092 pages[AR_BUFFERS + i] = ctx->pages[i]; 1093 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1094 if (!ctx->buffer) 1095 goto out_of_memory; 1096 1097 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1098 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1099 1100 for (i = 0; i < AR_BUFFERS; i++) { 1101 d = &ctx->descriptors[i]; 1102 d->req_count = cpu_to_le16(PAGE_SIZE); 1103 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1104 DESCRIPTOR_STATUS | 1105 DESCRIPTOR_BRANCH_ALWAYS); 1106 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1107 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1108 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1109 } 1110 1111 return 0; 1112 1113 out_of_memory: 1114 ar_context_release(ctx); 1115 1116 return -ENOMEM; 1117 } 1118 1119 static void ar_context_run(struct ar_context *ctx) 1120 { 1121 unsigned int i; 1122 1123 for (i = 0; i < AR_BUFFERS; i++) 1124 ar_context_link_page(ctx, i); 1125 1126 ctx->pointer = ctx->buffer; 1127 1128 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1129 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1130 } 1131 1132 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1133 { 1134 __le16 branch; 1135 1136 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1137 1138 /* figure out which descriptor the branch address goes in */ 1139 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1140 return d; 1141 else 1142 return d + z - 1; 1143 } 1144 1145 static void context_tasklet(unsigned long data) 1146 { 1147 struct context *ctx = (struct context *) data; 1148 struct descriptor *d, *last; 1149 u32 address; 1150 int z; 1151 struct descriptor_buffer *desc; 1152 1153 desc = list_entry(ctx->buffer_list.next, 1154 struct descriptor_buffer, list); 1155 last = ctx->last; 1156 while (last->branch_address != 0) { 1157 struct descriptor_buffer *old_desc = desc; 1158 address = le32_to_cpu(last->branch_address); 1159 z = address & 0xf; 1160 address &= ~0xf; 1161 ctx->current_bus = address; 1162 1163 /* If the branch address points to a buffer outside of the 1164 * current buffer, advance to the next buffer. */ 1165 if (address < desc->buffer_bus || 1166 address >= desc->buffer_bus + desc->used) 1167 desc = list_entry(desc->list.next, 1168 struct descriptor_buffer, list); 1169 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1170 last = find_branch_descriptor(d, z); 1171 1172 if (!ctx->callback(ctx, d, last)) 1173 break; 1174 1175 if (old_desc != desc) { 1176 /* If we've advanced to the next buffer, move the 1177 * previous buffer to the free list. */ 1178 unsigned long flags; 1179 old_desc->used = 0; 1180 spin_lock_irqsave(&ctx->ohci->lock, flags); 1181 list_move_tail(&old_desc->list, &ctx->buffer_list); 1182 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1183 } 1184 ctx->last = last; 1185 } 1186 } 1187 1188 /* 1189 * Allocate a new buffer and add it to the list of free buffers for this 1190 * context. Must be called with ohci->lock held. 1191 */ 1192 static int context_add_buffer(struct context *ctx) 1193 { 1194 struct descriptor_buffer *desc; 1195 dma_addr_t bus_addr; 1196 int offset; 1197 1198 /* 1199 * 16MB of descriptors should be far more than enough for any DMA 1200 * program. This will catch run-away userspace or DoS attacks. 1201 */ 1202 if (ctx->total_allocation >= 16*1024*1024) 1203 return -ENOMEM; 1204 1205 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1206 if (!desc) 1207 return -ENOMEM; 1208 1209 offset = (void *)&desc->buffer - (void *)desc; 1210 /* 1211 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1212 * for descriptors, even 0x10-byte ones. This can cause page faults when 1213 * an IOMMU is in use and the oversized read crosses a page boundary. 1214 * Work around this by always leaving at least 0x10 bytes of padding. 1215 */ 1216 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1217 desc->buffer_bus = bus_addr + offset; 1218 desc->used = 0; 1219 1220 list_add_tail(&desc->list, &ctx->buffer_list); 1221 ctx->total_allocation += PAGE_SIZE; 1222 1223 return 0; 1224 } 1225 1226 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1227 u32 regs, descriptor_callback_t callback) 1228 { 1229 ctx->ohci = ohci; 1230 ctx->regs = regs; 1231 ctx->total_allocation = 0; 1232 1233 INIT_LIST_HEAD(&ctx->buffer_list); 1234 if (context_add_buffer(ctx) < 0) 1235 return -ENOMEM; 1236 1237 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1238 struct descriptor_buffer, list); 1239 1240 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1241 ctx->callback = callback; 1242 1243 /* 1244 * We put a dummy descriptor in the buffer that has a NULL 1245 * branch address and looks like it's been sent. That way we 1246 * have a descriptor to append DMA programs to. 1247 */ 1248 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1249 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1250 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1251 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1252 ctx->last = ctx->buffer_tail->buffer; 1253 ctx->prev = ctx->buffer_tail->buffer; 1254 ctx->prev_z = 1; 1255 1256 return 0; 1257 } 1258 1259 static void context_release(struct context *ctx) 1260 { 1261 struct fw_card *card = &ctx->ohci->card; 1262 struct descriptor_buffer *desc, *tmp; 1263 1264 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1265 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1266 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1267 } 1268 } 1269 1270 /* Must be called with ohci->lock held */ 1271 static struct descriptor *context_get_descriptors(struct context *ctx, 1272 int z, dma_addr_t *d_bus) 1273 { 1274 struct descriptor *d = NULL; 1275 struct descriptor_buffer *desc = ctx->buffer_tail; 1276 1277 if (z * sizeof(*d) > desc->buffer_size) 1278 return NULL; 1279 1280 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1281 /* No room for the descriptor in this buffer, so advance to the 1282 * next one. */ 1283 1284 if (desc->list.next == &ctx->buffer_list) { 1285 /* If there is no free buffer next in the list, 1286 * allocate one. */ 1287 if (context_add_buffer(ctx) < 0) 1288 return NULL; 1289 } 1290 desc = list_entry(desc->list.next, 1291 struct descriptor_buffer, list); 1292 ctx->buffer_tail = desc; 1293 } 1294 1295 d = desc->buffer + desc->used / sizeof(*d); 1296 memset(d, 0, z * sizeof(*d)); 1297 *d_bus = desc->buffer_bus + desc->used; 1298 1299 return d; 1300 } 1301 1302 static void context_run(struct context *ctx, u32 extra) 1303 { 1304 struct fw_ohci *ohci = ctx->ohci; 1305 1306 reg_write(ohci, COMMAND_PTR(ctx->regs), 1307 le32_to_cpu(ctx->last->branch_address)); 1308 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1309 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1310 ctx->running = true; 1311 flush_writes(ohci); 1312 } 1313 1314 static void context_append(struct context *ctx, 1315 struct descriptor *d, int z, int extra) 1316 { 1317 dma_addr_t d_bus; 1318 struct descriptor_buffer *desc = ctx->buffer_tail; 1319 struct descriptor *d_branch; 1320 1321 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1322 1323 desc->used += (z + extra) * sizeof(*d); 1324 1325 wmb(); /* finish init of new descriptors before branch_address update */ 1326 1327 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1328 d_branch->branch_address = cpu_to_le32(d_bus | z); 1329 1330 /* 1331 * VT6306 incorrectly checks only the single descriptor at the 1332 * CommandPtr when the wake bit is written, so if it's a 1333 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1334 * the branch address in the first descriptor. 1335 * 1336 * Not doing this for transmit contexts since not sure how it interacts 1337 * with skip addresses. 1338 */ 1339 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1340 d_branch != ctx->prev && 1341 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1342 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1343 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1344 } 1345 1346 ctx->prev = d; 1347 ctx->prev_z = z; 1348 } 1349 1350 static void context_stop(struct context *ctx) 1351 { 1352 struct fw_ohci *ohci = ctx->ohci; 1353 u32 reg; 1354 int i; 1355 1356 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1357 ctx->running = false; 1358 1359 for (i = 0; i < 1000; i++) { 1360 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1361 if ((reg & CONTEXT_ACTIVE) == 0) 1362 return; 1363 1364 if (i) 1365 udelay(10); 1366 } 1367 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1368 } 1369 1370 struct driver_data { 1371 u8 inline_data[8]; 1372 struct fw_packet *packet; 1373 }; 1374 1375 /* 1376 * This function apppends a packet to the DMA queue for transmission. 1377 * Must always be called with the ochi->lock held to ensure proper 1378 * generation handling and locking around packet queue manipulation. 1379 */ 1380 static int at_context_queue_packet(struct context *ctx, 1381 struct fw_packet *packet) 1382 { 1383 struct fw_ohci *ohci = ctx->ohci; 1384 dma_addr_t d_bus, payload_bus; 1385 struct driver_data *driver_data; 1386 struct descriptor *d, *last; 1387 __le32 *header; 1388 int z, tcode; 1389 1390 d = context_get_descriptors(ctx, 4, &d_bus); 1391 if (d == NULL) { 1392 packet->ack = RCODE_SEND_ERROR; 1393 return -1; 1394 } 1395 1396 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1397 d[0].res_count = cpu_to_le16(packet->timestamp); 1398 1399 tcode = async_header_get_tcode(packet->header); 1400 header = (__le32 *) &d[1]; 1401 switch (tcode) { 1402 case TCODE_WRITE_QUADLET_REQUEST: 1403 case TCODE_WRITE_BLOCK_REQUEST: 1404 case TCODE_WRITE_RESPONSE: 1405 case TCODE_READ_QUADLET_REQUEST: 1406 case TCODE_READ_BLOCK_REQUEST: 1407 case TCODE_READ_QUADLET_RESPONSE: 1408 case TCODE_READ_BLOCK_RESPONSE: 1409 case TCODE_LOCK_REQUEST: 1410 case TCODE_LOCK_RESPONSE: 1411 ohci1394_at_data_set_src_bus_id(header, false); 1412 ohci1394_at_data_set_speed(header, packet->speed); 1413 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header)); 1414 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header)); 1415 ohci1394_at_data_set_tcode(header, tcode); 1416 1417 ohci1394_at_data_set_destination_id(header, 1418 async_header_get_destination(packet->header)); 1419 1420 if (ctx == &ctx->ohci->at_response_ctx) { 1421 ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header)); 1422 } else { 1423 ohci1394_at_data_set_destination_offset(header, 1424 async_header_get_offset(packet->header)); 1425 } 1426 1427 if (tcode_is_block_packet(tcode)) 1428 header[3] = cpu_to_le32(packet->header[3]); 1429 else 1430 header[3] = (__force __le32) packet->header[3]; 1431 1432 d[0].req_count = cpu_to_le16(packet->header_length); 1433 break; 1434 case TCODE_LINK_INTERNAL: 1435 ohci1394_at_data_set_speed(header, packet->speed); 1436 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL); 1437 1438 header[1] = cpu_to_le32(packet->header[1]); 1439 header[2] = cpu_to_le32(packet->header[2]); 1440 d[0].req_count = cpu_to_le16(12); 1441 1442 if (is_ping_packet(&packet->header[1])) 1443 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1444 break; 1445 1446 case TCODE_STREAM_DATA: 1447 ohci1394_it_data_set_speed(header, packet->speed); 1448 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0])); 1449 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0])); 1450 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 1451 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0])); 1452 1453 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0])); 1454 1455 d[0].req_count = cpu_to_le16(8); 1456 break; 1457 1458 default: 1459 /* BUG(); */ 1460 packet->ack = RCODE_SEND_ERROR; 1461 return -1; 1462 } 1463 1464 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1465 driver_data = (struct driver_data *) &d[3]; 1466 driver_data->packet = packet; 1467 packet->driver_data = driver_data; 1468 1469 if (packet->payload_length > 0) { 1470 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1471 payload_bus = dma_map_single(ohci->card.device, 1472 packet->payload, 1473 packet->payload_length, 1474 DMA_TO_DEVICE); 1475 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1476 packet->ack = RCODE_SEND_ERROR; 1477 return -1; 1478 } 1479 packet->payload_bus = payload_bus; 1480 packet->payload_mapped = true; 1481 } else { 1482 memcpy(driver_data->inline_data, packet->payload, 1483 packet->payload_length); 1484 payload_bus = d_bus + 3 * sizeof(*d); 1485 } 1486 1487 d[2].req_count = cpu_to_le16(packet->payload_length); 1488 d[2].data_address = cpu_to_le32(payload_bus); 1489 last = &d[2]; 1490 z = 3; 1491 } else { 1492 last = &d[0]; 1493 z = 2; 1494 } 1495 1496 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1497 DESCRIPTOR_IRQ_ALWAYS | 1498 DESCRIPTOR_BRANCH_ALWAYS); 1499 1500 /* FIXME: Document how the locking works. */ 1501 if (ohci->generation != packet->generation) { 1502 if (packet->payload_mapped) 1503 dma_unmap_single(ohci->card.device, payload_bus, 1504 packet->payload_length, DMA_TO_DEVICE); 1505 packet->ack = RCODE_GENERATION; 1506 return -1; 1507 } 1508 1509 context_append(ctx, d, z, 4 - z); 1510 1511 if (ctx->running) 1512 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1513 else 1514 context_run(ctx, 0); 1515 1516 return 0; 1517 } 1518 1519 static void at_context_flush(struct context *ctx) 1520 { 1521 tasklet_disable(&ctx->tasklet); 1522 1523 ctx->flushing = true; 1524 context_tasklet((unsigned long)ctx); 1525 ctx->flushing = false; 1526 1527 tasklet_enable(&ctx->tasklet); 1528 } 1529 1530 static int handle_at_packet(struct context *context, 1531 struct descriptor *d, 1532 struct descriptor *last) 1533 { 1534 struct driver_data *driver_data; 1535 struct fw_packet *packet; 1536 struct fw_ohci *ohci = context->ohci; 1537 int evt; 1538 1539 if (last->transfer_status == 0 && !context->flushing) 1540 /* This descriptor isn't done yet, stop iteration. */ 1541 return 0; 1542 1543 driver_data = (struct driver_data *) &d[3]; 1544 packet = driver_data->packet; 1545 if (packet == NULL) 1546 /* This packet was cancelled, just continue. */ 1547 return 1; 1548 1549 if (packet->payload_mapped) 1550 dma_unmap_single(ohci->card.device, packet->payload_bus, 1551 packet->payload_length, DMA_TO_DEVICE); 1552 1553 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1554 packet->timestamp = le16_to_cpu(last->res_count); 1555 1556 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1557 1558 switch (evt) { 1559 case OHCI1394_evt_timeout: 1560 /* Async response transmit timed out. */ 1561 packet->ack = RCODE_CANCELLED; 1562 break; 1563 1564 case OHCI1394_evt_flushed: 1565 /* 1566 * The packet was flushed should give same error as 1567 * when we try to use a stale generation count. 1568 */ 1569 packet->ack = RCODE_GENERATION; 1570 break; 1571 1572 case OHCI1394_evt_missing_ack: 1573 if (context->flushing) 1574 packet->ack = RCODE_GENERATION; 1575 else { 1576 /* 1577 * Using a valid (current) generation count, but the 1578 * node is not on the bus or not sending acks. 1579 */ 1580 packet->ack = RCODE_NO_ACK; 1581 } 1582 break; 1583 1584 case ACK_COMPLETE + 0x10: 1585 case ACK_PENDING + 0x10: 1586 case ACK_BUSY_X + 0x10: 1587 case ACK_BUSY_A + 0x10: 1588 case ACK_BUSY_B + 0x10: 1589 case ACK_DATA_ERROR + 0x10: 1590 case ACK_TYPE_ERROR + 0x10: 1591 packet->ack = evt - 0x10; 1592 break; 1593 1594 case OHCI1394_evt_no_status: 1595 if (context->flushing) { 1596 packet->ack = RCODE_GENERATION; 1597 break; 1598 } 1599 fallthrough; 1600 1601 default: 1602 packet->ack = RCODE_SEND_ERROR; 1603 break; 1604 } 1605 1606 packet->callback(packet, &ohci->card, packet->ack); 1607 1608 return 1; 1609 } 1610 1611 static u32 get_cycle_time(struct fw_ohci *ohci); 1612 1613 static void handle_local_rom(struct fw_ohci *ohci, 1614 struct fw_packet *packet, u32 csr) 1615 { 1616 struct fw_packet response; 1617 int tcode, length, i; 1618 1619 tcode = async_header_get_tcode(packet->header); 1620 if (tcode_is_block_packet(tcode)) 1621 length = async_header_get_data_length(packet->header); 1622 else 1623 length = 4; 1624 1625 i = csr - CSR_CONFIG_ROM; 1626 if (i + length > CONFIG_ROM_SIZE) { 1627 fw_fill_response(&response, packet->header, 1628 RCODE_ADDRESS_ERROR, NULL, 0); 1629 } else if (!tcode_is_read_request(tcode)) { 1630 fw_fill_response(&response, packet->header, 1631 RCODE_TYPE_ERROR, NULL, 0); 1632 } else { 1633 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1634 (void *) ohci->config_rom + i, length); 1635 } 1636 1637 // Timestamping on behalf of the hardware. 1638 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1639 fw_core_handle_response(&ohci->card, &response); 1640 } 1641 1642 static void handle_local_lock(struct fw_ohci *ohci, 1643 struct fw_packet *packet, u32 csr) 1644 { 1645 struct fw_packet response; 1646 int tcode, length, ext_tcode, sel, try; 1647 __be32 *payload, lock_old; 1648 u32 lock_arg, lock_data; 1649 1650 tcode = async_header_get_tcode(packet->header); 1651 length = async_header_get_data_length(packet->header); 1652 payload = packet->payload; 1653 ext_tcode = async_header_get_extended_tcode(packet->header); 1654 1655 if (tcode == TCODE_LOCK_REQUEST && 1656 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1657 lock_arg = be32_to_cpu(payload[0]); 1658 lock_data = be32_to_cpu(payload[1]); 1659 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1660 lock_arg = 0; 1661 lock_data = 0; 1662 } else { 1663 fw_fill_response(&response, packet->header, 1664 RCODE_TYPE_ERROR, NULL, 0); 1665 goto out; 1666 } 1667 1668 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1669 reg_write(ohci, OHCI1394_CSRData, lock_data); 1670 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1671 reg_write(ohci, OHCI1394_CSRControl, sel); 1672 1673 for (try = 0; try < 20; try++) 1674 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1675 lock_old = cpu_to_be32(reg_read(ohci, 1676 OHCI1394_CSRData)); 1677 fw_fill_response(&response, packet->header, 1678 RCODE_COMPLETE, 1679 &lock_old, sizeof(lock_old)); 1680 goto out; 1681 } 1682 1683 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1684 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1685 1686 out: 1687 // Timestamping on behalf of the hardware. 1688 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1689 fw_core_handle_response(&ohci->card, &response); 1690 } 1691 1692 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1693 { 1694 u64 offset, csr; 1695 1696 if (ctx == &ctx->ohci->at_request_ctx) { 1697 packet->ack = ACK_PENDING; 1698 packet->callback(packet, &ctx->ohci->card, packet->ack); 1699 } 1700 1701 offset = async_header_get_offset(packet->header); 1702 csr = offset - CSR_REGISTER_BASE; 1703 1704 /* Handle config rom reads. */ 1705 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1706 handle_local_rom(ctx->ohci, packet, csr); 1707 else switch (csr) { 1708 case CSR_BUS_MANAGER_ID: 1709 case CSR_BANDWIDTH_AVAILABLE: 1710 case CSR_CHANNELS_AVAILABLE_HI: 1711 case CSR_CHANNELS_AVAILABLE_LO: 1712 handle_local_lock(ctx->ohci, packet, csr); 1713 break; 1714 default: 1715 if (ctx == &ctx->ohci->at_request_ctx) 1716 fw_core_handle_request(&ctx->ohci->card, packet); 1717 else 1718 fw_core_handle_response(&ctx->ohci->card, packet); 1719 break; 1720 } 1721 1722 if (ctx == &ctx->ohci->at_response_ctx) { 1723 packet->ack = ACK_COMPLETE; 1724 packet->callback(packet, &ctx->ohci->card, packet->ack); 1725 } 1726 } 1727 1728 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1729 { 1730 unsigned long flags; 1731 int ret; 1732 1733 spin_lock_irqsave(&ctx->ohci->lock, flags); 1734 1735 if (async_header_get_destination(packet->header) == ctx->ohci->node_id && 1736 ctx->ohci->generation == packet->generation) { 1737 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1738 1739 // Timestamping on behalf of the hardware. 1740 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1741 1742 handle_local_request(ctx, packet); 1743 return; 1744 } 1745 1746 ret = at_context_queue_packet(ctx, packet); 1747 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1748 1749 if (ret < 0) { 1750 // Timestamping on behalf of the hardware. 1751 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1752 1753 packet->callback(packet, &ctx->ohci->card, packet->ack); 1754 } 1755 } 1756 1757 static void detect_dead_context(struct fw_ohci *ohci, 1758 const char *name, unsigned int regs) 1759 { 1760 u32 ctl; 1761 1762 ctl = reg_read(ohci, CONTROL_SET(regs)); 1763 if (ctl & CONTEXT_DEAD) 1764 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1765 name, evts[ctl & 0x1f]); 1766 } 1767 1768 static void handle_dead_contexts(struct fw_ohci *ohci) 1769 { 1770 unsigned int i; 1771 char name[8]; 1772 1773 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1774 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1775 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1776 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1777 for (i = 0; i < 32; ++i) { 1778 if (!(ohci->it_context_support & (1 << i))) 1779 continue; 1780 sprintf(name, "IT%u", i); 1781 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1782 } 1783 for (i = 0; i < 32; ++i) { 1784 if (!(ohci->ir_context_support & (1 << i))) 1785 continue; 1786 sprintf(name, "IR%u", i); 1787 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1788 } 1789 /* TODO: maybe try to flush and restart the dead contexts */ 1790 } 1791 1792 static u32 cycle_timer_ticks(u32 cycle_timer) 1793 { 1794 u32 ticks; 1795 1796 ticks = cycle_timer & 0xfff; 1797 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1798 ticks += (3072 * 8000) * (cycle_timer >> 25); 1799 1800 return ticks; 1801 } 1802 1803 /* 1804 * Some controllers exhibit one or more of the following bugs when updating the 1805 * iso cycle timer register: 1806 * - When the lowest six bits are wrapping around to zero, a read that happens 1807 * at the same time will return garbage in the lowest ten bits. 1808 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1809 * not incremented for about 60 ns. 1810 * - Occasionally, the entire register reads zero. 1811 * 1812 * To catch these, we read the register three times and ensure that the 1813 * difference between each two consecutive reads is approximately the same, i.e. 1814 * less than twice the other. Furthermore, any negative difference indicates an 1815 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1816 * execute, so we have enough precision to compute the ratio of the differences.) 1817 */ 1818 static u32 get_cycle_time(struct fw_ohci *ohci) 1819 { 1820 u32 c0, c1, c2; 1821 u32 t0, t1, t2; 1822 s32 diff01, diff12; 1823 int i; 1824 1825 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1826 return 0; 1827 1828 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1829 1830 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1831 i = 0; 1832 c1 = c2; 1833 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1834 do { 1835 c0 = c1; 1836 c1 = c2; 1837 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1838 t0 = cycle_timer_ticks(c0); 1839 t1 = cycle_timer_ticks(c1); 1840 t2 = cycle_timer_ticks(c2); 1841 diff01 = t1 - t0; 1842 diff12 = t2 - t1; 1843 } while ((diff01 <= 0 || diff12 <= 0 || 1844 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1845 && i++ < 20); 1846 } 1847 1848 return c2; 1849 } 1850 1851 /* 1852 * This function has to be called at least every 64 seconds. The bus_time 1853 * field stores not only the upper 25 bits of the BUS_TIME register but also 1854 * the most significant bit of the cycle timer in bit 6 so that we can detect 1855 * changes in this bit. 1856 */ 1857 static u32 update_bus_time(struct fw_ohci *ohci) 1858 { 1859 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1860 1861 if (unlikely(!ohci->bus_time_running)) { 1862 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1863 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1864 (cycle_time_seconds & 0x40); 1865 ohci->bus_time_running = true; 1866 } 1867 1868 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1869 ohci->bus_time += 0x40; 1870 1871 return ohci->bus_time | cycle_time_seconds; 1872 } 1873 1874 static int get_status_for_port(struct fw_ohci *ohci, int port_index, 1875 enum phy_packet_self_id_port_status *status) 1876 { 1877 int reg; 1878 1879 scoped_guard(mutex, &ohci->phy_reg_mutex) { 1880 reg = write_phy_reg(ohci, 7, port_index); 1881 if (reg < 0) 1882 return reg; 1883 1884 reg = read_phy_reg(ohci, 8); 1885 if (reg < 0) 1886 return reg; 1887 } 1888 1889 switch (reg & 0x0f) { 1890 case 0x06: 1891 // is child node (connected to parent node) 1892 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT; 1893 break; 1894 case 0x0e: 1895 // is parent node (connected to child node) 1896 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD; 1897 break; 1898 default: 1899 // not connected 1900 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN; 1901 break; 1902 } 1903 1904 return 0; 1905 } 1906 1907 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1908 int self_id_count) 1909 { 1910 unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id); 1911 int i; 1912 1913 for (i = 0; i < self_id_count; i++) { 1914 u32 entry = ohci->self_id_buffer[i]; 1915 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry); 1916 1917 if (left_phy_id == right_phy_id) 1918 return -1; 1919 if (left_phy_id < right_phy_id) 1920 return i; 1921 } 1922 return i; 1923 } 1924 1925 static bool initiated_reset(struct fw_ohci *ohci) 1926 { 1927 int reg; 1928 1929 guard(mutex)(&ohci->phy_reg_mutex); 1930 1931 // Select page 7 1932 reg = write_phy_reg(ohci, 7, 0xe0); 1933 if (reg < 0) 1934 return reg; 1935 1936 reg = read_phy_reg(ohci, 8); 1937 if (reg < 0) 1938 return reg; 1939 1940 // set PMODE bit 1941 reg |= 0x40; 1942 reg = write_phy_reg(ohci, 8, reg); 1943 if (reg < 0) 1944 return reg; 1945 1946 // read register 12 1947 reg = read_phy_reg(ohci, 12); 1948 if (reg < 0) 1949 return reg; 1950 1951 // bit 3 indicates "initiated reset" 1952 return !!((reg & 0x08) == 0x08); 1953 } 1954 1955 /* 1956 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1957 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1958 * Construct the selfID from phy register contents. 1959 */ 1960 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1961 { 1962 int reg, i, pos; 1963 u32 self_id = 0; 1964 1965 // link active 1, speed 3, bridge 0, contender 1, more packets 0. 1966 phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID); 1967 phy_packet_self_id_zero_set_link_active(&self_id, true); 1968 phy_packet_self_id_zero_set_scode(&self_id, SCODE_800); 1969 phy_packet_self_id_zero_set_contender(&self_id, true); 1970 1971 reg = reg_read(ohci, OHCI1394_NodeID); 1972 if (!(reg & OHCI1394_NodeID_idValid)) { 1973 ohci_notice(ohci, 1974 "node ID not valid, new bus reset in progress\n"); 1975 return -EBUSY; 1976 } 1977 phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f); 1978 1979 reg = ohci_read_phy_reg(&ohci->card, 4); 1980 if (reg < 0) 1981 return reg; 1982 phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07); 1983 1984 reg = ohci_read_phy_reg(&ohci->card, 1); 1985 if (reg < 0) 1986 return reg; 1987 phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f); 1988 1989 for (i = 0; i < 3; i++) { 1990 enum phy_packet_self_id_port_status status; 1991 int err; 1992 1993 err = get_status_for_port(ohci, i, &status); 1994 if (err < 0) 1995 return err; 1996 1997 self_id_sequence_set_port_status(&self_id, 1, i, status); 1998 } 1999 2000 phy_packet_self_id_zero_set_initiated_reset(&self_id, initiated_reset(ohci)); 2001 2002 pos = get_self_id_pos(ohci, self_id, self_id_count); 2003 if (pos >= 0) { 2004 memmove(&(ohci->self_id_buffer[pos+1]), 2005 &(ohci->self_id_buffer[pos]), 2006 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 2007 ohci->self_id_buffer[pos] = self_id; 2008 self_id_count++; 2009 } 2010 return self_id_count; 2011 } 2012 2013 static void bus_reset_work(struct work_struct *work) 2014 { 2015 struct fw_ohci *ohci = 2016 container_of(work, struct fw_ohci, bus_reset_work); 2017 int self_id_count, generation, new_generation, i, j; 2018 u32 reg, quadlet; 2019 void *free_rom = NULL; 2020 dma_addr_t free_rom_bus = 0; 2021 bool is_new_root; 2022 2023 reg = reg_read(ohci, OHCI1394_NodeID); 2024 if (!(reg & OHCI1394_NodeID_idValid)) { 2025 ohci_notice(ohci, 2026 "node ID not valid, new bus reset in progress\n"); 2027 return; 2028 } 2029 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 2030 ohci_notice(ohci, "malconfigured bus\n"); 2031 return; 2032 } 2033 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 2034 OHCI1394_NodeID_nodeNumber); 2035 2036 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 2037 if (!(ohci->is_root && is_new_root)) 2038 reg_write(ohci, OHCI1394_LinkControlSet, 2039 OHCI1394_LinkControl_cycleMaster); 2040 ohci->is_root = is_new_root; 2041 2042 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2043 if (ohci1394_self_id_count_is_error(reg)) { 2044 ohci_notice(ohci, "self ID receive error\n"); 2045 return; 2046 } 2047 /* 2048 * The count in the SelfIDCount register is the number of 2049 * bytes in the self ID receive buffer. Since we also receive 2050 * the inverted quadlets and a header quadlet, we shift one 2051 * bit extra to get the actual number of self IDs. 2052 */ 2053 self_id_count = ohci1394_self_id_count_get_size(reg) >> 1; 2054 2055 if (self_id_count > 252) { 2056 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 2057 return; 2058 } 2059 2060 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); 2061 generation = ohci1394_self_id_receive_q0_get_generation(quadlet); 2062 rmb(); 2063 2064 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 2065 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); 2066 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); 2067 2068 if (id != ~id2) { 2069 /* 2070 * If the invalid data looks like a cycle start packet, 2071 * it's likely to be the result of the cycle master 2072 * having a wrong gap count. In this case, the self IDs 2073 * so far are valid and should be processed so that the 2074 * bus manager can then correct the gap count. 2075 */ 2076 if (id == 0xffff008f) { 2077 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2078 self_id_count = j; 2079 break; 2080 } 2081 2082 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2083 j, self_id_count, id, id2); 2084 return; 2085 } 2086 ohci->self_id_buffer[j] = id; 2087 } 2088 2089 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2090 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2091 if (self_id_count < 0) { 2092 ohci_notice(ohci, 2093 "could not construct local self ID\n"); 2094 return; 2095 } 2096 } 2097 2098 if (self_id_count == 0) { 2099 ohci_notice(ohci, "no self IDs\n"); 2100 return; 2101 } 2102 rmb(); 2103 2104 /* 2105 * Check the consistency of the self IDs we just read. The 2106 * problem we face is that a new bus reset can start while we 2107 * read out the self IDs from the DMA buffer. If this happens, 2108 * the DMA buffer will be overwritten with new self IDs and we 2109 * will read out inconsistent data. The OHCI specification 2110 * (section 11.2) recommends a technique similar to 2111 * linux/seqlock.h, where we remember the generation of the 2112 * self IDs in the buffer before reading them out and compare 2113 * it to the current generation after reading them out. If 2114 * the two generations match we know we have a consistent set 2115 * of self IDs. 2116 */ 2117 2118 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2119 new_generation = ohci1394_self_id_count_get_generation(reg); 2120 if (new_generation != generation) { 2121 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2122 return; 2123 } 2124 2125 /* FIXME: Document how the locking works. */ 2126 spin_lock_irq(&ohci->lock); 2127 2128 ohci->generation = -1; /* prevent AT packet queueing */ 2129 context_stop(&ohci->at_request_ctx); 2130 context_stop(&ohci->at_response_ctx); 2131 2132 spin_unlock_irq(&ohci->lock); 2133 2134 /* 2135 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2136 * packets in the AT queues and software needs to drain them. 2137 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2138 */ 2139 at_context_flush(&ohci->at_request_ctx); 2140 at_context_flush(&ohci->at_response_ctx); 2141 2142 spin_lock_irq(&ohci->lock); 2143 2144 ohci->generation = generation; 2145 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2146 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2147 2148 if (ohci->quirks & QUIRK_RESET_PACKET) 2149 ohci->request_generation = generation; 2150 2151 /* 2152 * This next bit is unrelated to the AT context stuff but we 2153 * have to do it under the spinlock also. If a new config rom 2154 * was set up before this reset, the old one is now no longer 2155 * in use and we can free it. Update the config rom pointers 2156 * to point to the current config rom and clear the 2157 * next_config_rom pointer so a new update can take place. 2158 */ 2159 2160 if (ohci->next_config_rom != NULL) { 2161 if (ohci->next_config_rom != ohci->config_rom) { 2162 free_rom = ohci->config_rom; 2163 free_rom_bus = ohci->config_rom_bus; 2164 } 2165 ohci->config_rom = ohci->next_config_rom; 2166 ohci->config_rom_bus = ohci->next_config_rom_bus; 2167 ohci->next_config_rom = NULL; 2168 2169 /* 2170 * Restore config_rom image and manually update 2171 * config_rom registers. Writing the header quadlet 2172 * will indicate that the config rom is ready, so we 2173 * do that last. 2174 */ 2175 reg_write(ohci, OHCI1394_BusOptions, 2176 be32_to_cpu(ohci->config_rom[2])); 2177 ohci->config_rom[0] = ohci->next_header; 2178 reg_write(ohci, OHCI1394_ConfigROMhdr, 2179 be32_to_cpu(ohci->next_header)); 2180 } 2181 2182 if (param_remote_dma) { 2183 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2184 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2185 } 2186 2187 spin_unlock_irq(&ohci->lock); 2188 2189 if (free_rom) 2190 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2191 2192 log_selfids(ohci, generation, self_id_count); 2193 2194 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2195 self_id_count, ohci->self_id_buffer, 2196 ohci->csr_state_setclear_abdicate); 2197 ohci->csr_state_setclear_abdicate = false; 2198 } 2199 2200 static irqreturn_t irq_handler(int irq, void *data) 2201 { 2202 struct fw_ohci *ohci = data; 2203 u32 event, iso_event; 2204 int i; 2205 2206 event = reg_read(ohci, OHCI1394_IntEventClear); 2207 2208 if (!event || !~event) 2209 return IRQ_NONE; 2210 2211 /* 2212 * busReset and postedWriteErr events must not be cleared yet 2213 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2214 */ 2215 reg_write(ohci, OHCI1394_IntEventClear, 2216 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2217 trace_irqs(ohci->card.index, event); 2218 log_irqs(ohci, event); 2219 // The flag is masked again at bus_reset_work() scheduled by selfID event. 2220 if (event & OHCI1394_busReset) 2221 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2222 2223 if (event & OHCI1394_selfIDComplete) { 2224 if (trace_self_id_complete_enabled()) { 2225 u32 reg = reg_read(ohci, OHCI1394_SelfIDCount); 2226 2227 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, 2228 has_be_header_quirk(ohci)); 2229 } 2230 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2231 } 2232 2233 if (event & OHCI1394_RQPkt) 2234 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2235 2236 if (event & OHCI1394_RSPkt) 2237 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2238 2239 if (event & OHCI1394_reqTxComplete) 2240 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2241 2242 if (event & OHCI1394_respTxComplete) 2243 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2244 2245 if (event & OHCI1394_isochRx) { 2246 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2247 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2248 2249 while (iso_event) { 2250 i = ffs(iso_event) - 1; 2251 tasklet_schedule( 2252 &ohci->ir_context_list[i].context.tasklet); 2253 iso_event &= ~(1 << i); 2254 } 2255 } 2256 2257 if (event & OHCI1394_isochTx) { 2258 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2259 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2260 2261 while (iso_event) { 2262 i = ffs(iso_event) - 1; 2263 tasklet_schedule( 2264 &ohci->it_context_list[i].context.tasklet); 2265 iso_event &= ~(1 << i); 2266 } 2267 } 2268 2269 if (unlikely(event & OHCI1394_regAccessFail)) 2270 ohci_err(ohci, "register access failure\n"); 2271 2272 if (unlikely(event & OHCI1394_postedWriteErr)) { 2273 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2274 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2275 reg_write(ohci, OHCI1394_IntEventClear, 2276 OHCI1394_postedWriteErr); 2277 if (printk_ratelimit()) 2278 ohci_err(ohci, "PCI posted write error\n"); 2279 } 2280 2281 if (unlikely(event & OHCI1394_cycleTooLong)) { 2282 if (printk_ratelimit()) 2283 ohci_notice(ohci, "isochronous cycle too long\n"); 2284 reg_write(ohci, OHCI1394_LinkControlSet, 2285 OHCI1394_LinkControl_cycleMaster); 2286 } 2287 2288 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2289 /* 2290 * We need to clear this event bit in order to make 2291 * cycleMatch isochronous I/O work. In theory we should 2292 * stop active cycleMatch iso contexts now and restart 2293 * them at least two cycles later. (FIXME?) 2294 */ 2295 if (printk_ratelimit()) 2296 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2297 } 2298 2299 if (unlikely(event & OHCI1394_unrecoverableError)) 2300 handle_dead_contexts(ohci); 2301 2302 if (event & OHCI1394_cycle64Seconds) { 2303 guard(spinlock)(&ohci->lock); 2304 update_bus_time(ohci); 2305 } else 2306 flush_writes(ohci); 2307 2308 return IRQ_HANDLED; 2309 } 2310 2311 static int software_reset(struct fw_ohci *ohci) 2312 { 2313 u32 val; 2314 int i; 2315 2316 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2317 for (i = 0; i < 500; i++) { 2318 val = reg_read(ohci, OHCI1394_HCControlSet); 2319 if (!~val) 2320 return -ENODEV; /* Card was ejected. */ 2321 2322 if (!(val & OHCI1394_HCControl_softReset)) 2323 return 0; 2324 2325 msleep(1); 2326 } 2327 2328 return -EBUSY; 2329 } 2330 2331 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2332 { 2333 size_t size = length * 4; 2334 2335 memcpy(dest, src, size); 2336 if (size < CONFIG_ROM_SIZE) 2337 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2338 } 2339 2340 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2341 { 2342 bool enable_1394a; 2343 int ret, clear, set, offset; 2344 2345 /* Check if the driver should configure link and PHY. */ 2346 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2347 OHCI1394_HCControl_programPhyEnable)) 2348 return 0; 2349 2350 /* Paranoia: check whether the PHY supports 1394a, too. */ 2351 enable_1394a = false; 2352 ret = read_phy_reg(ohci, 2); 2353 if (ret < 0) 2354 return ret; 2355 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2356 ret = read_paged_phy_reg(ohci, 1, 8); 2357 if (ret < 0) 2358 return ret; 2359 if (ret >= 1) 2360 enable_1394a = true; 2361 } 2362 2363 if (ohci->quirks & QUIRK_NO_1394A) 2364 enable_1394a = false; 2365 2366 /* Configure PHY and link consistently. */ 2367 if (enable_1394a) { 2368 clear = 0; 2369 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2370 } else { 2371 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2372 set = 0; 2373 } 2374 ret = update_phy_reg(ohci, 5, clear, set); 2375 if (ret < 0) 2376 return ret; 2377 2378 if (enable_1394a) 2379 offset = OHCI1394_HCControlSet; 2380 else 2381 offset = OHCI1394_HCControlClear; 2382 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2383 2384 /* Clean up: configuration has been taken care of. */ 2385 reg_write(ohci, OHCI1394_HCControlClear, 2386 OHCI1394_HCControl_programPhyEnable); 2387 2388 return 0; 2389 } 2390 2391 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2392 { 2393 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2394 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2395 int reg, i; 2396 2397 reg = read_phy_reg(ohci, 2); 2398 if (reg < 0) 2399 return reg; 2400 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2401 return 0; 2402 2403 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2404 reg = read_paged_phy_reg(ohci, 1, i + 10); 2405 if (reg < 0) 2406 return reg; 2407 if (reg != id[i]) 2408 return 0; 2409 } 2410 return 1; 2411 } 2412 2413 static int ohci_enable(struct fw_card *card, 2414 const __be32 *config_rom, size_t length) 2415 { 2416 struct fw_ohci *ohci = fw_ohci(card); 2417 u32 lps, version, irqs; 2418 int i, ret; 2419 2420 ret = software_reset(ohci); 2421 if (ret < 0) { 2422 ohci_err(ohci, "failed to reset ohci card\n"); 2423 return ret; 2424 } 2425 2426 /* 2427 * Now enable LPS, which we need in order to start accessing 2428 * most of the registers. In fact, on some cards (ALI M5251), 2429 * accessing registers in the SClk domain without LPS enabled 2430 * will lock up the machine. Wait 50msec to make sure we have 2431 * full link enabled. However, with some cards (well, at least 2432 * a JMicron PCIe card), we have to try again sometimes. 2433 * 2434 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2435 * cannot actually use the phy at that time. These need tens of 2436 * millisecods pause between LPS write and first phy access too. 2437 */ 2438 2439 reg_write(ohci, OHCI1394_HCControlSet, 2440 OHCI1394_HCControl_LPS | 2441 OHCI1394_HCControl_postedWriteEnable); 2442 flush_writes(ohci); 2443 2444 for (lps = 0, i = 0; !lps && i < 3; i++) { 2445 msleep(50); 2446 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2447 OHCI1394_HCControl_LPS; 2448 } 2449 2450 if (!lps) { 2451 ohci_err(ohci, "failed to set Link Power Status\n"); 2452 return -EIO; 2453 } 2454 2455 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2456 ret = probe_tsb41ba3d(ohci); 2457 if (ret < 0) 2458 return ret; 2459 if (ret) 2460 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2461 else 2462 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2463 } 2464 2465 reg_write(ohci, OHCI1394_HCControlClear, 2466 OHCI1394_HCControl_noByteSwapData); 2467 2468 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2469 reg_write(ohci, OHCI1394_LinkControlSet, 2470 OHCI1394_LinkControl_cycleTimerEnable | 2471 OHCI1394_LinkControl_cycleMaster); 2472 2473 reg_write(ohci, OHCI1394_ATRetries, 2474 OHCI1394_MAX_AT_REQ_RETRIES | 2475 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2476 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2477 (200 << 16)); 2478 2479 ohci->bus_time_running = false; 2480 2481 for (i = 0; i < 32; i++) 2482 if (ohci->ir_context_support & (1 << i)) 2483 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2484 IR_CONTEXT_MULTI_CHANNEL_MODE); 2485 2486 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2487 if (version >= OHCI_VERSION_1_1) { 2488 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2489 0xfffffffe); 2490 card->broadcast_channel_auto_allocated = true; 2491 } 2492 2493 /* Get implemented bits of the priority arbitration request counter. */ 2494 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2495 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2496 reg_write(ohci, OHCI1394_FairnessControl, 0); 2497 card->priority_budget_implemented = ohci->pri_req_max != 0; 2498 2499 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2500 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2501 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2502 2503 ret = configure_1394a_enhancements(ohci); 2504 if (ret < 0) 2505 return ret; 2506 2507 /* Activate link_on bit and contender bit in our self ID packets.*/ 2508 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2509 if (ret < 0) 2510 return ret; 2511 2512 /* 2513 * When the link is not yet enabled, the atomic config rom 2514 * update mechanism described below in ohci_set_config_rom() 2515 * is not active. We have to update ConfigRomHeader and 2516 * BusOptions manually, and the write to ConfigROMmap takes 2517 * effect immediately. We tie this to the enabling of the 2518 * link, so we have a valid config rom before enabling - the 2519 * OHCI requires that ConfigROMhdr and BusOptions have valid 2520 * values before enabling. 2521 * 2522 * However, when the ConfigROMmap is written, some controllers 2523 * always read back quadlets 0 and 2 from the config rom to 2524 * the ConfigRomHeader and BusOptions registers on bus reset. 2525 * They shouldn't do that in this initial case where the link 2526 * isn't enabled. This means we have to use the same 2527 * workaround here, setting the bus header to 0 and then write 2528 * the right values in the bus reset tasklet. 2529 */ 2530 2531 if (config_rom) { 2532 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2533 &ohci->next_config_rom_bus, GFP_KERNEL); 2534 if (ohci->next_config_rom == NULL) 2535 return -ENOMEM; 2536 2537 copy_config_rom(ohci->next_config_rom, config_rom, length); 2538 } else { 2539 /* 2540 * In the suspend case, config_rom is NULL, which 2541 * means that we just reuse the old config rom. 2542 */ 2543 ohci->next_config_rom = ohci->config_rom; 2544 ohci->next_config_rom_bus = ohci->config_rom_bus; 2545 } 2546 2547 ohci->next_header = ohci->next_config_rom[0]; 2548 ohci->next_config_rom[0] = 0; 2549 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2550 reg_write(ohci, OHCI1394_BusOptions, 2551 be32_to_cpu(ohci->next_config_rom[2])); 2552 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2553 2554 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2555 2556 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2557 OHCI1394_RQPkt | OHCI1394_RSPkt | 2558 OHCI1394_isochTx | OHCI1394_isochRx | 2559 OHCI1394_postedWriteErr | 2560 OHCI1394_selfIDComplete | 2561 OHCI1394_regAccessFail | 2562 OHCI1394_cycleInconsistent | 2563 OHCI1394_unrecoverableError | 2564 OHCI1394_cycleTooLong | 2565 OHCI1394_masterIntEnable | 2566 OHCI1394_busReset; 2567 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2568 2569 reg_write(ohci, OHCI1394_HCControlSet, 2570 OHCI1394_HCControl_linkEnable | 2571 OHCI1394_HCControl_BIBimageValid); 2572 2573 reg_write(ohci, OHCI1394_LinkControlSet, 2574 OHCI1394_LinkControl_rcvSelfID | 2575 OHCI1394_LinkControl_rcvPhyPkt); 2576 2577 ar_context_run(&ohci->ar_request_ctx); 2578 ar_context_run(&ohci->ar_response_ctx); 2579 2580 flush_writes(ohci); 2581 2582 /* We are ready to go, reset bus to finish initialization. */ 2583 fw_schedule_bus_reset(&ohci->card, false, true); 2584 2585 return 0; 2586 } 2587 2588 static int ohci_set_config_rom(struct fw_card *card, 2589 const __be32 *config_rom, size_t length) 2590 { 2591 struct fw_ohci *ohci; 2592 __be32 *next_config_rom; 2593 dma_addr_t next_config_rom_bus; 2594 2595 ohci = fw_ohci(card); 2596 2597 /* 2598 * When the OHCI controller is enabled, the config rom update 2599 * mechanism is a bit tricky, but easy enough to use. See 2600 * section 5.5.6 in the OHCI specification. 2601 * 2602 * The OHCI controller caches the new config rom address in a 2603 * shadow register (ConfigROMmapNext) and needs a bus reset 2604 * for the changes to take place. When the bus reset is 2605 * detected, the controller loads the new values for the 2606 * ConfigRomHeader and BusOptions registers from the specified 2607 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2608 * shadow register. All automatically and atomically. 2609 * 2610 * Now, there's a twist to this story. The automatic load of 2611 * ConfigRomHeader and BusOptions doesn't honor the 2612 * noByteSwapData bit, so with a be32 config rom, the 2613 * controller will load be32 values in to these registers 2614 * during the atomic update, even on litte endian 2615 * architectures. The workaround we use is to put a 0 in the 2616 * header quadlet; 0 is endian agnostic and means that the 2617 * config rom isn't ready yet. In the bus reset tasklet we 2618 * then set up the real values for the two registers. 2619 * 2620 * We use ohci->lock to avoid racing with the code that sets 2621 * ohci->next_config_rom to NULL (see bus_reset_work). 2622 */ 2623 2624 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2625 &next_config_rom_bus, GFP_KERNEL); 2626 if (next_config_rom == NULL) 2627 return -ENOMEM; 2628 2629 spin_lock_irq(&ohci->lock); 2630 2631 /* 2632 * If there is not an already pending config_rom update, 2633 * push our new allocation into the ohci->next_config_rom 2634 * and then mark the local variable as null so that we 2635 * won't deallocate the new buffer. 2636 * 2637 * OTOH, if there is a pending config_rom update, just 2638 * use that buffer with the new config_rom data, and 2639 * let this routine free the unused DMA allocation. 2640 */ 2641 2642 if (ohci->next_config_rom == NULL) { 2643 ohci->next_config_rom = next_config_rom; 2644 ohci->next_config_rom_bus = next_config_rom_bus; 2645 next_config_rom = NULL; 2646 } 2647 2648 copy_config_rom(ohci->next_config_rom, config_rom, length); 2649 2650 ohci->next_header = config_rom[0]; 2651 ohci->next_config_rom[0] = 0; 2652 2653 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2654 2655 spin_unlock_irq(&ohci->lock); 2656 2657 /* If we didn't use the DMA allocation, delete it. */ 2658 if (next_config_rom != NULL) { 2659 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2660 next_config_rom_bus); 2661 } 2662 2663 /* 2664 * Now initiate a bus reset to have the changes take 2665 * effect. We clean up the old config rom memory and DMA 2666 * mappings in the bus reset tasklet, since the OHCI 2667 * controller could need to access it before the bus reset 2668 * takes effect. 2669 */ 2670 2671 fw_schedule_bus_reset(&ohci->card, true, true); 2672 2673 return 0; 2674 } 2675 2676 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2677 { 2678 struct fw_ohci *ohci = fw_ohci(card); 2679 2680 at_context_transmit(&ohci->at_request_ctx, packet); 2681 } 2682 2683 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2684 { 2685 struct fw_ohci *ohci = fw_ohci(card); 2686 2687 at_context_transmit(&ohci->at_response_ctx, packet); 2688 } 2689 2690 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2691 { 2692 struct fw_ohci *ohci = fw_ohci(card); 2693 struct context *ctx = &ohci->at_request_ctx; 2694 struct driver_data *driver_data = packet->driver_data; 2695 int ret = -ENOENT; 2696 2697 tasklet_disable_in_atomic(&ctx->tasklet); 2698 2699 if (packet->ack != 0) 2700 goto out; 2701 2702 if (packet->payload_mapped) 2703 dma_unmap_single(ohci->card.device, packet->payload_bus, 2704 packet->payload_length, DMA_TO_DEVICE); 2705 2706 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2707 driver_data->packet = NULL; 2708 packet->ack = RCODE_CANCELLED; 2709 2710 // Timestamping on behalf of the hardware. 2711 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2712 2713 packet->callback(packet, &ohci->card, packet->ack); 2714 ret = 0; 2715 out: 2716 tasklet_enable(&ctx->tasklet); 2717 2718 return ret; 2719 } 2720 2721 static int ohci_enable_phys_dma(struct fw_card *card, 2722 int node_id, int generation) 2723 { 2724 struct fw_ohci *ohci = fw_ohci(card); 2725 unsigned long flags; 2726 int n, ret = 0; 2727 2728 if (param_remote_dma) 2729 return 0; 2730 2731 /* 2732 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2733 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2734 */ 2735 2736 spin_lock_irqsave(&ohci->lock, flags); 2737 2738 if (ohci->generation != generation) { 2739 ret = -ESTALE; 2740 goto out; 2741 } 2742 2743 /* 2744 * Note, if the node ID contains a non-local bus ID, physical DMA is 2745 * enabled for _all_ nodes on remote buses. 2746 */ 2747 2748 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2749 if (n < 32) 2750 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2751 else 2752 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2753 2754 flush_writes(ohci); 2755 out: 2756 spin_unlock_irqrestore(&ohci->lock, flags); 2757 2758 return ret; 2759 } 2760 2761 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2762 { 2763 struct fw_ohci *ohci = fw_ohci(card); 2764 u32 value; 2765 2766 switch (csr_offset) { 2767 case CSR_STATE_CLEAR: 2768 case CSR_STATE_SET: 2769 if (ohci->is_root && 2770 (reg_read(ohci, OHCI1394_LinkControlSet) & 2771 OHCI1394_LinkControl_cycleMaster)) 2772 value = CSR_STATE_BIT_CMSTR; 2773 else 2774 value = 0; 2775 if (ohci->csr_state_setclear_abdicate) 2776 value |= CSR_STATE_BIT_ABDICATE; 2777 2778 return value; 2779 2780 case CSR_NODE_IDS: 2781 return reg_read(ohci, OHCI1394_NodeID) << 16; 2782 2783 case CSR_CYCLE_TIME: 2784 return get_cycle_time(ohci); 2785 2786 case CSR_BUS_TIME: 2787 { 2788 // We might be called just after the cycle timer has wrapped around but just before 2789 // the cycle64Seconds handler, so we better check here, too, if the bus time needs 2790 // to be updated. 2791 2792 guard(spinlock_irqsave)(&ohci->lock); 2793 return update_bus_time(ohci); 2794 } 2795 case CSR_BUSY_TIMEOUT: 2796 value = reg_read(ohci, OHCI1394_ATRetries); 2797 return (value >> 4) & 0x0ffff00f; 2798 2799 case CSR_PRIORITY_BUDGET: 2800 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2801 (ohci->pri_req_max << 8); 2802 2803 default: 2804 WARN_ON(1); 2805 return 0; 2806 } 2807 } 2808 2809 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2810 { 2811 struct fw_ohci *ohci = fw_ohci(card); 2812 2813 switch (csr_offset) { 2814 case CSR_STATE_CLEAR: 2815 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2816 reg_write(ohci, OHCI1394_LinkControlClear, 2817 OHCI1394_LinkControl_cycleMaster); 2818 flush_writes(ohci); 2819 } 2820 if (value & CSR_STATE_BIT_ABDICATE) 2821 ohci->csr_state_setclear_abdicate = false; 2822 break; 2823 2824 case CSR_STATE_SET: 2825 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2826 reg_write(ohci, OHCI1394_LinkControlSet, 2827 OHCI1394_LinkControl_cycleMaster); 2828 flush_writes(ohci); 2829 } 2830 if (value & CSR_STATE_BIT_ABDICATE) 2831 ohci->csr_state_setclear_abdicate = true; 2832 break; 2833 2834 case CSR_NODE_IDS: 2835 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2836 flush_writes(ohci); 2837 break; 2838 2839 case CSR_CYCLE_TIME: 2840 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2841 reg_write(ohci, OHCI1394_IntEventSet, 2842 OHCI1394_cycleInconsistent); 2843 flush_writes(ohci); 2844 break; 2845 2846 case CSR_BUS_TIME: 2847 { 2848 guard(spinlock_irqsave)(&ohci->lock); 2849 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); 2850 break; 2851 } 2852 case CSR_BUSY_TIMEOUT: 2853 value = (value & 0xf) | ((value & 0xf) << 4) | 2854 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2855 reg_write(ohci, OHCI1394_ATRetries, value); 2856 flush_writes(ohci); 2857 break; 2858 2859 case CSR_PRIORITY_BUDGET: 2860 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2861 flush_writes(ohci); 2862 break; 2863 2864 default: 2865 WARN_ON(1); 2866 break; 2867 } 2868 } 2869 2870 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause) 2871 { 2872 trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2873 ctx->header_length); 2874 trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header, 2875 ctx->header_length); 2876 2877 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2878 ctx->header_length, ctx->header, 2879 ctx->base.callback_data); 2880 ctx->header_length = 0; 2881 } 2882 2883 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2884 { 2885 u32 *ctx_hdr; 2886 2887 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2888 if (ctx->base.drop_overflow_headers) 2889 return; 2890 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 2891 } 2892 2893 ctx_hdr = ctx->header + ctx->header_length; 2894 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2895 2896 /* 2897 * The two iso header quadlets are byteswapped to little 2898 * endian by the controller, but we want to present them 2899 * as big endian for consistency with the bus endianness. 2900 */ 2901 if (ctx->base.header_size > 0) 2902 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2903 if (ctx->base.header_size > 4) 2904 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2905 if (ctx->base.header_size > 8) 2906 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2907 ctx->header_length += ctx->base.header_size; 2908 } 2909 2910 static int handle_ir_packet_per_buffer(struct context *context, 2911 struct descriptor *d, 2912 struct descriptor *last) 2913 { 2914 struct iso_context *ctx = 2915 container_of(context, struct iso_context, context); 2916 struct descriptor *pd; 2917 u32 buffer_dma; 2918 2919 for (pd = d; pd <= last; pd++) 2920 if (pd->transfer_status) 2921 break; 2922 if (pd > last) 2923 /* Descriptor(s) not done yet, stop iteration */ 2924 return 0; 2925 2926 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2927 d++; 2928 buffer_dma = le32_to_cpu(d->data_address); 2929 dma_sync_single_range_for_cpu(context->ohci->card.device, 2930 buffer_dma & PAGE_MASK, 2931 buffer_dma & ~PAGE_MASK, 2932 le16_to_cpu(d->req_count), 2933 DMA_FROM_DEVICE); 2934 } 2935 2936 copy_iso_headers(ctx, (u32 *) (last + 1)); 2937 2938 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2939 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2940 2941 return 1; 2942 } 2943 2944 /* d == last because each descriptor block is only a single descriptor. */ 2945 static int handle_ir_buffer_fill(struct context *context, 2946 struct descriptor *d, 2947 struct descriptor *last) 2948 { 2949 struct iso_context *ctx = 2950 container_of(context, struct iso_context, context); 2951 unsigned int req_count, res_count, completed; 2952 u32 buffer_dma; 2953 2954 req_count = le16_to_cpu(last->req_count); 2955 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2956 completed = req_count - res_count; 2957 buffer_dma = le32_to_cpu(last->data_address); 2958 2959 if (completed > 0) { 2960 ctx->mc_buffer_bus = buffer_dma; 2961 ctx->mc_completed = completed; 2962 } 2963 2964 if (res_count != 0) 2965 /* Descriptor(s) not done yet, stop iteration */ 2966 return 0; 2967 2968 dma_sync_single_range_for_cpu(context->ohci->card.device, 2969 buffer_dma & PAGE_MASK, 2970 buffer_dma & ~PAGE_MASK, 2971 completed, DMA_FROM_DEVICE); 2972 2973 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2974 trace_isoc_inbound_multiple_completions(&ctx->base, completed, 2975 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 2976 2977 ctx->base.callback.mc(&ctx->base, 2978 buffer_dma + completed, 2979 ctx->base.callback_data); 2980 ctx->mc_completed = 0; 2981 } 2982 2983 return 1; 2984 } 2985 2986 static void flush_ir_buffer_fill(struct iso_context *ctx) 2987 { 2988 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2989 ctx->mc_buffer_bus & PAGE_MASK, 2990 ctx->mc_buffer_bus & ~PAGE_MASK, 2991 ctx->mc_completed, DMA_FROM_DEVICE); 2992 2993 trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed, 2994 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 2995 2996 ctx->base.callback.mc(&ctx->base, 2997 ctx->mc_buffer_bus + ctx->mc_completed, 2998 ctx->base.callback_data); 2999 ctx->mc_completed = 0; 3000 } 3001 3002 static inline void sync_it_packet_for_cpu(struct context *context, 3003 struct descriptor *pd) 3004 { 3005 __le16 control; 3006 u32 buffer_dma; 3007 3008 /* only packets beginning with OUTPUT_MORE* have data buffers */ 3009 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3010 return; 3011 3012 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 3013 pd += 2; 3014 3015 /* 3016 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 3017 * data buffer is in the context program's coherent page and must not 3018 * be synced. 3019 */ 3020 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 3021 (context->current_bus & PAGE_MASK)) { 3022 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 3023 return; 3024 pd++; 3025 } 3026 3027 do { 3028 buffer_dma = le32_to_cpu(pd->data_address); 3029 dma_sync_single_range_for_cpu(context->ohci->card.device, 3030 buffer_dma & PAGE_MASK, 3031 buffer_dma & ~PAGE_MASK, 3032 le16_to_cpu(pd->req_count), 3033 DMA_TO_DEVICE); 3034 control = pd->control; 3035 pd++; 3036 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 3037 } 3038 3039 static int handle_it_packet(struct context *context, 3040 struct descriptor *d, 3041 struct descriptor *last) 3042 { 3043 struct iso_context *ctx = 3044 container_of(context, struct iso_context, context); 3045 struct descriptor *pd; 3046 __be32 *ctx_hdr; 3047 3048 for (pd = d; pd <= last; pd++) 3049 if (pd->transfer_status) 3050 break; 3051 if (pd > last) 3052 /* Descriptor(s) not done yet, stop iteration */ 3053 return 0; 3054 3055 sync_it_packet_for_cpu(context, d); 3056 3057 if (ctx->header_length + 4 > PAGE_SIZE) { 3058 if (ctx->base.drop_overflow_headers) 3059 return 1; 3060 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW); 3061 } 3062 3063 ctx_hdr = ctx->header + ctx->header_length; 3064 ctx->last_timestamp = le16_to_cpu(last->res_count); 3065 /* Present this value as big-endian to match the receive code */ 3066 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 3067 le16_to_cpu(pd->res_count)); 3068 ctx->header_length += 4; 3069 3070 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 3071 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_IRQ); 3072 3073 return 1; 3074 } 3075 3076 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 3077 { 3078 u32 hi = channels >> 32, lo = channels; 3079 3080 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 3081 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 3082 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 3083 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 3084 ohci->mc_channels = channels; 3085 } 3086 3087 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 3088 int type, int channel, size_t header_size) 3089 { 3090 struct fw_ohci *ohci = fw_ohci(card); 3091 struct iso_context *ctx; 3092 descriptor_callback_t callback; 3093 u64 *channels; 3094 u32 *mask, regs; 3095 int index, ret = -EBUSY; 3096 3097 spin_lock_irq(&ohci->lock); 3098 3099 switch (type) { 3100 case FW_ISO_CONTEXT_TRANSMIT: 3101 mask = &ohci->it_context_mask; 3102 callback = handle_it_packet; 3103 index = ffs(*mask) - 1; 3104 if (index >= 0) { 3105 *mask &= ~(1 << index); 3106 regs = OHCI1394_IsoXmitContextBase(index); 3107 ctx = &ohci->it_context_list[index]; 3108 } 3109 break; 3110 3111 case FW_ISO_CONTEXT_RECEIVE: 3112 channels = &ohci->ir_context_channels; 3113 mask = &ohci->ir_context_mask; 3114 callback = handle_ir_packet_per_buffer; 3115 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3116 if (index >= 0) { 3117 *channels &= ~(1ULL << channel); 3118 *mask &= ~(1 << index); 3119 regs = OHCI1394_IsoRcvContextBase(index); 3120 ctx = &ohci->ir_context_list[index]; 3121 } 3122 break; 3123 3124 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3125 mask = &ohci->ir_context_mask; 3126 callback = handle_ir_buffer_fill; 3127 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3128 if (index >= 0) { 3129 ohci->mc_allocated = true; 3130 *mask &= ~(1 << index); 3131 regs = OHCI1394_IsoRcvContextBase(index); 3132 ctx = &ohci->ir_context_list[index]; 3133 } 3134 break; 3135 3136 default: 3137 index = -1; 3138 ret = -ENOSYS; 3139 } 3140 3141 spin_unlock_irq(&ohci->lock); 3142 3143 if (index < 0) 3144 return ERR_PTR(ret); 3145 3146 memset(ctx, 0, sizeof(*ctx)); 3147 ctx->header_length = 0; 3148 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3149 if (ctx->header == NULL) { 3150 ret = -ENOMEM; 3151 goto out; 3152 } 3153 ret = context_init(&ctx->context, ohci, regs, callback); 3154 if (ret < 0) 3155 goto out_with_header; 3156 3157 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3158 set_multichannel_mask(ohci, 0); 3159 ctx->mc_completed = 0; 3160 } 3161 3162 return &ctx->base; 3163 3164 out_with_header: 3165 free_page((unsigned long)ctx->header); 3166 out: 3167 spin_lock_irq(&ohci->lock); 3168 3169 switch (type) { 3170 case FW_ISO_CONTEXT_RECEIVE: 3171 *channels |= 1ULL << channel; 3172 break; 3173 3174 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3175 ohci->mc_allocated = false; 3176 break; 3177 } 3178 *mask |= 1 << index; 3179 3180 spin_unlock_irq(&ohci->lock); 3181 3182 return ERR_PTR(ret); 3183 } 3184 3185 static int ohci_start_iso(struct fw_iso_context *base, 3186 s32 cycle, u32 sync, u32 tags) 3187 { 3188 struct iso_context *ctx = container_of(base, struct iso_context, base); 3189 struct fw_ohci *ohci = ctx->context.ohci; 3190 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3191 int index; 3192 3193 /* the controller cannot start without any queued packets */ 3194 if (ctx->context.last->branch_address == 0) 3195 return -ENODATA; 3196 3197 switch (ctx->base.type) { 3198 case FW_ISO_CONTEXT_TRANSMIT: 3199 index = ctx - ohci->it_context_list; 3200 match = 0; 3201 if (cycle >= 0) 3202 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3203 (cycle & 0x7fff) << 16; 3204 3205 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3206 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3207 context_run(&ctx->context, match); 3208 break; 3209 3210 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3211 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3212 fallthrough; 3213 case FW_ISO_CONTEXT_RECEIVE: 3214 index = ctx - ohci->ir_context_list; 3215 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3216 if (cycle >= 0) { 3217 match |= (cycle & 0x07fff) << 12; 3218 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3219 } 3220 3221 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3222 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3223 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3224 context_run(&ctx->context, control); 3225 3226 ctx->sync = sync; 3227 ctx->tags = tags; 3228 3229 break; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int ohci_stop_iso(struct fw_iso_context *base) 3236 { 3237 struct fw_ohci *ohci = fw_ohci(base->card); 3238 struct iso_context *ctx = container_of(base, struct iso_context, base); 3239 int index; 3240 3241 switch (ctx->base.type) { 3242 case FW_ISO_CONTEXT_TRANSMIT: 3243 index = ctx - ohci->it_context_list; 3244 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3245 break; 3246 3247 case FW_ISO_CONTEXT_RECEIVE: 3248 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3249 index = ctx - ohci->ir_context_list; 3250 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3251 break; 3252 } 3253 flush_writes(ohci); 3254 context_stop(&ctx->context); 3255 tasklet_kill(&ctx->context.tasklet); 3256 3257 return 0; 3258 } 3259 3260 static void ohci_free_iso_context(struct fw_iso_context *base) 3261 { 3262 struct fw_ohci *ohci = fw_ohci(base->card); 3263 struct iso_context *ctx = container_of(base, struct iso_context, base); 3264 unsigned long flags; 3265 int index; 3266 3267 ohci_stop_iso(base); 3268 context_release(&ctx->context); 3269 free_page((unsigned long)ctx->header); 3270 3271 spin_lock_irqsave(&ohci->lock, flags); 3272 3273 switch (base->type) { 3274 case FW_ISO_CONTEXT_TRANSMIT: 3275 index = ctx - ohci->it_context_list; 3276 ohci->it_context_mask |= 1 << index; 3277 break; 3278 3279 case FW_ISO_CONTEXT_RECEIVE: 3280 index = ctx - ohci->ir_context_list; 3281 ohci->ir_context_mask |= 1 << index; 3282 ohci->ir_context_channels |= 1ULL << base->channel; 3283 break; 3284 3285 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3286 index = ctx - ohci->ir_context_list; 3287 ohci->ir_context_mask |= 1 << index; 3288 ohci->ir_context_channels |= ohci->mc_channels; 3289 ohci->mc_channels = 0; 3290 ohci->mc_allocated = false; 3291 break; 3292 } 3293 3294 spin_unlock_irqrestore(&ohci->lock, flags); 3295 } 3296 3297 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3298 { 3299 struct fw_ohci *ohci = fw_ohci(base->card); 3300 unsigned long flags; 3301 int ret; 3302 3303 switch (base->type) { 3304 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3305 3306 spin_lock_irqsave(&ohci->lock, flags); 3307 3308 /* Don't allow multichannel to grab other contexts' channels. */ 3309 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3310 *channels = ohci->ir_context_channels; 3311 ret = -EBUSY; 3312 } else { 3313 set_multichannel_mask(ohci, *channels); 3314 ret = 0; 3315 } 3316 3317 spin_unlock_irqrestore(&ohci->lock, flags); 3318 3319 break; 3320 default: 3321 ret = -EINVAL; 3322 } 3323 3324 return ret; 3325 } 3326 3327 #ifdef CONFIG_PM 3328 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3329 { 3330 int i; 3331 struct iso_context *ctx; 3332 3333 for (i = 0 ; i < ohci->n_ir ; i++) { 3334 ctx = &ohci->ir_context_list[i]; 3335 if (ctx->context.running) 3336 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3337 } 3338 3339 for (i = 0 ; i < ohci->n_it ; i++) { 3340 ctx = &ohci->it_context_list[i]; 3341 if (ctx->context.running) 3342 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3343 } 3344 } 3345 #endif 3346 3347 static int queue_iso_transmit(struct iso_context *ctx, 3348 struct fw_iso_packet *packet, 3349 struct fw_iso_buffer *buffer, 3350 unsigned long payload) 3351 { 3352 struct descriptor *d, *last, *pd; 3353 struct fw_iso_packet *p; 3354 __le32 *header; 3355 dma_addr_t d_bus, page_bus; 3356 u32 z, header_z, payload_z, irq; 3357 u32 payload_index, payload_end_index, next_page_index; 3358 int page, end_page, i, length, offset; 3359 3360 p = packet; 3361 payload_index = payload; 3362 3363 if (p->skip) 3364 z = 1; 3365 else 3366 z = 2; 3367 if (p->header_length > 0) 3368 z++; 3369 3370 /* Determine the first page the payload isn't contained in. */ 3371 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3372 if (p->payload_length > 0) 3373 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3374 else 3375 payload_z = 0; 3376 3377 z += payload_z; 3378 3379 /* Get header size in number of descriptors. */ 3380 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3381 3382 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3383 if (d == NULL) 3384 return -ENOMEM; 3385 3386 if (!p->skip) { 3387 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3388 d[0].req_count = cpu_to_le16(8); 3389 /* 3390 * Link the skip address to this descriptor itself. This causes 3391 * a context to skip a cycle whenever lost cycles or FIFO 3392 * overruns occur, without dropping the data. The application 3393 * should then decide whether this is an error condition or not. 3394 * FIXME: Make the context's cycle-lost behaviour configurable? 3395 */ 3396 d[0].branch_address = cpu_to_le32(d_bus | z); 3397 3398 header = (__le32 *) &d[1]; 3399 3400 ohci1394_it_data_set_speed(header, ctx->base.speed); 3401 ohci1394_it_data_set_tag(header, p->tag); 3402 ohci1394_it_data_set_channel(header, ctx->base.channel); 3403 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA); 3404 ohci1394_it_data_set_sync(header, p->sy); 3405 3406 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length); 3407 } 3408 3409 if (p->header_length > 0) { 3410 d[2].req_count = cpu_to_le16(p->header_length); 3411 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3412 memcpy(&d[z], p->header, p->header_length); 3413 } 3414 3415 pd = d + z - payload_z; 3416 payload_end_index = payload_index + p->payload_length; 3417 for (i = 0; i < payload_z; i++) { 3418 page = payload_index >> PAGE_SHIFT; 3419 offset = payload_index & ~PAGE_MASK; 3420 next_page_index = (page + 1) << PAGE_SHIFT; 3421 length = 3422 min(next_page_index, payload_end_index) - payload_index; 3423 pd[i].req_count = cpu_to_le16(length); 3424 3425 page_bus = page_private(buffer->pages[page]); 3426 pd[i].data_address = cpu_to_le32(page_bus + offset); 3427 3428 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3429 page_bus, offset, length, 3430 DMA_TO_DEVICE); 3431 3432 payload_index += length; 3433 } 3434 3435 if (p->interrupt) 3436 irq = DESCRIPTOR_IRQ_ALWAYS; 3437 else 3438 irq = DESCRIPTOR_NO_IRQ; 3439 3440 last = z == 2 ? d : d + z - 1; 3441 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3442 DESCRIPTOR_STATUS | 3443 DESCRIPTOR_BRANCH_ALWAYS | 3444 irq); 3445 3446 context_append(&ctx->context, d, z, header_z); 3447 3448 return 0; 3449 } 3450 3451 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3452 struct fw_iso_packet *packet, 3453 struct fw_iso_buffer *buffer, 3454 unsigned long payload) 3455 { 3456 struct device *device = ctx->context.ohci->card.device; 3457 struct descriptor *d, *pd; 3458 dma_addr_t d_bus, page_bus; 3459 u32 z, header_z, rest; 3460 int i, j, length; 3461 int page, offset, packet_count, header_size, payload_per_buffer; 3462 3463 /* 3464 * The OHCI controller puts the isochronous header and trailer in the 3465 * buffer, so we need at least 8 bytes. 3466 */ 3467 packet_count = packet->header_length / ctx->base.header_size; 3468 header_size = max(ctx->base.header_size, (size_t)8); 3469 3470 /* Get header size in number of descriptors. */ 3471 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3472 page = payload >> PAGE_SHIFT; 3473 offset = payload & ~PAGE_MASK; 3474 payload_per_buffer = packet->payload_length / packet_count; 3475 3476 for (i = 0; i < packet_count; i++) { 3477 /* d points to the header descriptor */ 3478 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3479 d = context_get_descriptors(&ctx->context, 3480 z + header_z, &d_bus); 3481 if (d == NULL) 3482 return -ENOMEM; 3483 3484 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3485 DESCRIPTOR_INPUT_MORE); 3486 if (packet->skip && i == 0) 3487 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3488 d->req_count = cpu_to_le16(header_size); 3489 d->res_count = d->req_count; 3490 d->transfer_status = 0; 3491 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3492 3493 rest = payload_per_buffer; 3494 pd = d; 3495 for (j = 1; j < z; j++) { 3496 pd++; 3497 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3498 DESCRIPTOR_INPUT_MORE); 3499 3500 if (offset + rest < PAGE_SIZE) 3501 length = rest; 3502 else 3503 length = PAGE_SIZE - offset; 3504 pd->req_count = cpu_to_le16(length); 3505 pd->res_count = pd->req_count; 3506 pd->transfer_status = 0; 3507 3508 page_bus = page_private(buffer->pages[page]); 3509 pd->data_address = cpu_to_le32(page_bus + offset); 3510 3511 dma_sync_single_range_for_device(device, page_bus, 3512 offset, length, 3513 DMA_FROM_DEVICE); 3514 3515 offset = (offset + length) & ~PAGE_MASK; 3516 rest -= length; 3517 if (offset == 0) 3518 page++; 3519 } 3520 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3521 DESCRIPTOR_INPUT_LAST | 3522 DESCRIPTOR_BRANCH_ALWAYS); 3523 if (packet->interrupt && i == packet_count - 1) 3524 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3525 3526 context_append(&ctx->context, d, z, header_z); 3527 } 3528 3529 return 0; 3530 } 3531 3532 static int queue_iso_buffer_fill(struct iso_context *ctx, 3533 struct fw_iso_packet *packet, 3534 struct fw_iso_buffer *buffer, 3535 unsigned long payload) 3536 { 3537 struct descriptor *d; 3538 dma_addr_t d_bus, page_bus; 3539 int page, offset, rest, z, i, length; 3540 3541 page = payload >> PAGE_SHIFT; 3542 offset = payload & ~PAGE_MASK; 3543 rest = packet->payload_length; 3544 3545 /* We need one descriptor for each page in the buffer. */ 3546 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3547 3548 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3549 return -EFAULT; 3550 3551 for (i = 0; i < z; i++) { 3552 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3553 if (d == NULL) 3554 return -ENOMEM; 3555 3556 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3557 DESCRIPTOR_BRANCH_ALWAYS); 3558 if (packet->skip && i == 0) 3559 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3560 if (packet->interrupt && i == z - 1) 3561 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3562 3563 if (offset + rest < PAGE_SIZE) 3564 length = rest; 3565 else 3566 length = PAGE_SIZE - offset; 3567 d->req_count = cpu_to_le16(length); 3568 d->res_count = d->req_count; 3569 d->transfer_status = 0; 3570 3571 page_bus = page_private(buffer->pages[page]); 3572 d->data_address = cpu_to_le32(page_bus + offset); 3573 3574 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3575 page_bus, offset, length, 3576 DMA_FROM_DEVICE); 3577 3578 rest -= length; 3579 offset = 0; 3580 page++; 3581 3582 context_append(&ctx->context, d, 1, 0); 3583 } 3584 3585 return 0; 3586 } 3587 3588 static int ohci_queue_iso(struct fw_iso_context *base, 3589 struct fw_iso_packet *packet, 3590 struct fw_iso_buffer *buffer, 3591 unsigned long payload) 3592 { 3593 struct iso_context *ctx = container_of(base, struct iso_context, base); 3594 unsigned long flags; 3595 int ret = -ENOSYS; 3596 3597 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3598 switch (base->type) { 3599 case FW_ISO_CONTEXT_TRANSMIT: 3600 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3601 break; 3602 case FW_ISO_CONTEXT_RECEIVE: 3603 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3604 break; 3605 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3606 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3607 break; 3608 } 3609 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3610 3611 return ret; 3612 } 3613 3614 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3615 { 3616 struct context *ctx = 3617 &container_of(base, struct iso_context, base)->context; 3618 3619 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3620 } 3621 3622 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3623 { 3624 struct iso_context *ctx = container_of(base, struct iso_context, base); 3625 int ret = 0; 3626 3627 tasklet_disable_in_atomic(&ctx->context.tasklet); 3628 3629 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3630 context_tasklet((unsigned long)&ctx->context); 3631 3632 switch (base->type) { 3633 case FW_ISO_CONTEXT_TRANSMIT: 3634 case FW_ISO_CONTEXT_RECEIVE: 3635 if (ctx->header_length != 0) 3636 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH); 3637 break; 3638 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3639 if (ctx->mc_completed != 0) 3640 flush_ir_buffer_fill(ctx); 3641 break; 3642 default: 3643 ret = -ENOSYS; 3644 } 3645 3646 clear_bit_unlock(0, &ctx->flushing_completions); 3647 smp_mb__after_atomic(); 3648 } 3649 3650 tasklet_enable(&ctx->context.tasklet); 3651 3652 return ret; 3653 } 3654 3655 static const struct fw_card_driver ohci_driver = { 3656 .enable = ohci_enable, 3657 .read_phy_reg = ohci_read_phy_reg, 3658 .update_phy_reg = ohci_update_phy_reg, 3659 .set_config_rom = ohci_set_config_rom, 3660 .send_request = ohci_send_request, 3661 .send_response = ohci_send_response, 3662 .cancel_packet = ohci_cancel_packet, 3663 .enable_phys_dma = ohci_enable_phys_dma, 3664 .read_csr = ohci_read_csr, 3665 .write_csr = ohci_write_csr, 3666 3667 .allocate_iso_context = ohci_allocate_iso_context, 3668 .free_iso_context = ohci_free_iso_context, 3669 .set_iso_channels = ohci_set_iso_channels, 3670 .queue_iso = ohci_queue_iso, 3671 .flush_queue_iso = ohci_flush_queue_iso, 3672 .flush_iso_completions = ohci_flush_iso_completions, 3673 .start_iso = ohci_start_iso, 3674 .stop_iso = ohci_stop_iso, 3675 }; 3676 3677 #ifdef CONFIG_PPC_PMAC 3678 static void pmac_ohci_on(struct pci_dev *dev) 3679 { 3680 if (machine_is(powermac)) { 3681 struct device_node *ofn = pci_device_to_OF_node(dev); 3682 3683 if (ofn) { 3684 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3685 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3686 } 3687 } 3688 } 3689 3690 static void pmac_ohci_off(struct pci_dev *dev) 3691 { 3692 if (machine_is(powermac)) { 3693 struct device_node *ofn = pci_device_to_OF_node(dev); 3694 3695 if (ofn) { 3696 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3697 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3698 } 3699 } 3700 } 3701 #else 3702 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3703 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3704 #endif /* CONFIG_PPC_PMAC */ 3705 3706 static void release_ohci(struct device *dev, void *data) 3707 { 3708 struct pci_dev *pdev = to_pci_dev(dev); 3709 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3710 3711 pmac_ohci_off(pdev); 3712 3713 ar_context_release(&ohci->ar_response_ctx); 3714 ar_context_release(&ohci->ar_request_ctx); 3715 3716 dev_notice(dev, "removed fw-ohci device\n"); 3717 } 3718 3719 static int pci_probe(struct pci_dev *dev, 3720 const struct pci_device_id *ent) 3721 { 3722 struct fw_ohci *ohci; 3723 u32 bus_options, max_receive, link_speed, version; 3724 u64 guid; 3725 int i, flags, irq, err; 3726 size_t size; 3727 3728 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3729 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3730 return -ENOSYS; 3731 } 3732 3733 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3734 if (ohci == NULL) 3735 return -ENOMEM; 3736 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3737 pci_set_drvdata(dev, ohci); 3738 pmac_ohci_on(dev); 3739 devres_add(&dev->dev, ohci); 3740 3741 err = pcim_enable_device(dev); 3742 if (err) { 3743 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3744 return err; 3745 } 3746 3747 pci_set_master(dev); 3748 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3749 3750 spin_lock_init(&ohci->lock); 3751 mutex_init(&ohci->phy_reg_mutex); 3752 3753 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3754 3755 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3756 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3757 ohci_err(ohci, "invalid MMIO resource\n"); 3758 return -ENXIO; 3759 } 3760 3761 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3762 if (err) { 3763 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3764 return -ENXIO; 3765 } 3766 ohci->registers = pcim_iomap_table(dev)[0]; 3767 3768 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3769 if ((ohci_quirks[i].vendor == dev->vendor) && 3770 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3771 ohci_quirks[i].device == dev->device) && 3772 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3773 ohci_quirks[i].revision >= dev->revision)) { 3774 ohci->quirks = ohci_quirks[i].flags; 3775 break; 3776 } 3777 if (param_quirks) 3778 ohci->quirks = param_quirks; 3779 3780 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3781 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3782 3783 /* 3784 * Because dma_alloc_coherent() allocates at least one page, 3785 * we save space by using a common buffer for the AR request/ 3786 * response descriptors and the self IDs buffer. 3787 */ 3788 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3789 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3790 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3791 GFP_KERNEL); 3792 if (!ohci->misc_buffer) 3793 return -ENOMEM; 3794 3795 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3796 OHCI1394_AsReqRcvContextControlSet); 3797 if (err < 0) 3798 return err; 3799 3800 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3801 OHCI1394_AsRspRcvContextControlSet); 3802 if (err < 0) 3803 return err; 3804 3805 err = context_init(&ohci->at_request_ctx, ohci, 3806 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3807 if (err < 0) 3808 return err; 3809 3810 err = context_init(&ohci->at_response_ctx, ohci, 3811 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3812 if (err < 0) 3813 return err; 3814 3815 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3816 ohci->ir_context_channels = ~0ULL; 3817 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3818 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3819 ohci->ir_context_mask = ohci->ir_context_support; 3820 ohci->n_ir = hweight32(ohci->ir_context_mask); 3821 size = sizeof(struct iso_context) * ohci->n_ir; 3822 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3823 if (!ohci->ir_context_list) 3824 return -ENOMEM; 3825 3826 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3827 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3828 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3829 if (!ohci->it_context_support) { 3830 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3831 ohci->it_context_support = 0xf; 3832 } 3833 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3834 ohci->it_context_mask = ohci->it_context_support; 3835 ohci->n_it = hweight32(ohci->it_context_mask); 3836 size = sizeof(struct iso_context) * ohci->n_it; 3837 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3838 if (!ohci->it_context_list) 3839 return -ENOMEM; 3840 3841 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3842 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3843 3844 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3845 max_receive = (bus_options >> 12) & 0xf; 3846 link_speed = bus_options & 0x7; 3847 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3848 reg_read(ohci, OHCI1394_GUIDLo); 3849 3850 flags = PCI_IRQ_INTX; 3851 if (!(ohci->quirks & QUIRK_NO_MSI)) 3852 flags |= PCI_IRQ_MSI; 3853 err = pci_alloc_irq_vectors(dev, 1, 1, flags); 3854 if (err < 0) 3855 return err; 3856 irq = pci_irq_vector(dev, 0); 3857 if (irq < 0) { 3858 err = irq; 3859 goto fail_msi; 3860 } 3861 3862 err = request_threaded_irq(irq, irq_handler, NULL, 3863 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, 3864 ohci); 3865 if (err < 0) { 3866 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); 3867 goto fail_msi; 3868 } 3869 3870 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3871 if (err) 3872 goto fail_irq; 3873 3874 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3875 ohci_notice(ohci, 3876 "added OHCI v%x.%x device as card %d, " 3877 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3878 version >> 16, version & 0xff, ohci->card.index, 3879 ohci->n_ir, ohci->n_it, ohci->quirks, 3880 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3881 ", physUB" : ""); 3882 3883 return 0; 3884 3885 fail_irq: 3886 free_irq(irq, ohci); 3887 fail_msi: 3888 pci_free_irq_vectors(dev); 3889 3890 return err; 3891 } 3892 3893 static void pci_remove(struct pci_dev *dev) 3894 { 3895 struct fw_ohci *ohci = pci_get_drvdata(dev); 3896 int irq; 3897 3898 /* 3899 * If the removal is happening from the suspend state, LPS won't be 3900 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3901 */ 3902 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3903 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3904 flush_writes(ohci); 3905 } 3906 cancel_work_sync(&ohci->bus_reset_work); 3907 fw_core_remove_card(&ohci->card); 3908 3909 /* 3910 * FIXME: Fail all pending packets here, now that the upper 3911 * layers can't queue any more. 3912 */ 3913 3914 software_reset(ohci); 3915 3916 irq = pci_irq_vector(dev, 0); 3917 if (irq >= 0) 3918 free_irq(irq, ohci); 3919 pci_free_irq_vectors(dev); 3920 3921 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3922 } 3923 3924 #ifdef CONFIG_PM 3925 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3926 { 3927 struct fw_ohci *ohci = pci_get_drvdata(dev); 3928 int err; 3929 3930 software_reset(ohci); 3931 err = pci_save_state(dev); 3932 if (err) { 3933 ohci_err(ohci, "pci_save_state failed\n"); 3934 return err; 3935 } 3936 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3937 if (err) 3938 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3939 pmac_ohci_off(dev); 3940 3941 return 0; 3942 } 3943 3944 static int pci_resume(struct pci_dev *dev) 3945 { 3946 struct fw_ohci *ohci = pci_get_drvdata(dev); 3947 int err; 3948 3949 pmac_ohci_on(dev); 3950 pci_set_power_state(dev, PCI_D0); 3951 pci_restore_state(dev); 3952 err = pci_enable_device(dev); 3953 if (err) { 3954 ohci_err(ohci, "pci_enable_device failed\n"); 3955 return err; 3956 } 3957 3958 /* Some systems don't setup GUID register on resume from ram */ 3959 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3960 !reg_read(ohci, OHCI1394_GUIDHi)) { 3961 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3962 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3963 } 3964 3965 err = ohci_enable(&ohci->card, NULL, 0); 3966 if (err) 3967 return err; 3968 3969 ohci_resume_iso_dma(ohci); 3970 3971 return 0; 3972 } 3973 #endif 3974 3975 static const struct pci_device_id pci_table[] = { 3976 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3977 { } 3978 }; 3979 3980 MODULE_DEVICE_TABLE(pci, pci_table); 3981 3982 static struct pci_driver fw_ohci_pci_driver = { 3983 .name = ohci_driver_name, 3984 .id_table = pci_table, 3985 .probe = pci_probe, 3986 .remove = pci_remove, 3987 #ifdef CONFIG_PM 3988 .resume = pci_resume, 3989 .suspend = pci_suspend, 3990 #endif 3991 }; 3992 3993 static int __init fw_ohci_init(void) 3994 { 3995 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3996 if (!selfid_workqueue) 3997 return -ENOMEM; 3998 3999 return pci_register_driver(&fw_ohci_pci_driver); 4000 } 4001 4002 static void __exit fw_ohci_cleanup(void) 4003 { 4004 pci_unregister_driver(&fw_ohci_pci_driver); 4005 destroy_workqueue(selfid_workqueue); 4006 } 4007 4008 module_init(fw_ohci_init); 4009 module_exit(fw_ohci_cleanup); 4010 4011 MODULE_AUTHOR("Kristian Hoegsberg <[email protected]>"); 4012 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 4013 MODULE_LICENSE("GPL"); 4014 4015 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 4016 MODULE_ALIAS("ohci1394"); 4017