1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is [email protected]. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_AMD64 79 tristate "AMD64 (Opteron, Athlon64)" 80 depends on AMD_NB && EDAC_DECODE_MCE 81 depends on AMD_NODE 82 imply AMD_ATL 83 help 84 Support for error detection and correction of DRAM ECC errors on 85 the AMD64 families (>= K8) of memory controllers. 86 87 When EDAC_DEBUG is enabled, hardware error injection facilities 88 through sysfs are available: 89 90 AMD CPUs up to and excluding family 0x17 provide for Memory 91 Error Injection into the ECC detection circuits. The amd64_edac 92 module allows the operator/user to inject Uncorrectable and 93 Correctable errors into DRAM. 94 95 When enabled, in each of the respective memory controller directories 96 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 97 98 - inject_section (0..3, 16-byte section of 64-byte cacheline), 99 - inject_word (0..8, 16-bit word of 16-byte section), 100 - inject_ecc_vector (hex ecc vector: select bits of inject word) 101 102 In addition, there are two control files, inject_read and inject_write, 103 which trigger the DRAM ECC Read and Write respectively. 104 105config EDAC_AL_MC 106 tristate "Amazon's Annapurna Lab Memory Controller" 107 depends on (ARCH_ALPINE || COMPILE_TEST) 108 help 109 Support for error detection and correction for Amazon's Annapurna 110 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 111 112config EDAC_AMD76X 113 tristate "AMD 76x (760, 762, 768)" 114 depends on PCI && X86_32 115 help 116 Support for error detection and correction on the AMD 76x 117 series of chipsets used with the Athlon processor. 118 119config EDAC_E7XXX 120 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 121 depends on PCI && X86_32 122 help 123 Support for error detection and correction on the Intel 124 E7205, E7500, E7501 and E7505 server chipsets. 125 126config EDAC_E752X 127 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 128 depends on PCI && X86 129 help 130 Support for error detection and correction on the Intel 131 E7520, E7525, E7320 server chipsets. 132 133config EDAC_I82443BXGX 134 tristate "Intel 82443BX/GX (440BX/GX)" 135 depends on PCI && X86_32 136 depends on BROKEN 137 help 138 Support for error detection and correction on the Intel 139 82443BX/GX memory controllers (440BX/GX chipsets). 140 141config EDAC_I82875P 142 tristate "Intel 82875p (D82875P, E7210)" 143 depends on PCI && X86_32 144 help 145 Support for error detection and correction on the Intel 146 DP82785P and E7210 server chipsets. 147 148config EDAC_I82975X 149 tristate "Intel 82975x (D82975x)" 150 depends on PCI && X86 151 help 152 Support for error detection and correction on the Intel 153 DP82975x server chipsets. 154 155config EDAC_I3000 156 tristate "Intel 3000/3010" 157 depends on PCI && X86 158 help 159 Support for error detection and correction on the Intel 160 3000 and 3010 server chipsets. 161 162config EDAC_I3200 163 tristate "Intel 3200" 164 depends on PCI && X86 165 help 166 Support for error detection and correction on the Intel 167 3200 and 3210 server chipsets. 168 169config EDAC_IE31200 170 tristate "Intel e312xx" 171 depends on PCI && X86 172 help 173 Support for error detection and correction on the Intel 174 E3-1200 based DRAM controllers. 175 176config EDAC_X38 177 tristate "Intel X38" 178 depends on PCI && X86 179 help 180 Support for error detection and correction on the Intel 181 X38 server chipsets. 182 183config EDAC_I5400 184 tristate "Intel 5400 (Seaburg) chipsets" 185 depends on PCI && X86 186 help 187 Support for error detection and correction the Intel 188 i5400 MCH chipset (Seaburg). 189 190config EDAC_I7CORE 191 tristate "Intel i7 Core (Nehalem) processors" 192 depends on PCI && X86 && X86_MCE_INTEL 193 help 194 Support for error detection and correction the Intel 195 i7 Core (Nehalem) Integrated Memory Controller that exists on 196 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 197 and Xeon 55xx processors. 198 199config EDAC_I82860 200 tristate "Intel 82860" 201 depends on PCI && X86_32 202 help 203 Support for error detection and correction on the Intel 204 82860 chipset. 205 206config EDAC_R82600 207 tristate "Radisys 82600 embedded chipset" 208 depends on PCI && X86_32 209 help 210 Support for error detection and correction on the Radisys 211 82600 embedded chipset. 212 213config EDAC_I5000 214 tristate "Intel Greencreek/Blackford chipset" 215 depends on X86 && PCI 216 depends on BROKEN 217 help 218 Support for error detection and correction the Intel 219 Greekcreek/Blackford chipsets. 220 221config EDAC_I5100 222 tristate "Intel San Clemente MCH" 223 depends on X86 && PCI 224 help 225 Support for error detection and correction the Intel 226 San Clemente MCH. 227 228config EDAC_I7300 229 tristate "Intel Clarksboro MCH" 230 depends on X86 && PCI 231 help 232 Support for error detection and correction the Intel 233 Clarksboro MCH (Intel 7300 chipset). 234 235config EDAC_SBRIDGE 236 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 237 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 238 help 239 Support for error detection and correction the Intel 240 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 241 242config EDAC_SKX 243 tristate "Intel Skylake server Integrated MC" 244 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 245 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 246 select DMI 247 select ACPI_ADXL 248 help 249 Support for error detection and correction the Intel 250 Skylake server Integrated Memory Controllers. If your 251 system has non-volatile DIMMs you should also manually 252 select CONFIG_ACPI_NFIT. 253 254config EDAC_I10NM 255 tristate "Intel 10nm server Integrated MC" 256 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 257 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 258 select DMI 259 select ACPI_ADXL 260 help 261 Support for error detection and correction the Intel 262 10nm server Integrated Memory Controllers. If your 263 system has non-volatile DIMMs you should also manually 264 select CONFIG_ACPI_NFIT. 265 266config EDAC_PND2 267 tristate "Intel Pondicherry2" 268 depends on PCI && X86_64 && X86_MCE_INTEL 269 select P2SB if X86 270 help 271 Support for error detection and correction on the Intel 272 Pondicherry2 Integrated Memory Controller. This SoC IP is 273 first used on the Apollo Lake platform and Denverton 274 micro-server but may appear on others in the future. 275 276config EDAC_IGEN6 277 tristate "Intel client SoC Integrated MC" 278 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 279 depends on X86_64 && X86_MCE_INTEL 280 help 281 Support for error detection and correction on the Intel 282 client SoC Integrated Memory Controller using In-Band ECC IP. 283 This In-Band ECC is first used on the Elkhart Lake SoC but 284 may appear on others in the future. 285 286config EDAC_MPC85XX 287 bool "Freescale MPC83xx / MPC85xx" 288 depends on FSL_SOC && EDAC=y 289 help 290 Support for error detection and correction on the Freescale 291 MPC8349, MPC8560, MPC8540, MPC8548, T4240 292 293config EDAC_LAYERSCAPE 294 tristate "Freescale Layerscape DDR" 295 depends on ARCH_LAYERSCAPE || SOC_LS1021A 296 help 297 Support for error detection and correction on Freescale memory 298 controllers on Layerscape SoCs. 299 300config EDAC_PASEMI 301 tristate "PA Semi PWRficient" 302 depends on PPC_PASEMI && PCI 303 help 304 Support for error detection and correction on PA Semi 305 PWRficient. 306 307config EDAC_CELL 308 tristate "Cell Broadband Engine memory controller" 309 depends on PPC_CELL_COMMON 310 help 311 Support for error detection and correction on the 312 Cell Broadband Engine internal memory controller 313 on platform without a hypervisor 314 315config EDAC_CPC925 316 tristate "IBM CPC925 Memory Controller (PPC970FX)" 317 depends on PPC64 318 help 319 Support for error detection and correction on the 320 IBM CPC925 Bridge and Memory Controller, which is 321 a companion chip to the PowerPC 970 family of 322 processors. 323 324config EDAC_HIGHBANK_MC 325 tristate "Highbank Memory Controller" 326 depends on ARCH_HIGHBANK 327 help 328 Support for error detection and correction on the 329 Calxeda Highbank memory controller. 330 331config EDAC_HIGHBANK_L2 332 tristate "Highbank L2 Cache" 333 depends on ARCH_HIGHBANK 334 help 335 Support for error detection and correction on the 336 Calxeda Highbank memory controller. 337 338config EDAC_OCTEON_PC 339 tristate "Cavium Octeon Primary Caches" 340 depends on CPU_CAVIUM_OCTEON 341 help 342 Support for error detection and correction on the primary caches of 343 the cnMIPS cores of Cavium Octeon family SOCs. 344 345config EDAC_OCTEON_L2C 346 tristate "Cavium Octeon Secondary Caches (L2C)" 347 depends on CAVIUM_OCTEON_SOC 348 help 349 Support for error detection and correction on the 350 Cavium Octeon family of SOCs. 351 352config EDAC_OCTEON_LMC 353 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 354 depends on CAVIUM_OCTEON_SOC 355 help 356 Support for error detection and correction on the 357 Cavium Octeon family of SOCs. 358 359config EDAC_OCTEON_PCI 360 tristate "Cavium Octeon PCI Controller" 361 depends on PCI && CAVIUM_OCTEON_SOC 362 help 363 Support for error detection and correction on the 364 Cavium Octeon family of SOCs. 365 366config EDAC_THUNDERX 367 tristate "Cavium ThunderX EDAC" 368 depends on ARM64 369 depends on PCI 370 help 371 Support for error detection and correction on the 372 Cavium ThunderX memory controllers (LMC), Cache 373 Coherent Processor Interconnect (CCPI) and L2 cache 374 blocks (TAD, CBC, MCI). 375 376config EDAC_ALTERA 377 bool "Altera SOCFPGA ECC" 378 depends on EDAC=y && ARCH_INTEL_SOCFPGA 379 help 380 Support for error detection and correction on the 381 Altera SOCs. This is the global enable for the 382 various Altera peripherals. 383 384config EDAC_ALTERA_SDRAM 385 bool "Altera SDRAM ECC" 386 depends on EDAC_ALTERA=y 387 help 388 Support for error detection and correction on the 389 Altera SDRAM Memory for Altera SoCs. Note that the 390 preloader must initialize the SDRAM before loading 391 the kernel. 392 393config EDAC_ALTERA_L2C 394 bool "Altera L2 Cache ECC" 395 depends on EDAC_ALTERA=y && CACHE_L2X0 396 help 397 Support for error detection and correction on the 398 Altera L2 cache Memory for Altera SoCs. This option 399 requires L2 cache. 400 401config EDAC_ALTERA_OCRAM 402 bool "Altera On-Chip RAM ECC" 403 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 404 help 405 Support for error detection and correction on the 406 Altera On-Chip RAM Memory for Altera SoCs. 407 408config EDAC_ALTERA_ETHERNET 409 bool "Altera Ethernet FIFO ECC" 410 depends on EDAC_ALTERA=y 411 help 412 Support for error detection and correction on the 413 Altera Ethernet FIFO Memory for Altera SoCs. 414 415config EDAC_ALTERA_NAND 416 bool "Altera NAND FIFO ECC" 417 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 418 help 419 Support for error detection and correction on the 420 Altera NAND FIFO Memory for Altera SoCs. 421 422config EDAC_ALTERA_DMA 423 bool "Altera DMA FIFO ECC" 424 depends on EDAC_ALTERA=y && PL330_DMA=y 425 help 426 Support for error detection and correction on the 427 Altera DMA FIFO Memory for Altera SoCs. 428 429config EDAC_ALTERA_USB 430 bool "Altera USB FIFO ECC" 431 depends on EDAC_ALTERA=y && USB_DWC2 432 help 433 Support for error detection and correction on the 434 Altera USB FIFO Memory for Altera SoCs. 435 436config EDAC_ALTERA_QSPI 437 bool "Altera QSPI FIFO ECC" 438 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 439 help 440 Support for error detection and correction on the 441 Altera QSPI FIFO Memory for Altera SoCs. 442 443config EDAC_ALTERA_SDMMC 444 bool "Altera SDMMC FIFO ECC" 445 depends on EDAC_ALTERA=y && MMC_DW 446 help 447 Support for error detection and correction on the 448 Altera SDMMC FIFO Memory for Altera SoCs. 449 450config EDAC_SIFIVE 451 bool "Sifive platform EDAC driver" 452 depends on EDAC=y && SIFIVE_CCACHE 453 help 454 Support for error detection and correction on the SiFive SoCs. 455 456config EDAC_ARMADA_XP 457 bool "Marvell Armada XP DDR and L2 Cache ECC" 458 depends on MACH_MVEBU_V7 459 help 460 Support for error correction and detection on the Marvell Aramada XP 461 DDR RAM and L2 cache controllers. 462 463config EDAC_SYNOPSYS 464 tristate "Synopsys DDR Memory Controller" 465 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 466 help 467 Support for error detection and correction on the Synopsys DDR 468 memory controller. 469 470config EDAC_XGENE 471 tristate "APM X-Gene SoC" 472 depends on (ARM64 || COMPILE_TEST) 473 help 474 Support for error detection and correction on the 475 APM X-Gene family of SOCs. 476 477config EDAC_TI 478 tristate "Texas Instruments DDR3 ECC Controller" 479 depends on ARCH_KEYSTONE || SOC_DRA7XX 480 help 481 Support for error detection and correction on the TI SoCs. 482 483config EDAC_QCOM 484 tristate "QCOM EDAC Controller" 485 depends on ARCH_QCOM && QCOM_LLCC 486 help 487 Support for error detection and correction on the 488 Qualcomm Technologies, Inc. SoCs. 489 490 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 491 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 492 of Tag RAM and Data RAM. 493 494 For debugging issues having to do with stability and overall system 495 health, you should probably say 'Y' here. 496 497config EDAC_ASPEED 498 tristate "Aspeed AST BMC SoC" 499 depends on ARCH_ASPEED 500 help 501 Support for error detection and correction on the Aspeed AST BMC SoC. 502 503 First, ECC must be configured in the bootloader. Then, this driver 504 will expose error counters via the EDAC kernel framework. 505 506config EDAC_BLUEFIELD 507 tristate "Mellanox BlueField Memory ECC" 508 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 509 help 510 Support for error detection and correction on the 511 Mellanox BlueField SoCs. 512 513config EDAC_DMC520 514 tristate "ARM DMC-520 ECC" 515 depends on ARM64 516 help 517 Support for error detection and correction on the 518 SoCs with ARM DMC-520 DRAM controller. 519 520config EDAC_ZYNQMP 521 tristate "Xilinx ZynqMP OCM Controller" 522 depends on ARCH_ZYNQMP || COMPILE_TEST 523 help 524 This driver supports error detection and correction for the 525 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 526 built as a module. In that case it will be called zynqmp_edac. 527 528config EDAC_NPCM 529 tristate "Nuvoton NPCM DDR Memory Controller" 530 depends on (ARCH_NPCM || COMPILE_TEST) 531 help 532 Support for error detection and correction on the Nuvoton NPCM DDR 533 memory controller. 534 535 The memory controller supports single bit error correction, double bit 536 error detection (in-line ECC in which a section 1/8th of the memory 537 device used to store data is used for ECC storage). 538 539config EDAC_VERSAL 540 tristate "Xilinx Versal DDR Memory Controller" 541 depends on ARCH_ZYNQMP || COMPILE_TEST 542 help 543 Support for error detection and correction on the Xilinx Versal DDR 544 memory controller. 545 546 Report both single bit errors (CE) and double bit errors (UE). 547 Support injecting both correctable and uncorrectable errors 548 for debugging purposes. 549 550 551endif # EDAC 552