1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/fs.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/device.h> 15 #include <linux/idr.h> 16 #include <linux/iommu.h> 17 #include <uapi/linux/idxd.h> 18 #include <linux/dmaengine.h> 19 #include "../dmaengine.h" 20 #include "registers.h" 21 #include "idxd.h" 22 #include "perfmon.h" 23 24 MODULE_VERSION(IDXD_DRIVER_VERSION); 25 MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common driver"); 26 MODULE_LICENSE("GPL v2"); 27 MODULE_AUTHOR("Intel Corporation"); 28 MODULE_IMPORT_NS(IDXD); 29 30 static bool sva = true; 31 module_param(sva, bool, 0644); 32 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 33 34 bool tc_override; 35 module_param(tc_override, bool, 0644); 36 MODULE_PARM_DESC(tc_override, "Override traffic class defaults"); 37 38 #define DRV_NAME "idxd" 39 40 bool support_enqcmd; 41 DEFINE_IDA(idxd_ida); 42 43 static struct idxd_driver_data idxd_driver_data[] = { 44 [IDXD_TYPE_DSA] = { 45 .name_prefix = "dsa", 46 .type = IDXD_TYPE_DSA, 47 .compl_size = sizeof(struct dsa_completion_record), 48 .align = 32, 49 .dev_type = &dsa_device_type, 50 .evl_cr_off = offsetof(struct dsa_evl_entry, cr), 51 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */ 52 .cr_status_off = offsetof(struct dsa_completion_record, status), 53 .cr_result_off = offsetof(struct dsa_completion_record, result), 54 }, 55 [IDXD_TYPE_IAX] = { 56 .name_prefix = "iax", 57 .type = IDXD_TYPE_IAX, 58 .compl_size = sizeof(struct iax_completion_record), 59 .align = 64, 60 .dev_type = &iax_device_type, 61 .evl_cr_off = offsetof(struct iax_evl_entry, cr), 62 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */ 63 .cr_status_off = offsetof(struct iax_completion_record, status), 64 .cr_result_off = offsetof(struct iax_completion_record, error_code), 65 .load_device_defaults = idxd_load_iaa_device_defaults, 66 }, 67 }; 68 69 static struct pci_device_id idxd_pci_tbl[] = { 70 /* DSA ver 1.0 platforms */ 71 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) }, 72 /* DSA on GNR-D platforms */ 73 { PCI_DEVICE_DATA(INTEL, DSA_GNRD, &idxd_driver_data[IDXD_TYPE_DSA]) }, 74 /* DSA on DMR platforms */ 75 { PCI_DEVICE_DATA(INTEL, DSA_DMR, &idxd_driver_data[IDXD_TYPE_DSA]) }, 76 77 /* IAX ver 1.0 platforms */ 78 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) }, 79 /* IAA on DMR platforms */ 80 { PCI_DEVICE_DATA(INTEL, IAA_DMR, &idxd_driver_data[IDXD_TYPE_IAX]) }, 81 /* IAA PTL platforms */ 82 { PCI_DEVICE_DATA(INTEL, IAA_PTL, &idxd_driver_data[IDXD_TYPE_IAX]) }, 83 { 0, } 84 }; 85 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 86 87 static int idxd_setup_interrupts(struct idxd_device *idxd) 88 { 89 struct pci_dev *pdev = idxd->pdev; 90 struct device *dev = &pdev->dev; 91 struct idxd_irq_entry *ie; 92 int i, msixcnt; 93 int rc = 0; 94 95 msixcnt = pci_msix_vec_count(pdev); 96 if (msixcnt < 0) { 97 dev_err(dev, "Not MSI-X interrupt capable.\n"); 98 return -ENOSPC; 99 } 100 idxd->irq_cnt = msixcnt; 101 102 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX); 103 if (rc != msixcnt) { 104 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc); 105 return -ENOSPC; 106 } 107 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 108 109 110 ie = idxd_get_ie(idxd, 0); 111 ie->vector = pci_irq_vector(pdev, 0); 112 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie); 113 if (rc < 0) { 114 dev_err(dev, "Failed to allocate misc interrupt.\n"); 115 goto err_misc_irq; 116 } 117 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector); 118 119 for (i = 0; i < idxd->max_wqs; i++) { 120 int msix_idx = i + 1; 121 122 ie = idxd_get_ie(idxd, msix_idx); 123 ie->id = msix_idx; 124 ie->int_handle = INVALID_INT_HANDLE; 125 ie->pasid = IOMMU_PASID_INVALID; 126 127 spin_lock_init(&ie->list_lock); 128 init_llist_head(&ie->pending_llist); 129 INIT_LIST_HEAD(&ie->work_list); 130 } 131 132 idxd_unmask_error_interrupts(idxd); 133 return 0; 134 135 err_misc_irq: 136 idxd_mask_error_interrupts(idxd); 137 pci_free_irq_vectors(pdev); 138 dev_err(dev, "No usable interrupts\n"); 139 return rc; 140 } 141 142 static void idxd_cleanup_interrupts(struct idxd_device *idxd) 143 { 144 struct pci_dev *pdev = idxd->pdev; 145 struct idxd_irq_entry *ie; 146 int msixcnt; 147 148 msixcnt = pci_msix_vec_count(pdev); 149 if (msixcnt <= 0) 150 return; 151 152 ie = idxd_get_ie(idxd, 0); 153 idxd_mask_error_interrupts(idxd); 154 free_irq(ie->vector, ie); 155 pci_free_irq_vectors(pdev); 156 } 157 158 static int idxd_setup_wqs(struct idxd_device *idxd) 159 { 160 struct device *dev = &idxd->pdev->dev; 161 struct idxd_wq *wq; 162 struct device *conf_dev; 163 int i, rc; 164 165 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *), 166 GFP_KERNEL, dev_to_node(dev)); 167 if (!idxd->wqs) 168 return -ENOMEM; 169 170 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev)); 171 if (!idxd->wq_enable_map) { 172 kfree(idxd->wqs); 173 return -ENOMEM; 174 } 175 176 for (i = 0; i < idxd->max_wqs; i++) { 177 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev)); 178 if (!wq) { 179 rc = -ENOMEM; 180 goto err; 181 } 182 183 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ); 184 conf_dev = wq_confdev(wq); 185 wq->id = i; 186 wq->idxd = idxd; 187 device_initialize(wq_confdev(wq)); 188 conf_dev->parent = idxd_confdev(idxd); 189 conf_dev->bus = &dsa_bus_type; 190 conf_dev->type = &idxd_wq_device_type; 191 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id); 192 if (rc < 0) { 193 put_device(conf_dev); 194 goto err; 195 } 196 197 mutex_init(&wq->wq_lock); 198 init_waitqueue_head(&wq->err_queue); 199 init_completion(&wq->wq_dead); 200 init_completion(&wq->wq_resurrect); 201 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 202 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 203 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 204 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 205 if (!wq->wqcfg) { 206 put_device(conf_dev); 207 rc = -ENOMEM; 208 goto err; 209 } 210 211 if (idxd->hw.wq_cap.op_config) { 212 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL); 213 if (!wq->opcap_bmap) { 214 put_device(conf_dev); 215 rc = -ENOMEM; 216 goto err; 217 } 218 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 219 } 220 mutex_init(&wq->uc_lock); 221 xa_init(&wq->upasid_xa); 222 idxd->wqs[i] = wq; 223 } 224 225 return 0; 226 227 err: 228 while (--i >= 0) { 229 wq = idxd->wqs[i]; 230 conf_dev = wq_confdev(wq); 231 put_device(conf_dev); 232 } 233 return rc; 234 } 235 236 static int idxd_setup_engines(struct idxd_device *idxd) 237 { 238 struct idxd_engine *engine; 239 struct device *dev = &idxd->pdev->dev; 240 struct device *conf_dev; 241 int i, rc; 242 243 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 244 GFP_KERNEL, dev_to_node(dev)); 245 if (!idxd->engines) 246 return -ENOMEM; 247 248 for (i = 0; i < idxd->max_engines; i++) { 249 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev)); 250 if (!engine) { 251 rc = -ENOMEM; 252 goto err; 253 } 254 255 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE); 256 conf_dev = engine_confdev(engine); 257 engine->id = i; 258 engine->idxd = idxd; 259 device_initialize(conf_dev); 260 conf_dev->parent = idxd_confdev(idxd); 261 conf_dev->bus = &dsa_bus_type; 262 conf_dev->type = &idxd_engine_device_type; 263 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id); 264 if (rc < 0) { 265 put_device(conf_dev); 266 goto err; 267 } 268 269 idxd->engines[i] = engine; 270 } 271 272 return 0; 273 274 err: 275 while (--i >= 0) { 276 engine = idxd->engines[i]; 277 conf_dev = engine_confdev(engine); 278 put_device(conf_dev); 279 } 280 return rc; 281 } 282 283 static int idxd_setup_groups(struct idxd_device *idxd) 284 { 285 struct device *dev = &idxd->pdev->dev; 286 struct device *conf_dev; 287 struct idxd_group *group; 288 int i, rc; 289 290 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *), 291 GFP_KERNEL, dev_to_node(dev)); 292 if (!idxd->groups) 293 return -ENOMEM; 294 295 for (i = 0; i < idxd->max_groups; i++) { 296 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev)); 297 if (!group) { 298 rc = -ENOMEM; 299 goto err; 300 } 301 302 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP); 303 conf_dev = group_confdev(group); 304 group->id = i; 305 group->idxd = idxd; 306 device_initialize(conf_dev); 307 conf_dev->parent = idxd_confdev(idxd); 308 conf_dev->bus = &dsa_bus_type; 309 conf_dev->type = &idxd_group_device_type; 310 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id); 311 if (rc < 0) { 312 put_device(conf_dev); 313 goto err; 314 } 315 316 idxd->groups[i] = group; 317 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 318 group->tc_a = 1; 319 group->tc_b = 1; 320 } else { 321 group->tc_a = -1; 322 group->tc_b = -1; 323 } 324 /* 325 * The default value is the same as the value of 326 * total read buffers in GRPCAP. 327 */ 328 group->rdbufs_allowed = idxd->max_rdbufs; 329 } 330 331 return 0; 332 333 err: 334 while (--i >= 0) { 335 group = idxd->groups[i]; 336 put_device(group_confdev(group)); 337 } 338 return rc; 339 } 340 341 static void idxd_cleanup_internals(struct idxd_device *idxd) 342 { 343 int i; 344 345 for (i = 0; i < idxd->max_groups; i++) 346 put_device(group_confdev(idxd->groups[i])); 347 for (i = 0; i < idxd->max_engines; i++) 348 put_device(engine_confdev(idxd->engines[i])); 349 for (i = 0; i < idxd->max_wqs; i++) 350 put_device(wq_confdev(idxd->wqs[i])); 351 destroy_workqueue(idxd->wq); 352 } 353 354 static int idxd_init_evl(struct idxd_device *idxd) 355 { 356 struct device *dev = &idxd->pdev->dev; 357 unsigned int evl_cache_size; 358 struct idxd_evl *evl; 359 const char *idxd_name; 360 361 if (idxd->hw.gen_cap.evl_support == 0) 362 return 0; 363 364 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev)); 365 if (!evl) 366 return -ENOMEM; 367 368 mutex_init(&evl->lock); 369 evl->size = IDXD_EVL_SIZE_MIN; 370 371 idxd_name = dev_name(idxd_confdev(idxd)); 372 evl_cache_size = sizeof(struct idxd_evl_fault) + evl_ent_size(idxd); 373 /* 374 * Since completion record in evl_cache will be copied to user 375 * when handling completion record page fault, need to create 376 * the cache suitable for user copy. 377 */ 378 idxd->evl_cache = kmem_cache_create_usercopy(idxd_name, evl_cache_size, 379 0, 0, 0, evl_cache_size, 380 NULL); 381 if (!idxd->evl_cache) { 382 kfree(evl); 383 return -ENOMEM; 384 } 385 386 idxd->evl = evl; 387 return 0; 388 } 389 390 static int idxd_setup_internals(struct idxd_device *idxd) 391 { 392 struct device *dev = &idxd->pdev->dev; 393 int rc, i; 394 395 init_waitqueue_head(&idxd->cmd_waitq); 396 397 rc = idxd_setup_wqs(idxd); 398 if (rc < 0) 399 goto err_wqs; 400 401 rc = idxd_setup_engines(idxd); 402 if (rc < 0) 403 goto err_engine; 404 405 rc = idxd_setup_groups(idxd); 406 if (rc < 0) 407 goto err_group; 408 409 idxd->wq = create_workqueue(dev_name(dev)); 410 if (!idxd->wq) { 411 rc = -ENOMEM; 412 goto err_wkq_create; 413 } 414 415 rc = idxd_init_evl(idxd); 416 if (rc < 0) 417 goto err_evl; 418 419 return 0; 420 421 err_evl: 422 destroy_workqueue(idxd->wq); 423 err_wkq_create: 424 for (i = 0; i < idxd->max_groups; i++) 425 put_device(group_confdev(idxd->groups[i])); 426 err_group: 427 for (i = 0; i < idxd->max_engines; i++) 428 put_device(engine_confdev(idxd->engines[i])); 429 err_engine: 430 for (i = 0; i < idxd->max_wqs; i++) 431 put_device(wq_confdev(idxd->wqs[i])); 432 err_wqs: 433 return rc; 434 } 435 436 static void idxd_read_table_offsets(struct idxd_device *idxd) 437 { 438 union offsets_reg offsets; 439 struct device *dev = &idxd->pdev->dev; 440 441 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 442 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 443 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 444 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 445 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 446 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 447 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 448 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 449 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 450 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 451 } 452 453 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count) 454 { 455 int i, j, nr; 456 457 for (i = 0, nr = 0; i < count; i++) { 458 for (j = 0; j < BITS_PER_LONG_LONG; j++) { 459 if (val[i] & BIT(j)) 460 set_bit(nr, bmap); 461 nr++; 462 } 463 } 464 } 465 466 static void idxd_read_caps(struct idxd_device *idxd) 467 { 468 struct device *dev = &idxd->pdev->dev; 469 int i; 470 471 /* reading generic capabilities */ 472 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 473 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 474 475 if (idxd->hw.gen_cap.cmd_cap) { 476 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET); 477 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap); 478 } 479 480 /* reading command capabilities */ 481 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) 482 idxd->request_int_handles = true; 483 484 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 485 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 486 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift); 487 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 488 if (idxd->hw.gen_cap.config_en) 489 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 490 491 /* reading group capabilities */ 492 idxd->hw.group_cap.bits = 493 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 494 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 495 idxd->max_groups = idxd->hw.group_cap.num_groups; 496 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 497 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs; 498 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs); 499 idxd->nr_rdbufs = idxd->max_rdbufs; 500 501 /* read engine capabilities */ 502 idxd->hw.engine_cap.bits = 503 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 504 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 505 idxd->max_engines = idxd->hw.engine_cap.num_engines; 506 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 507 508 /* read workqueue capabilities */ 509 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 510 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 511 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 512 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 513 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 514 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 515 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 516 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 517 518 /* reading operation capabilities */ 519 for (i = 0; i < 4; i++) { 520 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 521 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 522 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 523 } 524 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); 525 526 /* read iaa cap */ 527 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2) 528 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET); 529 } 530 531 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data) 532 { 533 struct device *dev = &pdev->dev; 534 struct device *conf_dev; 535 struct idxd_device *idxd; 536 int rc; 537 538 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev)); 539 if (!idxd) 540 return NULL; 541 542 conf_dev = idxd_confdev(idxd); 543 idxd->pdev = pdev; 544 idxd->data = data; 545 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type); 546 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL); 547 if (idxd->id < 0) 548 return NULL; 549 550 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev)); 551 if (!idxd->opcap_bmap) { 552 ida_free(&idxd_ida, idxd->id); 553 return NULL; 554 } 555 556 device_initialize(conf_dev); 557 conf_dev->parent = dev; 558 conf_dev->bus = &dsa_bus_type; 559 conf_dev->type = idxd->data->dev_type; 560 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id); 561 if (rc < 0) { 562 put_device(conf_dev); 563 return NULL; 564 } 565 566 spin_lock_init(&idxd->dev_lock); 567 spin_lock_init(&idxd->cmd_lock); 568 569 return idxd; 570 } 571 572 static int idxd_enable_system_pasid(struct idxd_device *idxd) 573 { 574 struct pci_dev *pdev = idxd->pdev; 575 struct device *dev = &pdev->dev; 576 struct iommu_domain *domain; 577 ioasid_t pasid; 578 int ret; 579 580 /* 581 * Attach a global PASID to the DMA domain so that we can use ENQCMDS 582 * to submit work on buffers mapped by DMA API. 583 */ 584 domain = iommu_get_domain_for_dev(dev); 585 if (!domain) 586 return -EPERM; 587 588 pasid = iommu_alloc_global_pasid(dev); 589 if (pasid == IOMMU_PASID_INVALID) 590 return -ENOSPC; 591 592 /* 593 * DMA domain is owned by the driver, it should support all valid 594 * types such as DMA-FQ, identity, etc. 595 */ 596 ret = iommu_attach_device_pasid(domain, dev, pasid, NULL); 597 if (ret) { 598 dev_err(dev, "failed to attach device pasid %d, domain type %d", 599 pasid, domain->type); 600 iommu_free_global_pasid(pasid); 601 return ret; 602 } 603 604 /* Since we set user privilege for kernel DMA, enable completion IRQ */ 605 idxd_set_user_intr(idxd, 1); 606 idxd->pasid = pasid; 607 608 return ret; 609 } 610 611 static void idxd_disable_system_pasid(struct idxd_device *idxd) 612 { 613 struct pci_dev *pdev = idxd->pdev; 614 struct device *dev = &pdev->dev; 615 struct iommu_domain *domain; 616 617 domain = iommu_get_domain_for_dev(dev); 618 if (!domain) 619 return; 620 621 iommu_detach_device_pasid(domain, dev, idxd->pasid); 622 iommu_free_global_pasid(idxd->pasid); 623 624 idxd_set_user_intr(idxd, 0); 625 idxd->sva = NULL; 626 idxd->pasid = IOMMU_PASID_INVALID; 627 } 628 629 static int idxd_enable_sva(struct pci_dev *pdev) 630 { 631 int ret; 632 633 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 634 if (ret) 635 return ret; 636 637 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 638 if (ret) 639 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 640 641 return ret; 642 } 643 644 static void idxd_disable_sva(struct pci_dev *pdev) 645 { 646 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 647 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF); 648 } 649 650 static int idxd_probe(struct idxd_device *idxd) 651 { 652 struct pci_dev *pdev = idxd->pdev; 653 struct device *dev = &pdev->dev; 654 int rc; 655 656 dev_dbg(dev, "%s entered and resetting device\n", __func__); 657 rc = idxd_device_init_reset(idxd); 658 if (rc < 0) 659 return rc; 660 661 dev_dbg(dev, "IDXD reset complete\n"); 662 663 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 664 if (idxd_enable_sva(pdev)) { 665 dev_warn(dev, "Unable to turn on user SVA feature.\n"); 666 } else { 667 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags); 668 669 rc = idxd_enable_system_pasid(idxd); 670 if (rc) 671 dev_warn(dev, "No in-kernel DMA with PASID. %d\n", rc); 672 else 673 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 674 } 675 } else if (!sva) { 676 dev_warn(dev, "User forced SVA off via module param.\n"); 677 } 678 679 idxd_read_caps(idxd); 680 idxd_read_table_offsets(idxd); 681 682 rc = idxd_setup_internals(idxd); 683 if (rc) 684 goto err; 685 686 /* If the configs are readonly, then load them from device */ 687 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 688 dev_dbg(dev, "Loading RO device config\n"); 689 rc = idxd_device_load_config(idxd); 690 if (rc < 0) 691 goto err_config; 692 } 693 694 rc = idxd_setup_interrupts(idxd); 695 if (rc) 696 goto err_config; 697 698 idxd->major = idxd_cdev_get_major(idxd); 699 700 rc = perfmon_pmu_init(idxd); 701 if (rc < 0) 702 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc); 703 704 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 705 return 0; 706 707 err_config: 708 idxd_cleanup_internals(idxd); 709 err: 710 if (device_pasid_enabled(idxd)) 711 idxd_disable_system_pasid(idxd); 712 if (device_user_pasid_enabled(idxd)) 713 idxd_disable_sva(pdev); 714 return rc; 715 } 716 717 static void idxd_cleanup(struct idxd_device *idxd) 718 { 719 perfmon_pmu_remove(idxd); 720 idxd_cleanup_interrupts(idxd); 721 idxd_cleanup_internals(idxd); 722 if (device_pasid_enabled(idxd)) 723 idxd_disable_system_pasid(idxd); 724 if (device_user_pasid_enabled(idxd)) 725 idxd_disable_sva(idxd->pdev); 726 } 727 728 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 729 { 730 struct device *dev = &pdev->dev; 731 struct idxd_device *idxd; 732 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data; 733 int rc; 734 735 rc = pci_enable_device(pdev); 736 if (rc) 737 return rc; 738 739 dev_dbg(dev, "Alloc IDXD context\n"); 740 idxd = idxd_alloc(pdev, data); 741 if (!idxd) { 742 rc = -ENOMEM; 743 goto err_idxd_alloc; 744 } 745 746 dev_dbg(dev, "Mapping BARs\n"); 747 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0); 748 if (!idxd->reg_base) { 749 rc = -ENOMEM; 750 goto err_iomap; 751 } 752 753 dev_dbg(dev, "Set DMA masks\n"); 754 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 755 if (rc) 756 goto err; 757 758 dev_dbg(dev, "Set PCI master\n"); 759 pci_set_master(pdev); 760 pci_set_drvdata(pdev, idxd); 761 762 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 763 rc = idxd_probe(idxd); 764 if (rc) { 765 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 766 goto err; 767 } 768 769 if (data->load_device_defaults) { 770 rc = data->load_device_defaults(idxd); 771 if (rc) 772 dev_warn(dev, "IDXD loading device defaults failed\n"); 773 } 774 775 rc = idxd_register_devices(idxd); 776 if (rc) { 777 dev_err(dev, "IDXD sysfs setup failed\n"); 778 goto err_dev_register; 779 } 780 781 rc = idxd_device_init_debugfs(idxd); 782 if (rc) 783 dev_warn(dev, "IDXD debugfs failed to setup\n"); 784 785 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 786 idxd->hw.version); 787 788 idxd->user_submission_safe = data->user_submission_safe; 789 790 return 0; 791 792 err_dev_register: 793 idxd_cleanup(idxd); 794 err: 795 pci_iounmap(pdev, idxd->reg_base); 796 err_iomap: 797 put_device(idxd_confdev(idxd)); 798 err_idxd_alloc: 799 pci_disable_device(pdev); 800 return rc; 801 } 802 803 void idxd_wqs_quiesce(struct idxd_device *idxd) 804 { 805 struct idxd_wq *wq; 806 int i; 807 808 for (i = 0; i < idxd->max_wqs; i++) { 809 wq = idxd->wqs[i]; 810 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL) 811 idxd_wq_quiesce(wq); 812 } 813 } 814 815 static void idxd_shutdown(struct pci_dev *pdev) 816 { 817 struct idxd_device *idxd = pci_get_drvdata(pdev); 818 struct idxd_irq_entry *irq_entry; 819 int rc; 820 821 rc = idxd_device_disable(idxd); 822 if (rc) 823 dev_err(&pdev->dev, "Disabling device failed\n"); 824 825 irq_entry = &idxd->ie; 826 synchronize_irq(irq_entry->vector); 827 idxd_mask_error_interrupts(idxd); 828 flush_workqueue(idxd->wq); 829 } 830 831 static void idxd_remove(struct pci_dev *pdev) 832 { 833 struct idxd_device *idxd = pci_get_drvdata(pdev); 834 struct idxd_irq_entry *irq_entry; 835 836 idxd_unregister_devices(idxd); 837 /* 838 * When ->release() is called for the idxd->conf_dev, it frees all the memory related 839 * to the idxd context. The driver still needs those bits in order to do the rest of 840 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref 841 * on the device here to hold off the freeing while allowing the idxd sub-driver 842 * to unbind. 843 */ 844 get_device(idxd_confdev(idxd)); 845 device_unregister(idxd_confdev(idxd)); 846 idxd_shutdown(pdev); 847 if (device_pasid_enabled(idxd)) 848 idxd_disable_system_pasid(idxd); 849 idxd_device_remove_debugfs(idxd); 850 851 irq_entry = idxd_get_ie(idxd, 0); 852 free_irq(irq_entry->vector, irq_entry); 853 pci_free_irq_vectors(pdev); 854 pci_iounmap(pdev, idxd->reg_base); 855 if (device_user_pasid_enabled(idxd)) 856 idxd_disable_sva(pdev); 857 pci_disable_device(pdev); 858 destroy_workqueue(idxd->wq); 859 perfmon_pmu_remove(idxd); 860 put_device(idxd_confdev(idxd)); 861 } 862 863 static struct pci_driver idxd_pci_driver = { 864 .name = DRV_NAME, 865 .id_table = idxd_pci_tbl, 866 .probe = idxd_pci_probe, 867 .remove = idxd_remove, 868 .shutdown = idxd_shutdown, 869 }; 870 871 static int __init idxd_init_module(void) 872 { 873 int err; 874 875 /* 876 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 877 * enumerating the device. We can not utilize it. 878 */ 879 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) { 880 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 881 return -ENODEV; 882 } 883 884 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 885 pr_warn("Platform does not have ENQCMD(S) support.\n"); 886 else 887 support_enqcmd = true; 888 889 err = idxd_driver_register(&idxd_drv); 890 if (err < 0) 891 goto err_idxd_driver_register; 892 893 err = idxd_driver_register(&idxd_dmaengine_drv); 894 if (err < 0) 895 goto err_idxd_dmaengine_driver_register; 896 897 err = idxd_driver_register(&idxd_user_drv); 898 if (err < 0) 899 goto err_idxd_user_driver_register; 900 901 err = idxd_cdev_register(); 902 if (err) 903 goto err_cdev_register; 904 905 err = idxd_init_debugfs(); 906 if (err) 907 goto err_debugfs; 908 909 err = pci_register_driver(&idxd_pci_driver); 910 if (err) 911 goto err_pci_register; 912 913 return 0; 914 915 err_pci_register: 916 idxd_remove_debugfs(); 917 err_debugfs: 918 idxd_cdev_remove(); 919 err_cdev_register: 920 idxd_driver_unregister(&idxd_user_drv); 921 err_idxd_user_driver_register: 922 idxd_driver_unregister(&idxd_dmaengine_drv); 923 err_idxd_dmaengine_driver_register: 924 idxd_driver_unregister(&idxd_drv); 925 err_idxd_driver_register: 926 return err; 927 } 928 module_init(idxd_init_module); 929 930 static void __exit idxd_exit_module(void) 931 { 932 idxd_driver_unregister(&idxd_user_drv); 933 idxd_driver_unregister(&idxd_dmaengine_drv); 934 idxd_driver_unregister(&idxd_drv); 935 pci_unregister_driver(&idxd_pci_driver); 936 idxd_cdev_remove(); 937 idxd_remove_debugfs(); 938 } 939 module_exit(idxd_exit_module); 940