1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DMA Engine test module 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 * Copyright (C) 2013 Intel Corporation 7 */ 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/err.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/freezer.h> 15 #include <linux/init.h> 16 #include <linux/kthread.h> 17 #include <linux/sched/task.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/random.h> 21 #include <linux/slab.h> 22 #include <linux/wait.h> 23 24 static unsigned int test_buf_size = 16384; 25 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); 26 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); 27 28 static char test_device[32]; 29 module_param_string(device, test_device, sizeof(test_device), 30 S_IRUGO | S_IWUSR); 31 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); 32 33 static unsigned int threads_per_chan = 1; 34 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); 35 MODULE_PARM_DESC(threads_per_chan, 36 "Number of threads to start per channel (default: 1)"); 37 38 static unsigned int max_channels; 39 module_param(max_channels, uint, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(max_channels, 41 "Maximum number of channels to use (default: all)"); 42 43 static unsigned int iterations; 44 module_param(iterations, uint, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(iterations, 46 "Iterations before stopping test (default: infinite)"); 47 48 static unsigned int dmatest; 49 module_param(dmatest, uint, S_IRUGO | S_IWUSR); 50 MODULE_PARM_DESC(dmatest, 51 "dmatest 0-memcpy 1-memset (default: 0)"); 52 53 static unsigned int xor_sources = 3; 54 module_param(xor_sources, uint, S_IRUGO | S_IWUSR); 55 MODULE_PARM_DESC(xor_sources, 56 "Number of xor source buffers (default: 3)"); 57 58 static unsigned int pq_sources = 3; 59 module_param(pq_sources, uint, S_IRUGO | S_IWUSR); 60 MODULE_PARM_DESC(pq_sources, 61 "Number of p+q source buffers (default: 3)"); 62 63 static int timeout = 3000; 64 module_param(timeout, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " 66 "Pass -1 for infinite timeout"); 67 68 static bool noverify; 69 module_param(noverify, bool, S_IRUGO | S_IWUSR); 70 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)"); 71 72 static bool norandom; 73 module_param(norandom, bool, 0644); 74 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)"); 75 76 static bool verbose; 77 module_param(verbose, bool, S_IRUGO | S_IWUSR); 78 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); 79 80 static int alignment = -1; 81 module_param(alignment, int, 0644); 82 MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))"); 83 84 static unsigned int transfer_size; 85 module_param(transfer_size, uint, 0644); 86 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))"); 87 88 static bool polled; 89 module_param(polled, bool, S_IRUGO | S_IWUSR); 90 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts"); 91 92 /** 93 * struct dmatest_params - test parameters. 94 * @buf_size: size of the memcpy test buffer 95 * @channel: bus ID of the channel to test 96 * @device: bus ID of the DMA Engine to test 97 * @threads_per_chan: number of threads to start per channel 98 * @max_channels: maximum number of channels to use 99 * @iterations: iterations before stopping test 100 * @xor_sources: number of xor source buffers 101 * @pq_sources: number of p+q source buffers 102 * @timeout: transfer timeout in msec, -1 for infinite timeout 103 * @noverify: disable data verification 104 * @norandom: disable random offset setup 105 * @alignment: custom data address alignment taken as 2^alignment 106 * @transfer_size: custom transfer size in bytes 107 * @polled: use polling for completion instead of interrupts 108 */ 109 struct dmatest_params { 110 unsigned int buf_size; 111 char channel[20]; 112 char device[32]; 113 unsigned int threads_per_chan; 114 unsigned int max_channels; 115 unsigned int iterations; 116 unsigned int xor_sources; 117 unsigned int pq_sources; 118 int timeout; 119 bool noverify; 120 bool norandom; 121 int alignment; 122 unsigned int transfer_size; 123 bool polled; 124 }; 125 126 /** 127 * struct dmatest_info - test information. 128 * @params: test parameters 129 * @channels: channels under test 130 * @nr_channels: number of channels under test 131 * @lock: access protection to the fields of this structure 132 * @did_init: module has been initialized completely 133 */ 134 static struct dmatest_info { 135 /* Test parameters */ 136 struct dmatest_params params; 137 138 /* Internal state */ 139 struct list_head channels; 140 unsigned int nr_channels; 141 struct mutex lock; 142 bool did_init; 143 } test_info = { 144 .channels = LIST_HEAD_INIT(test_info.channels), 145 .lock = __MUTEX_INITIALIZER(test_info.lock), 146 }; 147 148 static int dmatest_run_set(const char *val, const struct kernel_param *kp); 149 static int dmatest_run_get(char *val, const struct kernel_param *kp); 150 static const struct kernel_param_ops run_ops = { 151 .set = dmatest_run_set, 152 .get = dmatest_run_get, 153 }; 154 static bool dmatest_run; 155 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); 156 MODULE_PARM_DESC(run, "Run the test (default: false)"); 157 158 static int dmatest_chan_set(const char *val, const struct kernel_param *kp); 159 static int dmatest_chan_get(char *val, const struct kernel_param *kp); 160 static const struct kernel_param_ops multi_chan_ops = { 161 .set = dmatest_chan_set, 162 .get = dmatest_chan_get, 163 }; 164 165 static char test_channel[20]; 166 static struct kparam_string newchan_kps = { 167 .string = test_channel, 168 .maxlen = 20, 169 }; 170 module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644); 171 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); 172 173 static int dmatest_test_list_get(char *val, const struct kernel_param *kp); 174 static const struct kernel_param_ops test_list_ops = { 175 .get = dmatest_test_list_get, 176 }; 177 module_param_cb(test_list, &test_list_ops, NULL, 0444); 178 MODULE_PARM_DESC(test_list, "Print current test list"); 179 180 /* Maximum amount of mismatched bytes in buffer to print */ 181 #define MAX_ERROR_COUNT 32 182 183 /* 184 * Initialization patterns. All bytes in the source buffer has bit 7 185 * set, all bytes in the destination buffer has bit 7 cleared. 186 * 187 * Bit 6 is set for all bytes which are to be copied by the DMA 188 * engine. Bit 5 is set for all bytes which are to be overwritten by 189 * the DMA engine. 190 * 191 * The remaining bits are the inverse of a counter which increments by 192 * one for each byte address. 193 */ 194 #define PATTERN_SRC 0x80 195 #define PATTERN_DST 0x00 196 #define PATTERN_COPY 0x40 197 #define PATTERN_OVERWRITE 0x20 198 #define PATTERN_COUNT_MASK 0x1f 199 #define PATTERN_MEMSET_IDX 0x01 200 201 /* Fixed point arithmetic ops */ 202 #define FIXPT_SHIFT 8 203 #define FIXPNT_MASK 0xFF 204 #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT) 205 #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT) 206 #define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT) 207 208 /* poor man's completion - we want to use wait_event_freezable() on it */ 209 struct dmatest_done { 210 bool done; 211 wait_queue_head_t *wait; 212 }; 213 214 struct dmatest_data { 215 u8 **raw; 216 u8 **aligned; 217 unsigned int cnt; 218 unsigned int off; 219 }; 220 221 struct dmatest_thread { 222 struct list_head node; 223 struct dmatest_info *info; 224 struct task_struct *task; 225 struct dma_chan *chan; 226 struct dmatest_data src; 227 struct dmatest_data dst; 228 enum dma_transaction_type type; 229 wait_queue_head_t done_wait; 230 struct dmatest_done test_done; 231 bool done; 232 bool pending; 233 }; 234 235 struct dmatest_chan { 236 struct list_head node; 237 struct dma_chan *chan; 238 struct list_head threads; 239 }; 240 241 static DECLARE_WAIT_QUEUE_HEAD(thread_wait); 242 static bool wait; 243 244 static bool is_threaded_test_run(struct dmatest_info *info) 245 { 246 struct dmatest_chan *dtc; 247 248 list_for_each_entry(dtc, &info->channels, node) { 249 struct dmatest_thread *thread; 250 251 list_for_each_entry(thread, &dtc->threads, node) { 252 if (!thread->done && !thread->pending) 253 return true; 254 } 255 } 256 257 return false; 258 } 259 260 static bool is_threaded_test_pending(struct dmatest_info *info) 261 { 262 struct dmatest_chan *dtc; 263 264 list_for_each_entry(dtc, &info->channels, node) { 265 struct dmatest_thread *thread; 266 267 list_for_each_entry(thread, &dtc->threads, node) { 268 if (thread->pending) 269 return true; 270 } 271 } 272 273 return false; 274 } 275 276 static int dmatest_wait_get(char *val, const struct kernel_param *kp) 277 { 278 struct dmatest_info *info = &test_info; 279 struct dmatest_params *params = &info->params; 280 281 if (params->iterations) 282 wait_event(thread_wait, !is_threaded_test_run(info)); 283 wait = true; 284 return param_get_bool(val, kp); 285 } 286 287 static const struct kernel_param_ops wait_ops = { 288 .get = dmatest_wait_get, 289 .set = param_set_bool, 290 }; 291 module_param_cb(wait, &wait_ops, &wait, S_IRUGO); 292 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); 293 294 static bool dmatest_match_channel(struct dmatest_params *params, 295 struct dma_chan *chan) 296 { 297 if (params->channel[0] == '\0') 298 return true; 299 return strcmp(dma_chan_name(chan), params->channel) == 0; 300 } 301 302 static bool dmatest_match_device(struct dmatest_params *params, 303 struct dma_device *device) 304 { 305 if (params->device[0] == '\0') 306 return true; 307 return strcmp(dev_name(device->dev), params->device) == 0; 308 } 309 310 static unsigned long dmatest_random(void) 311 { 312 unsigned long buf; 313 314 prandom_bytes(&buf, sizeof(buf)); 315 return buf; 316 } 317 318 static inline u8 gen_inv_idx(u8 index, bool is_memset) 319 { 320 u8 val = is_memset ? PATTERN_MEMSET_IDX : index; 321 322 return ~val & PATTERN_COUNT_MASK; 323 } 324 325 static inline u8 gen_src_value(u8 index, bool is_memset) 326 { 327 return PATTERN_SRC | gen_inv_idx(index, is_memset); 328 } 329 330 static inline u8 gen_dst_value(u8 index, bool is_memset) 331 { 332 return PATTERN_DST | gen_inv_idx(index, is_memset); 333 } 334 335 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, 336 unsigned int buf_size, bool is_memset) 337 { 338 unsigned int i; 339 u8 *buf; 340 341 for (; (buf = *bufs); bufs++) { 342 for (i = 0; i < start; i++) 343 buf[i] = gen_src_value(i, is_memset); 344 for ( ; i < start + len; i++) 345 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY; 346 for ( ; i < buf_size; i++) 347 buf[i] = gen_src_value(i, is_memset); 348 buf++; 349 } 350 } 351 352 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, 353 unsigned int buf_size, bool is_memset) 354 { 355 unsigned int i; 356 u8 *buf; 357 358 for (; (buf = *bufs); bufs++) { 359 for (i = 0; i < start; i++) 360 buf[i] = gen_dst_value(i, is_memset); 361 for ( ; i < start + len; i++) 362 buf[i] = gen_dst_value(i, is_memset) | 363 PATTERN_OVERWRITE; 364 for ( ; i < buf_size; i++) 365 buf[i] = gen_dst_value(i, is_memset); 366 } 367 } 368 369 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, 370 unsigned int counter, bool is_srcbuf, bool is_memset) 371 { 372 u8 diff = actual ^ pattern; 373 u8 expected = pattern | gen_inv_idx(counter, is_memset); 374 const char *thread_name = current->comm; 375 376 if (is_srcbuf) 377 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", 378 thread_name, index, expected, actual); 379 else if ((pattern & PATTERN_COPY) 380 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) 381 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", 382 thread_name, index, expected, actual); 383 else if (diff & PATTERN_SRC) 384 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", 385 thread_name, index, expected, actual); 386 else 387 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", 388 thread_name, index, expected, actual); 389 } 390 391 static unsigned int dmatest_verify(u8 **bufs, unsigned int start, 392 unsigned int end, unsigned int counter, u8 pattern, 393 bool is_srcbuf, bool is_memset) 394 { 395 unsigned int i; 396 unsigned int error_count = 0; 397 u8 actual; 398 u8 expected; 399 u8 *buf; 400 unsigned int counter_orig = counter; 401 402 for (; (buf = *bufs); bufs++) { 403 counter = counter_orig; 404 for (i = start; i < end; i++) { 405 actual = buf[i]; 406 expected = pattern | gen_inv_idx(counter, is_memset); 407 if (actual != expected) { 408 if (error_count < MAX_ERROR_COUNT) 409 dmatest_mismatch(actual, pattern, i, 410 counter, is_srcbuf, 411 is_memset); 412 error_count++; 413 } 414 counter++; 415 } 416 } 417 418 if (error_count > MAX_ERROR_COUNT) 419 pr_warn("%s: %u errors suppressed\n", 420 current->comm, error_count - MAX_ERROR_COUNT); 421 422 return error_count; 423 } 424 425 426 static void dmatest_callback(void *arg) 427 { 428 struct dmatest_done *done = arg; 429 struct dmatest_thread *thread = 430 container_of(done, struct dmatest_thread, test_done); 431 if (!thread->done) { 432 done->done = true; 433 wake_up_all(done->wait); 434 } else { 435 /* 436 * If thread->done, it means that this callback occurred 437 * after the parent thread has cleaned up. This can 438 * happen in the case that driver doesn't implement 439 * the terminate_all() functionality and a dma operation 440 * did not occur within the timeout period 441 */ 442 WARN(1, "dmatest: Kernel memory may be corrupted!!\n"); 443 } 444 } 445 446 static unsigned int min_odd(unsigned int x, unsigned int y) 447 { 448 unsigned int val = min(x, y); 449 450 return val % 2 ? val : val - 1; 451 } 452 453 static void result(const char *err, unsigned int n, unsigned int src_off, 454 unsigned int dst_off, unsigned int len, unsigned long data) 455 { 456 if (IS_ERR_VALUE(data)) { 457 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n", 458 current->comm, n, err, src_off, dst_off, len, data); 459 } else { 460 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 461 current->comm, n, err, src_off, dst_off, len, data); 462 } 463 } 464 465 static void dbg_result(const char *err, unsigned int n, unsigned int src_off, 466 unsigned int dst_off, unsigned int len, 467 unsigned long data) 468 { 469 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 470 current->comm, n, err, src_off, dst_off, len, data); 471 } 472 473 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ 474 if (verbose) \ 475 result(err, n, src_off, dst_off, len, data); \ 476 else \ 477 dbg_result(err, n, src_off, dst_off, len, data);\ 478 }) 479 480 static unsigned long long dmatest_persec(s64 runtime, unsigned int val) 481 { 482 unsigned long long per_sec = 1000000; 483 484 if (runtime <= 0) 485 return 0; 486 487 /* drop precision until runtime is 32-bits */ 488 while (runtime > UINT_MAX) { 489 runtime >>= 1; 490 per_sec <<= 1; 491 } 492 493 per_sec *= val; 494 per_sec = INT_TO_FIXPT(per_sec); 495 do_div(per_sec, runtime); 496 497 return per_sec; 498 } 499 500 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) 501 { 502 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10)); 503 } 504 505 static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt) 506 { 507 unsigned int i; 508 509 for (i = 0; i < cnt; i++) 510 kfree(d->raw[i]); 511 512 kfree(d->aligned); 513 kfree(d->raw); 514 } 515 516 static void dmatest_free_test_data(struct dmatest_data *d) 517 { 518 __dmatest_free_test_data(d, d->cnt); 519 } 520 521 static int dmatest_alloc_test_data(struct dmatest_data *d, 522 unsigned int buf_size, u8 align) 523 { 524 unsigned int i = 0; 525 526 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); 527 if (!d->raw) 528 return -ENOMEM; 529 530 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); 531 if (!d->aligned) 532 goto err; 533 534 for (i = 0; i < d->cnt; i++) { 535 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL); 536 if (!d->raw[i]) 537 goto err; 538 539 /* align to alignment restriction */ 540 if (align) 541 d->aligned[i] = PTR_ALIGN(d->raw[i], align); 542 else 543 d->aligned[i] = d->raw[i]; 544 } 545 546 return 0; 547 err: 548 __dmatest_free_test_data(d, i); 549 return -ENOMEM; 550 } 551 552 /* 553 * This function repeatedly tests DMA transfers of various lengths and 554 * offsets for a given operation type until it is told to exit by 555 * kthread_stop(). There may be multiple threads running this function 556 * in parallel for a single channel, and there may be multiple channels 557 * being tested in parallel. 558 * 559 * Before each test, the source and destination buffer is initialized 560 * with a known pattern. This pattern is different depending on 561 * whether it's in an area which is supposed to be copied or 562 * overwritten, and different in the source and destination buffers. 563 * So if the DMA engine doesn't copy exactly what we tell it to copy, 564 * we'll notice. 565 */ 566 static int dmatest_func(void *data) 567 { 568 struct dmatest_thread *thread = data; 569 struct dmatest_done *done = &thread->test_done; 570 struct dmatest_info *info; 571 struct dmatest_params *params; 572 struct dma_chan *chan; 573 struct dma_device *dev; 574 unsigned int error_count; 575 unsigned int failed_tests = 0; 576 unsigned int total_tests = 0; 577 dma_cookie_t cookie; 578 enum dma_status status; 579 enum dma_ctrl_flags flags; 580 u8 *pq_coefs = NULL; 581 int ret; 582 unsigned int buf_size; 583 struct dmatest_data *src; 584 struct dmatest_data *dst; 585 int i; 586 ktime_t ktime, start, diff; 587 ktime_t filltime = 0; 588 ktime_t comparetime = 0; 589 s64 runtime = 0; 590 unsigned long long total_len = 0; 591 unsigned long long iops = 0; 592 u8 align = 0; 593 bool is_memset = false; 594 dma_addr_t *srcs; 595 dma_addr_t *dma_pq; 596 597 set_freezable(); 598 599 ret = -ENOMEM; 600 601 smp_rmb(); 602 thread->pending = false; 603 info = thread->info; 604 params = &info->params; 605 chan = thread->chan; 606 dev = chan->device; 607 src = &thread->src; 608 dst = &thread->dst; 609 if (thread->type == DMA_MEMCPY) { 610 align = params->alignment < 0 ? dev->copy_align : 611 params->alignment; 612 src->cnt = dst->cnt = 1; 613 } else if (thread->type == DMA_MEMSET) { 614 align = params->alignment < 0 ? dev->fill_align : 615 params->alignment; 616 src->cnt = dst->cnt = 1; 617 is_memset = true; 618 } else if (thread->type == DMA_XOR) { 619 /* force odd to ensure dst = src */ 620 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor); 621 dst->cnt = 1; 622 align = params->alignment < 0 ? dev->xor_align : 623 params->alignment; 624 } else if (thread->type == DMA_PQ) { 625 /* force odd to ensure dst = src */ 626 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); 627 dst->cnt = 2; 628 align = params->alignment < 0 ? dev->pq_align : 629 params->alignment; 630 631 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL); 632 if (!pq_coefs) 633 goto err_thread_type; 634 635 for (i = 0; i < src->cnt; i++) 636 pq_coefs[i] = 1; 637 } else 638 goto err_thread_type; 639 640 /* Check if buffer count fits into map count variable (u8) */ 641 if ((src->cnt + dst->cnt) >= 255) { 642 pr_err("too many buffers (%d of 255 supported)\n", 643 src->cnt + dst->cnt); 644 goto err_free_coefs; 645 } 646 647 buf_size = params->buf_size; 648 if (1 << align > buf_size) { 649 pr_err("%u-byte buffer too small for %d-byte alignment\n", 650 buf_size, 1 << align); 651 goto err_free_coefs; 652 } 653 654 if (dmatest_alloc_test_data(src, buf_size, align) < 0) 655 goto err_free_coefs; 656 657 if (dmatest_alloc_test_data(dst, buf_size, align) < 0) 658 goto err_src; 659 660 set_user_nice(current, 10); 661 662 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL); 663 if (!srcs) 664 goto err_dst; 665 666 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL); 667 if (!dma_pq) 668 goto err_srcs_array; 669 670 /* 671 * src and dst buffers are freed by ourselves below 672 */ 673 if (params->polled) 674 flags = DMA_CTRL_ACK; 675 else 676 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 677 678 ktime = ktime_get(); 679 while (!(kthread_should_stop() || 680 (params->iterations && total_tests >= params->iterations))) { 681 struct dma_async_tx_descriptor *tx = NULL; 682 struct dmaengine_unmap_data *um; 683 dma_addr_t *dsts; 684 unsigned int len; 685 686 total_tests++; 687 688 if (params->transfer_size) { 689 if (params->transfer_size >= buf_size) { 690 pr_err("%u-byte transfer size must be lower than %u-buffer size\n", 691 params->transfer_size, buf_size); 692 break; 693 } 694 len = params->transfer_size; 695 } else if (params->norandom) { 696 len = buf_size; 697 } else { 698 len = dmatest_random() % buf_size + 1; 699 } 700 701 /* Do not alter transfer size explicitly defined by user */ 702 if (!params->transfer_size) { 703 len = (len >> align) << align; 704 if (!len) 705 len = 1 << align; 706 } 707 total_len += len; 708 709 if (params->norandom) { 710 src->off = 0; 711 dst->off = 0; 712 } else { 713 src->off = dmatest_random() % (buf_size - len + 1); 714 dst->off = dmatest_random() % (buf_size - len + 1); 715 716 src->off = (src->off >> align) << align; 717 dst->off = (dst->off >> align) << align; 718 } 719 720 if (!params->noverify) { 721 start = ktime_get(); 722 dmatest_init_srcs(src->aligned, src->off, len, 723 buf_size, is_memset); 724 dmatest_init_dsts(dst->aligned, dst->off, len, 725 buf_size, is_memset); 726 727 diff = ktime_sub(ktime_get(), start); 728 filltime = ktime_add(filltime, diff); 729 } 730 731 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt, 732 GFP_KERNEL); 733 if (!um) { 734 failed_tests++; 735 result("unmap data NULL", total_tests, 736 src->off, dst->off, len, ret); 737 continue; 738 } 739 740 um->len = buf_size; 741 for (i = 0; i < src->cnt; i++) { 742 void *buf = src->aligned[i]; 743 struct page *pg = virt_to_page(buf); 744 unsigned long pg_off = offset_in_page(buf); 745 746 um->addr[i] = dma_map_page(dev->dev, pg, pg_off, 747 um->len, DMA_TO_DEVICE); 748 srcs[i] = um->addr[i] + src->off; 749 ret = dma_mapping_error(dev->dev, um->addr[i]); 750 if (ret) { 751 result("src mapping error", total_tests, 752 src->off, dst->off, len, ret); 753 goto error_unmap_continue; 754 } 755 um->to_cnt++; 756 } 757 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ 758 dsts = &um->addr[src->cnt]; 759 for (i = 0; i < dst->cnt; i++) { 760 void *buf = dst->aligned[i]; 761 struct page *pg = virt_to_page(buf); 762 unsigned long pg_off = offset_in_page(buf); 763 764 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, 765 DMA_BIDIRECTIONAL); 766 ret = dma_mapping_error(dev->dev, dsts[i]); 767 if (ret) { 768 result("dst mapping error", total_tests, 769 src->off, dst->off, len, ret); 770 goto error_unmap_continue; 771 } 772 um->bidi_cnt++; 773 } 774 775 if (thread->type == DMA_MEMCPY) 776 tx = dev->device_prep_dma_memcpy(chan, 777 dsts[0] + dst->off, 778 srcs[0], len, flags); 779 else if (thread->type == DMA_MEMSET) 780 tx = dev->device_prep_dma_memset(chan, 781 dsts[0] + dst->off, 782 *(src->aligned[0] + src->off), 783 len, flags); 784 else if (thread->type == DMA_XOR) 785 tx = dev->device_prep_dma_xor(chan, 786 dsts[0] + dst->off, 787 srcs, src->cnt, 788 len, flags); 789 else if (thread->type == DMA_PQ) { 790 for (i = 0; i < dst->cnt; i++) 791 dma_pq[i] = dsts[i] + dst->off; 792 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, 793 src->cnt, pq_coefs, 794 len, flags); 795 } 796 797 if (!tx) { 798 result("prep error", total_tests, src->off, 799 dst->off, len, ret); 800 msleep(100); 801 goto error_unmap_continue; 802 } 803 804 done->done = false; 805 if (!params->polled) { 806 tx->callback = dmatest_callback; 807 tx->callback_param = done; 808 } 809 cookie = tx->tx_submit(tx); 810 811 if (dma_submit_error(cookie)) { 812 result("submit error", total_tests, src->off, 813 dst->off, len, ret); 814 msleep(100); 815 goto error_unmap_continue; 816 } 817 818 if (params->polled) { 819 status = dma_sync_wait(chan, cookie); 820 dmaengine_terminate_sync(chan); 821 if (status == DMA_COMPLETE) 822 done->done = true; 823 } else { 824 dma_async_issue_pending(chan); 825 826 wait_event_freezable_timeout(thread->done_wait, 827 done->done, 828 msecs_to_jiffies(params->timeout)); 829 830 status = dma_async_is_tx_complete(chan, cookie, NULL, 831 NULL); 832 } 833 834 if (!done->done) { 835 result("test timed out", total_tests, src->off, dst->off, 836 len, 0); 837 goto error_unmap_continue; 838 } else if (status != DMA_COMPLETE && 839 !(dma_has_cap(DMA_COMPLETION_NO_ORDER, 840 dev->cap_mask) && 841 status == DMA_OUT_OF_ORDER)) { 842 result(status == DMA_ERROR ? 843 "completion error status" : 844 "completion busy status", total_tests, src->off, 845 dst->off, len, ret); 846 goto error_unmap_continue; 847 } 848 849 dmaengine_unmap_put(um); 850 851 if (params->noverify) { 852 verbose_result("test passed", total_tests, src->off, 853 dst->off, len, 0); 854 continue; 855 } 856 857 start = ktime_get(); 858 pr_debug("%s: verifying source buffer...\n", current->comm); 859 error_count = dmatest_verify(src->aligned, 0, src->off, 860 0, PATTERN_SRC, true, is_memset); 861 error_count += dmatest_verify(src->aligned, src->off, 862 src->off + len, src->off, 863 PATTERN_SRC | PATTERN_COPY, true, is_memset); 864 error_count += dmatest_verify(src->aligned, src->off + len, 865 buf_size, src->off + len, 866 PATTERN_SRC, true, is_memset); 867 868 pr_debug("%s: verifying dest buffer...\n", current->comm); 869 error_count += dmatest_verify(dst->aligned, 0, dst->off, 870 0, PATTERN_DST, false, is_memset); 871 872 error_count += dmatest_verify(dst->aligned, dst->off, 873 dst->off + len, src->off, 874 PATTERN_SRC | PATTERN_COPY, false, is_memset); 875 876 error_count += dmatest_verify(dst->aligned, dst->off + len, 877 buf_size, dst->off + len, 878 PATTERN_DST, false, is_memset); 879 880 diff = ktime_sub(ktime_get(), start); 881 comparetime = ktime_add(comparetime, diff); 882 883 if (error_count) { 884 result("data error", total_tests, src->off, dst->off, 885 len, error_count); 886 failed_tests++; 887 } else { 888 verbose_result("test passed", total_tests, src->off, 889 dst->off, len, 0); 890 } 891 892 continue; 893 894 error_unmap_continue: 895 dmaengine_unmap_put(um); 896 failed_tests++; 897 } 898 ktime = ktime_sub(ktime_get(), ktime); 899 ktime = ktime_sub(ktime, comparetime); 900 ktime = ktime_sub(ktime, filltime); 901 runtime = ktime_to_us(ktime); 902 903 ret = 0; 904 kfree(dma_pq); 905 err_srcs_array: 906 kfree(srcs); 907 err_dst: 908 dmatest_free_test_data(dst); 909 err_src: 910 dmatest_free_test_data(src); 911 err_free_coefs: 912 kfree(pq_coefs); 913 err_thread_type: 914 iops = dmatest_persec(runtime, total_tests); 915 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n", 916 current->comm, total_tests, failed_tests, 917 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops), 918 dmatest_KBs(runtime, total_len), ret); 919 920 /* terminate all transfers on specified channels */ 921 if (ret || failed_tests) 922 dmaengine_terminate_sync(chan); 923 924 thread->done = true; 925 wake_up(&thread_wait); 926 927 return ret; 928 } 929 930 static void dmatest_cleanup_channel(struct dmatest_chan *dtc) 931 { 932 struct dmatest_thread *thread; 933 struct dmatest_thread *_thread; 934 int ret; 935 936 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { 937 ret = kthread_stop(thread->task); 938 pr_debug("thread %s exited with status %d\n", 939 thread->task->comm, ret); 940 list_del(&thread->node); 941 put_task_struct(thread->task); 942 kfree(thread); 943 } 944 945 /* terminate all transfers on specified channels */ 946 dmaengine_terminate_sync(dtc->chan); 947 948 kfree(dtc); 949 } 950 951 static int dmatest_add_threads(struct dmatest_info *info, 952 struct dmatest_chan *dtc, enum dma_transaction_type type) 953 { 954 struct dmatest_params *params = &info->params; 955 struct dmatest_thread *thread; 956 struct dma_chan *chan = dtc->chan; 957 char *op; 958 unsigned int i; 959 960 if (type == DMA_MEMCPY) 961 op = "copy"; 962 else if (type == DMA_MEMSET) 963 op = "set"; 964 else if (type == DMA_XOR) 965 op = "xor"; 966 else if (type == DMA_PQ) 967 op = "pq"; 968 else 969 return -EINVAL; 970 971 for (i = 0; i < params->threads_per_chan; i++) { 972 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); 973 if (!thread) { 974 pr_warn("No memory for %s-%s%u\n", 975 dma_chan_name(chan), op, i); 976 break; 977 } 978 thread->info = info; 979 thread->chan = dtc->chan; 980 thread->type = type; 981 thread->test_done.wait = &thread->done_wait; 982 init_waitqueue_head(&thread->done_wait); 983 smp_wmb(); 984 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", 985 dma_chan_name(chan), op, i); 986 if (IS_ERR(thread->task)) { 987 pr_warn("Failed to create thread %s-%s%u\n", 988 dma_chan_name(chan), op, i); 989 kfree(thread); 990 break; 991 } 992 993 /* srcbuf and dstbuf are allocated by the thread itself */ 994 get_task_struct(thread->task); 995 list_add_tail(&thread->node, &dtc->threads); 996 thread->pending = true; 997 } 998 999 return i; 1000 } 1001 1002 static int dmatest_add_channel(struct dmatest_info *info, 1003 struct dma_chan *chan) 1004 { 1005 struct dmatest_chan *dtc; 1006 struct dma_device *dma_dev = chan->device; 1007 unsigned int thread_count = 0; 1008 int cnt; 1009 1010 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); 1011 if (!dtc) { 1012 pr_warn("No memory for %s\n", dma_chan_name(chan)); 1013 return -ENOMEM; 1014 } 1015 1016 dtc->chan = chan; 1017 INIT_LIST_HEAD(&dtc->threads); 1018 1019 if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) && 1020 info->params.polled) { 1021 info->params.polled = false; 1022 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n"); 1023 } 1024 1025 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { 1026 if (dmatest == 0) { 1027 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); 1028 thread_count += cnt > 0 ? cnt : 0; 1029 } 1030 } 1031 1032 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { 1033 if (dmatest == 1) { 1034 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET); 1035 thread_count += cnt > 0 ? cnt : 0; 1036 } 1037 } 1038 1039 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { 1040 cnt = dmatest_add_threads(info, dtc, DMA_XOR); 1041 thread_count += cnt > 0 ? cnt : 0; 1042 } 1043 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { 1044 cnt = dmatest_add_threads(info, dtc, DMA_PQ); 1045 thread_count += cnt > 0 ? cnt : 0; 1046 } 1047 1048 pr_info("Added %u threads using %s\n", 1049 thread_count, dma_chan_name(chan)); 1050 1051 list_add_tail(&dtc->node, &info->channels); 1052 info->nr_channels++; 1053 1054 return 0; 1055 } 1056 1057 static bool filter(struct dma_chan *chan, void *param) 1058 { 1059 struct dmatest_params *params = param; 1060 1061 if (!dmatest_match_channel(params, chan) || 1062 !dmatest_match_device(params, chan->device)) 1063 return false; 1064 else 1065 return true; 1066 } 1067 1068 static void request_channels(struct dmatest_info *info, 1069 enum dma_transaction_type type) 1070 { 1071 dma_cap_mask_t mask; 1072 1073 dma_cap_zero(mask); 1074 dma_cap_set(type, mask); 1075 for (;;) { 1076 struct dmatest_params *params = &info->params; 1077 struct dma_chan *chan; 1078 1079 chan = dma_request_channel(mask, filter, params); 1080 if (chan) { 1081 if (dmatest_add_channel(info, chan)) { 1082 dma_release_channel(chan); 1083 break; /* add_channel failed, punt */ 1084 } 1085 } else 1086 break; /* no more channels available */ 1087 if (params->max_channels && 1088 info->nr_channels >= params->max_channels) 1089 break; /* we have all we need */ 1090 } 1091 } 1092 1093 static void add_threaded_test(struct dmatest_info *info) 1094 { 1095 struct dmatest_params *params = &info->params; 1096 1097 /* Copy test parameters */ 1098 params->buf_size = test_buf_size; 1099 strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); 1100 strlcpy(params->device, strim(test_device), sizeof(params->device)); 1101 params->threads_per_chan = threads_per_chan; 1102 params->max_channels = max_channels; 1103 params->iterations = iterations; 1104 params->xor_sources = xor_sources; 1105 params->pq_sources = pq_sources; 1106 params->timeout = timeout; 1107 params->noverify = noverify; 1108 params->norandom = norandom; 1109 params->alignment = alignment; 1110 params->transfer_size = transfer_size; 1111 params->polled = polled; 1112 1113 request_channels(info, DMA_MEMCPY); 1114 request_channels(info, DMA_MEMSET); 1115 request_channels(info, DMA_XOR); 1116 request_channels(info, DMA_PQ); 1117 } 1118 1119 static void run_pending_tests(struct dmatest_info *info) 1120 { 1121 struct dmatest_chan *dtc; 1122 unsigned int thread_count = 0; 1123 1124 list_for_each_entry(dtc, &info->channels, node) { 1125 struct dmatest_thread *thread; 1126 1127 thread_count = 0; 1128 list_for_each_entry(thread, &dtc->threads, node) { 1129 wake_up_process(thread->task); 1130 thread_count++; 1131 } 1132 pr_info("Started %u threads using %s\n", 1133 thread_count, dma_chan_name(dtc->chan)); 1134 } 1135 } 1136 1137 static void stop_threaded_test(struct dmatest_info *info) 1138 { 1139 struct dmatest_chan *dtc, *_dtc; 1140 struct dma_chan *chan; 1141 1142 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { 1143 list_del(&dtc->node); 1144 chan = dtc->chan; 1145 dmatest_cleanup_channel(dtc); 1146 pr_debug("dropped channel %s\n", dma_chan_name(chan)); 1147 dma_release_channel(chan); 1148 } 1149 1150 info->nr_channels = 0; 1151 } 1152 1153 static void start_threaded_tests(struct dmatest_info *info) 1154 { 1155 /* we might be called early to set run=, defer running until all 1156 * parameters have been evaluated 1157 */ 1158 if (!info->did_init) 1159 return; 1160 1161 run_pending_tests(info); 1162 } 1163 1164 static int dmatest_run_get(char *val, const struct kernel_param *kp) 1165 { 1166 struct dmatest_info *info = &test_info; 1167 1168 mutex_lock(&info->lock); 1169 if (is_threaded_test_run(info)) { 1170 dmatest_run = true; 1171 } else { 1172 if (!is_threaded_test_pending(info)) 1173 stop_threaded_test(info); 1174 dmatest_run = false; 1175 } 1176 mutex_unlock(&info->lock); 1177 1178 return param_get_bool(val, kp); 1179 } 1180 1181 static int dmatest_run_set(const char *val, const struct kernel_param *kp) 1182 { 1183 struct dmatest_info *info = &test_info; 1184 int ret; 1185 1186 mutex_lock(&info->lock); 1187 ret = param_set_bool(val, kp); 1188 if (ret) { 1189 mutex_unlock(&info->lock); 1190 return ret; 1191 } else if (dmatest_run) { 1192 if (!is_threaded_test_pending(info)) { 1193 pr_info("No channels configured, continue with any\n"); 1194 if (!is_threaded_test_run(info)) 1195 stop_threaded_test(info); 1196 add_threaded_test(info); 1197 } 1198 start_threaded_tests(info); 1199 } else { 1200 stop_threaded_test(info); 1201 } 1202 1203 mutex_unlock(&info->lock); 1204 1205 return ret; 1206 } 1207 1208 static int dmatest_chan_set(const char *val, const struct kernel_param *kp) 1209 { 1210 struct dmatest_info *info = &test_info; 1211 struct dmatest_chan *dtc; 1212 char chan_reset_val[20]; 1213 int ret = 0; 1214 1215 mutex_lock(&info->lock); 1216 ret = param_set_copystring(val, kp); 1217 if (ret) { 1218 mutex_unlock(&info->lock); 1219 return ret; 1220 } 1221 /*Clear any previously run threads */ 1222 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) 1223 stop_threaded_test(info); 1224 /* Reject channels that are already registered */ 1225 if (is_threaded_test_pending(info)) { 1226 list_for_each_entry(dtc, &info->channels, node) { 1227 if (strcmp(dma_chan_name(dtc->chan), 1228 strim(test_channel)) == 0) { 1229 dtc = list_last_entry(&info->channels, 1230 struct dmatest_chan, 1231 node); 1232 strlcpy(chan_reset_val, 1233 dma_chan_name(dtc->chan), 1234 sizeof(chan_reset_val)); 1235 ret = -EBUSY; 1236 goto add_chan_err; 1237 } 1238 } 1239 } 1240 1241 add_threaded_test(info); 1242 1243 /* Check if channel was added successfully */ 1244 dtc = list_last_entry(&info->channels, struct dmatest_chan, node); 1245 1246 if (dtc->chan) { 1247 /* 1248 * if new channel was not successfully added, revert the 1249 * "test_channel" string to the name of the last successfully 1250 * added channel. exception for when users issues empty string 1251 * to channel parameter. 1252 */ 1253 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0) 1254 && (strcmp("", strim(test_channel)) != 0)) { 1255 ret = -EINVAL; 1256 strlcpy(chan_reset_val, dma_chan_name(dtc->chan), 1257 sizeof(chan_reset_val)); 1258 goto add_chan_err; 1259 } 1260 1261 } else { 1262 /* Clear test_channel if no channels were added successfully */ 1263 strlcpy(chan_reset_val, "", sizeof(chan_reset_val)); 1264 ret = -EBUSY; 1265 goto add_chan_err; 1266 } 1267 1268 mutex_unlock(&info->lock); 1269 1270 return ret; 1271 1272 add_chan_err: 1273 param_set_copystring(chan_reset_val, kp); 1274 mutex_unlock(&info->lock); 1275 1276 return ret; 1277 } 1278 1279 static int dmatest_chan_get(char *val, const struct kernel_param *kp) 1280 { 1281 struct dmatest_info *info = &test_info; 1282 1283 mutex_lock(&info->lock); 1284 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) { 1285 stop_threaded_test(info); 1286 strlcpy(test_channel, "", sizeof(test_channel)); 1287 } 1288 mutex_unlock(&info->lock); 1289 1290 return param_get_string(val, kp); 1291 } 1292 1293 static int dmatest_test_list_get(char *val, const struct kernel_param *kp) 1294 { 1295 struct dmatest_info *info = &test_info; 1296 struct dmatest_chan *dtc; 1297 unsigned int thread_count = 0; 1298 1299 list_for_each_entry(dtc, &info->channels, node) { 1300 struct dmatest_thread *thread; 1301 1302 thread_count = 0; 1303 list_for_each_entry(thread, &dtc->threads, node) { 1304 thread_count++; 1305 } 1306 pr_info("%u threads using %s\n", 1307 thread_count, dma_chan_name(dtc->chan)); 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int __init dmatest_init(void) 1314 { 1315 struct dmatest_info *info = &test_info; 1316 struct dmatest_params *params = &info->params; 1317 1318 if (dmatest_run) { 1319 mutex_lock(&info->lock); 1320 add_threaded_test(info); 1321 run_pending_tests(info); 1322 mutex_unlock(&info->lock); 1323 } 1324 1325 if (params->iterations && wait) 1326 wait_event(thread_wait, !is_threaded_test_run(info)); 1327 1328 /* module parameters are stable, inittime tests are started, 1329 * let userspace take over 'run' control 1330 */ 1331 info->did_init = true; 1332 1333 return 0; 1334 } 1335 /* when compiled-in wait for drivers to load first */ 1336 late_initcall(dmatest_init); 1337 1338 static void __exit dmatest_exit(void) 1339 { 1340 struct dmatest_info *info = &test_info; 1341 1342 mutex_lock(&info->lock); 1343 stop_threaded_test(info); 1344 mutex_unlock(&info->lock); 1345 } 1346 module_exit(dmatest_exit); 1347 1348 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1349 MODULE_LICENSE("GPL v2"); 1350