1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2010 Google, Inc.
4  *
5  * Author:
6  *	Colin Cross <[email protected]>
7  */
8 
9 #define pr_fmt(fmt)	"tegra-timer: " fmt
10 
11 #include <linux/clk.h>
12 #include <linux/clockchips.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/percpu.h>
21 #include <linux/sched_clock.h>
22 #include <linux/time.h>
23 
24 #include "timer-of.h"
25 
26 #define RTC_SECONDS		0x08
27 #define RTC_SHADOW_SECONDS	0x0c
28 #define RTC_MILLISECONDS	0x10
29 
30 #define TIMERUS_CNTR_1US	0x10
31 #define TIMERUS_USEC_CFG	0x14
32 #define TIMERUS_CNTR_FREEZE	0x4c
33 
34 #define TIMER_PTV		0x0
35 #define TIMER_PTV_EN		BIT(31)
36 #define TIMER_PTV_PER		BIT(30)
37 #define TIMER_PCR		0x4
38 #define TIMER_PCR_INTR_CLR	BIT(30)
39 
40 #define TIMER1_BASE		0x00
41 #define TIMER2_BASE		0x08
42 #define TIMER3_BASE		0x50
43 #define TIMER4_BASE		0x58
44 #define TIMER10_BASE		0x90
45 
46 #define TIMER1_IRQ_IDX		0
47 #define TIMER10_IRQ_IDX		10
48 
49 #define TIMER_1MHz		1000000
50 
51 static u32 usec_config;
52 static void __iomem *timer_reg_base;
53 
54 static int tegra_timer_set_next_event(unsigned long cycles,
55 				      struct clock_event_device *evt)
56 {
57 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
58 
59 	writel_relaxed(TIMER_PTV_EN |
60 		       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
61 		       reg_base + TIMER_PTV);
62 
63 	return 0;
64 }
65 
66 static int tegra_timer_shutdown(struct clock_event_device *evt)
67 {
68 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
69 
70 	writel_relaxed(0, reg_base + TIMER_PTV);
71 
72 	return 0;
73 }
74 
75 static int tegra_timer_set_periodic(struct clock_event_device *evt)
76 {
77 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
78 	unsigned long period = timer_of_period(to_timer_of(evt));
79 
80 	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
81 		       reg_base + TIMER_PTV);
82 
83 	return 0;
84 }
85 
86 static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
87 {
88 	struct clock_event_device *evt = dev_id;
89 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
90 
91 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
92 	evt->event_handler(evt);
93 
94 	return IRQ_HANDLED;
95 }
96 
97 static void tegra_timer_suspend(struct clock_event_device *evt)
98 {
99 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
100 
101 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
102 }
103 
104 static void tegra_timer_resume(struct clock_event_device *evt)
105 {
106 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
107 }
108 
109 static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
110 	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
111 
112 	.clkevt = {
113 		.name = "tegra_timer",
114 		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
115 		.set_next_event = tegra_timer_set_next_event,
116 		.set_state_shutdown = tegra_timer_shutdown,
117 		.set_state_periodic = tegra_timer_set_periodic,
118 		.set_state_oneshot = tegra_timer_shutdown,
119 		.tick_resume = tegra_timer_shutdown,
120 		.suspend = tegra_timer_suspend,
121 		.resume = tegra_timer_resume,
122 	},
123 };
124 
125 static int tegra_timer_setup(unsigned int cpu)
126 {
127 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
128 
129 	writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
130 	writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
131 
132 	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
133 	enable_irq(to->clkevt.irq);
134 
135 	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
136 					1, /* min */
137 					0x1fffffff); /* 29 bits */
138 
139 	return 0;
140 }
141 
142 static int tegra_timer_stop(unsigned int cpu)
143 {
144 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
145 
146 	to->clkevt.set_state_shutdown(&to->clkevt);
147 	disable_irq_nosync(to->clkevt.irq);
148 
149 	return 0;
150 }
151 
152 static u64 notrace tegra_read_sched_clock(void)
153 {
154 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
155 }
156 
157 #ifdef CONFIG_ARM
158 static unsigned long tegra_delay_timer_read_counter_long(void)
159 {
160 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
161 }
162 
163 static struct delay_timer tegra_delay_timer = {
164 	.read_current_timer = tegra_delay_timer_read_counter_long,
165 	.freq = TIMER_1MHz,
166 };
167 #endif
168 
169 static struct timer_of suspend_rtc_to = {
170 	.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
171 };
172 
173 /*
174  * tegra_rtc_read - Reads the Tegra RTC registers
175  * Care must be taken that this function is not called while the
176  * tegra_rtc driver could be executing to avoid race conditions
177  * on the RTC shadow register
178  */
179 static u64 tegra_rtc_read_ms(struct clocksource *cs)
180 {
181 	void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
182 
183 	u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
184 	u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
185 
186 	return (u64)s * MSEC_PER_SEC + ms;
187 }
188 
189 static struct clocksource suspend_rtc_clocksource = {
190 	.name	= "tegra_suspend_timer",
191 	.rating	= 200,
192 	.read	= tegra_rtc_read_ms,
193 	.mask	= CLOCKSOURCE_MASK(32),
194 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
195 };
196 
197 static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
198 {
199 	if (tegra20) {
200 		switch (cpu) {
201 		case 0:
202 			return TIMER1_BASE;
203 		case 1:
204 			return TIMER2_BASE;
205 		case 2:
206 			return TIMER3_BASE;
207 		default:
208 			return TIMER4_BASE;
209 		}
210 	}
211 
212 	return TIMER10_BASE + cpu * 8;
213 }
214 
215 static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
216 {
217 	if (tegra20)
218 		return TIMER1_IRQ_IDX + cpu;
219 
220 	return TIMER10_IRQ_IDX + cpu;
221 }
222 
223 static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
224 						 bool tegra20)
225 {
226 	/*
227 	 * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
228 	 * parent clock.
229 	 */
230 	if (tegra20)
231 		return TIMER_1MHz;
232 
233 	return timer_of_rate(to);
234 }
235 
236 static int __init tegra_init_timer(struct device_node *np, bool tegra20,
237 				   int rating)
238 {
239 	struct timer_of *to;
240 	int cpu, ret;
241 
242 	to = this_cpu_ptr(&tegra_to);
243 	ret = timer_of_init(np, to);
244 	if (ret)
245 		goto out;
246 
247 	timer_reg_base = timer_of_base(to);
248 
249 	/*
250 	 * Configure microsecond timers to have 1MHz clock
251 	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
252 	 * Uses n+1 scheme
253 	 */
254 	switch (timer_of_rate(to)) {
255 	case 12000000:
256 		usec_config = 0x000b; /* (11+1)/(0+1) */
257 		break;
258 	case 12800000:
259 		usec_config = 0x043f; /* (63+1)/(4+1) */
260 		break;
261 	case 13000000:
262 		usec_config = 0x000c; /* (12+1)/(0+1) */
263 		break;
264 	case 16800000:
265 		usec_config = 0x0453; /* (83+1)/(4+1) */
266 		break;
267 	case 19200000:
268 		usec_config = 0x045f; /* (95+1)/(4+1) */
269 		break;
270 	case 26000000:
271 		usec_config = 0x0019; /* (25+1)/(0+1) */
272 		break;
273 	case 38400000:
274 		usec_config = 0x04bf; /* (191+1)/(4+1) */
275 		break;
276 	case 48000000:
277 		usec_config = 0x002f; /* (47+1)/(0+1) */
278 		break;
279 	default:
280 		ret = -EINVAL;
281 		goto out;
282 	}
283 
284 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
285 
286 	for_each_possible_cpu(cpu) {
287 		struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
288 		unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
289 		unsigned long rate = tegra_rate_for_timer(to, tegra20);
290 		unsigned int base = tegra_base_for_cpu(cpu, tegra20);
291 		unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
292 		unsigned int irq = irq_of_parse_and_map(np, idx);
293 
294 		if (!irq) {
295 			pr_err("failed to map irq for cpu%d\n", cpu);
296 			ret = -EINVAL;
297 			goto out_irq;
298 		}
299 
300 		cpu_to->clkevt.irq = irq;
301 		cpu_to->clkevt.rating = rating;
302 		cpu_to->clkevt.cpumask = cpumask_of(cpu);
303 		cpu_to->of_base.base = timer_reg_base + base;
304 		cpu_to->of_clk.period = rate / HZ;
305 		cpu_to->of_clk.rate = rate;
306 
307 		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
308 
309 		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
310 				  cpu_to->clkevt.name, &cpu_to->clkevt);
311 		if (ret) {
312 			pr_err("failed to set up irq for cpu%d: %d\n",
313 			       cpu, ret);
314 			irq_dispose_mapping(cpu_to->clkevt.irq);
315 			cpu_to->clkevt.irq = 0;
316 			goto out_irq;
317 		}
318 	}
319 
320 	sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
321 
322 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
323 				    "timer_us", TIMER_1MHz, 300, 32,
324 				    clocksource_mmio_readl_up);
325 	if (ret)
326 		pr_err("failed to register clocksource: %d\n", ret);
327 
328 #ifdef CONFIG_ARM
329 	register_current_timer_delay(&tegra_delay_timer);
330 #endif
331 
332 	ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
333 				"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
334 				tegra_timer_stop);
335 	if (ret)
336 		pr_err("failed to set up cpu hp state: %d\n", ret);
337 
338 	return ret;
339 
340 out_irq:
341 	for_each_possible_cpu(cpu) {
342 		struct timer_of *cpu_to;
343 
344 		cpu_to = per_cpu_ptr(&tegra_to, cpu);
345 		if (cpu_to->clkevt.irq) {
346 			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
347 			irq_dispose_mapping(cpu_to->clkevt.irq);
348 		}
349 	}
350 
351 	to->of_base.base = timer_reg_base;
352 out:
353 	timer_of_cleanup(to);
354 
355 	return ret;
356 }
357 
358 static int __init tegra210_init_timer(struct device_node *np)
359 {
360 	/*
361 	 * Arch-timer can't survive across power cycle of CPU core and
362 	 * after CPUPORESET signal due to a system design shortcoming,
363 	 * hence tegra-timer is more preferable on Tegra210.
364 	 */
365 	return tegra_init_timer(np, false, 460);
366 }
367 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
368 
369 static int __init tegra20_init_timer(struct device_node *np)
370 {
371 	int rating;
372 
373 	/*
374 	 * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
375 	 * that timer runs off the CPU clock and hence is subjected to
376 	 * a jitter caused by DVFS clock rate changes. Tegra-timer is
377 	 * more preferable for older Tegra's, while later SoC generations
378 	 * have arch-timer as a main per-CPU timer and it is not affected
379 	 * by DVFS changes.
380 	 */
381 	if (of_machine_is_compatible("nvidia,tegra20") ||
382 	    of_machine_is_compatible("nvidia,tegra30"))
383 		rating = 460;
384 	else
385 		rating = 330;
386 
387 	return tegra_init_timer(np, true, rating);
388 }
389 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
390 
391 static int __init tegra20_init_rtc(struct device_node *np)
392 {
393 	int ret;
394 
395 	ret = timer_of_init(np, &suspend_rtc_to);
396 	if (ret)
397 		return ret;
398 
399 	return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
400 }
401 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
402