1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2010 Google, Inc.
4  *
5  * Author:
6  *	Colin Cross <[email protected]>
7  */
8 
9 #define pr_fmt(fmt)	"tegra-timer: " fmt
10 
11 #include <linux/clk.h>
12 #include <linux/clockchips.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/percpu.h>
21 #include <linux/sched_clock.h>
22 #include <linux/time.h>
23 
24 #include "timer-of.h"
25 
26 #define RTC_SECONDS		0x08
27 #define RTC_SHADOW_SECONDS	0x0c
28 #define RTC_MILLISECONDS	0x10
29 
30 #define TIMERUS_CNTR_1US	0x10
31 #define TIMERUS_USEC_CFG	0x14
32 #define TIMERUS_CNTR_FREEZE	0x4c
33 
34 #define TIMER_PTV		0x0
35 #define TIMER_PTV_EN		BIT(31)
36 #define TIMER_PTV_PER		BIT(30)
37 #define TIMER_PCR		0x4
38 #define TIMER_PCR_INTR_CLR	BIT(30)
39 
40 #define TIMER1_BASE		0x00
41 #define TIMER2_BASE		0x08
42 #define TIMER3_BASE		0x50
43 #define TIMER4_BASE		0x58
44 #define TIMER10_BASE		0x90
45 
46 #define TIMER1_IRQ_IDX		0
47 #define TIMER10_IRQ_IDX		10
48 
49 static u32 usec_config;
50 static void __iomem *timer_reg_base;
51 
52 static int tegra_timer_set_next_event(unsigned long cycles,
53 				      struct clock_event_device *evt)
54 {
55 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
56 
57 	writel_relaxed(TIMER_PTV_EN |
58 		       ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
59 		       reg_base + TIMER_PTV);
60 
61 	return 0;
62 }
63 
64 static int tegra_timer_shutdown(struct clock_event_device *evt)
65 {
66 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
67 
68 	writel_relaxed(0, reg_base + TIMER_PTV);
69 
70 	return 0;
71 }
72 
73 static int tegra_timer_set_periodic(struct clock_event_device *evt)
74 {
75 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
76 	unsigned long period = timer_of_period(to_timer_of(evt));
77 
78 	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
79 		       reg_base + TIMER_PTV);
80 
81 	return 0;
82 }
83 
84 static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
85 {
86 	struct clock_event_device *evt = dev_id;
87 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
88 
89 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
90 	evt->event_handler(evt);
91 
92 	return IRQ_HANDLED;
93 }
94 
95 static void tegra_timer_suspend(struct clock_event_device *evt)
96 {
97 	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
98 
99 	writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
100 }
101 
102 static void tegra_timer_resume(struct clock_event_device *evt)
103 {
104 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
105 }
106 
107 static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
108 	.flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
109 
110 	.clkevt = {
111 		.name = "tegra_timer",
112 		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
113 		.set_next_event = tegra_timer_set_next_event,
114 		.set_state_shutdown = tegra_timer_shutdown,
115 		.set_state_periodic = tegra_timer_set_periodic,
116 		.set_state_oneshot = tegra_timer_shutdown,
117 		.tick_resume = tegra_timer_shutdown,
118 		.suspend = tegra_timer_suspend,
119 		.resume = tegra_timer_resume,
120 	},
121 };
122 
123 static int tegra_timer_setup(unsigned int cpu)
124 {
125 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
126 
127 	writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
128 	writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
129 
130 	irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
131 	enable_irq(to->clkevt.irq);
132 
133 	clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
134 					1, /* min */
135 					0x1fffffff); /* 29 bits */
136 
137 	return 0;
138 }
139 
140 static int tegra_timer_stop(unsigned int cpu)
141 {
142 	struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
143 
144 	to->clkevt.set_state_shutdown(&to->clkevt);
145 	disable_irq_nosync(to->clkevt.irq);
146 
147 	return 0;
148 }
149 
150 static u64 notrace tegra_read_sched_clock(void)
151 {
152 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
153 }
154 
155 #ifdef CONFIG_ARM
156 static unsigned long tegra_delay_timer_read_counter_long(void)
157 {
158 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
159 }
160 
161 static struct delay_timer tegra_delay_timer = {
162 	.read_current_timer = tegra_delay_timer_read_counter_long,
163 	.freq = 1000000,
164 };
165 #endif
166 
167 static struct timer_of suspend_rtc_to = {
168 	.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
169 };
170 
171 /*
172  * tegra_rtc_read - Reads the Tegra RTC registers
173  * Care must be taken that this function is not called while the
174  * tegra_rtc driver could be executing to avoid race conditions
175  * on the RTC shadow register
176  */
177 static u64 tegra_rtc_read_ms(struct clocksource *cs)
178 {
179 	void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
180 
181 	u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
182 	u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
183 
184 	return (u64)s * MSEC_PER_SEC + ms;
185 }
186 
187 static struct clocksource suspend_rtc_clocksource = {
188 	.name	= "tegra_suspend_timer",
189 	.rating	= 200,
190 	.read	= tegra_rtc_read_ms,
191 	.mask	= CLOCKSOURCE_MASK(32),
192 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
193 };
194 
195 static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
196 {
197 	if (tegra20) {
198 		switch (cpu) {
199 		case 0:
200 			return TIMER1_BASE;
201 		case 1:
202 			return TIMER2_BASE;
203 		case 2:
204 			return TIMER3_BASE;
205 		default:
206 			return TIMER4_BASE;
207 		}
208 	}
209 
210 	return TIMER10_BASE + cpu * 8;
211 }
212 
213 static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
214 {
215 	if (tegra20)
216 		return TIMER1_IRQ_IDX + cpu;
217 
218 	return TIMER10_IRQ_IDX + cpu;
219 }
220 
221 static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
222 						 bool tegra20)
223 {
224 	/*
225 	 * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
226 	 * parent clock.
227 	 */
228 	if (tegra20)
229 		return 1000000;
230 
231 	return timer_of_rate(to);
232 }
233 
234 static int __init tegra_init_timer(struct device_node *np, bool tegra20,
235 				   int rating)
236 {
237 	struct timer_of *to;
238 	int cpu, ret;
239 
240 	to = this_cpu_ptr(&tegra_to);
241 	ret = timer_of_init(np, to);
242 	if (ret)
243 		goto out;
244 
245 	timer_reg_base = timer_of_base(to);
246 
247 	/*
248 	 * Configure microsecond timers to have 1MHz clock
249 	 * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
250 	 * Uses n+1 scheme
251 	 */
252 	switch (timer_of_rate(to)) {
253 	case 12000000:
254 		usec_config = 0x000b; /* (11+1)/(0+1) */
255 		break;
256 	case 12800000:
257 		usec_config = 0x043f; /* (63+1)/(4+1) */
258 		break;
259 	case 13000000:
260 		usec_config = 0x000c; /* (12+1)/(0+1) */
261 		break;
262 	case 16800000:
263 		usec_config = 0x0453; /* (83+1)/(4+1) */
264 		break;
265 	case 19200000:
266 		usec_config = 0x045f; /* (95+1)/(4+1) */
267 		break;
268 	case 26000000:
269 		usec_config = 0x0019; /* (25+1)/(0+1) */
270 		break;
271 	case 38400000:
272 		usec_config = 0x04bf; /* (191+1)/(4+1) */
273 		break;
274 	case 48000000:
275 		usec_config = 0x002f; /* (47+1)/(0+1) */
276 		break;
277 	default:
278 		ret = -EINVAL;
279 		goto out;
280 	}
281 
282 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
283 
284 	for_each_possible_cpu(cpu) {
285 		struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
286 		unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
287 		unsigned long rate = tegra_rate_for_timer(to, tegra20);
288 		unsigned int base = tegra_base_for_cpu(cpu, tegra20);
289 		unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
290 		unsigned int irq = irq_of_parse_and_map(np, idx);
291 
292 		if (!irq) {
293 			pr_err("failed to map irq for cpu%d\n", cpu);
294 			ret = -EINVAL;
295 			goto out_irq;
296 		}
297 
298 		cpu_to->clkevt.irq = irq;
299 		cpu_to->clkevt.rating = rating;
300 		cpu_to->clkevt.cpumask = cpumask_of(cpu);
301 		cpu_to->of_base.base = timer_reg_base + base;
302 		cpu_to->of_clk.period = rate / HZ;
303 		cpu_to->of_clk.rate = rate;
304 
305 		irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
306 
307 		ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
308 				  cpu_to->clkevt.name, &cpu_to->clkevt);
309 		if (ret) {
310 			pr_err("failed to set up irq for cpu%d: %d\n",
311 			       cpu, ret);
312 			irq_dispose_mapping(cpu_to->clkevt.irq);
313 			cpu_to->clkevt.irq = 0;
314 			goto out_irq;
315 		}
316 	}
317 
318 	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
319 
320 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
321 				    "timer_us", 1000000,
322 				    300, 32, clocksource_mmio_readl_up);
323 	if (ret)
324 		pr_err("failed to register clocksource: %d\n", ret);
325 
326 #ifdef CONFIG_ARM
327 	register_current_timer_delay(&tegra_delay_timer);
328 #endif
329 
330 	ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
331 				"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
332 				tegra_timer_stop);
333 	if (ret)
334 		pr_err("failed to set up cpu hp state: %d\n", ret);
335 
336 	return ret;
337 
338 out_irq:
339 	for_each_possible_cpu(cpu) {
340 		struct timer_of *cpu_to;
341 
342 		cpu_to = per_cpu_ptr(&tegra_to, cpu);
343 		if (cpu_to->clkevt.irq) {
344 			free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
345 			irq_dispose_mapping(cpu_to->clkevt.irq);
346 		}
347 	}
348 out:
349 	timer_of_cleanup(to);
350 
351 	return ret;
352 }
353 
354 static int __init tegra210_init_timer(struct device_node *np)
355 {
356 	/*
357 	 * Arch-timer can't survive across power cycle of CPU core and
358 	 * after CPUPORESET signal due to a system design shortcoming,
359 	 * hence tegra-timer is more preferable on Tegra210.
360 	 */
361 	return tegra_init_timer(np, false, 460);
362 }
363 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
364 
365 static int __init tegra20_init_timer(struct device_node *np)
366 {
367 	int rating;
368 
369 	/*
370 	 * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
371 	 * that timer runs off the CPU clock and hence is subjected to
372 	 * a jitter caused by DVFS clock rate changes. Tegra-timer is
373 	 * more preferable for older Tegra's, while later SoC generations
374 	 * have arch-timer as a main per-CPU timer and it is not affected
375 	 * by DVFS changes.
376 	 */
377 	if (of_machine_is_compatible("nvidia,tegra20") ||
378 	    of_machine_is_compatible("nvidia,tegra30"))
379 		rating = 460;
380 	else
381 		rating = 330;
382 
383 	return tegra_init_timer(np, true, rating);
384 }
385 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
386 
387 static int __init tegra20_init_rtc(struct device_node *np)
388 {
389 	int ret;
390 
391 	ret = timer_of_init(np, &suspend_rtc_to);
392 	if (ret)
393 		return ret;
394 
395 	return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
396 }
397 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
398