1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/cpu_pm.h> 10 #include <linux/delay.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/slab.h> 20 #include <linux/sys_soc.h> 21 #include <linux/timekeeping.h> 22 #include <linux/iopoll.h> 23 24 #include <linux/platform_data/ti-sysc.h> 25 26 #include <dt-bindings/bus/ti-sysc.h> 27 28 #define DIS_ISP BIT(2) 29 #define DIS_IVA BIT(1) 30 #define DIS_SGX BIT(0) 31 32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 33 34 #define MAX_MODULE_SOFTRESET_WAIT 10000 35 36 enum sysc_soc { 37 SOC_UNKNOWN, 38 SOC_2420, 39 SOC_2430, 40 SOC_3430, 41 SOC_AM35, 42 SOC_3630, 43 SOC_4430, 44 SOC_4460, 45 SOC_4470, 46 SOC_5430, 47 SOC_AM3, 48 SOC_AM4, 49 SOC_DRA7, 50 }; 51 52 struct sysc_address { 53 unsigned long base; 54 struct list_head node; 55 }; 56 57 struct sysc_module { 58 struct sysc *ddata; 59 struct list_head node; 60 }; 61 62 struct sysc_soc_info { 63 unsigned long general_purpose:1; 64 enum sysc_soc soc; 65 struct mutex list_lock; /* disabled and restored modules list lock */ 66 struct list_head disabled_modules; 67 struct list_head restored_modules; 68 struct notifier_block nb; 69 }; 70 71 enum sysc_clocks { 72 SYSC_FCK, 73 SYSC_ICK, 74 SYSC_OPTFCK0, 75 SYSC_OPTFCK1, 76 SYSC_OPTFCK2, 77 SYSC_OPTFCK3, 78 SYSC_OPTFCK4, 79 SYSC_OPTFCK5, 80 SYSC_OPTFCK6, 81 SYSC_OPTFCK7, 82 SYSC_MAX_CLOCKS, 83 }; 84 85 static struct sysc_soc_info *sysc_soc; 86 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 87 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 88 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 89 "opt5", "opt6", "opt7", 90 }; 91 92 #define SYSC_IDLEMODE_MASK 3 93 #define SYSC_CLOCKACTIVITY_MASK 3 94 95 /** 96 * struct sysc - TI sysc interconnect target module registers and capabilities 97 * @dev: struct device pointer 98 * @module_pa: physical address of the interconnect target module 99 * @module_size: size of the interconnect target module 100 * @module_va: virtual address of the interconnect target module 101 * @offsets: register offsets from module base 102 * @mdata: ti-sysc to hwmod translation data for a module 103 * @clocks: clocks used by the interconnect target module 104 * @clock_roles: clock role names for the found clocks 105 * @nr_clocks: number of clocks used by the interconnect target module 106 * @rsts: resets used by the interconnect target module 107 * @legacy_mode: configured for legacy mode if set 108 * @cap: interconnect target module capabilities 109 * @cfg: interconnect target module configuration 110 * @cookie: data used by legacy platform callbacks 111 * @name: name if available 112 * @revision: interconnect target module revision 113 * @sysconfig: saved sysconfig register value 114 * @reserved: target module is reserved and already in use 115 * @enabled: sysc runtime enabled status 116 * @needs_resume: runtime resume needed on resume from suspend 117 * @child_needs_resume: runtime resume needed for child on resume from suspend 118 * @disable_on_idle: status flag used for disabling modules with resets 119 * @idle_work: work structure used to perform delayed idle on a module 120 * @pre_reset_quirk: module specific pre-reset quirk 121 * @post_reset_quirk: module specific post-reset quirk 122 * @reset_done_quirk: module specific reset done quirk 123 * @module_enable_quirk: module specific enable quirk 124 * @module_disable_quirk: module specific disable quirk 125 * @module_unlock_quirk: module specific sysconfig unlock quirk 126 * @module_lock_quirk: module specific sysconfig lock quirk 127 */ 128 struct sysc { 129 struct device *dev; 130 u64 module_pa; 131 u32 module_size; 132 void __iomem *module_va; 133 int offsets[SYSC_MAX_REGS]; 134 struct ti_sysc_module_data *mdata; 135 struct clk **clocks; 136 const char **clock_roles; 137 int nr_clocks; 138 struct reset_control *rsts; 139 const char *legacy_mode; 140 const struct sysc_capabilities *cap; 141 struct sysc_config cfg; 142 struct ti_sysc_cookie cookie; 143 const char *name; 144 u32 revision; 145 u32 sysconfig; 146 unsigned int reserved:1; 147 unsigned int enabled:1; 148 unsigned int needs_resume:1; 149 unsigned int child_needs_resume:1; 150 struct delayed_work idle_work; 151 void (*pre_reset_quirk)(struct sysc *sysc); 152 void (*post_reset_quirk)(struct sysc *sysc); 153 void (*reset_done_quirk)(struct sysc *sysc); 154 void (*module_enable_quirk)(struct sysc *sysc); 155 void (*module_disable_quirk)(struct sysc *sysc); 156 void (*module_unlock_quirk)(struct sysc *sysc); 157 void (*module_lock_quirk)(struct sysc *sysc); 158 }; 159 160 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 161 bool is_child); 162 static int sysc_reset(struct sysc *ddata); 163 164 static void sysc_write(struct sysc *ddata, int offset, u32 value) 165 { 166 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 167 writew_relaxed(value & 0xffff, ddata->module_va + offset); 168 169 /* Only i2c revision has LO and HI register with stride of 4 */ 170 if (ddata->offsets[SYSC_REVISION] >= 0 && 171 offset == ddata->offsets[SYSC_REVISION]) { 172 u16 hi = value >> 16; 173 174 writew_relaxed(hi, ddata->module_va + offset + 4); 175 } 176 177 return; 178 } 179 180 writel_relaxed(value, ddata->module_va + offset); 181 } 182 183 static u32 sysc_read(struct sysc *ddata, int offset) 184 { 185 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 186 u32 val; 187 188 val = readw_relaxed(ddata->module_va + offset); 189 190 /* Only i2c revision has LO and HI register with stride of 4 */ 191 if (ddata->offsets[SYSC_REVISION] >= 0 && 192 offset == ddata->offsets[SYSC_REVISION]) { 193 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 194 195 val |= tmp << 16; 196 } 197 198 return val; 199 } 200 201 return readl_relaxed(ddata->module_va + offset); 202 } 203 204 static bool sysc_opt_clks_needed(struct sysc *ddata) 205 { 206 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 207 } 208 209 static u32 sysc_read_revision(struct sysc *ddata) 210 { 211 int offset = ddata->offsets[SYSC_REVISION]; 212 213 if (offset < 0) 214 return 0; 215 216 return sysc_read(ddata, offset); 217 } 218 219 static u32 sysc_read_sysconfig(struct sysc *ddata) 220 { 221 int offset = ddata->offsets[SYSC_SYSCONFIG]; 222 223 if (offset < 0) 224 return 0; 225 226 return sysc_read(ddata, offset); 227 } 228 229 static u32 sysc_read_sysstatus(struct sysc *ddata) 230 { 231 int offset = ddata->offsets[SYSC_SYSSTATUS]; 232 233 if (offset < 0) 234 return 0; 235 236 return sysc_read(ddata, offset); 237 } 238 239 static int sysc_poll_reset_sysstatus(struct sysc *ddata) 240 { 241 int error, retries; 242 u32 syss_done, rstval; 243 244 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 245 syss_done = 0; 246 else 247 syss_done = ddata->cfg.syss_mask; 248 249 if (likely(!timekeeping_suspended)) { 250 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 251 rstval, (rstval & ddata->cfg.syss_mask) == 252 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 253 } else { 254 retries = MAX_MODULE_SOFTRESET_WAIT; 255 while (retries--) { 256 rstval = sysc_read_sysstatus(ddata); 257 if ((rstval & ddata->cfg.syss_mask) == syss_done) 258 return 0; 259 udelay(2); /* Account for udelay flakeyness */ 260 } 261 error = -ETIMEDOUT; 262 } 263 264 return error; 265 } 266 267 static int sysc_poll_reset_sysconfig(struct sysc *ddata) 268 { 269 int error, retries; 270 u32 sysc_mask, rstval; 271 272 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 273 274 if (likely(!timekeeping_suspended)) { 275 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 276 rstval, !(rstval & sysc_mask), 277 100, MAX_MODULE_SOFTRESET_WAIT); 278 } else { 279 retries = MAX_MODULE_SOFTRESET_WAIT; 280 while (retries--) { 281 rstval = sysc_read_sysconfig(ddata); 282 if (!(rstval & sysc_mask)) 283 return 0; 284 udelay(2); /* Account for udelay flakeyness */ 285 } 286 error = -ETIMEDOUT; 287 } 288 289 return error; 290 } 291 292 /* Poll on reset status */ 293 static int sysc_wait_softreset(struct sysc *ddata) 294 { 295 int syss_offset, error = 0; 296 297 if (ddata->cap->regbits->srst_shift < 0) 298 return 0; 299 300 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 301 302 if (syss_offset >= 0) 303 error = sysc_poll_reset_sysstatus(ddata); 304 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) 305 error = sysc_poll_reset_sysconfig(ddata); 306 307 return error; 308 } 309 310 static int sysc_add_named_clock_from_child(struct sysc *ddata, 311 const char *name, 312 const char *optfck_name) 313 { 314 struct device_node *np = ddata->dev->of_node; 315 struct device_node *child; 316 struct clk_lookup *cl; 317 struct clk *clock; 318 const char *n; 319 320 if (name) 321 n = name; 322 else 323 n = optfck_name; 324 325 /* Does the clock alias already exist? */ 326 clock = of_clk_get_by_name(np, n); 327 if (!IS_ERR(clock)) { 328 clk_put(clock); 329 330 return 0; 331 } 332 333 child = of_get_next_available_child(np, NULL); 334 if (!child) 335 return -ENODEV; 336 337 clock = devm_get_clk_from_child(ddata->dev, child, name); 338 if (IS_ERR(clock)) 339 return PTR_ERR(clock); 340 341 /* 342 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 343 * limit for clk_get(). If cl ever needs to be freed, it should be done 344 * with clkdev_drop(). 345 */ 346 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 347 if (!cl) 348 return -ENOMEM; 349 350 cl->con_id = n; 351 cl->dev_id = dev_name(ddata->dev); 352 cl->clk = clock; 353 clkdev_add(cl); 354 355 clk_put(clock); 356 357 return 0; 358 } 359 360 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 361 { 362 const char *optfck_name; 363 int error, index; 364 365 if (ddata->nr_clocks < SYSC_OPTFCK0) 366 index = SYSC_OPTFCK0; 367 else 368 index = ddata->nr_clocks; 369 370 if (name) 371 optfck_name = name; 372 else 373 optfck_name = clock_names[index]; 374 375 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 376 if (error) 377 return error; 378 379 ddata->clock_roles[index] = optfck_name; 380 ddata->nr_clocks++; 381 382 return 0; 383 } 384 385 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 386 { 387 int error, i, index = -ENODEV; 388 389 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 390 index = SYSC_FCK; 391 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 392 index = SYSC_ICK; 393 394 if (index < 0) { 395 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 396 if (!ddata->clocks[i]) { 397 index = i; 398 break; 399 } 400 } 401 } 402 403 if (index < 0) { 404 dev_err(ddata->dev, "clock %s not added\n", name); 405 return index; 406 } 407 408 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 409 if (IS_ERR(ddata->clocks[index])) { 410 dev_err(ddata->dev, "clock get error for %s: %li\n", 411 name, PTR_ERR(ddata->clocks[index])); 412 413 return PTR_ERR(ddata->clocks[index]); 414 } 415 416 error = clk_prepare(ddata->clocks[index]); 417 if (error) { 418 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 419 name, error); 420 421 return error; 422 } 423 424 return 0; 425 } 426 427 static int sysc_get_clocks(struct sysc *ddata) 428 { 429 struct device_node *np = ddata->dev->of_node; 430 struct property *prop; 431 const char *name; 432 int nr_fck = 0, nr_ick = 0, i, error = 0; 433 434 ddata->clock_roles = devm_kcalloc(ddata->dev, 435 SYSC_MAX_CLOCKS, 436 sizeof(*ddata->clock_roles), 437 GFP_KERNEL); 438 if (!ddata->clock_roles) 439 return -ENOMEM; 440 441 of_property_for_each_string(np, "clock-names", prop, name) { 442 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 443 nr_fck++; 444 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 445 nr_ick++; 446 ddata->clock_roles[ddata->nr_clocks] = name; 447 ddata->nr_clocks++; 448 } 449 450 if (ddata->nr_clocks < 1) 451 return 0; 452 453 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 454 error = sysc_init_ext_opt_clock(ddata, NULL); 455 if (error) 456 return error; 457 } 458 459 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 460 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 461 462 return -EINVAL; 463 } 464 465 if (nr_fck > 1 || nr_ick > 1) { 466 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 467 468 return -EINVAL; 469 } 470 471 /* Always add a slot for main clocks fck and ick even if unused */ 472 if (!nr_fck) 473 ddata->nr_clocks++; 474 if (!nr_ick) 475 ddata->nr_clocks++; 476 477 ddata->clocks = devm_kcalloc(ddata->dev, 478 ddata->nr_clocks, sizeof(*ddata->clocks), 479 GFP_KERNEL); 480 if (!ddata->clocks) 481 return -ENOMEM; 482 483 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 484 const char *name = ddata->clock_roles[i]; 485 486 if (!name) 487 continue; 488 489 error = sysc_get_one_clock(ddata, name); 490 if (error) 491 return error; 492 } 493 494 return 0; 495 } 496 497 static int sysc_enable_main_clocks(struct sysc *ddata) 498 { 499 struct clk *clock; 500 int i, error; 501 502 if (!ddata->clocks) 503 return 0; 504 505 for (i = 0; i < SYSC_OPTFCK0; i++) { 506 clock = ddata->clocks[i]; 507 508 /* Main clocks may not have ick */ 509 if (IS_ERR_OR_NULL(clock)) 510 continue; 511 512 error = clk_enable(clock); 513 if (error) 514 goto err_disable; 515 } 516 517 return 0; 518 519 err_disable: 520 for (i--; i >= 0; i--) { 521 clock = ddata->clocks[i]; 522 523 /* Main clocks may not have ick */ 524 if (IS_ERR_OR_NULL(clock)) 525 continue; 526 527 clk_disable(clock); 528 } 529 530 return error; 531 } 532 533 static void sysc_disable_main_clocks(struct sysc *ddata) 534 { 535 struct clk *clock; 536 int i; 537 538 if (!ddata->clocks) 539 return; 540 541 for (i = 0; i < SYSC_OPTFCK0; i++) { 542 clock = ddata->clocks[i]; 543 if (IS_ERR_OR_NULL(clock)) 544 continue; 545 546 clk_disable(clock); 547 } 548 } 549 550 static int sysc_enable_opt_clocks(struct sysc *ddata) 551 { 552 struct clk *clock; 553 int i, error; 554 555 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 556 return 0; 557 558 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 559 clock = ddata->clocks[i]; 560 561 /* Assume no holes for opt clocks */ 562 if (IS_ERR_OR_NULL(clock)) 563 return 0; 564 565 error = clk_enable(clock); 566 if (error) 567 goto err_disable; 568 } 569 570 return 0; 571 572 err_disable: 573 for (i--; i >= 0; i--) { 574 clock = ddata->clocks[i]; 575 if (IS_ERR_OR_NULL(clock)) 576 continue; 577 578 clk_disable(clock); 579 } 580 581 return error; 582 } 583 584 static void sysc_disable_opt_clocks(struct sysc *ddata) 585 { 586 struct clk *clock; 587 int i; 588 589 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 590 return; 591 592 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 593 clock = ddata->clocks[i]; 594 595 /* Assume no holes for opt clocks */ 596 if (IS_ERR_OR_NULL(clock)) 597 return; 598 599 clk_disable(clock); 600 } 601 } 602 603 static void sysc_clkdm_deny_idle(struct sysc *ddata) 604 { 605 struct ti_sysc_platform_data *pdata; 606 607 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 608 return; 609 610 pdata = dev_get_platdata(ddata->dev); 611 if (pdata && pdata->clkdm_deny_idle) 612 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 613 } 614 615 static void sysc_clkdm_allow_idle(struct sysc *ddata) 616 { 617 struct ti_sysc_platform_data *pdata; 618 619 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 620 return; 621 622 pdata = dev_get_platdata(ddata->dev); 623 if (pdata && pdata->clkdm_allow_idle) 624 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 625 } 626 627 /** 628 * sysc_init_resets - init rstctrl reset line if configured 629 * @ddata: device driver data 630 * 631 * See sysc_rstctrl_reset_deassert(). 632 */ 633 static int sysc_init_resets(struct sysc *ddata) 634 { 635 ddata->rsts = 636 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 637 638 return PTR_ERR_OR_ZERO(ddata->rsts); 639 } 640 641 /** 642 * sysc_parse_and_check_child_range - parses module IO region from ranges 643 * @ddata: device driver data 644 * 645 * In general we only need rev, syss, and sysc registers and not the whole 646 * module range. But we do want the offsets for these registers from the 647 * module base. This allows us to check them against the legacy hwmod 648 * platform data. Let's also check the ranges are configured properly. 649 */ 650 static int sysc_parse_and_check_child_range(struct sysc *ddata) 651 { 652 struct device_node *np = ddata->dev->of_node; 653 struct of_range_parser parser; 654 struct of_range range; 655 int error; 656 657 error = of_range_parser_init(&parser, np); 658 if (error) 659 return error; 660 661 for_each_of_range(&parser, &range) { 662 ddata->module_pa = range.cpu_addr; 663 ddata->module_size = range.size; 664 break; 665 } 666 667 return 0; 668 } 669 670 /* Interconnect instances to probe before l4_per instances */ 671 static struct resource early_bus_ranges[] = { 672 /* am3/4 l4_wkup */ 673 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, 674 /* omap4/5 and dra7 l4_cfg */ 675 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, 676 /* omap4 l4_wkup */ 677 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, 678 /* omap5 and dra7 l4_wkup without dra7 dcan segment */ 679 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, 680 }; 681 682 static atomic_t sysc_defer = ATOMIC_INIT(10); 683 684 /** 685 * sysc_defer_non_critical - defer non_critical interconnect probing 686 * @ddata: device driver data 687 * 688 * We want to probe l4_cfg and l4_wkup interconnect instances before any 689 * l4_per instances as l4_per instances depend on resources on l4_cfg and 690 * l4_wkup interconnects. 691 */ 692 static int sysc_defer_non_critical(struct sysc *ddata) 693 { 694 struct resource *res; 695 int i; 696 697 if (!atomic_read(&sysc_defer)) 698 return 0; 699 700 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { 701 res = &early_bus_ranges[i]; 702 if (ddata->module_pa >= res->start && 703 ddata->module_pa <= res->end) { 704 atomic_set(&sysc_defer, 0); 705 706 return 0; 707 } 708 } 709 710 atomic_dec_if_positive(&sysc_defer); 711 712 return -EPROBE_DEFER; 713 } 714 715 static struct device_node *stdout_path; 716 717 static void sysc_init_stdout_path(struct sysc *ddata) 718 { 719 struct device_node *np = NULL; 720 const char *uart; 721 722 if (IS_ERR(stdout_path)) 723 return; 724 725 if (stdout_path) 726 return; 727 728 np = of_find_node_by_path("/chosen"); 729 if (!np) 730 goto err; 731 732 uart = of_get_property(np, "stdout-path", NULL); 733 if (!uart) 734 goto err; 735 736 np = of_find_node_by_path(uart); 737 if (!np) 738 goto err; 739 740 stdout_path = np; 741 742 return; 743 744 err: 745 stdout_path = ERR_PTR(-ENODEV); 746 } 747 748 static void sysc_check_quirk_stdout(struct sysc *ddata, 749 struct device_node *np) 750 { 751 sysc_init_stdout_path(ddata); 752 if (np != stdout_path) 753 return; 754 755 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 756 SYSC_QUIRK_NO_RESET_ON_INIT; 757 } 758 759 /** 760 * sysc_check_one_child - check child configuration 761 * @ddata: device driver data 762 * @np: child device node 763 * 764 * Let's avoid messy situations where we have new interconnect target 765 * node but children have "ti,hwmods". These belong to the interconnect 766 * target node and are managed by this driver. 767 */ 768 static void sysc_check_one_child(struct sysc *ddata, 769 struct device_node *np) 770 { 771 const char *name; 772 773 name = of_get_property(np, "ti,hwmods", NULL); 774 if (name && !of_device_is_compatible(np, "ti,sysc")) 775 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 776 777 sysc_check_quirk_stdout(ddata, np); 778 sysc_parse_dts_quirks(ddata, np, true); 779 } 780 781 static void sysc_check_children(struct sysc *ddata) 782 { 783 struct device_node *child; 784 785 for_each_child_of_node(ddata->dev->of_node, child) 786 sysc_check_one_child(ddata, child); 787 } 788 789 /* 790 * So far only I2C uses 16-bit read access with clockactivity with revision 791 * in two registers with stride of 4. We can detect this based on the rev 792 * register size to configure things far enough to be able to properly read 793 * the revision register. 794 */ 795 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 796 { 797 if (resource_size(res) == 8) 798 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 799 } 800 801 /** 802 * sysc_parse_one - parses the interconnect target module registers 803 * @ddata: device driver data 804 * @reg: register to parse 805 */ 806 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 807 { 808 struct resource *res; 809 const char *name; 810 811 switch (reg) { 812 case SYSC_REVISION: 813 case SYSC_SYSCONFIG: 814 case SYSC_SYSSTATUS: 815 name = reg_names[reg]; 816 break; 817 default: 818 return -EINVAL; 819 } 820 821 res = platform_get_resource_byname(to_platform_device(ddata->dev), 822 IORESOURCE_MEM, name); 823 if (!res) { 824 ddata->offsets[reg] = -ENODEV; 825 826 return 0; 827 } 828 829 ddata->offsets[reg] = res->start - ddata->module_pa; 830 if (reg == SYSC_REVISION) 831 sysc_check_quirk_16bit(ddata, res); 832 833 return 0; 834 } 835 836 static int sysc_parse_registers(struct sysc *ddata) 837 { 838 int i, error; 839 840 for (i = 0; i < SYSC_MAX_REGS; i++) { 841 error = sysc_parse_one(ddata, i); 842 if (error) 843 return error; 844 } 845 846 return 0; 847 } 848 849 /** 850 * sysc_check_registers - check for misconfigured register overlaps 851 * @ddata: device driver data 852 */ 853 static int sysc_check_registers(struct sysc *ddata) 854 { 855 int i, j, nr_regs = 0, nr_matches = 0; 856 857 for (i = 0; i < SYSC_MAX_REGS; i++) { 858 if (ddata->offsets[i] < 0) 859 continue; 860 861 if (ddata->offsets[i] > (ddata->module_size - 4)) { 862 dev_err(ddata->dev, "register outside module range"); 863 864 return -EINVAL; 865 } 866 867 for (j = 0; j < SYSC_MAX_REGS; j++) { 868 if (ddata->offsets[j] < 0) 869 continue; 870 871 if (ddata->offsets[i] == ddata->offsets[j]) 872 nr_matches++; 873 } 874 nr_regs++; 875 } 876 877 if (nr_matches > nr_regs) { 878 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 879 nr_regs, nr_matches); 880 881 return -EINVAL; 882 } 883 884 return 0; 885 } 886 887 /** 888 * sysc_ioremap - ioremap register space for the interconnect target module 889 * @ddata: device driver data 890 * 891 * Note that the interconnect target module registers can be anywhere 892 * within the interconnect target module range. For example, SGX has 893 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 894 * has them at offset 0x1200 in the CPSW_WR child. Usually the 895 * interconnect target module registers are at the beginning of 896 * the module range though. 897 */ 898 static int sysc_ioremap(struct sysc *ddata) 899 { 900 int size; 901 902 if (ddata->offsets[SYSC_REVISION] < 0 && 903 ddata->offsets[SYSC_SYSCONFIG] < 0 && 904 ddata->offsets[SYSC_SYSSTATUS] < 0) { 905 size = ddata->module_size; 906 } else { 907 size = max3(ddata->offsets[SYSC_REVISION], 908 ddata->offsets[SYSC_SYSCONFIG], 909 ddata->offsets[SYSC_SYSSTATUS]); 910 911 if (size < SZ_1K) 912 size = SZ_1K; 913 914 if ((size + sizeof(u32)) > ddata->module_size) 915 size = ddata->module_size; 916 } 917 918 ddata->module_va = devm_ioremap(ddata->dev, 919 ddata->module_pa, 920 size + sizeof(u32)); 921 if (!ddata->module_va) 922 return -EIO; 923 924 return 0; 925 } 926 927 /** 928 * sysc_map_and_check_registers - ioremap and check device registers 929 * @ddata: device driver data 930 */ 931 static int sysc_map_and_check_registers(struct sysc *ddata) 932 { 933 struct device_node *np = ddata->dev->of_node; 934 int error; 935 936 error = sysc_parse_and_check_child_range(ddata); 937 if (error) 938 return error; 939 940 error = sysc_defer_non_critical(ddata); 941 if (error) 942 return error; 943 944 sysc_check_children(ddata); 945 946 if (!of_property_present(np, "reg")) 947 return 0; 948 949 error = sysc_parse_registers(ddata); 950 if (error) 951 return error; 952 953 error = sysc_ioremap(ddata); 954 if (error) 955 return error; 956 957 error = sysc_check_registers(ddata); 958 if (error) 959 return error; 960 961 return 0; 962 } 963 964 /** 965 * sysc_show_rev - read and show interconnect target module revision 966 * @bufp: buffer to print the information to 967 * @ddata: device driver data 968 */ 969 static int sysc_show_rev(char *bufp, struct sysc *ddata) 970 { 971 int len; 972 973 if (ddata->offsets[SYSC_REVISION] < 0) 974 return sprintf(bufp, ":NA"); 975 976 len = sprintf(bufp, ":%08x", ddata->revision); 977 978 return len; 979 } 980 981 static int sysc_show_reg(struct sysc *ddata, 982 char *bufp, enum sysc_registers reg) 983 { 984 if (ddata->offsets[reg] < 0) 985 return sprintf(bufp, ":NA"); 986 987 return sprintf(bufp, ":%x", ddata->offsets[reg]); 988 } 989 990 static int sysc_show_name(char *bufp, struct sysc *ddata) 991 { 992 if (!ddata->name) 993 return 0; 994 995 return sprintf(bufp, ":%s", ddata->name); 996 } 997 998 /** 999 * sysc_show_registers - show information about interconnect target module 1000 * @ddata: device driver data 1001 */ 1002 static void sysc_show_registers(struct sysc *ddata) 1003 { 1004 char buf[128]; 1005 char *bufp = buf; 1006 int i; 1007 1008 for (i = 0; i < SYSC_MAX_REGS; i++) 1009 bufp += sysc_show_reg(ddata, bufp, i); 1010 1011 bufp += sysc_show_rev(bufp, ddata); 1012 bufp += sysc_show_name(bufp, ddata); 1013 1014 dev_dbg(ddata->dev, "%llx:%x%s\n", 1015 ddata->module_pa, ddata->module_size, 1016 buf); 1017 } 1018 1019 /** 1020 * sysc_write_sysconfig - handle sysconfig quirks for register write 1021 * @ddata: device driver data 1022 * @value: register value 1023 */ 1024 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 1025 { 1026 if (ddata->module_unlock_quirk) 1027 ddata->module_unlock_quirk(ddata); 1028 1029 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 1030 1031 if (ddata->module_lock_quirk) 1032 ddata->module_lock_quirk(ddata); 1033 } 1034 1035 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 1036 #define SYSC_CLOCACT_ICK 2 1037 1038 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1039 static int sysc_enable_module(struct device *dev) 1040 { 1041 struct sysc *ddata; 1042 const struct sysc_regbits *regbits; 1043 u32 reg, idlemodes, best_mode; 1044 int error; 1045 1046 ddata = dev_get_drvdata(dev); 1047 1048 /* 1049 * Some modules like DSS reset automatically on idle. Enable optional 1050 * reset clocks and wait for OCP softreset to complete. 1051 */ 1052 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1053 error = sysc_enable_opt_clocks(ddata); 1054 if (error) { 1055 dev_err(ddata->dev, 1056 "Optional clocks failed for enable: %i\n", 1057 error); 1058 return error; 1059 } 1060 } 1061 /* 1062 * Some modules like i2c and hdq1w have unusable reset status unless 1063 * the module reset quirk is enabled. Skip status check on enable. 1064 */ 1065 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1066 error = sysc_wait_softreset(ddata); 1067 if (error) 1068 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1069 } 1070 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1071 sysc_disable_opt_clocks(ddata); 1072 1073 /* 1074 * Some subsystem private interconnects, like DSS top level module, 1075 * need only the automatic OCP softreset handling with no sysconfig 1076 * register bits to configure. 1077 */ 1078 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1079 return 0; 1080 1081 regbits = ddata->cap->regbits; 1082 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1083 1084 /* 1085 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1086 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1087 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1088 */ 1089 if (regbits->clkact_shift >= 0 && 1090 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1091 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1092 1093 /* Set SIDLE mode */ 1094 idlemodes = ddata->cfg.sidlemodes; 1095 if (!idlemodes || regbits->sidle_shift < 0) 1096 goto set_midle; 1097 1098 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1099 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1100 best_mode = SYSC_IDLE_NO; 1101 } else { 1102 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1103 if (best_mode > SYSC_IDLE_MASK) { 1104 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1105 return -EINVAL; 1106 } 1107 1108 /* Set WAKEUP */ 1109 if (regbits->enwkup_shift >= 0 && 1110 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1111 reg |= BIT(regbits->enwkup_shift); 1112 } 1113 1114 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1115 reg |= best_mode << regbits->sidle_shift; 1116 sysc_write_sysconfig(ddata, reg); 1117 1118 set_midle: 1119 /* Set MIDLE mode */ 1120 idlemodes = ddata->cfg.midlemodes; 1121 if (!idlemodes || regbits->midle_shift < 0) 1122 goto set_autoidle; 1123 1124 best_mode = fls(ddata->cfg.midlemodes) - 1; 1125 if (best_mode > SYSC_IDLE_MASK) { 1126 dev_err(dev, "%s: invalid midlemode\n", __func__); 1127 error = -EINVAL; 1128 goto save_context; 1129 } 1130 1131 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1132 best_mode = SYSC_IDLE_NO; 1133 1134 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1135 reg |= best_mode << regbits->midle_shift; 1136 sysc_write_sysconfig(ddata, reg); 1137 1138 set_autoidle: 1139 /* Autoidle bit must enabled separately if available */ 1140 if (regbits->autoidle_shift >= 0 && 1141 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1142 reg |= 1 << regbits->autoidle_shift; 1143 sysc_write_sysconfig(ddata, reg); 1144 } 1145 1146 error = 0; 1147 1148 save_context: 1149 /* Save context and flush posted write */ 1150 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1151 1152 if (ddata->module_enable_quirk) 1153 ddata->module_enable_quirk(ddata); 1154 1155 return error; 1156 } 1157 1158 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1159 { 1160 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1161 *best_mode = SYSC_IDLE_SMART_WKUP; 1162 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1163 *best_mode = SYSC_IDLE_SMART; 1164 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1165 *best_mode = SYSC_IDLE_FORCE; 1166 else 1167 return -EINVAL; 1168 1169 return 0; 1170 } 1171 1172 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1173 static int sysc_disable_module(struct device *dev) 1174 { 1175 struct sysc *ddata; 1176 const struct sysc_regbits *regbits; 1177 u32 reg, idlemodes, best_mode; 1178 int ret; 1179 1180 ddata = dev_get_drvdata(dev); 1181 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1182 return 0; 1183 1184 if (ddata->module_disable_quirk) 1185 ddata->module_disable_quirk(ddata); 1186 1187 regbits = ddata->cap->regbits; 1188 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1189 1190 /* Set MIDLE mode */ 1191 idlemodes = ddata->cfg.midlemodes; 1192 if (!idlemodes || regbits->midle_shift < 0) 1193 goto set_sidle; 1194 1195 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1196 if (ret) { 1197 dev_err(dev, "%s: invalid midlemode\n", __func__); 1198 return ret; 1199 } 1200 1201 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1202 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1203 best_mode = SYSC_IDLE_FORCE; 1204 1205 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1206 reg |= best_mode << regbits->midle_shift; 1207 sysc_write_sysconfig(ddata, reg); 1208 1209 set_sidle: 1210 /* Set SIDLE mode */ 1211 idlemodes = ddata->cfg.sidlemodes; 1212 if (!idlemodes || regbits->sidle_shift < 0) { 1213 ret = 0; 1214 goto save_context; 1215 } 1216 1217 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1218 best_mode = SYSC_IDLE_FORCE; 1219 } else { 1220 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1221 if (ret) { 1222 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1223 ret = -EINVAL; 1224 goto save_context; 1225 } 1226 } 1227 1228 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1229 reg |= best_mode << regbits->sidle_shift; 1230 if (regbits->autoidle_shift >= 0 && 1231 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1232 reg |= 1 << regbits->autoidle_shift; 1233 sysc_write_sysconfig(ddata, reg); 1234 1235 ret = 0; 1236 1237 save_context: 1238 /* Save context and flush posted write */ 1239 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1240 1241 return ret; 1242 } 1243 1244 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1245 struct sysc *ddata) 1246 { 1247 struct ti_sysc_platform_data *pdata; 1248 int error; 1249 1250 pdata = dev_get_platdata(ddata->dev); 1251 if (!pdata) 1252 return 0; 1253 1254 if (!pdata->idle_module) 1255 return -ENODEV; 1256 1257 error = pdata->idle_module(dev, &ddata->cookie); 1258 if (error) 1259 dev_err(dev, "%s: could not idle: %i\n", 1260 __func__, error); 1261 1262 reset_control_assert(ddata->rsts); 1263 1264 return 0; 1265 } 1266 1267 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1268 struct sysc *ddata) 1269 { 1270 struct ti_sysc_platform_data *pdata; 1271 int error; 1272 1273 pdata = dev_get_platdata(ddata->dev); 1274 if (!pdata) 1275 return 0; 1276 1277 if (!pdata->enable_module) 1278 return -ENODEV; 1279 1280 error = pdata->enable_module(dev, &ddata->cookie); 1281 if (error) 1282 dev_err(dev, "%s: could not enable: %i\n", 1283 __func__, error); 1284 1285 reset_control_deassert(ddata->rsts); 1286 1287 return 0; 1288 } 1289 1290 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1291 { 1292 struct sysc *ddata; 1293 int error = 0; 1294 1295 ddata = dev_get_drvdata(dev); 1296 1297 if (!ddata->enabled) 1298 return 0; 1299 1300 sysc_clkdm_deny_idle(ddata); 1301 1302 if (ddata->legacy_mode) { 1303 error = sysc_runtime_suspend_legacy(dev, ddata); 1304 if (error) 1305 goto err_allow_idle; 1306 } else { 1307 error = sysc_disable_module(dev); 1308 if (error) 1309 goto err_allow_idle; 1310 } 1311 1312 sysc_disable_main_clocks(ddata); 1313 1314 if (sysc_opt_clks_needed(ddata)) 1315 sysc_disable_opt_clocks(ddata); 1316 1317 ddata->enabled = false; 1318 1319 err_allow_idle: 1320 sysc_clkdm_allow_idle(ddata); 1321 1322 reset_control_assert(ddata->rsts); 1323 1324 return error; 1325 } 1326 1327 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1328 { 1329 struct sysc *ddata; 1330 int error = 0; 1331 1332 ddata = dev_get_drvdata(dev); 1333 1334 if (ddata->enabled) 1335 return 0; 1336 1337 1338 sysc_clkdm_deny_idle(ddata); 1339 1340 if (sysc_opt_clks_needed(ddata)) { 1341 error = sysc_enable_opt_clocks(ddata); 1342 if (error) 1343 goto err_allow_idle; 1344 } 1345 1346 error = sysc_enable_main_clocks(ddata); 1347 if (error) 1348 goto err_opt_clocks; 1349 1350 reset_control_deassert(ddata->rsts); 1351 1352 if (ddata->legacy_mode) { 1353 error = sysc_runtime_resume_legacy(dev, ddata); 1354 if (error) 1355 goto err_main_clocks; 1356 } else { 1357 error = sysc_enable_module(dev); 1358 if (error) 1359 goto err_main_clocks; 1360 } 1361 1362 ddata->enabled = true; 1363 1364 sysc_clkdm_allow_idle(ddata); 1365 1366 return 0; 1367 1368 err_main_clocks: 1369 sysc_disable_main_clocks(ddata); 1370 err_opt_clocks: 1371 if (sysc_opt_clks_needed(ddata)) 1372 sysc_disable_opt_clocks(ddata); 1373 err_allow_idle: 1374 sysc_clkdm_allow_idle(ddata); 1375 1376 return error; 1377 } 1378 1379 /* 1380 * Checks if device context was lost. Assumes the sysconfig register value 1381 * after lost context is different from the configured value. Only works for 1382 * enabled devices. 1383 * 1384 * Eventually we may want to also add support to using the context lost 1385 * registers that some SoCs have. 1386 */ 1387 static int sysc_check_context(struct sysc *ddata) 1388 { 1389 u32 reg; 1390 1391 if (!ddata->enabled) 1392 return -ENODATA; 1393 1394 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1395 if (reg == ddata->sysconfig) 1396 return 0; 1397 1398 return -EACCES; 1399 } 1400 1401 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1402 { 1403 struct device *dev = ddata->dev; 1404 int error; 1405 1406 if (ddata->enabled) { 1407 /* Nothing to do if enabled and context not lost */ 1408 error = sysc_check_context(ddata); 1409 if (!error) 1410 return 0; 1411 1412 /* Disable target module if it is enabled */ 1413 error = sysc_runtime_suspend(dev); 1414 if (error) 1415 dev_warn(dev, "reinit suspend failed: %i\n", error); 1416 } 1417 1418 /* Enable target module */ 1419 error = sysc_runtime_resume(dev); 1420 if (error) 1421 dev_warn(dev, "reinit resume failed: %i\n", error); 1422 1423 /* Some modules like am335x gpmc need reset and restore of sysconfig */ 1424 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) { 1425 error = sysc_reset(ddata); 1426 if (error) 1427 dev_warn(dev, "reinit reset failed: %i\n", error); 1428 1429 sysc_write_sysconfig(ddata, ddata->sysconfig); 1430 } 1431 1432 if (leave_enabled) 1433 return error; 1434 1435 /* Disable target module if no leave_enabled was set */ 1436 error = sysc_runtime_suspend(dev); 1437 if (error) 1438 dev_warn(dev, "reinit suspend failed: %i\n", error); 1439 1440 return error; 1441 } 1442 1443 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1444 { 1445 struct sysc *ddata; 1446 1447 ddata = dev_get_drvdata(dev); 1448 1449 if (ddata->cfg.quirks & 1450 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1451 return 0; 1452 1453 if (!ddata->enabled) 1454 return 0; 1455 1456 ddata->needs_resume = 1; 1457 1458 return sysc_runtime_suspend(dev); 1459 } 1460 1461 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1462 { 1463 struct sysc *ddata; 1464 int error = 0; 1465 1466 ddata = dev_get_drvdata(dev); 1467 1468 if (ddata->cfg.quirks & 1469 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1470 return 0; 1471 1472 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1473 error = sysc_reinit_module(ddata, ddata->needs_resume); 1474 if (error) 1475 dev_warn(dev, "noirq_resume failed: %i\n", error); 1476 } else if (ddata->needs_resume) { 1477 error = sysc_runtime_resume(dev); 1478 if (error) 1479 dev_warn(dev, "noirq_resume failed: %i\n", error); 1480 } 1481 1482 ddata->needs_resume = 0; 1483 1484 return error; 1485 } 1486 1487 static const struct dev_pm_ops sysc_pm_ops = { 1488 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1489 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1490 sysc_runtime_resume, 1491 NULL) 1492 }; 1493 1494 /* Module revision register based quirks */ 1495 struct sysc_revision_quirk { 1496 const char *name; 1497 u32 base; 1498 int rev_offset; 1499 int sysc_offset; 1500 int syss_offset; 1501 u32 revision; 1502 u32 revision_mask; 1503 u32 quirks; 1504 }; 1505 1506 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1507 optrev_val, optrevmask, optquirkmask) \ 1508 { \ 1509 .name = (optname), \ 1510 .base = (optbase), \ 1511 .rev_offset = (optrev), \ 1512 .sysc_offset = (optsysc), \ 1513 .syss_offset = (optsyss), \ 1514 .revision = (optrev_val), \ 1515 .revision_mask = (optrevmask), \ 1516 .quirks = (optquirkmask), \ 1517 } 1518 1519 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1520 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1521 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1522 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1523 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1524 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1525 /* Uarts on omap4 and later */ 1526 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1527 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1528 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1529 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1530 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, 1531 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1532 1533 /* Quirks that need to be set based on the module address */ 1534 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1535 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1536 SYSC_QUIRK_SWSUP_SIDLE), 1537 1538 /* Quirks that need to be set based on detected module */ 1539 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1540 SYSC_MODULE_QUIRK_AESS), 1541 /* Errata i893 handling for dra7 dcan1 and 2 */ 1542 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1543 SYSC_QUIRK_CLKDM_NOAUTO), 1544 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1545 SYSC_QUIRK_CLKDM_NOAUTO), 1546 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1547 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1548 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1549 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1550 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1551 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1552 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1553 SYSC_QUIRK_CLKDM_NOAUTO), 1554 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1555 SYSC_QUIRK_CLKDM_NOAUTO), 1556 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1557 SYSC_QUIRK_OPT_CLKS_IN_RESET), 1558 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1559 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST | 1560 SYSC_QUIRK_GPMC_DEBUG), 1561 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1562 SYSC_QUIRK_OPT_CLKS_NEEDED), 1563 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1564 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1565 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1566 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1567 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1568 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1569 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1570 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1571 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1572 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1573 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1574 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1575 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1576 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1577 SYSC_MODULE_QUIRK_SGX), 1578 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1579 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1580 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 1581 SYSC_QUIRK_SWSUP_SIDLE), 1582 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1583 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1584 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1585 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1586 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1587 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1588 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1589 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1590 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1591 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1592 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1593 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1594 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033, 1595 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1596 SYSC_MODULE_QUIRK_OTG), 1597 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040, 1598 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1599 SYSC_MODULE_QUIRK_OTG), 1600 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1601 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1602 SYSC_MODULE_QUIRK_OTG), 1603 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1604 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1605 SYSC_QUIRK_REINIT_ON_CTX_LOST), 1606 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1607 SYSC_MODULE_QUIRK_WDT), 1608 /* PRUSS on am3, am4 and am5 */ 1609 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1610 SYSC_MODULE_QUIRK_PRUSS), 1611 /* Watchdog on am3 and am4 */ 1612 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1613 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1614 1615 #ifdef DEBUG 1616 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1617 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1618 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1619 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1620 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1621 0xffff00f0, 0), 1622 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1623 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1624 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1625 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1626 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1627 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1628 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1629 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1630 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1631 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1632 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1633 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1634 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1635 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1636 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1637 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1638 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1639 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1640 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1641 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1642 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1643 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1644 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1645 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1646 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1647 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1648 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1649 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1650 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1651 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1652 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1653 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1654 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1655 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1656 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1657 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1658 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1659 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1660 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1661 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1662 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1663 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1664 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1665 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1666 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1667 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1668 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1669 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1670 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0), 1671 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1672 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1673 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), 1674 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), 1675 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1676 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1677 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1678 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1679 /* Some timers on omap4 and later */ 1680 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1681 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1682 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1683 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1684 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1685 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1686 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1687 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1688 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1689 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1690 #endif 1691 }; 1692 1693 /* 1694 * Early quirks based on module base and register offsets only that are 1695 * needed before the module revision can be read 1696 */ 1697 static void sysc_init_early_quirks(struct sysc *ddata) 1698 { 1699 const struct sysc_revision_quirk *q; 1700 int i; 1701 1702 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1703 q = &sysc_revision_quirks[i]; 1704 1705 if (!q->base) 1706 continue; 1707 1708 if (q->base != ddata->module_pa) 1709 continue; 1710 1711 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1712 continue; 1713 1714 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1715 continue; 1716 1717 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1718 continue; 1719 1720 ddata->name = q->name; 1721 ddata->cfg.quirks |= q->quirks; 1722 } 1723 } 1724 1725 /* Quirks that also consider the revision register value */ 1726 static void sysc_init_revision_quirks(struct sysc *ddata) 1727 { 1728 const struct sysc_revision_quirk *q; 1729 int i; 1730 1731 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1732 q = &sysc_revision_quirks[i]; 1733 1734 if (q->base && q->base != ddata->module_pa) 1735 continue; 1736 1737 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1738 continue; 1739 1740 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1741 continue; 1742 1743 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1744 continue; 1745 1746 if (q->revision == ddata->revision || 1747 (q->revision & q->revision_mask) == 1748 (ddata->revision & q->revision_mask)) { 1749 ddata->name = q->name; 1750 ddata->cfg.quirks |= q->quirks; 1751 } 1752 } 1753 } 1754 1755 /* 1756 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1757 * enabled DSS interrupts. Eventually we may be able to do this on 1758 * dispc init rather than top-level DSS init. 1759 */ 1760 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1761 bool disable) 1762 { 1763 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1764 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1765 int manager_count; 1766 bool framedonetv_irq = true; 1767 u32 val, irq_mask = 0; 1768 1769 switch (sysc_soc->soc) { 1770 case SOC_2420 ... SOC_3630: 1771 manager_count = 2; 1772 framedonetv_irq = false; 1773 break; 1774 case SOC_4430 ... SOC_4470: 1775 manager_count = 3; 1776 break; 1777 case SOC_5430: 1778 case SOC_DRA7: 1779 manager_count = 4; 1780 break; 1781 case SOC_AM4: 1782 manager_count = 1; 1783 framedonetv_irq = false; 1784 break; 1785 case SOC_UNKNOWN: 1786 default: 1787 return 0; 1788 } 1789 1790 /* Remap the whole module range to be able to reset dispc outputs */ 1791 devm_iounmap(ddata->dev, ddata->module_va); 1792 ddata->module_va = devm_ioremap(ddata->dev, 1793 ddata->module_pa, 1794 ddata->module_size); 1795 if (!ddata->module_va) 1796 return -EIO; 1797 1798 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ 1799 val = sysc_read(ddata, dispc_offset + 0x40); 1800 lcd_en = val & lcd_en_mask; 1801 digit_en = val & digit_en_mask; 1802 if (lcd_en) 1803 irq_mask |= BIT(0); /* FRAMEDONE */ 1804 if (digit_en) { 1805 if (framedonetv_irq) 1806 irq_mask |= BIT(24); /* FRAMEDONETV */ 1807 else 1808 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1809 } 1810 if (disable && (lcd_en || digit_en)) 1811 sysc_write(ddata, dispc_offset + 0x40, 1812 val & ~(lcd_en_mask | digit_en_mask)); 1813 1814 if (manager_count <= 2) 1815 return irq_mask; 1816 1817 /* DISPC_CONTROL2 */ 1818 val = sysc_read(ddata, dispc_offset + 0x238); 1819 lcd2_en = val & lcd_en_mask; 1820 if (lcd2_en) 1821 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1822 if (disable && lcd2_en) 1823 sysc_write(ddata, dispc_offset + 0x238, 1824 val & ~lcd_en_mask); 1825 1826 if (manager_count <= 3) 1827 return irq_mask; 1828 1829 /* DISPC_CONTROL3 */ 1830 val = sysc_read(ddata, dispc_offset + 0x848); 1831 lcd3_en = val & lcd_en_mask; 1832 if (lcd3_en) 1833 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1834 if (disable && lcd3_en) 1835 sysc_write(ddata, dispc_offset + 0x848, 1836 val & ~lcd_en_mask); 1837 1838 return irq_mask; 1839 } 1840 1841 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1842 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1843 { 1844 const int dispc_offset = 0x1000; 1845 int error; 1846 u32 irq_mask, val; 1847 1848 /* Get enabled outputs */ 1849 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1850 if (!irq_mask) 1851 return; 1852 1853 /* Clear IRQSTATUS */ 1854 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1855 1856 /* Disable outputs */ 1857 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1858 1859 /* Poll IRQSTATUS */ 1860 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1861 val, val != irq_mask, 100, 50); 1862 if (error) 1863 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1864 __func__, val, irq_mask); 1865 1866 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) { 1867 /* Clear DSS_SDI_CONTROL */ 1868 sysc_write(ddata, 0x44, 0); 1869 1870 /* Clear DSS_PLL_CONTROL */ 1871 sysc_write(ddata, 0x48, 0); 1872 } 1873 1874 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1875 sysc_write(ddata, 0x40, 0); 1876 } 1877 1878 /* 1-wire needs module's internal clocks enabled for reset */ 1879 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1880 { 1881 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1882 u16 val; 1883 1884 val = sysc_read(ddata, offset); 1885 val |= BIT(5); 1886 sysc_write(ddata, offset, val); 1887 } 1888 1889 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1890 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1891 { 1892 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1893 1894 sysc_write(ddata, offset, 1); 1895 } 1896 1897 /* I2C needs to be disabled for reset */ 1898 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1899 { 1900 int offset; 1901 u16 val; 1902 1903 /* I2C_CON, omap2/3 is different from omap4 and later */ 1904 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1905 offset = 0x24; 1906 else 1907 offset = 0xa4; 1908 1909 /* I2C_EN */ 1910 val = sysc_read(ddata, offset); 1911 if (enable) 1912 val |= BIT(15); 1913 else 1914 val &= ~BIT(15); 1915 sysc_write(ddata, offset, val); 1916 } 1917 1918 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1919 { 1920 sysc_clk_quirk_i2c(ddata, false); 1921 } 1922 1923 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1924 { 1925 sysc_clk_quirk_i2c(ddata, true); 1926 } 1927 1928 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1929 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1930 { 1931 u32 val, kick0_val = 0, kick1_val = 0; 1932 unsigned long flags; 1933 int error; 1934 1935 if (!lock) { 1936 kick0_val = 0x83e70b13; 1937 kick1_val = 0x95a4f1e0; 1938 } 1939 1940 local_irq_save(flags); 1941 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1942 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1943 !(val & BIT(0)), 100, 50); 1944 if (error) 1945 dev_warn(ddata->dev, "rtc busy timeout\n"); 1946 /* Now we have ~15 microseconds to read/write various registers */ 1947 sysc_write(ddata, 0x6c, kick0_val); 1948 sysc_write(ddata, 0x70, kick1_val); 1949 local_irq_restore(flags); 1950 } 1951 1952 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1953 { 1954 sysc_quirk_rtc(ddata, false); 1955 } 1956 1957 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1958 { 1959 sysc_quirk_rtc(ddata, true); 1960 } 1961 1962 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */ 1963 static void sysc_module_enable_quirk_otg(struct sysc *ddata) 1964 { 1965 int offset = 0x414; /* OTG_FORCESTDBY */ 1966 1967 sysc_write(ddata, offset, 0); 1968 } 1969 1970 static void sysc_module_disable_quirk_otg(struct sysc *ddata) 1971 { 1972 int offset = 0x414; /* OTG_FORCESTDBY */ 1973 u32 val = BIT(0); /* ENABLEFORCE */ 1974 1975 sysc_write(ddata, offset, val); 1976 } 1977 1978 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1979 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1980 { 1981 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1982 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1983 1984 sysc_write(ddata, offset, val); 1985 } 1986 1987 /* Watchdog timer needs a disable sequence after reset */ 1988 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1989 { 1990 int wps, spr, error; 1991 u32 val; 1992 1993 wps = 0x34; 1994 spr = 0x48; 1995 1996 sysc_write(ddata, spr, 0xaaaa); 1997 error = readl_poll_timeout(ddata->module_va + wps, val, 1998 !(val & 0x10), 100, 1999 MAX_MODULE_SOFTRESET_WAIT); 2000 if (error) 2001 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 2002 2003 sysc_write(ddata, spr, 0x5555); 2004 error = readl_poll_timeout(ddata->module_va + wps, val, 2005 !(val & 0x10), 100, 2006 MAX_MODULE_SOFTRESET_WAIT); 2007 if (error) 2008 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 2009 } 2010 2011 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 2012 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 2013 { 2014 u32 reg; 2015 2016 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 2017 reg |= SYSC_PRUSS_STANDBY_INIT; 2018 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 2019 } 2020 2021 static void sysc_init_module_quirks(struct sysc *ddata) 2022 { 2023 if (ddata->legacy_mode || !ddata->name) 2024 return; 2025 2026 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 2027 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 2028 2029 return; 2030 } 2031 2032 #ifdef CONFIG_OMAP_GPMC_DEBUG 2033 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 2034 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 2035 2036 return; 2037 } 2038 #endif 2039 2040 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 2041 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 2042 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 2043 2044 return; 2045 } 2046 2047 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 2048 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 2049 2050 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 2051 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 2052 2053 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 2054 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 2055 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 2056 2057 return; 2058 } 2059 2060 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) { 2061 ddata->module_enable_quirk = sysc_module_enable_quirk_otg; 2062 ddata->module_disable_quirk = sysc_module_disable_quirk_otg; 2063 } 2064 2065 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 2066 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 2067 2068 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 2069 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 2070 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 2071 } 2072 2073 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 2074 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 2075 } 2076 2077 static int sysc_clockdomain_init(struct sysc *ddata) 2078 { 2079 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2080 struct clk *fck = NULL, *ick = NULL; 2081 int error; 2082 2083 if (!pdata || !pdata->init_clockdomain) 2084 return 0; 2085 2086 switch (ddata->nr_clocks) { 2087 case 2: 2088 ick = ddata->clocks[SYSC_ICK]; 2089 fallthrough; 2090 case 1: 2091 fck = ddata->clocks[SYSC_FCK]; 2092 break; 2093 case 0: 2094 return 0; 2095 } 2096 2097 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 2098 if (!error || error == -ENODEV) 2099 return 0; 2100 2101 return error; 2102 } 2103 2104 /* 2105 * Note that pdata->init_module() typically does a reset first. After 2106 * pdata->init_module() is done, PM runtime can be used for the interconnect 2107 * target module. 2108 */ 2109 static int sysc_legacy_init(struct sysc *ddata) 2110 { 2111 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2112 int error; 2113 2114 if (!pdata || !pdata->init_module) 2115 return 0; 2116 2117 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2118 if (error == -EEXIST) 2119 error = 0; 2120 2121 return error; 2122 } 2123 2124 /* 2125 * Note that the caller must ensure the interconnect target module is enabled 2126 * before calling reset. Otherwise reset will not complete. 2127 */ 2128 static int sysc_reset(struct sysc *ddata) 2129 { 2130 int sysc_offset, sysc_val, error; 2131 u32 sysc_mask; 2132 2133 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2134 2135 if (ddata->legacy_mode || 2136 ddata->cap->regbits->srst_shift < 0 || 2137 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 2138 return 0; 2139 2140 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2141 2142 if (ddata->pre_reset_quirk) 2143 ddata->pre_reset_quirk(ddata); 2144 2145 if (sysc_offset >= 0) { 2146 sysc_val = sysc_read_sysconfig(ddata); 2147 sysc_val |= sysc_mask; 2148 sysc_write(ddata, sysc_offset, sysc_val); 2149 /* Flush posted write */ 2150 sysc_val = sysc_read_sysconfig(ddata); 2151 } 2152 2153 if (ddata->cfg.srst_udelay) 2154 fsleep(ddata->cfg.srst_udelay); 2155 2156 if (ddata->post_reset_quirk) 2157 ddata->post_reset_quirk(ddata); 2158 2159 error = sysc_wait_softreset(ddata); 2160 if (error) 2161 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2162 2163 if (ddata->reset_done_quirk) 2164 ddata->reset_done_quirk(ddata); 2165 2166 return error; 2167 } 2168 2169 /* 2170 * At this point the module is configured enough to read the revision but 2171 * module may not be completely configured yet to use PM runtime. Enable 2172 * all clocks directly during init to configure the quirks needed for PM 2173 * runtime based on the revision register. 2174 */ 2175 static int sysc_init_module(struct sysc *ddata) 2176 { 2177 bool rstctrl_deasserted = false; 2178 int error = 0; 2179 2180 error = sysc_clockdomain_init(ddata); 2181 if (error) 2182 return error; 2183 2184 sysc_clkdm_deny_idle(ddata); 2185 2186 /* 2187 * Always enable clocks. The bootloader may or may not have enabled 2188 * the related clocks. 2189 */ 2190 error = sysc_enable_opt_clocks(ddata); 2191 if (error) 2192 return error; 2193 2194 error = sysc_enable_main_clocks(ddata); 2195 if (error) 2196 goto err_opt_clocks; 2197 2198 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2199 error = reset_control_deassert(ddata->rsts); 2200 if (error) 2201 goto err_main_clocks; 2202 rstctrl_deasserted = true; 2203 } 2204 2205 ddata->revision = sysc_read_revision(ddata); 2206 sysc_init_revision_quirks(ddata); 2207 sysc_init_module_quirks(ddata); 2208 2209 if (ddata->legacy_mode) { 2210 error = sysc_legacy_init(ddata); 2211 if (error) 2212 goto err_main_clocks; 2213 } 2214 2215 if (!ddata->legacy_mode) { 2216 error = sysc_enable_module(ddata->dev); 2217 if (error) 2218 goto err_main_clocks; 2219 } 2220 2221 error = sysc_reset(ddata); 2222 if (error) 2223 dev_err(ddata->dev, "Reset failed with %d\n", error); 2224 2225 if (error && !ddata->legacy_mode) 2226 sysc_disable_module(ddata->dev); 2227 2228 err_main_clocks: 2229 if (error) 2230 sysc_disable_main_clocks(ddata); 2231 err_opt_clocks: 2232 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2233 if (error) { 2234 sysc_disable_opt_clocks(ddata); 2235 sysc_clkdm_allow_idle(ddata); 2236 } 2237 2238 if (error && rstctrl_deasserted && 2239 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2240 reset_control_assert(ddata->rsts); 2241 2242 return error; 2243 } 2244 2245 static int sysc_init_sysc_mask(struct sysc *ddata) 2246 { 2247 struct device_node *np = ddata->dev->of_node; 2248 int error; 2249 u32 val; 2250 2251 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2252 if (error) 2253 return 0; 2254 2255 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2256 2257 return 0; 2258 } 2259 2260 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2261 const char *name) 2262 { 2263 struct device_node *np = ddata->dev->of_node; 2264 struct property *prop; 2265 const __be32 *p; 2266 u32 val; 2267 2268 of_property_for_each_u32(np, name, prop, p, val) { 2269 if (val >= SYSC_NR_IDLEMODES) { 2270 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2271 return -EINVAL; 2272 } 2273 *idlemodes |= (1 << val); 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int sysc_init_idlemodes(struct sysc *ddata) 2280 { 2281 int error; 2282 2283 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2284 "ti,sysc-midle"); 2285 if (error) 2286 return error; 2287 2288 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2289 "ti,sysc-sidle"); 2290 if (error) 2291 return error; 2292 2293 return 0; 2294 } 2295 2296 /* 2297 * Only some devices on omap4 and later have SYSCONFIG reset done 2298 * bit. We can detect this if there is no SYSSTATUS at all, or the 2299 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2300 * have multiple bits for the child devices like OHCI and EHCI. 2301 * Depends on SYSC being parsed first. 2302 */ 2303 static int sysc_init_syss_mask(struct sysc *ddata) 2304 { 2305 struct device_node *np = ddata->dev->of_node; 2306 int error; 2307 u32 val; 2308 2309 error = of_property_read_u32(np, "ti,syss-mask", &val); 2310 if (error) { 2311 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2312 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2313 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2314 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2315 2316 return 0; 2317 } 2318 2319 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2320 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2321 2322 ddata->cfg.syss_mask = val; 2323 2324 return 0; 2325 } 2326 2327 /* 2328 * Many child device drivers need to have fck and opt clocks available 2329 * to get the clock rate for device internal configuration etc. 2330 */ 2331 static int sysc_child_add_named_clock(struct sysc *ddata, 2332 struct device *child, 2333 const char *name) 2334 { 2335 struct clk *clk; 2336 struct clk_lookup *l; 2337 int error = 0; 2338 2339 if (!name) 2340 return 0; 2341 2342 clk = clk_get(child, name); 2343 if (!IS_ERR(clk)) { 2344 error = -EEXIST; 2345 goto put_clk; 2346 } 2347 2348 clk = clk_get(ddata->dev, name); 2349 if (IS_ERR(clk)) 2350 return -ENODEV; 2351 2352 l = clkdev_create(clk, name, dev_name(child)); 2353 if (!l) 2354 error = -ENOMEM; 2355 put_clk: 2356 clk_put(clk); 2357 2358 return error; 2359 } 2360 2361 static int sysc_child_add_clocks(struct sysc *ddata, 2362 struct device *child) 2363 { 2364 int i, error; 2365 2366 for (i = 0; i < ddata->nr_clocks; i++) { 2367 error = sysc_child_add_named_clock(ddata, 2368 child, 2369 ddata->clock_roles[i]); 2370 if (error && error != -EEXIST) { 2371 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2372 ddata->clock_roles[i], error); 2373 2374 return error; 2375 } 2376 } 2377 2378 return 0; 2379 } 2380 2381 static struct device_type sysc_device_type = { 2382 }; 2383 2384 static struct sysc *sysc_child_to_parent(struct device *dev) 2385 { 2386 struct device *parent = dev->parent; 2387 2388 if (!parent || parent->type != &sysc_device_type) 2389 return NULL; 2390 2391 return dev_get_drvdata(parent); 2392 } 2393 2394 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2395 { 2396 struct sysc *ddata; 2397 int error; 2398 2399 ddata = sysc_child_to_parent(dev); 2400 2401 error = pm_generic_runtime_suspend(dev); 2402 if (error) 2403 return error; 2404 2405 if (!ddata->enabled) 2406 return 0; 2407 2408 return sysc_runtime_suspend(ddata->dev); 2409 } 2410 2411 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2412 { 2413 struct sysc *ddata; 2414 int error; 2415 2416 ddata = sysc_child_to_parent(dev); 2417 2418 if (!ddata->enabled) { 2419 error = sysc_runtime_resume(ddata->dev); 2420 if (error < 0) 2421 dev_err(ddata->dev, 2422 "%s error: %i\n", __func__, error); 2423 } 2424 2425 return pm_generic_runtime_resume(dev); 2426 } 2427 2428 #ifdef CONFIG_PM_SLEEP 2429 static int sysc_child_suspend_noirq(struct device *dev) 2430 { 2431 struct sysc *ddata; 2432 int error; 2433 2434 ddata = sysc_child_to_parent(dev); 2435 2436 dev_dbg(ddata->dev, "%s %s\n", __func__, 2437 ddata->name ? ddata->name : ""); 2438 2439 error = pm_generic_suspend_noirq(dev); 2440 if (error) { 2441 dev_err(dev, "%s error at %i: %i\n", 2442 __func__, __LINE__, error); 2443 2444 return error; 2445 } 2446 2447 if (!pm_runtime_status_suspended(dev)) { 2448 error = pm_generic_runtime_suspend(dev); 2449 if (error) { 2450 dev_dbg(dev, "%s busy at %i: %i\n", 2451 __func__, __LINE__, error); 2452 2453 return 0; 2454 } 2455 2456 error = sysc_runtime_suspend(ddata->dev); 2457 if (error) { 2458 dev_err(dev, "%s error at %i: %i\n", 2459 __func__, __LINE__, error); 2460 2461 return error; 2462 } 2463 2464 ddata->child_needs_resume = true; 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int sysc_child_resume_noirq(struct device *dev) 2471 { 2472 struct sysc *ddata; 2473 int error; 2474 2475 ddata = sysc_child_to_parent(dev); 2476 2477 dev_dbg(ddata->dev, "%s %s\n", __func__, 2478 ddata->name ? ddata->name : ""); 2479 2480 if (ddata->child_needs_resume) { 2481 ddata->child_needs_resume = false; 2482 2483 error = sysc_runtime_resume(ddata->dev); 2484 if (error) 2485 dev_err(ddata->dev, 2486 "%s runtime resume error: %i\n", 2487 __func__, error); 2488 2489 error = pm_generic_runtime_resume(dev); 2490 if (error) 2491 dev_err(ddata->dev, 2492 "%s generic runtime resume: %i\n", 2493 __func__, error); 2494 } 2495 2496 return pm_generic_resume_noirq(dev); 2497 } 2498 #endif 2499 2500 static struct dev_pm_domain sysc_child_pm_domain = { 2501 .ops = { 2502 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2503 sysc_child_runtime_resume, 2504 NULL) 2505 USE_PLATFORM_PM_SLEEP_OPS 2506 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2507 sysc_child_resume_noirq) 2508 } 2509 }; 2510 2511 /* Caller needs to take list_lock if ever used outside of cpu_pm */ 2512 static void sysc_reinit_modules(struct sysc_soc_info *soc) 2513 { 2514 struct sysc_module *module; 2515 struct sysc *ddata; 2516 2517 list_for_each_entry(module, &sysc_soc->restored_modules, node) { 2518 ddata = module->ddata; 2519 sysc_reinit_module(ddata, ddata->enabled); 2520 } 2521 } 2522 2523 /** 2524 * sysc_context_notifier - optionally reset and restore module after idle 2525 * @nb: notifier block 2526 * @cmd: unused 2527 * @v: unused 2528 * 2529 * Some interconnect target modules need to be restored, or reset and restored 2530 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x 2531 * OTG and GPMC target modules even if the modules are unused. 2532 */ 2533 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, 2534 void *v) 2535 { 2536 struct sysc_soc_info *soc; 2537 2538 soc = container_of(nb, struct sysc_soc_info, nb); 2539 2540 switch (cmd) { 2541 case CPU_CLUSTER_PM_ENTER: 2542 break; 2543 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2544 break; 2545 case CPU_CLUSTER_PM_EXIT: 2546 sysc_reinit_modules(soc); 2547 break; 2548 } 2549 2550 return NOTIFY_OK; 2551 } 2552 2553 /** 2554 * sysc_add_restored - optionally add reset and restore quirk hanlling 2555 * @ddata: device data 2556 */ 2557 static void sysc_add_restored(struct sysc *ddata) 2558 { 2559 struct sysc_module *restored_module; 2560 2561 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); 2562 if (!restored_module) 2563 return; 2564 2565 restored_module->ddata = ddata; 2566 2567 mutex_lock(&sysc_soc->list_lock); 2568 2569 list_add(&restored_module->node, &sysc_soc->restored_modules); 2570 2571 if (sysc_soc->nb.notifier_call) 2572 goto out_unlock; 2573 2574 sysc_soc->nb.notifier_call = sysc_context_notifier; 2575 cpu_pm_register_notifier(&sysc_soc->nb); 2576 2577 out_unlock: 2578 mutex_unlock(&sysc_soc->list_lock); 2579 } 2580 2581 /** 2582 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2583 * @ddata: device driver data 2584 * @child: child device driver 2585 * 2586 * Allow idle for child devices as done with _od_runtime_suspend(). 2587 * Otherwise many child devices will not idle because of the permanent 2588 * parent usecount set in pm_runtime_irq_safe(). 2589 * 2590 * Note that the long term solution is to just modify the child device 2591 * drivers to not set pm_runtime_irq_safe() and then this can be just 2592 * dropped. 2593 */ 2594 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2595 { 2596 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2597 dev_pm_domain_set(child, &sysc_child_pm_domain); 2598 } 2599 2600 static int sysc_notifier_call(struct notifier_block *nb, 2601 unsigned long event, void *device) 2602 { 2603 struct device *dev = device; 2604 struct sysc *ddata; 2605 int error; 2606 2607 ddata = sysc_child_to_parent(dev); 2608 if (!ddata) 2609 return NOTIFY_DONE; 2610 2611 switch (event) { 2612 case BUS_NOTIFY_ADD_DEVICE: 2613 error = sysc_child_add_clocks(ddata, dev); 2614 if (error) 2615 return error; 2616 sysc_legacy_idle_quirk(ddata, dev); 2617 break; 2618 default: 2619 break; 2620 } 2621 2622 return NOTIFY_DONE; 2623 } 2624 2625 static struct notifier_block sysc_nb = { 2626 .notifier_call = sysc_notifier_call, 2627 }; 2628 2629 /* Device tree configured quirks */ 2630 struct sysc_dts_quirk { 2631 const char *name; 2632 u32 mask; 2633 }; 2634 2635 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2636 { .name = "ti,no-idle-on-init", 2637 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2638 { .name = "ti,no-reset-on-init", 2639 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2640 { .name = "ti,no-idle", 2641 .mask = SYSC_QUIRK_NO_IDLE, }, 2642 }; 2643 2644 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2645 bool is_child) 2646 { 2647 const struct property *prop; 2648 int i, len; 2649 2650 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2651 const char *name = sysc_dts_quirks[i].name; 2652 2653 prop = of_get_property(np, name, &len); 2654 if (!prop) 2655 continue; 2656 2657 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2658 if (is_child) { 2659 dev_warn(ddata->dev, 2660 "dts flag should be at module level for %s\n", 2661 name); 2662 } 2663 } 2664 } 2665 2666 static int sysc_init_dts_quirks(struct sysc *ddata) 2667 { 2668 struct device_node *np = ddata->dev->of_node; 2669 int error; 2670 u32 val; 2671 2672 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2673 2674 sysc_parse_dts_quirks(ddata, np, false); 2675 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2676 if (!error) { 2677 if (val > 255) { 2678 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2679 val); 2680 } 2681 2682 ddata->cfg.srst_udelay = (u8)val; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static void sysc_unprepare(struct sysc *ddata) 2689 { 2690 int i; 2691 2692 if (!ddata->clocks) 2693 return; 2694 2695 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2696 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2697 clk_unprepare(ddata->clocks[i]); 2698 } 2699 } 2700 2701 /* 2702 * Common sysc register bits found on omap2, also known as type1 2703 */ 2704 static const struct sysc_regbits sysc_regbits_omap2 = { 2705 .dmadisable_shift = -ENODEV, 2706 .midle_shift = 12, 2707 .sidle_shift = 3, 2708 .clkact_shift = 8, 2709 .emufree_shift = 5, 2710 .enwkup_shift = 2, 2711 .srst_shift = 1, 2712 .autoidle_shift = 0, 2713 }; 2714 2715 static const struct sysc_capabilities sysc_omap2 = { 2716 .type = TI_SYSC_OMAP2, 2717 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2718 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2719 SYSC_OMAP2_AUTOIDLE, 2720 .regbits = &sysc_regbits_omap2, 2721 }; 2722 2723 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2724 static const struct sysc_capabilities sysc_omap2_timer = { 2725 .type = TI_SYSC_OMAP2_TIMER, 2726 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2727 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2728 SYSC_OMAP2_AUTOIDLE, 2729 .regbits = &sysc_regbits_omap2, 2730 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2731 }; 2732 2733 /* 2734 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2735 * with different sidle position 2736 */ 2737 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2738 .dmadisable_shift = -ENODEV, 2739 .midle_shift = -ENODEV, 2740 .sidle_shift = 4, 2741 .clkact_shift = -ENODEV, 2742 .enwkup_shift = -ENODEV, 2743 .srst_shift = 1, 2744 .autoidle_shift = 0, 2745 .emufree_shift = -ENODEV, 2746 }; 2747 2748 static const struct sysc_capabilities sysc_omap3_sham = { 2749 .type = TI_SYSC_OMAP3_SHAM, 2750 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2751 .regbits = &sysc_regbits_omap3_sham, 2752 }; 2753 2754 /* 2755 * AES register bits found on omap3 and later, a variant of 2756 * sysc_regbits_omap2 with different sidle position 2757 */ 2758 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2759 .dmadisable_shift = -ENODEV, 2760 .midle_shift = -ENODEV, 2761 .sidle_shift = 6, 2762 .clkact_shift = -ENODEV, 2763 .enwkup_shift = -ENODEV, 2764 .srst_shift = 1, 2765 .autoidle_shift = 0, 2766 .emufree_shift = -ENODEV, 2767 }; 2768 2769 static const struct sysc_capabilities sysc_omap3_aes = { 2770 .type = TI_SYSC_OMAP3_AES, 2771 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2772 .regbits = &sysc_regbits_omap3_aes, 2773 }; 2774 2775 /* 2776 * Common sysc register bits found on omap4, also known as type2 2777 */ 2778 static const struct sysc_regbits sysc_regbits_omap4 = { 2779 .dmadisable_shift = 16, 2780 .midle_shift = 4, 2781 .sidle_shift = 2, 2782 .clkact_shift = -ENODEV, 2783 .enwkup_shift = -ENODEV, 2784 .emufree_shift = 1, 2785 .srst_shift = 0, 2786 .autoidle_shift = -ENODEV, 2787 }; 2788 2789 static const struct sysc_capabilities sysc_omap4 = { 2790 .type = TI_SYSC_OMAP4, 2791 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2792 SYSC_OMAP4_SOFTRESET, 2793 .regbits = &sysc_regbits_omap4, 2794 }; 2795 2796 static const struct sysc_capabilities sysc_omap4_timer = { 2797 .type = TI_SYSC_OMAP4_TIMER, 2798 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2799 SYSC_OMAP4_SOFTRESET, 2800 .regbits = &sysc_regbits_omap4, 2801 }; 2802 2803 /* 2804 * Common sysc register bits found on omap4, also known as type3 2805 */ 2806 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2807 .dmadisable_shift = -ENODEV, 2808 .midle_shift = 2, 2809 .sidle_shift = 0, 2810 .clkact_shift = -ENODEV, 2811 .enwkup_shift = -ENODEV, 2812 .srst_shift = -ENODEV, 2813 .emufree_shift = -ENODEV, 2814 .autoidle_shift = -ENODEV, 2815 }; 2816 2817 static const struct sysc_capabilities sysc_omap4_simple = { 2818 .type = TI_SYSC_OMAP4_SIMPLE, 2819 .regbits = &sysc_regbits_omap4_simple, 2820 }; 2821 2822 /* 2823 * SmartReflex sysc found on omap34xx 2824 */ 2825 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2826 .dmadisable_shift = -ENODEV, 2827 .midle_shift = -ENODEV, 2828 .sidle_shift = -ENODEV, 2829 .clkact_shift = 20, 2830 .enwkup_shift = -ENODEV, 2831 .srst_shift = -ENODEV, 2832 .emufree_shift = -ENODEV, 2833 .autoidle_shift = -ENODEV, 2834 }; 2835 2836 static const struct sysc_capabilities sysc_34xx_sr = { 2837 .type = TI_SYSC_OMAP34XX_SR, 2838 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2839 .regbits = &sysc_regbits_omap34xx_sr, 2840 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2841 SYSC_QUIRK_LEGACY_IDLE, 2842 }; 2843 2844 /* 2845 * SmartReflex sysc found on omap36xx and later 2846 */ 2847 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2848 .dmadisable_shift = -ENODEV, 2849 .midle_shift = -ENODEV, 2850 .sidle_shift = 24, 2851 .clkact_shift = -ENODEV, 2852 .enwkup_shift = 26, 2853 .srst_shift = -ENODEV, 2854 .emufree_shift = -ENODEV, 2855 .autoidle_shift = -ENODEV, 2856 }; 2857 2858 static const struct sysc_capabilities sysc_36xx_sr = { 2859 .type = TI_SYSC_OMAP36XX_SR, 2860 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2861 .regbits = &sysc_regbits_omap36xx_sr, 2862 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2863 }; 2864 2865 static const struct sysc_capabilities sysc_omap4_sr = { 2866 .type = TI_SYSC_OMAP4_SR, 2867 .regbits = &sysc_regbits_omap36xx_sr, 2868 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2869 }; 2870 2871 /* 2872 * McASP register bits found on omap4 and later 2873 */ 2874 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2875 .dmadisable_shift = -ENODEV, 2876 .midle_shift = -ENODEV, 2877 .sidle_shift = 0, 2878 .clkact_shift = -ENODEV, 2879 .enwkup_shift = -ENODEV, 2880 .srst_shift = -ENODEV, 2881 .emufree_shift = -ENODEV, 2882 .autoidle_shift = -ENODEV, 2883 }; 2884 2885 static const struct sysc_capabilities sysc_omap4_mcasp = { 2886 .type = TI_SYSC_OMAP4_MCASP, 2887 .regbits = &sysc_regbits_omap4_mcasp, 2888 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2889 }; 2890 2891 /* 2892 * McASP found on dra7 and later 2893 */ 2894 static const struct sysc_capabilities sysc_dra7_mcasp = { 2895 .type = TI_SYSC_OMAP4_SIMPLE, 2896 .regbits = &sysc_regbits_omap4_simple, 2897 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2898 }; 2899 2900 /* 2901 * FS USB host found on omap4 and later 2902 */ 2903 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2904 .dmadisable_shift = -ENODEV, 2905 .midle_shift = -ENODEV, 2906 .sidle_shift = 24, 2907 .clkact_shift = -ENODEV, 2908 .enwkup_shift = 26, 2909 .srst_shift = -ENODEV, 2910 .emufree_shift = -ENODEV, 2911 .autoidle_shift = -ENODEV, 2912 }; 2913 2914 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2915 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2916 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2917 .regbits = &sysc_regbits_omap4_usb_host_fs, 2918 }; 2919 2920 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2921 .dmadisable_shift = -ENODEV, 2922 .midle_shift = -ENODEV, 2923 .sidle_shift = -ENODEV, 2924 .clkact_shift = -ENODEV, 2925 .enwkup_shift = 4, 2926 .srst_shift = 0, 2927 .emufree_shift = -ENODEV, 2928 .autoidle_shift = -ENODEV, 2929 }; 2930 2931 static const struct sysc_capabilities sysc_dra7_mcan = { 2932 .type = TI_SYSC_DRA7_MCAN, 2933 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2934 .regbits = &sysc_regbits_dra7_mcan, 2935 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2936 }; 2937 2938 /* 2939 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2940 */ 2941 static const struct sysc_capabilities sysc_pruss = { 2942 .type = TI_SYSC_PRUSS, 2943 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2944 .regbits = &sysc_regbits_omap4_simple, 2945 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2946 }; 2947 2948 static int sysc_init_pdata(struct sysc *ddata) 2949 { 2950 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2951 struct ti_sysc_module_data *mdata; 2952 2953 if (!pdata) 2954 return 0; 2955 2956 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2957 if (!mdata) 2958 return -ENOMEM; 2959 2960 if (ddata->legacy_mode) { 2961 mdata->name = ddata->legacy_mode; 2962 mdata->module_pa = ddata->module_pa; 2963 mdata->module_size = ddata->module_size; 2964 mdata->offsets = ddata->offsets; 2965 mdata->nr_offsets = SYSC_MAX_REGS; 2966 mdata->cap = ddata->cap; 2967 mdata->cfg = &ddata->cfg; 2968 } 2969 2970 ddata->mdata = mdata; 2971 2972 return 0; 2973 } 2974 2975 static int sysc_init_match(struct sysc *ddata) 2976 { 2977 const struct sysc_capabilities *cap; 2978 2979 cap = of_device_get_match_data(ddata->dev); 2980 if (!cap) 2981 return -EINVAL; 2982 2983 ddata->cap = cap; 2984 if (ddata->cap) 2985 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2986 2987 return 0; 2988 } 2989 2990 static void ti_sysc_idle(struct work_struct *work) 2991 { 2992 struct sysc *ddata; 2993 2994 ddata = container_of(work, struct sysc, idle_work.work); 2995 2996 /* 2997 * One time decrement of clock usage counts if left on from init. 2998 * Note that we disable opt clocks unconditionally in this case 2999 * as they are enabled unconditionally during init without 3000 * considering sysc_opt_clks_needed() at that point. 3001 */ 3002 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3003 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 3004 sysc_disable_main_clocks(ddata); 3005 sysc_disable_opt_clocks(ddata); 3006 sysc_clkdm_allow_idle(ddata); 3007 } 3008 3009 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 3010 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 3011 return; 3012 3013 /* 3014 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 3015 * and SYSC_QUIRK_NO_RESET_ON_INIT 3016 */ 3017 if (pm_runtime_active(ddata->dev)) 3018 pm_runtime_put_sync(ddata->dev); 3019 } 3020 3021 /* 3022 * SoC model and features detection. Only needed for SoCs that need 3023 * special handling for quirks, no need to list others. 3024 */ 3025 static const struct soc_device_attribute sysc_soc_match[] = { 3026 SOC_FLAG("OMAP242*", SOC_2420), 3027 SOC_FLAG("OMAP243*", SOC_2430), 3028 SOC_FLAG("AM35*", SOC_AM35), 3029 SOC_FLAG("OMAP3[45]*", SOC_3430), 3030 SOC_FLAG("OMAP3[67]*", SOC_3630), 3031 SOC_FLAG("OMAP443*", SOC_4430), 3032 SOC_FLAG("OMAP446*", SOC_4460), 3033 SOC_FLAG("OMAP447*", SOC_4470), 3034 SOC_FLAG("OMAP54*", SOC_5430), 3035 SOC_FLAG("AM433", SOC_AM3), 3036 SOC_FLAG("AM43*", SOC_AM4), 3037 SOC_FLAG("DRA7*", SOC_DRA7), 3038 3039 { /* sentinel */ } 3040 }; 3041 3042 /* 3043 * List of SoCs variants with disabled features. By default we assume all 3044 * devices in the device tree are available so no need to list those SoCs. 3045 */ 3046 static const struct soc_device_attribute sysc_soc_feat_match[] = { 3047 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 3048 SOC_FLAG("AM3505", DIS_SGX), 3049 SOC_FLAG("OMAP3525", DIS_SGX), 3050 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 3051 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 3052 3053 /* OMAP3630/DM3730 variants with some accelerators disabled */ 3054 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 3055 SOC_FLAG("DM3725", DIS_SGX), 3056 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 3057 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 3058 SOC_FLAG("OMAP3621", DIS_ISP), 3059 3060 { /* sentinel */ } 3061 }; 3062 3063 static int sysc_add_disabled(unsigned long base) 3064 { 3065 struct sysc_address *disabled_module; 3066 3067 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 3068 if (!disabled_module) 3069 return -ENOMEM; 3070 3071 disabled_module->base = base; 3072 3073 mutex_lock(&sysc_soc->list_lock); 3074 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 3075 mutex_unlock(&sysc_soc->list_lock); 3076 3077 return 0; 3078 } 3079 3080 /* 3081 * One time init to detect the booted SoC, disable unavailable features 3082 * and initialize list for optional cpu_pm notifier. 3083 * 3084 * Note that we initialize static data shared across all ti-sysc instances 3085 * so ddata is only used for SoC type. This can be called from module_init 3086 * once we no longer need to rely on platform data. 3087 */ 3088 static int sysc_init_static_data(struct sysc *ddata) 3089 { 3090 const struct soc_device_attribute *match; 3091 struct ti_sysc_platform_data *pdata; 3092 unsigned long features = 0; 3093 struct device_node *np; 3094 3095 if (sysc_soc) 3096 return 0; 3097 3098 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 3099 if (!sysc_soc) 3100 return -ENOMEM; 3101 3102 mutex_init(&sysc_soc->list_lock); 3103 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 3104 INIT_LIST_HEAD(&sysc_soc->restored_modules); 3105 sysc_soc->general_purpose = true; 3106 3107 pdata = dev_get_platdata(ddata->dev); 3108 if (pdata && pdata->soc_type_gp) 3109 sysc_soc->general_purpose = pdata->soc_type_gp(); 3110 3111 match = soc_device_match(sysc_soc_match); 3112 if (match && match->data) 3113 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data; 3114 3115 /* 3116 * Check and warn about possible old incomplete dtb. We now want to see 3117 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 3118 */ 3119 switch (sysc_soc->soc) { 3120 case SOC_AM3: 3121 case SOC_AM4: 3122 case SOC_4430 ... SOC_4470: 3123 case SOC_5430: 3124 case SOC_DRA7: 3125 np = of_find_node_by_path("/ocp"); 3126 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 3127 "ti-sysc: Incomplete old dtb, please update\n"); 3128 break; 3129 default: 3130 break; 3131 } 3132 3133 /* Ignore devices that are not available on HS and EMU SoCs */ 3134 if (!sysc_soc->general_purpose) { 3135 switch (sysc_soc->soc) { 3136 case SOC_3430 ... SOC_3630: 3137 sysc_add_disabled(0x48304000); /* timer12 */ 3138 break; 3139 case SOC_AM3: 3140 sysc_add_disabled(0x48310000); /* rng */ 3141 break; 3142 default: 3143 break; 3144 } 3145 } 3146 3147 match = soc_device_match(sysc_soc_feat_match); 3148 if (!match) 3149 return 0; 3150 3151 if (match->data) 3152 features = (unsigned long)match->data; 3153 3154 /* 3155 * Add disabled devices to the list based on the module base. 3156 * Note that this must be done before we attempt to access the 3157 * device and have module revision checks working. 3158 */ 3159 if (features & DIS_ISP) 3160 sysc_add_disabled(0x480bd400); 3161 if (features & DIS_IVA) 3162 sysc_add_disabled(0x5d000000); 3163 if (features & DIS_SGX) 3164 sysc_add_disabled(0x50000000); 3165 3166 return 0; 3167 } 3168 3169 static void sysc_cleanup_static_data(void) 3170 { 3171 struct sysc_module *restored_module; 3172 struct sysc_address *disabled_module; 3173 struct list_head *pos, *tmp; 3174 3175 if (!sysc_soc) 3176 return; 3177 3178 if (sysc_soc->nb.notifier_call) 3179 cpu_pm_unregister_notifier(&sysc_soc->nb); 3180 3181 mutex_lock(&sysc_soc->list_lock); 3182 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { 3183 restored_module = list_entry(pos, struct sysc_module, node); 3184 list_del(pos); 3185 kfree(restored_module); 3186 } 3187 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 3188 disabled_module = list_entry(pos, struct sysc_address, node); 3189 list_del(pos); 3190 kfree(disabled_module); 3191 } 3192 mutex_unlock(&sysc_soc->list_lock); 3193 } 3194 3195 static int sysc_check_disabled_devices(struct sysc *ddata) 3196 { 3197 struct sysc_address *disabled_module; 3198 int error = 0; 3199 3200 mutex_lock(&sysc_soc->list_lock); 3201 list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) { 3202 if (ddata->module_pa == disabled_module->base) { 3203 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3204 error = -ENODEV; 3205 break; 3206 } 3207 } 3208 mutex_unlock(&sysc_soc->list_lock); 3209 3210 return error; 3211 } 3212 3213 /* 3214 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3215 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3216 * are needed, we could also look at the timer register configuration. 3217 */ 3218 static int sysc_check_active_timer(struct sysc *ddata) 3219 { 3220 int error; 3221 3222 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3223 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3224 return 0; 3225 3226 /* 3227 * Quirk for omap3 beagleboard revision A to B4 to use gpt12. 3228 * Revision C and later are fixed with commit 23885389dbbb ("ARM: 3229 * dts: Fix timer regression for beagleboard revision c"). This all 3230 * can be dropped if we stop supporting old beagleboard revisions 3231 * A to B4 at some point. 3232 */ 3233 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) 3234 error = -ENXIO; 3235 else 3236 error = -EBUSY; 3237 3238 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3239 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3240 return error; 3241 3242 return 0; 3243 } 3244 3245 static const struct of_device_id sysc_match_table[] = { 3246 { .compatible = "simple-bus", }, 3247 { /* sentinel */ }, 3248 }; 3249 3250 static int sysc_probe(struct platform_device *pdev) 3251 { 3252 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3253 struct sysc *ddata; 3254 int error; 3255 3256 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3257 if (!ddata) 3258 return -ENOMEM; 3259 3260 ddata->offsets[SYSC_REVISION] = -ENODEV; 3261 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3262 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3263 ddata->dev = &pdev->dev; 3264 platform_set_drvdata(pdev, ddata); 3265 3266 error = sysc_init_static_data(ddata); 3267 if (error) 3268 return error; 3269 3270 error = sysc_init_match(ddata); 3271 if (error) 3272 return error; 3273 3274 error = sysc_init_dts_quirks(ddata); 3275 if (error) 3276 return error; 3277 3278 error = sysc_map_and_check_registers(ddata); 3279 if (error) 3280 return error; 3281 3282 error = sysc_init_sysc_mask(ddata); 3283 if (error) 3284 return error; 3285 3286 error = sysc_init_idlemodes(ddata); 3287 if (error) 3288 return error; 3289 3290 error = sysc_init_syss_mask(ddata); 3291 if (error) 3292 return error; 3293 3294 error = sysc_init_pdata(ddata); 3295 if (error) 3296 return error; 3297 3298 sysc_init_early_quirks(ddata); 3299 3300 error = sysc_check_disabled_devices(ddata); 3301 if (error) 3302 return error; 3303 3304 error = sysc_check_active_timer(ddata); 3305 if (error == -ENXIO) 3306 ddata->reserved = true; 3307 else if (error) 3308 return error; 3309 3310 error = sysc_get_clocks(ddata); 3311 if (error) 3312 return error; 3313 3314 error = sysc_init_resets(ddata); 3315 if (error) 3316 goto unprepare; 3317 3318 error = sysc_init_module(ddata); 3319 if (error) 3320 goto unprepare; 3321 3322 pm_runtime_enable(ddata->dev); 3323 error = pm_runtime_resume_and_get(ddata->dev); 3324 if (error < 0) { 3325 pm_runtime_disable(ddata->dev); 3326 goto unprepare; 3327 } 3328 3329 /* Balance use counts as PM runtime should have enabled these all */ 3330 if (!(ddata->cfg.quirks & 3331 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3332 sysc_disable_main_clocks(ddata); 3333 sysc_disable_opt_clocks(ddata); 3334 sysc_clkdm_allow_idle(ddata); 3335 } 3336 3337 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3338 reset_control_assert(ddata->rsts); 3339 3340 sysc_show_registers(ddata); 3341 3342 ddata->dev->type = &sysc_device_type; 3343 3344 if (!ddata->reserved) { 3345 error = of_platform_populate(ddata->dev->of_node, 3346 sysc_match_table, 3347 pdata ? pdata->auxdata : NULL, 3348 ddata->dev); 3349 if (error) 3350 goto err; 3351 } 3352 3353 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3354 3355 /* At least earlycon won't survive without deferred idle */ 3356 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3357 SYSC_QUIRK_NO_IDLE_ON_INIT | 3358 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3359 schedule_delayed_work(&ddata->idle_work, 3000); 3360 } else { 3361 pm_runtime_put(&pdev->dev); 3362 } 3363 3364 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) 3365 sysc_add_restored(ddata); 3366 3367 return 0; 3368 3369 err: 3370 pm_runtime_put_sync(&pdev->dev); 3371 pm_runtime_disable(&pdev->dev); 3372 unprepare: 3373 sysc_unprepare(ddata); 3374 3375 return error; 3376 } 3377 3378 static int sysc_remove(struct platform_device *pdev) 3379 { 3380 struct sysc *ddata = platform_get_drvdata(pdev); 3381 int error; 3382 3383 /* Device can still be enabled, see deferred idle quirk in probe */ 3384 if (cancel_delayed_work_sync(&ddata->idle_work)) 3385 ti_sysc_idle(&ddata->idle_work.work); 3386 3387 error = pm_runtime_resume_and_get(ddata->dev); 3388 if (error < 0) { 3389 pm_runtime_disable(ddata->dev); 3390 goto unprepare; 3391 } 3392 3393 of_platform_depopulate(&pdev->dev); 3394 3395 pm_runtime_put_sync(&pdev->dev); 3396 pm_runtime_disable(&pdev->dev); 3397 3398 if (!reset_control_status(ddata->rsts)) 3399 reset_control_assert(ddata->rsts); 3400 3401 unprepare: 3402 sysc_unprepare(ddata); 3403 3404 return 0; 3405 } 3406 3407 static const struct of_device_id sysc_match[] = { 3408 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3409 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3410 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3411 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3412 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3413 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3414 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3415 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3416 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3417 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3418 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3419 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3420 { .compatible = "ti,sysc-usb-host-fs", 3421 .data = &sysc_omap4_usb_host_fs, }, 3422 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3423 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3424 { }, 3425 }; 3426 MODULE_DEVICE_TABLE(of, sysc_match); 3427 3428 static struct platform_driver sysc_driver = { 3429 .probe = sysc_probe, 3430 .remove = sysc_remove, 3431 .driver = { 3432 .name = "ti-sysc", 3433 .of_match_table = sysc_match, 3434 .pm = &sysc_pm_ops, 3435 }, 3436 }; 3437 3438 static int __init sysc_init(void) 3439 { 3440 bus_register_notifier(&platform_bus_type, &sysc_nb); 3441 3442 return platform_driver_register(&sysc_driver); 3443 } 3444 module_init(sysc_init); 3445 3446 static void __exit sysc_exit(void) 3447 { 3448 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3449 platform_driver_unregister(&sysc_driver); 3450 sysc_cleanup_static_data(); 3451 } 3452 module_exit(sysc_exit); 3453 3454 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3455 MODULE_LICENSE("GPL v2"); 3456