1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Tejun Heo <[email protected]> 5 * Please ALWAYS copy [email protected] 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/device.h> 43 #include <linux/dmi.h> 44 #include <linux/gfp.h> 45 #include <linux/msi.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <linux/libata.h> 49 #include "ahci.h" 50 51 #define DRV_NAME "ahci" 52 #define DRV_VERSION "3.0" 53 54 enum { 55 AHCI_PCI_BAR_STA2X11 = 0, 56 AHCI_PCI_BAR_CAVIUM = 0, 57 AHCI_PCI_BAR_ENMOTUS = 2, 58 AHCI_PCI_BAR_STANDARD = 5, 59 }; 60 61 enum board_ids { 62 /* board IDs by feature in alphabetical order */ 63 board_ahci, 64 board_ahci_ign_iferr, 65 board_ahci_nomsi, 66 board_ahci_noncq, 67 board_ahci_nosntf, 68 board_ahci_yes_fbs, 69 70 /* board IDs for specific chipsets in alphabetical order */ 71 board_ahci_avn, 72 board_ahci_mcp65, 73 board_ahci_mcp77, 74 board_ahci_mcp89, 75 board_ahci_mv, 76 board_ahci_sb600, 77 board_ahci_sb700, /* for SB700 and SB800 */ 78 board_ahci_vt8251, 79 80 /* aliases */ 81 board_ahci_mcp_linux = board_ahci_mcp65, 82 board_ahci_mcp67 = board_ahci_mcp65, 83 board_ahci_mcp73 = board_ahci_mcp65, 84 board_ahci_mcp79 = board_ahci_mcp77, 85 }; 86 87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 91 unsigned long deadline); 92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 93 static bool is_mcp89_apple(struct pci_dev *pdev); 94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 95 unsigned long deadline); 96 #ifdef CONFIG_PM 97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 98 static int ahci_pci_device_resume(struct pci_dev *pdev); 99 #endif 100 101 static struct scsi_host_template ahci_sht = { 102 AHCI_SHT("ahci"), 103 }; 104 105 static struct ata_port_operations ahci_vt8251_ops = { 106 .inherits = &ahci_ops, 107 .hardreset = ahci_vt8251_hardreset, 108 }; 109 110 static struct ata_port_operations ahci_p5wdh_ops = { 111 .inherits = &ahci_ops, 112 .hardreset = ahci_p5wdh_hardreset, 113 }; 114 115 static struct ata_port_operations ahci_avn_ops = { 116 .inherits = &ahci_ops, 117 .hardreset = ahci_avn_hardreset, 118 }; 119 120 static const struct ata_port_info ahci_port_info[] = { 121 /* by features */ 122 [board_ahci] = { 123 .flags = AHCI_FLAG_COMMON, 124 .pio_mask = ATA_PIO4, 125 .udma_mask = ATA_UDMA6, 126 .port_ops = &ahci_ops, 127 }, 128 [board_ahci_ign_iferr] = { 129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 130 .flags = AHCI_FLAG_COMMON, 131 .pio_mask = ATA_PIO4, 132 .udma_mask = ATA_UDMA6, 133 .port_ops = &ahci_ops, 134 }, 135 [board_ahci_nomsi] = { 136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 137 .flags = AHCI_FLAG_COMMON, 138 .pio_mask = ATA_PIO4, 139 .udma_mask = ATA_UDMA6, 140 .port_ops = &ahci_ops, 141 }, 142 [board_ahci_noncq] = { 143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 144 .flags = AHCI_FLAG_COMMON, 145 .pio_mask = ATA_PIO4, 146 .udma_mask = ATA_UDMA6, 147 .port_ops = &ahci_ops, 148 }, 149 [board_ahci_nosntf] = { 150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 151 .flags = AHCI_FLAG_COMMON, 152 .pio_mask = ATA_PIO4, 153 .udma_mask = ATA_UDMA6, 154 .port_ops = &ahci_ops, 155 }, 156 [board_ahci_yes_fbs] = { 157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 158 .flags = AHCI_FLAG_COMMON, 159 .pio_mask = ATA_PIO4, 160 .udma_mask = ATA_UDMA6, 161 .port_ops = &ahci_ops, 162 }, 163 /* by chipsets */ 164 [board_ahci_avn] = { 165 .flags = AHCI_FLAG_COMMON, 166 .pio_mask = ATA_PIO4, 167 .udma_mask = ATA_UDMA6, 168 .port_ops = &ahci_avn_ops, 169 }, 170 [board_ahci_mcp65] = { 171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 172 AHCI_HFLAG_YES_NCQ), 173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 174 .pio_mask = ATA_PIO4, 175 .udma_mask = ATA_UDMA6, 176 .port_ops = &ahci_ops, 177 }, 178 [board_ahci_mcp77] = { 179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 180 .flags = AHCI_FLAG_COMMON, 181 .pio_mask = ATA_PIO4, 182 .udma_mask = ATA_UDMA6, 183 .port_ops = &ahci_ops, 184 }, 185 [board_ahci_mcp89] = { 186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 187 .flags = AHCI_FLAG_COMMON, 188 .pio_mask = ATA_PIO4, 189 .udma_mask = ATA_UDMA6, 190 .port_ops = &ahci_ops, 191 }, 192 [board_ahci_mv] = { 193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 196 .pio_mask = ATA_PIO4, 197 .udma_mask = ATA_UDMA6, 198 .port_ops = &ahci_ops, 199 }, 200 [board_ahci_sb600] = { 201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 203 AHCI_HFLAG_32BIT_ONLY), 204 .flags = AHCI_FLAG_COMMON, 205 .pio_mask = ATA_PIO4, 206 .udma_mask = ATA_UDMA6, 207 .port_ops = &ahci_pmp_retry_srst_ops, 208 }, 209 [board_ahci_sb700] = { /* for SB700 and SB800 */ 210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 211 .flags = AHCI_FLAG_COMMON, 212 .pio_mask = ATA_PIO4, 213 .udma_mask = ATA_UDMA6, 214 .port_ops = &ahci_pmp_retry_srst_ops, 215 }, 216 [board_ahci_vt8251] = { 217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 218 .flags = AHCI_FLAG_COMMON, 219 .pio_mask = ATA_PIO4, 220 .udma_mask = ATA_UDMA6, 221 .port_ops = &ahci_vt8251_ops, 222 }, 223 }; 224 225 static const struct pci_device_id ahci_pci_tbl[] = { 226 /* Intel */ 227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ 264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 267 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 268 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ 269 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 270 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ 271 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 272 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 273 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 274 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 275 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 276 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 277 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 278 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 279 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ 280 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 281 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 282 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 283 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ 284 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 285 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 286 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ 287 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 288 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ 289 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 290 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ 291 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 292 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ 293 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ 294 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ 295 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ 296 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ 297 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ 298 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ 299 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ 300 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ 301 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 302 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 303 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 304 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 305 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 306 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 307 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 308 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 309 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 310 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 311 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 312 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 313 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 314 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 315 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 316 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 317 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 318 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 319 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/ 320 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/ 321 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 322 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 323 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 324 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 325 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/ 326 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/ 327 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 328 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 329 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 330 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 331 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 332 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 333 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 334 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 335 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 336 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 337 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 338 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ 339 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ 342 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 343 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */ 344 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 345 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */ 346 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 347 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */ 348 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 349 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */ 350 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */ 351 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ 352 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ 353 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ 354 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 355 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ 356 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 357 358 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 359 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 360 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 361 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 362 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 363 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 364 /* May need to update quirk_jmicron_async_suspend() for additions */ 365 366 /* ATI */ 367 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 368 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 369 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 370 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 371 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 372 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 373 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 374 375 /* AMD */ 376 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 377 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 378 /* AMD is using RAID class only for ahci controllers */ 379 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 380 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 381 382 /* VIA */ 383 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 384 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 385 386 /* NVIDIA */ 387 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 388 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 389 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 390 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 391 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 392 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 393 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 394 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 395 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 396 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 397 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 398 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 399 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 400 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 401 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 402 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 403 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 404 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 405 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 406 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 407 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 408 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 409 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 410 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 411 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 412 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 413 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 414 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 415 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 416 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 417 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 418 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 419 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 420 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 421 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 422 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 423 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 424 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 425 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 426 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 427 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 428 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 429 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 430 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 431 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 432 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 433 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 434 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 435 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 436 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 437 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 438 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 439 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 440 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 441 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 442 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 443 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 444 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 445 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 446 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 447 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 448 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 449 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 450 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 451 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 452 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 453 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 454 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 455 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 456 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 457 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 458 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 459 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 460 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 461 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 462 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 463 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 464 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 465 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 466 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 467 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 468 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 469 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 470 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 471 472 /* SiS */ 473 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 474 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 475 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 476 477 /* ST Microelectronics */ 478 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 479 480 /* Marvell */ 481 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 482 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 483 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 484 .class = PCI_CLASS_STORAGE_SATA_AHCI, 485 .class_mask = 0xffffff, 486 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 487 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 488 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 489 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 490 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 491 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 492 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 493 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 494 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 495 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 496 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 497 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 498 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 499 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 500 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 501 .driver_data = board_ahci_yes_fbs }, 502 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 503 .driver_data = board_ahci_yes_fbs }, 504 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 505 .driver_data = board_ahci_yes_fbs }, 506 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 507 .driver_data = board_ahci_yes_fbs }, 508 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), 509 .driver_data = board_ahci_yes_fbs }, 510 511 /* Promise */ 512 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 513 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 514 515 /* Asmedia */ 516 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 517 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 518 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 519 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 520 521 /* 522 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 523 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 524 */ 525 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 526 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 527 528 /* Enmotus */ 529 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 530 531 /* Generic, PCI class code for AHCI */ 532 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 533 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 534 535 { } /* terminate list */ 536 }; 537 538 539 static struct pci_driver ahci_pci_driver = { 540 .name = DRV_NAME, 541 .id_table = ahci_pci_tbl, 542 .probe = ahci_init_one, 543 .remove = ata_pci_remove_one, 544 #ifdef CONFIG_PM 545 .suspend = ahci_pci_device_suspend, 546 .resume = ahci_pci_device_resume, 547 #endif 548 }; 549 550 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 551 static int marvell_enable; 552 #else 553 static int marvell_enable = 1; 554 #endif 555 module_param(marvell_enable, int, 0644); 556 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 557 558 559 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 560 struct ahci_host_priv *hpriv) 561 { 562 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 563 dev_info(&pdev->dev, "JMB361 has only one port\n"); 564 hpriv->force_port_map = 1; 565 } 566 567 /* 568 * Temporary Marvell 6145 hack: PATA port presence 569 * is asserted through the standard AHCI port 570 * presence register, as bit 4 (counting from 0) 571 */ 572 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 573 if (pdev->device == 0x6121) 574 hpriv->mask_port_map = 0x3; 575 else 576 hpriv->mask_port_map = 0xf; 577 dev_info(&pdev->dev, 578 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 579 } 580 581 ahci_save_initial_config(&pdev->dev, hpriv); 582 } 583 584 static int ahci_pci_reset_controller(struct ata_host *host) 585 { 586 struct pci_dev *pdev = to_pci_dev(host->dev); 587 588 ahci_reset_controller(host); 589 590 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 591 struct ahci_host_priv *hpriv = host->private_data; 592 u16 tmp16; 593 594 /* configure PCS */ 595 pci_read_config_word(pdev, 0x92, &tmp16); 596 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 597 tmp16 |= hpriv->port_map; 598 pci_write_config_word(pdev, 0x92, tmp16); 599 } 600 } 601 602 return 0; 603 } 604 605 static void ahci_pci_init_controller(struct ata_host *host) 606 { 607 struct ahci_host_priv *hpriv = host->private_data; 608 struct pci_dev *pdev = to_pci_dev(host->dev); 609 void __iomem *port_mmio; 610 u32 tmp; 611 int mv; 612 613 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 614 if (pdev->device == 0x6121) 615 mv = 2; 616 else 617 mv = 4; 618 port_mmio = __ahci_port_base(host, mv); 619 620 writel(0, port_mmio + PORT_IRQ_MASK); 621 622 /* clear port IRQ */ 623 tmp = readl(port_mmio + PORT_IRQ_STAT); 624 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 625 if (tmp) 626 writel(tmp, port_mmio + PORT_IRQ_STAT); 627 } 628 629 ahci_init_controller(host); 630 } 631 632 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 633 unsigned long deadline) 634 { 635 struct ata_port *ap = link->ap; 636 struct ahci_host_priv *hpriv = ap->host->private_data; 637 bool online; 638 int rc; 639 640 DPRINTK("ENTER\n"); 641 642 ahci_stop_engine(ap); 643 644 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 645 deadline, &online, NULL); 646 647 hpriv->start_engine(ap); 648 649 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 650 651 /* vt8251 doesn't clear BSY on signature FIS reception, 652 * request follow-up softreset. 653 */ 654 return online ? -EAGAIN : rc; 655 } 656 657 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 658 unsigned long deadline) 659 { 660 struct ata_port *ap = link->ap; 661 struct ahci_port_priv *pp = ap->private_data; 662 struct ahci_host_priv *hpriv = ap->host->private_data; 663 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 664 struct ata_taskfile tf; 665 bool online; 666 int rc; 667 668 ahci_stop_engine(ap); 669 670 /* clear D2H reception area to properly wait for D2H FIS */ 671 ata_tf_init(link->device, &tf); 672 tf.command = ATA_BUSY; 673 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 674 675 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 676 deadline, &online, NULL); 677 678 hpriv->start_engine(ap); 679 680 /* The pseudo configuration device on SIMG4726 attached to 681 * ASUS P5W-DH Deluxe doesn't send signature FIS after 682 * hardreset if no device is attached to the first downstream 683 * port && the pseudo device locks up on SRST w/ PMP==0. To 684 * work around this, wait for !BSY only briefly. If BSY isn't 685 * cleared, perform CLO and proceed to IDENTIFY (achieved by 686 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 687 * 688 * Wait for two seconds. Devices attached to downstream port 689 * which can't process the following IDENTIFY after this will 690 * have to be reset again. For most cases, this should 691 * suffice while making probing snappish enough. 692 */ 693 if (online) { 694 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 695 ahci_check_ready); 696 if (rc) 697 ahci_kick_engine(ap); 698 } 699 return rc; 700 } 701 702 /* 703 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 704 * 705 * It has been observed with some SSDs that the timing of events in the 706 * link synchronization phase can leave the port in a state that can not 707 * be recovered by a SATA-hard-reset alone. The failing signature is 708 * SStatus.DET stuck at 1 ("Device presence detected but Phy 709 * communication not established"). It was found that unloading and 710 * reloading the driver when this problem occurs allows the drive 711 * connection to be recovered (DET advanced to 0x3). The critical 712 * component of reloading the driver is that the port state machines are 713 * reset by bouncing "port enable" in the AHCI PCS configuration 714 * register. So, reproduce that effect by bouncing a port whenever we 715 * see DET==1 after a reset. 716 */ 717 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 718 unsigned long deadline) 719 { 720 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 721 struct ata_port *ap = link->ap; 722 struct ahci_port_priv *pp = ap->private_data; 723 struct ahci_host_priv *hpriv = ap->host->private_data; 724 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 725 unsigned long tmo = deadline - jiffies; 726 struct ata_taskfile tf; 727 bool online; 728 int rc, i; 729 730 DPRINTK("ENTER\n"); 731 732 ahci_stop_engine(ap); 733 734 for (i = 0; i < 2; i++) { 735 u16 val; 736 u32 sstatus; 737 int port = ap->port_no; 738 struct ata_host *host = ap->host; 739 struct pci_dev *pdev = to_pci_dev(host->dev); 740 741 /* clear D2H reception area to properly wait for D2H FIS */ 742 ata_tf_init(link->device, &tf); 743 tf.command = ATA_BUSY; 744 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 745 746 rc = sata_link_hardreset(link, timing, deadline, &online, 747 ahci_check_ready); 748 749 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 750 (sstatus & 0xf) != 1) 751 break; 752 753 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 754 port); 755 756 pci_read_config_word(pdev, 0x92, &val); 757 val &= ~(1 << port); 758 pci_write_config_word(pdev, 0x92, val); 759 ata_msleep(ap, 1000); 760 val |= 1 << port; 761 pci_write_config_word(pdev, 0x92, val); 762 deadline += tmo; 763 } 764 765 hpriv->start_engine(ap); 766 767 if (online) 768 *class = ahci_dev_classify(ap); 769 770 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 771 return rc; 772 } 773 774 775 #ifdef CONFIG_PM 776 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 777 { 778 struct ata_host *host = pci_get_drvdata(pdev); 779 struct ahci_host_priv *hpriv = host->private_data; 780 void __iomem *mmio = hpriv->mmio; 781 u32 ctl; 782 783 if (mesg.event & PM_EVENT_SUSPEND && 784 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 785 dev_err(&pdev->dev, 786 "BIOS update required for suspend/resume\n"); 787 return -EIO; 788 } 789 790 if (mesg.event & PM_EVENT_SLEEP) { 791 /* AHCI spec rev1.1 section 8.3.3: 792 * Software must disable interrupts prior to requesting a 793 * transition of the HBA to D3 state. 794 */ 795 ctl = readl(mmio + HOST_CTL); 796 ctl &= ~HOST_IRQ_EN; 797 writel(ctl, mmio + HOST_CTL); 798 readl(mmio + HOST_CTL); /* flush */ 799 } 800 801 return ata_pci_device_suspend(pdev, mesg); 802 } 803 804 static int ahci_pci_device_resume(struct pci_dev *pdev) 805 { 806 struct ata_host *host = pci_get_drvdata(pdev); 807 int rc; 808 809 rc = ata_pci_device_do_resume(pdev); 810 if (rc) 811 return rc; 812 813 /* Apple BIOS helpfully mangles the registers on resume */ 814 if (is_mcp89_apple(pdev)) 815 ahci_mcp89_apple_enable(pdev); 816 817 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 818 rc = ahci_pci_reset_controller(host); 819 if (rc) 820 return rc; 821 822 ahci_pci_init_controller(host); 823 } 824 825 ata_host_resume(host); 826 827 return 0; 828 } 829 #endif 830 831 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 832 { 833 int rc; 834 835 /* 836 * If the device fixup already set the dma_mask to some non-standard 837 * value, don't extend it here. This happens on STA2X11, for example. 838 */ 839 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 840 return 0; 841 842 if (using_dac && 843 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 844 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 845 if (rc) { 846 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 847 if (rc) { 848 dev_err(&pdev->dev, 849 "64-bit DMA enable failed\n"); 850 return rc; 851 } 852 } 853 } else { 854 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 855 if (rc) { 856 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 857 return rc; 858 } 859 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 860 if (rc) { 861 dev_err(&pdev->dev, 862 "32-bit consistent DMA enable failed\n"); 863 return rc; 864 } 865 } 866 return 0; 867 } 868 869 static void ahci_pci_print_info(struct ata_host *host) 870 { 871 struct pci_dev *pdev = to_pci_dev(host->dev); 872 u16 cc; 873 const char *scc_s; 874 875 pci_read_config_word(pdev, 0x0a, &cc); 876 if (cc == PCI_CLASS_STORAGE_IDE) 877 scc_s = "IDE"; 878 else if (cc == PCI_CLASS_STORAGE_SATA) 879 scc_s = "SATA"; 880 else if (cc == PCI_CLASS_STORAGE_RAID) 881 scc_s = "RAID"; 882 else 883 scc_s = "unknown"; 884 885 ahci_print_info(host, scc_s); 886 } 887 888 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 889 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 890 * support PMP and the 4726 either directly exports the device 891 * attached to the first downstream port or acts as a hardware storage 892 * controller and emulate a single ATA device (can be RAID 0/1 or some 893 * other configuration). 894 * 895 * When there's no device attached to the first downstream port of the 896 * 4726, "Config Disk" appears, which is a pseudo ATA device to 897 * configure the 4726. However, ATA emulation of the device is very 898 * lame. It doesn't send signature D2H Reg FIS after the initial 899 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 900 * 901 * The following function works around the problem by always using 902 * hardreset on the port and not depending on receiving signature FIS 903 * afterward. If signature FIS isn't received soon, ATA class is 904 * assumed without follow-up softreset. 905 */ 906 static void ahci_p5wdh_workaround(struct ata_host *host) 907 { 908 static const struct dmi_system_id sysids[] = { 909 { 910 .ident = "P5W DH Deluxe", 911 .matches = { 912 DMI_MATCH(DMI_SYS_VENDOR, 913 "ASUSTEK COMPUTER INC"), 914 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 915 }, 916 }, 917 { } 918 }; 919 struct pci_dev *pdev = to_pci_dev(host->dev); 920 921 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 922 dmi_check_system(sysids)) { 923 struct ata_port *ap = host->ports[1]; 924 925 dev_info(&pdev->dev, 926 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 927 928 ap->ops = &ahci_p5wdh_ops; 929 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 930 } 931 } 932 933 /* 934 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 935 * booting in BIOS compatibility mode. We restore the registers but not ID. 936 */ 937 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 938 { 939 u32 val; 940 941 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 942 943 pci_read_config_dword(pdev, 0xf8, &val); 944 val |= 1 << 0x1b; 945 /* the following changes the device ID, but appears not to affect function */ 946 /* val = (val & ~0xf0000000) | 0x80000000; */ 947 pci_write_config_dword(pdev, 0xf8, val); 948 949 pci_read_config_dword(pdev, 0x54c, &val); 950 val |= 1 << 0xc; 951 pci_write_config_dword(pdev, 0x54c, val); 952 953 pci_read_config_dword(pdev, 0x4a4, &val); 954 val &= 0xff; 955 val |= 0x01060100; 956 pci_write_config_dword(pdev, 0x4a4, val); 957 958 pci_read_config_dword(pdev, 0x54c, &val); 959 val &= ~(1 << 0xc); 960 pci_write_config_dword(pdev, 0x54c, val); 961 962 pci_read_config_dword(pdev, 0xf8, &val); 963 val &= ~(1 << 0x1b); 964 pci_write_config_dword(pdev, 0xf8, val); 965 } 966 967 static bool is_mcp89_apple(struct pci_dev *pdev) 968 { 969 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 970 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 971 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 972 pdev->subsystem_device == 0xcb89; 973 } 974 975 /* only some SB600 ahci controllers can do 64bit DMA */ 976 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 977 { 978 static const struct dmi_system_id sysids[] = { 979 /* 980 * The oldest version known to be broken is 0901 and 981 * working is 1501 which was released on 2007-10-26. 982 * Enable 64bit DMA on 1501 and anything newer. 983 * 984 * Please read bko#9412 for more info. 985 */ 986 { 987 .ident = "ASUS M2A-VM", 988 .matches = { 989 DMI_MATCH(DMI_BOARD_VENDOR, 990 "ASUSTeK Computer INC."), 991 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 992 }, 993 .driver_data = "20071026", /* yyyymmdd */ 994 }, 995 /* 996 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 997 * support 64bit DMA. 998 * 999 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1000 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1001 * This spelling mistake was fixed in BIOS version 1.5, so 1002 * 1.5 and later have the Manufacturer as 1003 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1004 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1005 * 1006 * BIOS versions earlier than 1.9 had a Board Product Name 1007 * DMI field of "MS-7376". This was changed to be 1008 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1009 * match on DMI_BOARD_NAME of "MS-7376". 1010 */ 1011 { 1012 .ident = "MSI K9A2 Platinum", 1013 .matches = { 1014 DMI_MATCH(DMI_BOARD_VENDOR, 1015 "MICRO-STAR INTER"), 1016 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1017 }, 1018 }, 1019 /* 1020 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1021 * 64bit DMA. 1022 * 1023 * This board also had the typo mentioned above in the 1024 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1025 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1026 */ 1027 { 1028 .ident = "MSI K9AGM2", 1029 .matches = { 1030 DMI_MATCH(DMI_BOARD_VENDOR, 1031 "MICRO-STAR INTER"), 1032 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1033 }, 1034 }, 1035 /* 1036 * All BIOS versions for the Asus M3A support 64bit DMA. 1037 * (all release versions from 0301 to 1206 were tested) 1038 */ 1039 { 1040 .ident = "ASUS M3A", 1041 .matches = { 1042 DMI_MATCH(DMI_BOARD_VENDOR, 1043 "ASUSTeK Computer INC."), 1044 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1045 }, 1046 }, 1047 { } 1048 }; 1049 const struct dmi_system_id *match; 1050 int year, month, date; 1051 char buf[9]; 1052 1053 match = dmi_first_match(sysids); 1054 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1055 !match) 1056 return false; 1057 1058 if (!match->driver_data) 1059 goto enable_64bit; 1060 1061 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1062 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1063 1064 if (strcmp(buf, match->driver_data) >= 0) 1065 goto enable_64bit; 1066 else { 1067 dev_warn(&pdev->dev, 1068 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1069 match->ident); 1070 return false; 1071 } 1072 1073 enable_64bit: 1074 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1075 return true; 1076 } 1077 1078 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1079 { 1080 static const struct dmi_system_id broken_systems[] = { 1081 { 1082 .ident = "HP Compaq nx6310", 1083 .matches = { 1084 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1085 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1086 }, 1087 /* PCI slot number of the controller */ 1088 .driver_data = (void *)0x1FUL, 1089 }, 1090 { 1091 .ident = "HP Compaq 6720s", 1092 .matches = { 1093 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1094 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1095 }, 1096 /* PCI slot number of the controller */ 1097 .driver_data = (void *)0x1FUL, 1098 }, 1099 1100 { } /* terminate list */ 1101 }; 1102 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1103 1104 if (dmi) { 1105 unsigned long slot = (unsigned long)dmi->driver_data; 1106 /* apply the quirk only to on-board controllers */ 1107 return slot == PCI_SLOT(pdev->devfn); 1108 } 1109 1110 return false; 1111 } 1112 1113 static bool ahci_broken_suspend(struct pci_dev *pdev) 1114 { 1115 static const struct dmi_system_id sysids[] = { 1116 /* 1117 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1118 * to the harddisk doesn't become online after 1119 * resuming from STR. Warn and fail suspend. 1120 * 1121 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1122 * 1123 * Use dates instead of versions to match as HP is 1124 * apparently recycling both product and version 1125 * strings. 1126 * 1127 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1128 */ 1129 { 1130 .ident = "dv4", 1131 .matches = { 1132 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1133 DMI_MATCH(DMI_PRODUCT_NAME, 1134 "HP Pavilion dv4 Notebook PC"), 1135 }, 1136 .driver_data = "20090105", /* F.30 */ 1137 }, 1138 { 1139 .ident = "dv5", 1140 .matches = { 1141 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1142 DMI_MATCH(DMI_PRODUCT_NAME, 1143 "HP Pavilion dv5 Notebook PC"), 1144 }, 1145 .driver_data = "20090506", /* F.16 */ 1146 }, 1147 { 1148 .ident = "dv6", 1149 .matches = { 1150 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1151 DMI_MATCH(DMI_PRODUCT_NAME, 1152 "HP Pavilion dv6 Notebook PC"), 1153 }, 1154 .driver_data = "20090423", /* F.21 */ 1155 }, 1156 { 1157 .ident = "HDX18", 1158 .matches = { 1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1160 DMI_MATCH(DMI_PRODUCT_NAME, 1161 "HP HDX18 Notebook PC"), 1162 }, 1163 .driver_data = "20090430", /* F.23 */ 1164 }, 1165 /* 1166 * Acer eMachines G725 has the same problem. BIOS 1167 * V1.03 is known to be broken. V3.04 is known to 1168 * work. Between, there are V1.06, V2.06 and V3.03 1169 * that we don't have much idea about. For now, 1170 * blacklist anything older than V3.04. 1171 * 1172 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1173 */ 1174 { 1175 .ident = "G725", 1176 .matches = { 1177 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1178 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1179 }, 1180 .driver_data = "20091216", /* V3.04 */ 1181 }, 1182 { } /* terminate list */ 1183 }; 1184 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1185 int year, month, date; 1186 char buf[9]; 1187 1188 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1189 return false; 1190 1191 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1192 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1193 1194 return strcmp(buf, dmi->driver_data) < 0; 1195 } 1196 1197 static bool ahci_broken_online(struct pci_dev *pdev) 1198 { 1199 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1200 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1201 static const struct dmi_system_id sysids[] = { 1202 /* 1203 * There are several gigabyte boards which use 1204 * SIMG5723s configured as hardware RAID. Certain 1205 * 5723 firmware revisions shipped there keep the link 1206 * online but fail to answer properly to SRST or 1207 * IDENTIFY when no device is attached downstream 1208 * causing libata to retry quite a few times leading 1209 * to excessive detection delay. 1210 * 1211 * As these firmwares respond to the second reset try 1212 * with invalid device signature, considering unknown 1213 * sig as offline works around the problem acceptably. 1214 */ 1215 { 1216 .ident = "EP45-DQ6", 1217 .matches = { 1218 DMI_MATCH(DMI_BOARD_VENDOR, 1219 "Gigabyte Technology Co., Ltd."), 1220 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1221 }, 1222 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1223 }, 1224 { 1225 .ident = "EP45-DS5", 1226 .matches = { 1227 DMI_MATCH(DMI_BOARD_VENDOR, 1228 "Gigabyte Technology Co., Ltd."), 1229 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1230 }, 1231 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1232 }, 1233 { } /* terminate list */ 1234 }; 1235 #undef ENCODE_BUSDEVFN 1236 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1237 unsigned int val; 1238 1239 if (!dmi) 1240 return false; 1241 1242 val = (unsigned long)dmi->driver_data; 1243 1244 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1245 } 1246 1247 static bool ahci_broken_devslp(struct pci_dev *pdev) 1248 { 1249 /* device with broken DEVSLP but still showing SDS capability */ 1250 static const struct pci_device_id ids[] = { 1251 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1252 {} 1253 }; 1254 1255 return pci_match_id(ids, pdev); 1256 } 1257 1258 #ifdef CONFIG_ATA_ACPI 1259 static void ahci_gtf_filter_workaround(struct ata_host *host) 1260 { 1261 static const struct dmi_system_id sysids[] = { 1262 /* 1263 * Aspire 3810T issues a bunch of SATA enable commands 1264 * via _GTF including an invalid one and one which is 1265 * rejected by the device. Among the successful ones 1266 * is FPDMA non-zero offset enable which when enabled 1267 * only on the drive side leads to NCQ command 1268 * failures. Filter it out. 1269 */ 1270 { 1271 .ident = "Aspire 3810T", 1272 .matches = { 1273 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1274 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1275 }, 1276 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1277 }, 1278 { } 1279 }; 1280 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1281 unsigned int filter; 1282 int i; 1283 1284 if (!dmi) 1285 return; 1286 1287 filter = (unsigned long)dmi->driver_data; 1288 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1289 filter, dmi->ident); 1290 1291 for (i = 0; i < host->n_ports; i++) { 1292 struct ata_port *ap = host->ports[i]; 1293 struct ata_link *link; 1294 struct ata_device *dev; 1295 1296 ata_for_each_link(link, ap, EDGE) 1297 ata_for_each_dev(dev, link, ALL) 1298 dev->gtf_filter |= filter; 1299 } 1300 } 1301 #else 1302 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1303 {} 1304 #endif 1305 1306 /* 1307 * ahci_init_msix() only implements single MSI-X support, not multiple 1308 * MSI-X per-port interrupts. This is needed for host controllers that only 1309 * have MSI-X support implemented, but no MSI or intx. 1310 */ 1311 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports, 1312 struct ahci_host_priv *hpriv) 1313 { 1314 int rc, nvec; 1315 struct msix_entry entry = {}; 1316 1317 /* Do not init MSI-X if MSI is disabled for the device */ 1318 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1319 return -ENODEV; 1320 1321 nvec = pci_msix_vec_count(pdev); 1322 if (nvec < 0) 1323 return nvec; 1324 1325 if (!nvec) { 1326 rc = -ENODEV; 1327 goto fail; 1328 } 1329 1330 /* 1331 * There can be more than one vector (e.g. for error detection or 1332 * hdd hotplug). Only the first vector (entry.entry = 0) is used. 1333 */ 1334 rc = pci_enable_msix_exact(pdev, &entry, 1); 1335 if (rc < 0) 1336 goto fail; 1337 1338 hpriv->irq = entry.vector; 1339 1340 return 1; 1341 fail: 1342 dev_err(&pdev->dev, 1343 "failed to enable MSI-X with error %d, # of vectors: %d\n", 1344 rc, nvec); 1345 1346 return rc; 1347 } 1348 1349 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1350 struct ahci_host_priv *hpriv) 1351 { 1352 int rc, nvec; 1353 1354 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1355 return -ENODEV; 1356 1357 nvec = pci_msi_vec_count(pdev); 1358 if (nvec < 0) 1359 return nvec; 1360 1361 /* 1362 * If number of MSIs is less than number of ports then Sharing Last 1363 * Message mode could be enforced. In this case assume that advantage 1364 * of multipe MSIs is negated and use single MSI mode instead. 1365 */ 1366 if (nvec < n_ports) 1367 goto single_msi; 1368 1369 rc = pci_enable_msi_exact(pdev, nvec); 1370 if (rc == -ENOSPC) 1371 goto single_msi; 1372 if (rc < 0) 1373 return rc; 1374 1375 /* fallback to single MSI mode if the controller enforced MRSM mode */ 1376 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) { 1377 pci_disable_msi(pdev); 1378 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n"); 1379 goto single_msi; 1380 } 1381 1382 if (nvec > 1) 1383 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1384 1385 goto out; 1386 1387 single_msi: 1388 nvec = 1; 1389 1390 rc = pci_enable_msi(pdev); 1391 if (rc < 0) 1392 return rc; 1393 out: 1394 hpriv->irq = pdev->irq; 1395 1396 return nvec; 1397 } 1398 1399 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, 1400 struct ahci_host_priv *hpriv) 1401 { 1402 int nvec; 1403 1404 nvec = ahci_init_msi(pdev, n_ports, hpriv); 1405 if (nvec >= 0) 1406 return nvec; 1407 1408 /* 1409 * Currently, MSI-X support only implements single IRQ mode and 1410 * exists for controllers which can't do other types of IRQ. Only 1411 * set it up if MSI fails. 1412 */ 1413 nvec = ahci_init_msix(pdev, n_ports, hpriv); 1414 if (nvec >= 0) 1415 return nvec; 1416 1417 /* lagacy intx interrupts */ 1418 pci_intx(pdev, 1); 1419 hpriv->irq = pdev->irq; 1420 1421 return 0; 1422 } 1423 1424 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1425 { 1426 unsigned int board_id = ent->driver_data; 1427 struct ata_port_info pi = ahci_port_info[board_id]; 1428 const struct ata_port_info *ppi[] = { &pi, NULL }; 1429 struct device *dev = &pdev->dev; 1430 struct ahci_host_priv *hpriv; 1431 struct ata_host *host; 1432 int n_ports, i, rc; 1433 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1434 1435 VPRINTK("ENTER\n"); 1436 1437 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1438 1439 ata_print_version_once(&pdev->dev, DRV_VERSION); 1440 1441 /* The AHCI driver can only drive the SATA ports, the PATA driver 1442 can drive them all so if both drivers are selected make sure 1443 AHCI stays out of the way */ 1444 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1445 return -ENODEV; 1446 1447 /* Apple BIOS on MCP89 prevents us using AHCI */ 1448 if (is_mcp89_apple(pdev)) 1449 ahci_mcp89_apple_enable(pdev); 1450 1451 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1452 * At the moment, we can only use the AHCI mode. Let the users know 1453 * that for SAS drives they're out of luck. 1454 */ 1455 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1456 dev_info(&pdev->dev, 1457 "PDC42819 can only drive SATA devices with this driver\n"); 1458 1459 /* Some devices use non-standard BARs */ 1460 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1461 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1462 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1463 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1464 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1465 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1466 1467 /* acquire resources */ 1468 rc = pcim_enable_device(pdev); 1469 if (rc) 1470 return rc; 1471 1472 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1473 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1474 u8 map; 1475 1476 /* ICH6s share the same PCI ID for both piix and ahci 1477 * modes. Enabling ahci mode while MAP indicates 1478 * combined mode is a bad idea. Yield to ata_piix. 1479 */ 1480 pci_read_config_byte(pdev, ICH_MAP, &map); 1481 if (map & 0x3) { 1482 dev_info(&pdev->dev, 1483 "controller is in combined mode, can't enable AHCI mode\n"); 1484 return -ENODEV; 1485 } 1486 } 1487 1488 /* AHCI controllers often implement SFF compatible interface. 1489 * Grab all PCI BARs just in case. 1490 */ 1491 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1492 if (rc == -EBUSY) 1493 pcim_pin_device(pdev); 1494 if (rc) 1495 return rc; 1496 1497 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1498 if (!hpriv) 1499 return -ENOMEM; 1500 hpriv->flags |= (unsigned long)pi.private_data; 1501 1502 /* MCP65 revision A1 and A2 can't do MSI */ 1503 if (board_id == board_ahci_mcp65 && 1504 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1505 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1506 1507 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1508 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1509 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1510 1511 /* only some SB600s can do 64bit DMA */ 1512 if (ahci_sb600_enable_64bit(pdev)) 1513 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1514 1515 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1516 1517 /* must set flag prior to save config in order to take effect */ 1518 if (ahci_broken_devslp(pdev)) 1519 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1520 1521 /* save initial config */ 1522 ahci_pci_save_initial_config(pdev, hpriv); 1523 1524 /* prepare host */ 1525 if (hpriv->cap & HOST_CAP_NCQ) { 1526 pi.flags |= ATA_FLAG_NCQ; 1527 /* 1528 * Auto-activate optimization is supposed to be 1529 * supported on all AHCI controllers indicating NCQ 1530 * capability, but it seems to be broken on some 1531 * chipsets including NVIDIAs. 1532 */ 1533 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1534 pi.flags |= ATA_FLAG_FPDMA_AA; 1535 1536 /* 1537 * All AHCI controllers should be forward-compatible 1538 * with the new auxiliary field. This code should be 1539 * conditionalized if any buggy AHCI controllers are 1540 * encountered. 1541 */ 1542 pi.flags |= ATA_FLAG_FPDMA_AUX; 1543 } 1544 1545 if (hpriv->cap & HOST_CAP_PMP) 1546 pi.flags |= ATA_FLAG_PMP; 1547 1548 ahci_set_em_messages(hpriv, &pi); 1549 1550 if (ahci_broken_system_poweroff(pdev)) { 1551 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1552 dev_info(&pdev->dev, 1553 "quirky BIOS, skipping spindown on poweroff\n"); 1554 } 1555 1556 if (ahci_broken_suspend(pdev)) { 1557 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1558 dev_warn(&pdev->dev, 1559 "BIOS update required for suspend/resume\n"); 1560 } 1561 1562 if (ahci_broken_online(pdev)) { 1563 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1564 dev_info(&pdev->dev, 1565 "online status unreliable, applying workaround\n"); 1566 } 1567 1568 /* CAP.NP sometimes indicate the index of the last enabled 1569 * port, at other times, that of the last possible port, so 1570 * determining the maximum port number requires looking at 1571 * both CAP.NP and port_map. 1572 */ 1573 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1574 1575 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1576 if (!host) 1577 return -ENOMEM; 1578 host->private_data = hpriv; 1579 1580 ahci_init_interrupts(pdev, n_ports, hpriv); 1581 1582 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1583 host->flags |= ATA_HOST_PARALLEL_SCAN; 1584 else 1585 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1586 1587 if (pi.flags & ATA_FLAG_EM) 1588 ahci_reset_em(host); 1589 1590 for (i = 0; i < host->n_ports; i++) { 1591 struct ata_port *ap = host->ports[i]; 1592 1593 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1594 ata_port_pbar_desc(ap, ahci_pci_bar, 1595 0x100 + ap->port_no * 0x80, "port"); 1596 1597 /* set enclosure management message type */ 1598 if (ap->flags & ATA_FLAG_EM) 1599 ap->em_message_type = hpriv->em_msg_type; 1600 1601 1602 /* disabled/not-implemented port */ 1603 if (!(hpriv->port_map & (1 << i))) 1604 ap->ops = &ata_dummy_port_ops; 1605 } 1606 1607 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1608 ahci_p5wdh_workaround(host); 1609 1610 /* apply gtf filter quirk */ 1611 ahci_gtf_filter_workaround(host); 1612 1613 /* initialize adapter */ 1614 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1615 if (rc) 1616 return rc; 1617 1618 rc = ahci_pci_reset_controller(host); 1619 if (rc) 1620 return rc; 1621 1622 ahci_pci_init_controller(host); 1623 ahci_pci_print_info(host); 1624 1625 pci_set_master(pdev); 1626 1627 return ahci_host_activate(host, &ahci_sht); 1628 } 1629 1630 module_pci_driver(ahci_pci_driver); 1631 1632 MODULE_AUTHOR("Jeff Garzik"); 1633 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1634 MODULE_LICENSE("GPL"); 1635 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1636 MODULE_VERSION(DRV_VERSION); 1637