1/* 2 * arch/xtensa/kernel/coprocessor.S 3 * 4 * Xtensa processor configuration-specific table of coprocessor and 5 * other custom register layout information. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Copyright (C) 2003 - 2007 Tensilica Inc. 12 */ 13 14 15#include <linux/linkage.h> 16#include <asm/asm-offsets.h> 17#include <asm/asmmacro.h> 18#include <asm/coprocessor.h> 19#include <asm/current.h> 20#include <asm/regs.h> 21 22#if XTENSA_HAVE_COPROCESSORS 23 24/* 25 * Macros for lazy context switch. 26 */ 27 28#define SAVE_CP_REGS(x) \ 29 .if XTENSA_HAVE_COPROCESSOR(x); \ 30 .align 4; \ 31 .Lsave_cp_regs_cp##x: \ 32 xchal_cp##x##_store a2 a3 a4 a5 a6; \ 33 ret; \ 34 .endif 35 36#define LOAD_CP_REGS(x) \ 37 .if XTENSA_HAVE_COPROCESSOR(x); \ 38 .align 4; \ 39 .Lload_cp_regs_cp##x: \ 40 xchal_cp##x##_load a2 a3 a4 a5 a6; \ 41 ret; \ 42 .endif 43 44#define CP_REGS_TAB(x) \ 45 .if XTENSA_HAVE_COPROCESSOR(x); \ 46 .long .Lsave_cp_regs_cp##x; \ 47 .long .Lload_cp_regs_cp##x; \ 48 .else; \ 49 .long 0, 0; \ 50 .endif; \ 51 .long THREAD_XTREGS_CP##x 52 53#define CP_REGS_TAB_SAVE 0 54#define CP_REGS_TAB_LOAD 4 55#define CP_REGS_TAB_OFFSET 8 56 57 __XTENSA_HANDLER 58 59 SAVE_CP_REGS(0) 60 SAVE_CP_REGS(1) 61 SAVE_CP_REGS(2) 62 SAVE_CP_REGS(3) 63 SAVE_CP_REGS(4) 64 SAVE_CP_REGS(5) 65 SAVE_CP_REGS(6) 66 SAVE_CP_REGS(7) 67 68 LOAD_CP_REGS(0) 69 LOAD_CP_REGS(1) 70 LOAD_CP_REGS(2) 71 LOAD_CP_REGS(3) 72 LOAD_CP_REGS(4) 73 LOAD_CP_REGS(5) 74 LOAD_CP_REGS(6) 75 LOAD_CP_REGS(7) 76 77 .align 4 78.Lcp_regs_jump_table: 79 CP_REGS_TAB(0) 80 CP_REGS_TAB(1) 81 CP_REGS_TAB(2) 82 CP_REGS_TAB(3) 83 CP_REGS_TAB(4) 84 CP_REGS_TAB(5) 85 CP_REGS_TAB(6) 86 CP_REGS_TAB(7) 87 88/* 89 * Entry condition: 90 * 91 * a0: trashed, original value saved on stack (PT_AREG0) 92 * a1: a1 93 * a2: new stack pointer, original in DEPC 94 * a3: a3 95 * depc: a2, original value saved on stack (PT_DEPC) 96 * excsave_1: dispatch table 97 * 98 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 99 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 100 */ 101 102ENTRY(fast_coprocessor) 103 104 /* Save remaining registers a1-a3 and SAR */ 105 106 s32i a3, a2, PT_AREG3 107 rsr a3, sar 108 s32i a1, a2, PT_AREG1 109 s32i a3, a2, PT_SAR 110 mov a1, a2 111 rsr a2, depc 112 s32i a2, a1, PT_AREG2 113 114 /* The hal macros require up to 4 temporary registers. We use a3..a6. */ 115 116 s32i a4, a1, PT_AREG4 117 s32i a5, a1, PT_AREG5 118 s32i a6, a1, PT_AREG6 119 s32i a7, a1, PT_AREG7 120 121 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ 122 123 rsr a3, exccause 124 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 125 126 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/ 127 128 ssl a3 # SAR: 32 - coprocessor_number 129 movi a2, 1 130 rsr a0, cpenable 131 sll a2, a2 132 or a0, a0, a2 133 wsr a0, cpenable 134 rsync 135 136 /* Get coprocessor save/load table entry (a7). */ 137 138 movi a7, .Lcp_regs_jump_table 139 addx8 a7, a3, a7 140 addx4 a7, a3, a7 141 142 /* Retrieve previous owner. (a3 still holds CP number) */ 143 144 movi a0, coprocessor_owner # list of owners 145 addx4 a0, a3, a0 # entry for CP 146 l32i a4, a0, 0 147 148 beqz a4, 1f # skip 'save' if no previous owner 149 150 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */ 151 152 l32i a5, a4, THREAD_CPENABLE 153 xor a5, a5, a2 # (1 << cp-id) still in a2 154 s32i a5, a4, THREAD_CPENABLE 155 156 /* 157 * Get context save area and call save routine. 158 * (a4 still holds previous owner (thread_info), a3 CP number) 159 */ 160 161 l32i a2, a7, CP_REGS_TAB_OFFSET 162 l32i a3, a7, CP_REGS_TAB_SAVE 163 add a2, a2, a4 164 callx0 a3 165 166 /* Note that only a0 and a1 were preserved. */ 167 168 rsr a3, exccause 169 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 170 movi a0, coprocessor_owner 171 addx4 a0, a3, a0 172 173 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ 174 1751: GET_THREAD_INFO (a4, a1) 176 s32i a4, a0, 0 177 178 /* Get context save area and call load routine. */ 179 180 l32i a2, a7, CP_REGS_TAB_OFFSET 181 l32i a3, a7, CP_REGS_TAB_LOAD 182 add a2, a2, a4 183 callx0 a3 184 185 /* Restore all registers and return from exception handler. */ 186 187 l32i a7, a1, PT_AREG7 188 l32i a6, a1, PT_AREG6 189 l32i a5, a1, PT_AREG5 190 l32i a4, a1, PT_AREG4 191 192 l32i a0, a1, PT_SAR 193 l32i a3, a1, PT_AREG3 194 l32i a2, a1, PT_AREG2 195 wsr a0, sar 196 l32i a0, a1, PT_AREG0 197 l32i a1, a1, PT_AREG1 198 199 rfe 200 201ENDPROC(fast_coprocessor) 202 203 .text 204 205/* 206 * coprocessor_flush(struct thread_info*, index) 207 * a2 a3 208 * 209 * Save coprocessor registers for coprocessor 'index'. 210 * The register values are saved to or loaded from the coprocessor area 211 * inside the task_info structure. 212 * 213 * Note that this function doesn't update the coprocessor_owner information! 214 * 215 */ 216 217ENTRY(coprocessor_flush) 218 219 abi_entry_default 220 221 movi a4, .Lcp_regs_jump_table 222 addx8 a4, a3, a4 223 addx4 a3, a3, a4 224 l32i a4, a3, CP_REGS_TAB_SAVE 225 beqz a4, 1f 226 l32i a3, a3, CP_REGS_TAB_OFFSET 227 add a2, a2, a3 228 mov a7, a0 229 callx0 a4 230 mov a0, a7 2311: 232 abi_ret_default 233 234ENDPROC(coprocessor_flush) 235 236 .data 237 238ENTRY(coprocessor_owner) 239 240 .fill XCHAL_CP_MAX, 4, 0 241 242END(coprocessor_owner) 243 244#endif /* XTENSA_HAVE_COPROCESSORS */ 245