1/* 2 * arch/xtensa/kernel/coprocessor.S 3 * 4 * Xtensa processor configuration-specific table of coprocessor and 5 * other custom register layout information. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Copyright (C) 2003 - 2007 Tensilica Inc. 12 */ 13 14 15#include <linux/linkage.h> 16#include <asm/asm-offsets.h> 17#include <asm/asmmacro.h> 18#include <asm/coprocessor.h> 19#include <asm/current.h> 20#include <asm/regs.h> 21 22#if XTENSA_HAVE_COPROCESSORS 23 24/* 25 * Macros for lazy context switch. 26 */ 27 28#define SAVE_CP_REGS(x) \ 29 .if XTENSA_HAVE_COPROCESSOR(x); \ 30 .align 4; \ 31 .Lsave_cp_regs_cp##x: \ 32 xchal_cp##x##_store a2 a4 a5 a6 a7; \ 33 jx a0; \ 34 .endif 35 36#define SAVE_CP_REGS_TAB(x) \ 37 .if XTENSA_HAVE_COPROCESSOR(x); \ 38 .long .Lsave_cp_regs_cp##x; \ 39 .else; \ 40 .long 0; \ 41 .endif; \ 42 .long THREAD_XTREGS_CP##x 43 44 45#define LOAD_CP_REGS(x) \ 46 .if XTENSA_HAVE_COPROCESSOR(x); \ 47 .align 4; \ 48 .Lload_cp_regs_cp##x: \ 49 xchal_cp##x##_load a2 a4 a5 a6 a7; \ 50 jx a0; \ 51 .endif 52 53#define LOAD_CP_REGS_TAB(x) \ 54 .if XTENSA_HAVE_COPROCESSOR(x); \ 55 .long .Lload_cp_regs_cp##x; \ 56 .else; \ 57 .long 0; \ 58 .endif; \ 59 .long THREAD_XTREGS_CP##x 60 61 SAVE_CP_REGS(0) 62 SAVE_CP_REGS(1) 63 SAVE_CP_REGS(2) 64 SAVE_CP_REGS(3) 65 SAVE_CP_REGS(4) 66 SAVE_CP_REGS(5) 67 SAVE_CP_REGS(6) 68 SAVE_CP_REGS(7) 69 70 LOAD_CP_REGS(0) 71 LOAD_CP_REGS(1) 72 LOAD_CP_REGS(2) 73 LOAD_CP_REGS(3) 74 LOAD_CP_REGS(4) 75 LOAD_CP_REGS(5) 76 LOAD_CP_REGS(6) 77 LOAD_CP_REGS(7) 78 79 .section ".rodata", "a" 80 .align 4 81.Lsave_cp_regs_jump_table: 82 SAVE_CP_REGS_TAB(0) 83 SAVE_CP_REGS_TAB(1) 84 SAVE_CP_REGS_TAB(2) 85 SAVE_CP_REGS_TAB(3) 86 SAVE_CP_REGS_TAB(4) 87 SAVE_CP_REGS_TAB(5) 88 SAVE_CP_REGS_TAB(6) 89 SAVE_CP_REGS_TAB(7) 90 91.Lload_cp_regs_jump_table: 92 LOAD_CP_REGS_TAB(0) 93 LOAD_CP_REGS_TAB(1) 94 LOAD_CP_REGS_TAB(2) 95 LOAD_CP_REGS_TAB(3) 96 LOAD_CP_REGS_TAB(4) 97 LOAD_CP_REGS_TAB(5) 98 LOAD_CP_REGS_TAB(6) 99 LOAD_CP_REGS_TAB(7) 100 101 .previous 102 103/* 104 * coprocessor_flush(struct thread_info*, index) 105 * a2 a3 106 * 107 * Save coprocessor registers for coprocessor 'index'. 108 * The register values are saved to or loaded from the coprocessor area 109 * inside the task_info structure. 110 * 111 * Note that this function doesn't update the coprocessor_owner information! 112 * 113 */ 114 115ENTRY(coprocessor_flush) 116 117 /* reserve 4 bytes on stack to save a0 */ 118 abi_entry(4) 119 120 s32i a0, a1, 0 121 movi a0, .Lsave_cp_regs_jump_table 122 addx8 a3, a3, a0 123 l32i a4, a3, 4 124 l32i a3, a3, 0 125 add a2, a2, a4 126 beqz a3, 1f 127 callx0 a3 1281: l32i a0, a1, 0 129 130 abi_ret(4) 131 132ENDPROC(coprocessor_flush) 133 134/* 135 * Entry condition: 136 * 137 * a0: trashed, original value saved on stack (PT_AREG0) 138 * a1: a1 139 * a2: new stack pointer, original in DEPC 140 * a3: a3 141 * depc: a2, original value saved on stack (PT_DEPC) 142 * excsave_1: dispatch table 143 * 144 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 145 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 146 */ 147 148ENTRY(fast_coprocessor) 149 150 /* Save remaining registers a1-a3 and SAR */ 151 152 s32i a3, a2, PT_AREG3 153 rsr a3, sar 154 s32i a1, a2, PT_AREG1 155 s32i a3, a2, PT_SAR 156 mov a1, a2 157 rsr a2, depc 158 s32i a2, a1, PT_AREG2 159 160 /* 161 * The hal macros require up to 4 temporary registers. We use a3..a6. 162 */ 163 164 s32i a4, a1, PT_AREG4 165 s32i a5, a1, PT_AREG5 166 s32i a6, a1, PT_AREG6 167 168 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ 169 170 rsr a3, exccause 171 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 172 173 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/ 174 175 ssl a3 # SAR: 32 - coprocessor_number 176 movi a2, 1 177 rsr a0, cpenable 178 sll a2, a2 179 or a0, a0, a2 180 wsr a0, cpenable 181 rsync 182 183 /* Retrieve previous owner. (a3 still holds CP number) */ 184 185 movi a0, coprocessor_owner # list of owners 186 addx4 a0, a3, a0 # entry for CP 187 l32i a4, a0, 0 188 189 beqz a4, 1f # skip 'save' if no previous owner 190 191 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */ 192 193 l32i a5, a4, THREAD_CPENABLE 194 xor a5, a5, a2 # (1 << cp-id) still in a2 195 s32i a5, a4, THREAD_CPENABLE 196 197 /* 198 * Get context save area and 'call' save routine. 199 * (a4 still holds previous owner (thread_info), a3 CP number) 200 */ 201 202 movi a5, .Lsave_cp_regs_jump_table 203 movi a0, 2f # a0: 'return' address 204 addx8 a3, a3, a5 # a3: coprocessor number 205 l32i a2, a3, 4 # a2: xtregs offset 206 l32i a3, a3, 0 # a3: jump address 207 add a2, a2, a4 208 jx a3 209 210 /* Note that only a0 and a1 were preserved. */ 211 2122: rsr a3, exccause 213 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 214 movi a0, coprocessor_owner 215 addx4 a0, a3, a0 216 217 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ 218 2191: GET_THREAD_INFO (a4, a1) 220 s32i a4, a0, 0 221 222 /* Get context save area and 'call' load routine. */ 223 224 movi a5, .Lload_cp_regs_jump_table 225 movi a0, 1f 226 addx8 a3, a3, a5 227 l32i a2, a3, 4 # a2: xtregs offset 228 l32i a3, a3, 0 # a3: jump address 229 add a2, a2, a4 230 jx a3 231 232 /* Restore all registers and return from exception handler. */ 233 2341: l32i a6, a1, PT_AREG6 235 l32i a5, a1, PT_AREG5 236 l32i a4, a1, PT_AREG4 237 238 l32i a0, a1, PT_SAR 239 l32i a3, a1, PT_AREG3 240 l32i a2, a1, PT_AREG2 241 wsr a0, sar 242 l32i a0, a1, PT_AREG0 243 l32i a1, a1, PT_AREG1 244 245 rfe 246 247ENDPROC(fast_coprocessor) 248 249 .data 250 251ENTRY(coprocessor_owner) 252 253 .fill XCHAL_CP_MAX, 4, 0 254 255END(coprocessor_owner) 256 257#endif /* XTENSA_HAVE_COPROCESSORS */ 258