1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_CURRENT_STACK_POINTER 7 select ARCH_HAS_DEBUG_VM_PGTABLE 8 select ARCH_HAS_DMA_PREP_COHERENT if MMU 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_HAS_KCOV 11 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 13 select ARCH_HAS_DMA_SET_UNCACHED if MMU 14 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 15 select ARCH_HAS_STRNLEN_USER 16 select ARCH_USE_MEMTEST 17 select ARCH_USE_QUEUED_RWLOCKS 18 select ARCH_USE_QUEUED_SPINLOCKS 19 select ARCH_WANT_FRAME_POINTERS 20 select ARCH_WANT_IPC_PARSE_VERSION 21 select BUILDTIME_TABLE_SORT 22 select CLONE_BACKWARDS 23 select COMMON_CLK 24 select DMA_NONCOHERENT_MMAP if MMU 25 select GENERIC_ATOMIC64 26 select GENERIC_IRQ_SHOW 27 select GENERIC_LIB_CMPDI2 28 select GENERIC_LIB_MULDI3 29 select GENERIC_LIB_UCMPDI2 30 select GENERIC_PCI_IOMAP 31 select GENERIC_SCHED_CLOCK 32 select HAVE_ARCH_AUDITSYSCALL 33 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 34 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 35 select HAVE_ARCH_KCSAN 36 select HAVE_ARCH_SECCOMP_FILTER 37 select HAVE_ARCH_TRACEHOOK 38 select HAVE_CONTEXT_TRACKING_USER 39 select HAVE_DEBUG_KMEMLEAK 40 select HAVE_DMA_CONTIGUOUS 41 select HAVE_EXIT_THREAD 42 select HAVE_FUNCTION_TRACER 43 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000 44 select HAVE_HW_BREAKPOINT if PERF_EVENTS 45 select HAVE_IRQ_TIME_ACCOUNTING 46 select HAVE_PCI 47 select HAVE_PERF_EVENTS 48 select HAVE_STACKPROTECTOR 49 select HAVE_SYSCALL_TRACEPOINTS 50 select HAVE_VIRT_CPU_ACCOUNTING_GEN 51 select IRQ_DOMAIN 52 select LOCK_MM_AND_FIND_VMA 53 select MODULES_USE_ELF_RELA 54 select PERF_USE_VMALLOC 55 select TRACE_IRQFLAGS_SUPPORT 56 help 57 Xtensa processors are 32-bit RISC machines designed by Tensilica 58 primarily for embedded systems. These processors are both 59 configurable and extensible. The Linux port to the Xtensa 60 architecture supports all processor configurations and extensions, 61 with reasonable minimum requirements. The Xtensa Linux project has 62 a home page at <http://www.linux-xtensa.org/>. 63 64config GENERIC_HWEIGHT 65 def_bool y 66 67config ARCH_HAS_ILOG2_U32 68 def_bool n 69 70config ARCH_HAS_ILOG2_U64 71 def_bool n 72 73config NO_IOPORT_MAP 74 def_bool n 75 76config HZ 77 int 78 default 100 79 80config LOCKDEP_SUPPORT 81 def_bool y 82 83config STACKTRACE_SUPPORT 84 def_bool y 85 86config MMU 87 def_bool n 88 select PFAULT 89 90config HAVE_XTENSA_GPIO32 91 def_bool n 92 93config KASAN_SHADOW_OFFSET 94 hex 95 default 0x6e400000 96 97config CPU_BIG_ENDIAN 98 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 99 100config CPU_LITTLE_ENDIAN 101 def_bool !CPU_BIG_ENDIAN 102 103config CC_HAVE_CALL0_ABI 104 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) 105 106menu "Processor type and features" 107 108choice 109 prompt "Xtensa Processor Configuration" 110 default XTENSA_VARIANT_FSF 111 112config XTENSA_VARIANT_FSF 113 bool "fsf - default (not generic) configuration" 114 select MMU 115 116config XTENSA_VARIANT_DC232B 117 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 118 select MMU 119 select HAVE_XTENSA_GPIO32 120 help 121 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 122 123config XTENSA_VARIANT_DC233C 124 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 125 select MMU 126 select HAVE_XTENSA_GPIO32 127 help 128 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 129 130config XTENSA_VARIANT_CUSTOM 131 bool "Custom Xtensa processor configuration" 132 select HAVE_XTENSA_GPIO32 133 help 134 Select this variant to use a custom Xtensa processor configuration. 135 You will be prompted for a processor variant CORENAME. 136endchoice 137 138config XTENSA_VARIANT_CUSTOM_NAME 139 string "Xtensa Processor Custom Core Variant Name" 140 depends on XTENSA_VARIANT_CUSTOM 141 help 142 Provide the name of a custom Xtensa processor variant. 143 This CORENAME selects arch/xtensa/variant/CORENAME. 144 Don't forget you have to select MMU if you have one. 145 146config XTENSA_VARIANT_NAME 147 string 148 default "dc232b" if XTENSA_VARIANT_DC232B 149 default "dc233c" if XTENSA_VARIANT_DC233C 150 default "fsf" if XTENSA_VARIANT_FSF 151 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 152 153config XTENSA_VARIANT_MMU 154 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 155 depends on XTENSA_VARIANT_CUSTOM 156 default y 157 select MMU 158 help 159 Build a Conventional Kernel with full MMU support, 160 ie: it supports a TLB with auto-loading, page protection. 161 162config XTENSA_VARIANT_HAVE_PERF_EVENTS 163 bool "Core variant has Performance Monitor Module" 164 depends on XTENSA_VARIANT_CUSTOM 165 default n 166 help 167 Enable if core variant has Performance Monitor Module with 168 External Registers Interface. 169 170 If unsure, say N. 171 172config XTENSA_FAKE_NMI 173 bool "Treat PMM IRQ as NMI" 174 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 175 default n 176 help 177 If PMM IRQ is the only IRQ at EXCM level it is safe to 178 treat it as NMI, which improves accuracy of profiling. 179 180 If there are other interrupts at or above PMM IRQ priority level 181 but not above the EXCM level, PMM IRQ still may be treated as NMI, 182 but only if these IRQs are not used. There will be a build warning 183 saying that this is not safe, and a bugcheck if one of these IRQs 184 actually fire. 185 186 If unsure, say N. 187 188config PFAULT 189 bool "Handle protection faults" if EXPERT && !MMU 190 default y 191 help 192 Handle protection faults. MMU configurations must enable it. 193 noMMU configurations may disable it if used memory map never 194 generates protection faults or faults are always fatal. 195 196 If unsure, say Y. 197 198config XTENSA_UNALIGNED_USER 199 bool "Unaligned memory access in user space" 200 help 201 The Xtensa architecture currently does not handle unaligned 202 memory accesses in hardware but through an exception handler. 203 Per default, unaligned memory accesses are disabled in user space. 204 205 Say Y here to enable unaligned memory access in user space. 206 207config HAVE_SMP 208 bool "System Supports SMP (MX)" 209 depends on XTENSA_VARIANT_CUSTOM 210 select XTENSA_MX 211 help 212 This option is used to indicate that the system-on-a-chip (SOC) 213 supports Multiprocessing. Multiprocessor support implemented above 214 the CPU core definition and currently needs to be selected manually. 215 216 Multiprocessor support is implemented with external cache and 217 interrupt controllers. 218 219 The MX interrupt distributer adds Interprocessor Interrupts 220 and causes the IRQ numbers to be increased by 4 for devices 221 like the open cores ethernet driver and the serial interface. 222 223 You still have to select "Enable SMP" to enable SMP on this SOC. 224 225config SMP 226 bool "Enable Symmetric multi-processing support" 227 depends on HAVE_SMP 228 select GENERIC_SMP_IDLE_THREAD 229 help 230 Enabled SMP Software; allows more than one CPU/CORE 231 to be activated during startup. 232 233config NR_CPUS 234 depends on SMP 235 int "Maximum number of CPUs (2-32)" 236 range 2 32 237 default "4" 238 239config HOTPLUG_CPU 240 bool "Enable CPU hotplug support" 241 depends on SMP 242 help 243 Say Y here to allow turning CPUs off and on. CPUs can be 244 controlled through /sys/devices/system/cpu. 245 246 Say N if you want to disable CPU hotplug. 247 248config SECONDARY_RESET_VECTOR 249 bool "Secondary cores use alternative reset vector" 250 default y 251 depends on HAVE_SMP 252 help 253 Secondary cores may be configured to use alternative reset vector, 254 or all cores may use primary reset vector. 255 Say Y here to supply handler for the alternative reset location. 256 257config FAST_SYSCALL_XTENSA 258 bool "Enable fast atomic syscalls" 259 default n 260 help 261 fast_syscall_xtensa is a syscall that can make atomic operations 262 on UP kernel when processor has no s32c1i support. 263 264 This syscall is deprecated. It may have issues when called with 265 invalid arguments. It is provided only for backwards compatibility. 266 Only enable it if your userspace software requires it. 267 268 If unsure, say N. 269 270config FAST_SYSCALL_SPILL_REGISTERS 271 bool "Enable spill registers syscall" 272 default n 273 help 274 fast_syscall_spill_registers is a syscall that spills all active 275 register windows of a calling userspace task onto its stack. 276 277 This syscall is deprecated. It may have issues when called with 278 invalid arguments. It is provided only for backwards compatibility. 279 Only enable it if your userspace software requires it. 280 281 If unsure, say N. 282 283choice 284 prompt "Kernel ABI" 285 default KERNEL_ABI_DEFAULT 286 help 287 Select ABI for the kernel code. This ABI is independent of the 288 supported userspace ABI and any combination of the 289 kernel/userspace ABI is possible and should work. 290 291 In case both kernel and userspace support only call0 ABI 292 all register windows support code will be omitted from the 293 build. 294 295 If unsure, choose the default ABI. 296 297config KERNEL_ABI_DEFAULT 298 bool "Default ABI" 299 help 300 Select this option to compile kernel code with the default ABI 301 selected for the toolchain. 302 Normally cores with windowed registers option use windowed ABI and 303 cores without it use call0 ABI. 304 305config KERNEL_ABI_CALL0 306 bool "Call0 ABI" if CC_HAVE_CALL0_ABI 307 help 308 Select this option to compile kernel code with call0 ABI even with 309 toolchain that defaults to windowed ABI. 310 When this option is not selected the default toolchain ABI will 311 be used for the kernel code. 312 313endchoice 314 315config USER_ABI_CALL0 316 bool 317 318choice 319 prompt "Userspace ABI" 320 default USER_ABI_DEFAULT 321 help 322 Select supported userspace ABI. 323 324 If unsure, choose the default ABI. 325 326config USER_ABI_DEFAULT 327 bool "Default ABI only" 328 help 329 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 330 call0 ABI binaries may be run on such kernel, but signal delivery 331 will not work correctly for them. 332 333config USER_ABI_CALL0_ONLY 334 bool "Call0 ABI only" 335 select USER_ABI_CALL0 336 help 337 Select this option to support only call0 ABI in userspace. 338 Windowed ABI binaries will crash with a segfault caused by 339 an illegal instruction exception on the first 'entry' opcode. 340 341 Choose this option if you're planning to run only user code 342 built with call0 ABI. 343 344config USER_ABI_CALL0_PROBE 345 bool "Support both windowed and call0 ABI by probing" 346 select USER_ABI_CALL0 347 help 348 Select this option to support both windowed and call0 userspace 349 ABIs. When enabled all processes are started with PS.WOE disabled 350 and a fast user exception handler for an illegal instruction is 351 used to turn on PS.WOE bit on the first 'entry' opcode executed by 352 the userspace. 353 354 This option should be enabled for the kernel that must support 355 both call0 and windowed ABIs in userspace at the same time. 356 357 Note that Xtensa ISA does not guarantee that entry opcode will 358 raise an illegal instruction exception on cores with XEA2 when 359 PS.WOE is disabled, check whether the target core supports it. 360 361endchoice 362 363endmenu 364 365config XTENSA_CALIBRATE_CCOUNT 366 def_bool n 367 help 368 On some platforms (XT2000, for example), the CPU clock rate can 369 vary. The frequency can be determined, however, by measuring 370 against a well known, fixed frequency, such as an UART oscillator. 371 372config SERIAL_CONSOLE 373 def_bool n 374 375config PLATFORM_HAVE_XIP 376 def_bool n 377 378menu "Platform options" 379 380choice 381 prompt "Xtensa System Type" 382 default XTENSA_PLATFORM_ISS 383 384config XTENSA_PLATFORM_ISS 385 bool "ISS" 386 select XTENSA_CALIBRATE_CCOUNT 387 select SERIAL_CONSOLE 388 help 389 ISS is an acronym for Tensilica's Instruction Set Simulator. 390 391config XTENSA_PLATFORM_XT2000 392 bool "XT2000" 393 help 394 XT2000 is the name of Tensilica's feature-rich emulation platform. 395 This hardware is capable of running a full Linux distribution. 396 397config XTENSA_PLATFORM_XTFPGA 398 bool "XTFPGA" 399 select ETHOC if ETHERNET 400 select PLATFORM_WANT_DEFAULT_MEM if !MMU 401 select SERIAL_CONSOLE 402 select XTENSA_CALIBRATE_CCOUNT 403 select PLATFORM_HAVE_XIP 404 help 405 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 406 This hardware is capable of running a full Linux distribution. 407 408endchoice 409 410config PLATFORM_NR_IRQS 411 int 412 default 3 if XTENSA_PLATFORM_XT2000 413 default 0 414 415config XTENSA_CPU_CLOCK 416 int "CPU clock rate [MHz]" 417 depends on !XTENSA_CALIBRATE_CCOUNT 418 default 16 419 420config GENERIC_CALIBRATE_DELAY 421 bool "Auto calibration of the BogoMIPS value" 422 help 423 The BogoMIPS value can easily be derived from the CPU frequency. 424 425config CMDLINE_BOOL 426 bool "Default bootloader kernel arguments" 427 428config CMDLINE 429 string "Initial kernel command string" 430 depends on CMDLINE_BOOL 431 default "console=ttyS0,38400 root=/dev/ram" 432 help 433 On some architectures (EBSA110 and CATS), there is currently no way 434 for the boot loader to pass arguments to the kernel. For these 435 architectures, you should supply some command-line options at build 436 time by entering them here. As a minimum, you should specify the 437 memory size and the root device (e.g., mem=64M root=/dev/nfs). 438 439config USE_OF 440 bool "Flattened Device Tree support" 441 select OF 442 select OF_EARLY_FLATTREE 443 help 444 Include support for flattened device tree machine descriptions. 445 446config BUILTIN_DTB_SOURCE 447 string "DTB to build into the kernel image" 448 depends on OF 449 450config PARSE_BOOTPARAM 451 bool "Parse bootparam block" 452 default y 453 help 454 Parse parameters passed to the kernel from the bootloader. It may 455 be disabled if the kernel is known to run without the bootloader. 456 457 If unsure, say Y. 458 459choice 460 prompt "Semihosting interface" 461 default XTENSA_SIMCALL_ISS 462 depends on XTENSA_PLATFORM_ISS 463 help 464 Choose semihosting interface that will be used for serial port, 465 block device and networking. 466 467config XTENSA_SIMCALL_ISS 468 bool "simcall" 469 help 470 Use simcall instruction. simcall is only available on simulators, 471 it does nothing on hardware. 472 473config XTENSA_SIMCALL_GDBIO 474 bool "GDBIO" 475 help 476 Use break instruction. It is available on real hardware when GDB 477 is attached to it via JTAG. 478 479endchoice 480 481config BLK_DEV_SIMDISK 482 tristate "Host file-based simulated block device support" 483 default n 484 depends on XTENSA_PLATFORM_ISS && BLOCK 485 help 486 Create block devices that map to files in the host file system. 487 Device binding to host file may be changed at runtime via proc 488 interface provided the device is not in use. 489 490config BLK_DEV_SIMDISK_COUNT 491 int "Number of host file-based simulated block devices" 492 range 1 10 493 depends on BLK_DEV_SIMDISK 494 default 2 495 help 496 This is the default minimal number of created block devices. 497 Kernel/module parameter 'simdisk_count' may be used to change this 498 value at runtime. More file names (but no more than 10) may be 499 specified as parameters, simdisk_count grows accordingly. 500 501config SIMDISK0_FILENAME 502 string "Host filename for the first simulated device" 503 depends on BLK_DEV_SIMDISK = y 504 default "" 505 help 506 Attach a first simdisk to a host file. Conventionally, this file 507 contains a root file system. 508 509config SIMDISK1_FILENAME 510 string "Host filename for the second simulated device" 511 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 512 default "" 513 help 514 Another simulated disk in a host file for a buildroot-independent 515 storage. 516 517config XTFPGA_LCD 518 bool "Enable XTFPGA LCD driver" 519 depends on XTENSA_PLATFORM_XTFPGA 520 default n 521 help 522 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 523 progress messages there during bootup/shutdown. It may be useful 524 during board bringup. 525 526 If unsure, say N. 527 528config XTFPGA_LCD_BASE_ADDR 529 hex "XTFPGA LCD base address" 530 depends on XTFPGA_LCD 531 default "0x0d0c0000" 532 help 533 Base address of the LCD controller inside KIO region. 534 Different boards from XTFPGA family have LCD controller at different 535 addresses. Please consult prototyping user guide for your board for 536 the correct address. Wrong address here may lead to hardware lockup. 537 538config XTFPGA_LCD_8BIT_ACCESS 539 bool "Use 8-bit access to XTFPGA LCD" 540 depends on XTFPGA_LCD 541 default n 542 help 543 LCD may be connected with 4- or 8-bit interface, 8-bit access may 544 only be used with 8-bit interface. Please consult prototyping user 545 guide for your board for the correct interface width. 546 547comment "Kernel memory layout" 548 549config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 550 bool "Initialize Xtensa MMU inside the Linux kernel code" 551 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 552 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 553 help 554 Earlier version initialized the MMU in the exception vector 555 before jumping to _startup in head.S and had an advantage that 556 it was possible to place a software breakpoint at 'reset' and 557 then enter your normal kernel breakpoints once the MMU was mapped 558 to the kernel mappings (0XC0000000). 559 560 This unfortunately won't work for U-Boot and likely also won't 561 work for using KEXEC to have a hot kernel ready for doing a 562 KDUMP. 563 564 So now the MMU is initialized in head.S but it's necessary to 565 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 566 xt-gdb can't place a Software Breakpoint in the 0XD region prior 567 to mapping the MMU and after mapping even if the area of low memory 568 was mapped gdb wouldn't remove the breakpoint on hitting it as the 569 PC wouldn't match. Since Hardware Breakpoints are recommended for 570 Linux configurations it seems reasonable to just assume they exist 571 and leave this older mechanism for unfortunate souls that choose 572 not to follow Tensilica's recommendation. 573 574 Selecting this will cause U-Boot to set the KERNEL Load and Entry 575 address at 0x00003000 instead of the mapped std of 0xD0003000. 576 577 If in doubt, say Y. 578 579config XIP_KERNEL 580 bool "Kernel Execute-In-Place from ROM" 581 depends on PLATFORM_HAVE_XIP 582 help 583 Execute-In-Place allows the kernel to run from non-volatile storage 584 directly addressable by the CPU, such as NOR flash. This saves RAM 585 space since the text section of the kernel is not loaded from flash 586 to RAM. Read-write sections, such as the data section and stack, 587 are still copied to RAM. The XIP kernel is not compressed since 588 it has to run directly from flash, so it will take more space to 589 store it. The flash address used to link the kernel object files, 590 and for storing it, is configuration dependent. Therefore, if you 591 say Y here, you must know the proper physical address where to 592 store the kernel image depending on your own flash memory usage. 593 594 Also note that the make target becomes "make xipImage" rather than 595 "make Image" or "make uImage". The final kernel binary to put in 596 ROM memory will be arch/xtensa/boot/xipImage. 597 598 If unsure, say N. 599 600config MEMMAP_CACHEATTR 601 hex "Cache attributes for the memory address space" 602 depends on !MMU 603 default 0x22222222 604 help 605 These cache attributes are set up for noMMU systems. Each hex digit 606 specifies cache attributes for the corresponding 512MB memory 607 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 608 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 609 610 Cache attribute values are specific for the MMU type. 611 For region protection MMUs: 612 1: WT cached, 613 2: cache bypass, 614 4: WB cached, 615 f: illegal. 616 For full MMU: 617 bit 0: executable, 618 bit 1: writable, 619 bits 2..3: 620 0: cache bypass, 621 1: WB cache, 622 2: WT cache, 623 3: special (c and e are illegal, f is reserved). 624 For MPU: 625 0: illegal, 626 1: WB cache, 627 2: WB, no-write-allocate cache, 628 3: WT cache, 629 4: cache bypass. 630 631config KSEG_PADDR 632 hex "Physical address of the KSEG mapping" 633 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 634 default 0x00000000 635 help 636 This is the physical address where KSEG is mapped. Please refer to 637 the chosen KSEG layout help for the required address alignment. 638 Unpacked kernel image (including vectors) must be located completely 639 within KSEG. 640 Physical memory below this address is not available to linux. 641 642 If unsure, leave the default value here. 643 644config KERNEL_VIRTUAL_ADDRESS 645 hex "Kernel virtual address" 646 depends on MMU && XIP_KERNEL 647 default 0xd0003000 648 help 649 This is the virtual address where the XIP kernel is mapped. 650 XIP kernel may be mapped into KSEG or KIO region, virtual address 651 provided here must match kernel load address provided in 652 KERNEL_LOAD_ADDRESS. 653 654config KERNEL_LOAD_ADDRESS 655 hex "Kernel load address" 656 default 0x60003000 if !MMU 657 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 658 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 659 help 660 This is the address where the kernel is loaded. 661 It is virtual address for MMUv2 configurations and physical address 662 for all other configurations. 663 664 If unsure, leave the default value here. 665 666choice 667 prompt "Relocatable vectors location" 668 default XTENSA_VECTORS_IN_TEXT 669 help 670 Choose whether relocatable vectors are merged into the kernel .text 671 or placed separately at runtime. This option does not affect 672 configurations without VECBASE register where vectors are always 673 placed at their hardware-defined locations. 674 675config XTENSA_VECTORS_IN_TEXT 676 bool "Merge relocatable vectors into kernel text" 677 depends on !MTD_XIP 678 help 679 This option puts relocatable vectors into the kernel .text section 680 with proper alignment. 681 This is a safe choice for most configurations. 682 683config XTENSA_VECTORS_SEPARATE 684 bool "Put relocatable vectors at fixed address" 685 help 686 This option puts relocatable vectors at specific virtual address. 687 Vectors are merged with the .init data in the kernel image and 688 are copied into their designated location during kernel startup. 689 Use it to put vectors into IRAM or out of FLASH on kernels with 690 XIP-aware MTD support. 691 692endchoice 693 694config VECTORS_ADDR 695 hex "Kernel vectors virtual address" 696 default 0x00000000 697 depends on XTENSA_VECTORS_SEPARATE 698 help 699 This is the virtual address of the (relocatable) vectors base. 700 It must be within KSEG if MMU is used. 701 702config XIP_DATA_ADDR 703 hex "XIP kernel data virtual address" 704 depends on XIP_KERNEL 705 default 0x00000000 706 help 707 This is the virtual address where XIP kernel data is copied. 708 It must be within KSEG if MMU is used. 709 710config PLATFORM_WANT_DEFAULT_MEM 711 def_bool n 712 713config DEFAULT_MEM_START 714 hex 715 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 716 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 717 default 0x00000000 718 help 719 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 720 in noMMU configurations. 721 722 If unsure, leave the default value here. 723 724choice 725 prompt "KSEG layout" 726 depends on MMU 727 default XTENSA_KSEG_MMU_V2 728 729config XTENSA_KSEG_MMU_V2 730 bool "MMUv2: 128MB cached + 128MB uncached" 731 help 732 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 733 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 734 without cache. 735 KSEG_PADDR must be aligned to 128MB. 736 737config XTENSA_KSEG_256M 738 bool "256MB cached + 256MB uncached" 739 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 740 help 741 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 742 with cache and to 0xc0000000 without cache. 743 KSEG_PADDR must be aligned to 256MB. 744 745config XTENSA_KSEG_512M 746 bool "512MB cached + 512MB uncached" 747 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 748 help 749 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 750 with cache and to 0xc0000000 without cache. 751 KSEG_PADDR must be aligned to 256MB. 752 753endchoice 754 755config HIGHMEM 756 bool "High Memory Support" 757 depends on MMU 758 select KMAP_LOCAL 759 help 760 Linux can use the full amount of RAM in the system by 761 default. However, the default MMUv2 setup only maps the 762 lowermost 128 MB of memory linearly to the areas starting 763 at 0xd0000000 (cached) and 0xd8000000 (uncached). 764 When there are more than 128 MB memory in the system not 765 all of it can be "permanently mapped" by the kernel. 766 The physical memory that's not permanently mapped is called 767 "high memory". 768 769 If you are compiling a kernel which will never run on a 770 machine with more than 128 MB total physical RAM, answer 771 N here. 772 773 If unsure, say Y. 774 775config ARCH_FORCE_MAX_ORDER 776 int "Order of maximal physically contiguous allocations" 777 default "10" 778 help 779 The kernel page allocator limits the size of maximal physically 780 contiguous allocations. The limit is called MAX_ORDER and it 781 defines the maximal power of two of number of pages that can be 782 allocated as a single contiguous block. This option allows 783 overriding the default setting when ability to allocate very 784 large blocks of physically contiguous memory is required. 785 786 Don't change if unsure. 787 788endmenu 789 790menu "Power management options" 791 792config ARCH_HIBERNATION_POSSIBLE 793 def_bool y 794 795source "kernel/power/Kconfig" 796 797endmenu 798