1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _X86_MICROCODE_INTERNAL_H 3 #define _X86_MICROCODE_INTERNAL_H 4 5 #include <linux/earlycpio.h> 6 #include <linux/initrd.h> 7 8 #include <asm/cpu.h> 9 #include <asm/microcode.h> 10 11 struct device; 12 13 enum ucode_state { 14 UCODE_OK = 0, 15 UCODE_NEW, 16 UCODE_UPDATED, 17 UCODE_NFOUND, 18 UCODE_ERROR, 19 UCODE_TIMEOUT, 20 UCODE_OFFLINE, 21 }; 22 23 struct microcode_ops { 24 enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); 25 void (*microcode_fini_cpu)(int cpu); 26 27 /* 28 * The generic 'microcode_core' part guarantees that the callbacks 29 * below run on a target CPU when they are being called. 30 * See also the "Synchronization" section in microcode_core.c. 31 */ 32 enum ucode_state (*apply_microcode)(int cpu); 33 int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); 34 void (*finalize_late_load)(int result); 35 unsigned int nmi_safe : 1, 36 use_nmi : 1; 37 }; 38 39 extern struct ucode_cpu_info ucode_cpu_info[]; 40 struct cpio_data find_microcode_in_initrd(const char *path); 41 42 #define MAX_UCODE_COUNT 128 43 44 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) 45 #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') 46 #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') 47 #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') 48 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') 49 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') 50 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') 51 52 #define CPUID_IS(a, b, c, ebx, ecx, edx) \ 53 (!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c)))) 54 55 /* 56 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. 57 * x86_cpuid_vendor() gets vendor id for BSP. 58 * 59 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify 60 * coding, we still use x86_cpuid_vendor() to get vendor id for AP. 61 * 62 * x86_cpuid_vendor() gets vendor information directly from CPUID. 63 */ 64 static inline int x86_cpuid_vendor(void) 65 { 66 u32 eax = 0x00000000; 67 u32 ebx, ecx = 0, edx; 68 69 native_cpuid(&eax, &ebx, &ecx, &edx); 70 71 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) 72 return X86_VENDOR_INTEL; 73 74 if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) 75 return X86_VENDOR_AMD; 76 77 return X86_VENDOR_UNKNOWN; 78 } 79 80 static inline unsigned int x86_cpuid_family(void) 81 { 82 u32 eax = 0x00000001; 83 u32 ebx, ecx = 0, edx; 84 85 native_cpuid(&eax, &ebx, &ecx, &edx); 86 87 return x86_family(eax); 88 } 89 90 extern bool dis_ucode_ldr; 91 92 #ifdef CONFIG_CPU_SUP_AMD 93 void load_ucode_amd_bsp(unsigned int family); 94 void load_ucode_amd_ap(unsigned int family); 95 int save_microcode_in_initrd_amd(unsigned int family); 96 void reload_ucode_amd(unsigned int cpu); 97 struct microcode_ops *init_amd_microcode(void); 98 void exit_amd_microcode(void); 99 #else /* CONFIG_CPU_SUP_AMD */ 100 static inline void load_ucode_amd_bsp(unsigned int family) { } 101 static inline void load_ucode_amd_ap(unsigned int family) { } 102 static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } 103 static inline void reload_ucode_amd(unsigned int cpu) { } 104 static inline struct microcode_ops *init_amd_microcode(void) { return NULL; } 105 static inline void exit_amd_microcode(void) { } 106 #endif /* !CONFIG_CPU_SUP_AMD */ 107 108 #ifdef CONFIG_CPU_SUP_INTEL 109 void load_ucode_intel_bsp(void); 110 void load_ucode_intel_ap(void); 111 void reload_ucode_intel(void); 112 struct microcode_ops *init_intel_microcode(void); 113 #else /* CONFIG_CPU_SUP_INTEL */ 114 static inline void load_ucode_intel_bsp(void) { } 115 static inline void load_ucode_intel_ap(void) { } 116 static inline void reload_ucode_intel(void) { } 117 static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } 118 #endif /* !CONFIG_CPU_SUP_INTEL */ 119 120 #endif /* _X86_MICROCODE_INTERNAL_H */ 121