1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _X86_MICROCODE_INTERNAL_H 3 #define _X86_MICROCODE_INTERNAL_H 4 5 #include <linux/earlycpio.h> 6 #include <linux/initrd.h> 7 8 #include <asm/cpu.h> 9 #include <asm/microcode.h> 10 11 struct device; 12 13 enum ucode_state { 14 UCODE_OK = 0, 15 UCODE_NEW, 16 UCODE_UPDATED, 17 UCODE_NFOUND, 18 UCODE_ERROR, 19 }; 20 21 struct microcode_ops { 22 enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); 23 24 void (*microcode_fini_cpu)(int cpu); 25 26 /* 27 * The generic 'microcode_core' part guarantees that 28 * the callbacks below run on a target cpu when they 29 * are being called. 30 * See also the "Synchronization" section in microcode_core.c. 31 */ 32 enum ucode_state (*apply_microcode)(int cpu); 33 int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); 34 void (*finalize_late_load)(int result); 35 }; 36 37 extern struct ucode_cpu_info ucode_cpu_info[]; 38 struct cpio_data find_microcode_in_initrd(const char *path); 39 40 #define MAX_UCODE_COUNT 128 41 42 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) 43 #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') 44 #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') 45 #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') 46 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') 47 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') 48 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') 49 50 #define CPUID_IS(a, b, c, ebx, ecx, edx) \ 51 (!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c)))) 52 53 /* 54 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. 55 * x86_cpuid_vendor() gets vendor id for BSP. 56 * 57 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify 58 * coding, we still use x86_cpuid_vendor() to get vendor id for AP. 59 * 60 * x86_cpuid_vendor() gets vendor information directly from CPUID. 61 */ 62 static inline int x86_cpuid_vendor(void) 63 { 64 u32 eax = 0x00000000; 65 u32 ebx, ecx = 0, edx; 66 67 native_cpuid(&eax, &ebx, &ecx, &edx); 68 69 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) 70 return X86_VENDOR_INTEL; 71 72 if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) 73 return X86_VENDOR_AMD; 74 75 return X86_VENDOR_UNKNOWN; 76 } 77 78 static inline unsigned int x86_cpuid_family(void) 79 { 80 u32 eax = 0x00000001; 81 u32 ebx, ecx = 0, edx; 82 83 native_cpuid(&eax, &ebx, &ecx, &edx); 84 85 return x86_family(eax); 86 } 87 88 extern bool dis_ucode_ldr; 89 extern bool initrd_gone; 90 91 #ifdef CONFIG_CPU_SUP_AMD 92 void load_ucode_amd_bsp(unsigned int family); 93 void load_ucode_amd_ap(unsigned int family); 94 void load_ucode_amd_early(unsigned int cpuid_1_eax); 95 int save_microcode_in_initrd_amd(unsigned int family); 96 void reload_ucode_amd(unsigned int cpu); 97 struct microcode_ops *init_amd_microcode(void); 98 void exit_amd_microcode(void); 99 #else /* CONFIG_CPU_SUP_AMD */ 100 static inline void load_ucode_amd_bsp(unsigned int family) { } 101 static inline void load_ucode_amd_ap(unsigned int family) { } 102 static inline void load_ucode_amd_early(unsigned int family) { } 103 static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } 104 static inline void reload_ucode_amd(unsigned int cpu) { } 105 static inline struct microcode_ops *init_amd_microcode(void) { return NULL; } 106 static inline void exit_amd_microcode(void) { } 107 #endif /* !CONFIG_CPU_SUP_AMD */ 108 109 #ifdef CONFIG_CPU_SUP_INTEL 110 void load_ucode_intel_bsp(void); 111 void load_ucode_intel_ap(void); 112 void reload_ucode_intel(void); 113 struct microcode_ops *init_intel_microcode(void); 114 #else /* CONFIG_CPU_SUP_INTEL */ 115 static inline void load_ucode_intel_bsp(void) { } 116 static inline void load_ucode_intel_ap(void) { } 117 static inline void reload_ucode_intel(void) { } 118 static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } 119 #endif /* !CONFIG_CPU_SUP_INTEL */ 120 121 #endif /* _X86_MICROCODE_INTERNAL_H */ 122