1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/thread_info.h> 10 #include <linux/init.h> 11 #include <linux/uaccess.h> 12 13 #include <asm/cpufeature.h> 14 #include <asm/pgtable.h> 15 #include <asm/msr.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 #include <asm/intel-family.h> 19 #include <asm/microcode_intel.h> 20 #include <asm/hwcap2.h> 21 #include <asm/elf.h> 22 23 #ifdef CONFIG_X86_64 24 #include <linux/topology.h> 25 #endif 26 27 #include "cpu.h" 28 29 #ifdef CONFIG_X86_LOCAL_APIC 30 #include <asm/mpspec.h> 31 #include <asm/apic.h> 32 #endif 33 34 /* 35 * Just in case our CPU detection goes bad, or you have a weird system, 36 * allow a way to override the automatic disabling of MPX. 37 */ 38 static int forcempx; 39 40 static int __init forcempx_setup(char *__unused) 41 { 42 forcempx = 1; 43 44 return 1; 45 } 46 __setup("intel-skd-046-workaround=disable", forcempx_setup); 47 48 void check_mpx_erratum(struct cpuinfo_x86 *c) 49 { 50 if (forcempx) 51 return; 52 /* 53 * Turn off the MPX feature on CPUs where SMEP is not 54 * available or disabled. 55 * 56 * Works around Intel Erratum SKD046: "Branch Instructions 57 * May Initialize MPX Bound Registers Incorrectly". 58 * 59 * This might falsely disable MPX on systems without 60 * SMEP, like Atom processors without SMEP. But there 61 * is no such hardware known at the moment. 62 */ 63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 64 setup_clear_cpu_cap(X86_FEATURE_MPX); 65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 66 } 67 } 68 69 static bool ring3mwait_disabled __read_mostly; 70 71 static int __init ring3mwait_disable(char *__unused) 72 { 73 ring3mwait_disabled = true; 74 return 0; 75 } 76 __setup("ring3mwait=disable", ring3mwait_disable); 77 78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 79 { 80 /* 81 * Ring 3 MONITOR/MWAIT feature cannot be detected without 82 * cpu model and family comparison. 83 */ 84 if (c->x86 != 6) 85 return; 86 switch (c->x86_model) { 87 case INTEL_FAM6_XEON_PHI_KNL: 88 case INTEL_FAM6_XEON_PHI_KNM: 89 break; 90 default: 91 return; 92 } 93 94 if (ring3mwait_disabled) 95 return; 96 97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 98 this_cpu_or(msr_misc_features_shadow, 99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 100 101 if (c == &boot_cpu_data) 102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 103 } 104 105 /* 106 * Early microcode releases for the Spectre v2 mitigation were broken. 107 * Information taken from; 108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf 109 * - https://kb.vmware.com/s/article/52345 110 * - Microcode revisions observed in the wild 111 * - Release note from 20180108 microcode release 112 */ 113 struct sku_microcode { 114 u8 model; 115 u8 stepping; 116 u32 microcode; 117 }; 118 static const struct sku_microcode spectre_bad_microcodes[] = { 119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 }, 120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 }, 121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 }, 122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 }, 123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 }, 124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, 125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, 126 { INTEL_FAM6_SKYLAKE_DESKTOP, 0x03, 0xc2 }, 127 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 }, 128 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b }, 129 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 }, 130 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 }, 131 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, 132 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 }, 133 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 }, 134 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 }, 135 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, 136 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, 137 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, 138 /* Observed in the wild */ 139 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, 140 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, 141 }; 142 143 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 144 { 145 int i; 146 147 /* 148 * We know that the hypervisor lie to us on the microcode version so 149 * we may as well hope that it is running the correct version. 150 */ 151 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 152 return false; 153 154 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 155 if (c->x86_model == spectre_bad_microcodes[i].model && 156 c->x86_stepping == spectre_bad_microcodes[i].stepping) 157 return (c->microcode <= spectre_bad_microcodes[i].microcode); 158 } 159 return false; 160 } 161 162 static void early_init_intel(struct cpuinfo_x86 *c) 163 { 164 u64 misc_enable; 165 166 /* Unmask CPUID levels if masked: */ 167 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 168 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 169 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 170 c->cpuid_level = cpuid_eax(0); 171 get_cpu_cap(c); 172 } 173 } 174 175 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 176 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 177 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 178 179 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 180 c->microcode = intel_get_microcode_revision(); 181 182 /* Now if any of them are set, check the blacklist and clear the lot */ 183 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 184 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 185 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 186 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 187 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 188 setup_clear_cpu_cap(X86_FEATURE_IBRS); 189 setup_clear_cpu_cap(X86_FEATURE_IBPB); 190 setup_clear_cpu_cap(X86_FEATURE_STIBP); 191 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 192 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 193 } 194 195 /* 196 * Atom erratum AAE44/AAF40/AAG38/AAH41: 197 * 198 * A race condition between speculative fetches and invalidating 199 * a large page. This is worked around in microcode, but we 200 * need the microcode to have already been loaded... so if it is 201 * not, recommend a BIOS update and disable large pages. 202 */ 203 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && 204 c->microcode < 0x20e) { 205 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 206 clear_cpu_cap(c, X86_FEATURE_PSE); 207 } 208 209 #ifdef CONFIG_X86_64 210 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 211 #else 212 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 213 if (c->x86 == 15 && c->x86_cache_alignment == 64) 214 c->x86_cache_alignment = 128; 215 #endif 216 217 /* CPUID workaround for 0F33/0F34 CPU */ 218 if (c->x86 == 0xF && c->x86_model == 0x3 219 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 220 c->x86_phys_bits = 36; 221 222 /* 223 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 224 * with P/T states and does not stop in deep C-states. 225 * 226 * It is also reliable across cores and sockets. (but not across 227 * cabinets - we turn it off in that case explicitly.) 228 */ 229 if (c->x86_power & (1 << 8)) { 230 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 231 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 232 } 233 234 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 235 if (c->x86 == 6) { 236 switch (c->x86_model) { 237 case 0x27: /* Penwell */ 238 case 0x35: /* Cloverview */ 239 case 0x4a: /* Merrifield */ 240 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 241 break; 242 default: 243 break; 244 } 245 } 246 247 /* 248 * There is a known erratum on Pentium III and Core Solo 249 * and Core Duo CPUs. 250 * " Page with PAT set to WC while associated MTRR is UC 251 * may consolidate to UC " 252 * Because of this erratum, it is better to stick with 253 * setting WC in MTRR rather than using PAT on these CPUs. 254 * 255 * Enable PAT WC only on P4, Core 2 or later CPUs. 256 */ 257 if (c->x86 == 6 && c->x86_model < 15) 258 clear_cpu_cap(c, X86_FEATURE_PAT); 259 260 /* 261 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 262 * clear the fast string and enhanced fast string CPU capabilities. 263 */ 264 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 265 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 266 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 267 pr_info("Disabled fast string operations\n"); 268 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 269 setup_clear_cpu_cap(X86_FEATURE_ERMS); 270 } 271 } 272 273 /* 274 * Intel Quark Core DevMan_001.pdf section 6.4.11 275 * "The operating system also is required to invalidate (i.e., flush) 276 * the TLB when any changes are made to any of the page table entries. 277 * The operating system must reload CR3 to cause the TLB to be flushed" 278 * 279 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 280 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 281 * to be modified. 282 */ 283 if (c->x86 == 5 && c->x86_model == 9) { 284 pr_info("Disabling PGE capability bit\n"); 285 setup_clear_cpu_cap(X86_FEATURE_PGE); 286 } 287 288 if (c->cpuid_level >= 0x00000001) { 289 u32 eax, ebx, ecx, edx; 290 291 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 292 /* 293 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 294 * apicids which are reserved per package. Store the resulting 295 * shift value for the package management code. 296 */ 297 if (edx & (1U << 28)) 298 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 299 } 300 301 check_mpx_erratum(c); 302 } 303 304 #ifdef CONFIG_X86_32 305 /* 306 * Early probe support logic for ppro memory erratum #50 307 * 308 * This is called before we do cpu ident work 309 */ 310 311 int ppro_with_ram_bug(void) 312 { 313 /* Uses data from early_cpu_detect now */ 314 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 315 boot_cpu_data.x86 == 6 && 316 boot_cpu_data.x86_model == 1 && 317 boot_cpu_data.x86_stepping < 8) { 318 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 319 return 1; 320 } 321 return 0; 322 } 323 324 static void intel_smp_check(struct cpuinfo_x86 *c) 325 { 326 /* calling is from identify_secondary_cpu() ? */ 327 if (!c->cpu_index) 328 return; 329 330 /* 331 * Mask B, Pentium, but not Pentium MMX 332 */ 333 if (c->x86 == 5 && 334 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 335 c->x86_model <= 3) { 336 /* 337 * Remember we have B step Pentia with bugs 338 */ 339 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 340 "with B stepping processors.\n"); 341 } 342 } 343 344 static int forcepae; 345 static int __init forcepae_setup(char *__unused) 346 { 347 forcepae = 1; 348 return 1; 349 } 350 __setup("forcepae", forcepae_setup); 351 352 static void intel_workarounds(struct cpuinfo_x86 *c) 353 { 354 #ifdef CONFIG_X86_F00F_BUG 355 /* 356 * All models of Pentium and Pentium with MMX technology CPUs 357 * have the F0 0F bug, which lets nonprivileged users lock up the 358 * system. Announce that the fault handler will be checking for it. 359 * The Quark is also family 5, but does not have the same bug. 360 */ 361 clear_cpu_bug(c, X86_BUG_F00F); 362 if (c->x86 == 5 && c->x86_model < 9) { 363 static int f00f_workaround_enabled; 364 365 set_cpu_bug(c, X86_BUG_F00F); 366 if (!f00f_workaround_enabled) { 367 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 368 f00f_workaround_enabled = 1; 369 } 370 } 371 #endif 372 373 /* 374 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 375 * model 3 mask 3 376 */ 377 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 378 clear_cpu_cap(c, X86_FEATURE_SEP); 379 380 /* 381 * PAE CPUID issue: many Pentium M report no PAE but may have a 382 * functionally usable PAE implementation. 383 * Forcefully enable PAE if kernel parameter "forcepae" is present. 384 */ 385 if (forcepae) { 386 pr_warn("PAE forced!\n"); 387 set_cpu_cap(c, X86_FEATURE_PAE); 388 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 389 } 390 391 /* 392 * P4 Xeon erratum 037 workaround. 393 * Hardware prefetcher may cause stale data to be loaded into the cache. 394 */ 395 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 396 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 397 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 398 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 399 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 400 } 401 } 402 403 /* 404 * See if we have a good local APIC by checking for buggy Pentia, 405 * i.e. all B steppings and the C2 stepping of P54C when using their 406 * integrated APIC (see 11AP erratum in "Pentium Processor 407 * Specification Update"). 408 */ 409 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 410 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 411 set_cpu_bug(c, X86_BUG_11AP); 412 413 414 #ifdef CONFIG_X86_INTEL_USERCOPY 415 /* 416 * Set up the preferred alignment for movsl bulk memory moves 417 */ 418 switch (c->x86) { 419 case 4: /* 486: untested */ 420 break; 421 case 5: /* Old Pentia: untested */ 422 break; 423 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 424 movsl_mask.mask = 7; 425 break; 426 case 15: /* P4 is OK down to 8-byte alignment */ 427 movsl_mask.mask = 7; 428 break; 429 } 430 #endif 431 432 intel_smp_check(c); 433 } 434 #else 435 static void intel_workarounds(struct cpuinfo_x86 *c) 436 { 437 } 438 #endif 439 440 static void srat_detect_node(struct cpuinfo_x86 *c) 441 { 442 #ifdef CONFIG_NUMA 443 unsigned node; 444 int cpu = smp_processor_id(); 445 446 /* Don't do the funky fallback heuristics the AMD version employs 447 for now. */ 448 node = numa_cpu_node(cpu); 449 if (node == NUMA_NO_NODE || !node_online(node)) { 450 /* reuse the value from init_cpu_to_node() */ 451 node = cpu_to_node(cpu); 452 } 453 numa_set_node(cpu, node); 454 #endif 455 } 456 457 /* 458 * find out the number of processor cores on the die 459 */ 460 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 461 { 462 unsigned int eax, ebx, ecx, edx; 463 464 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 465 return 1; 466 467 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 468 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 469 if (eax & 0x1f) 470 return (eax >> 26) + 1; 471 else 472 return 1; 473 } 474 475 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 476 { 477 /* Intel VMX MSR indicated features */ 478 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 479 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 480 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 481 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 482 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 483 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 484 485 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 486 487 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 488 clear_cpu_cap(c, X86_FEATURE_VNMI); 489 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 490 clear_cpu_cap(c, X86_FEATURE_EPT); 491 clear_cpu_cap(c, X86_FEATURE_VPID); 492 493 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 494 msr_ctl = vmx_msr_high | vmx_msr_low; 495 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 496 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 497 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 498 set_cpu_cap(c, X86_FEATURE_VNMI); 499 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 500 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 501 vmx_msr_low, vmx_msr_high); 502 msr_ctl2 = vmx_msr_high | vmx_msr_low; 503 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 504 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 505 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 506 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 507 set_cpu_cap(c, X86_FEATURE_EPT); 508 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 509 set_cpu_cap(c, X86_FEATURE_VPID); 510 } 511 } 512 513 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 514 { 515 u64 epb; 516 517 /* 518 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 519 * (x86_energy_perf_policy(8) is available to change it at run-time.) 520 */ 521 if (!cpu_has(c, X86_FEATURE_EPB)) 522 return; 523 524 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 525 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 526 return; 527 528 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 529 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 530 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 531 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 532 } 533 534 static void intel_bsp_resume(struct cpuinfo_x86 *c) 535 { 536 /* 537 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 538 * so reinitialize it properly like during bootup: 539 */ 540 init_intel_energy_perf(c); 541 } 542 543 static void init_cpuid_fault(struct cpuinfo_x86 *c) 544 { 545 u64 msr; 546 547 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 548 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 549 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 550 } 551 } 552 553 static void init_intel_misc_features(struct cpuinfo_x86 *c) 554 { 555 u64 msr; 556 557 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 558 return; 559 560 /* Clear all MISC features */ 561 this_cpu_write(msr_misc_features_shadow, 0); 562 563 /* Check features and update capabilities and shadow control bits */ 564 init_cpuid_fault(c); 565 probe_xeon_phi_r3mwait(c); 566 567 msr = this_cpu_read(msr_misc_features_shadow); 568 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 569 } 570 571 static void init_intel(struct cpuinfo_x86 *c) 572 { 573 unsigned int l2 = 0; 574 575 early_init_intel(c); 576 577 intel_workarounds(c); 578 579 /* 580 * Detect the extended topology information if available. This 581 * will reinitialise the initial_apicid which will be used 582 * in init_intel_cacheinfo() 583 */ 584 detect_extended_topology(c); 585 586 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 587 /* 588 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 589 * detection. 590 */ 591 c->x86_max_cores = intel_num_cpu_cores(c); 592 #ifdef CONFIG_X86_32 593 detect_ht(c); 594 #endif 595 } 596 597 l2 = init_intel_cacheinfo(c); 598 599 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 600 if (l2 == 0) { 601 cpu_detect_cache_sizes(c); 602 l2 = c->x86_cache_size; 603 } 604 605 if (c->cpuid_level > 9) { 606 unsigned eax = cpuid_eax(10); 607 /* Check for version and the number of counters */ 608 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 609 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 610 } 611 612 if (cpu_has(c, X86_FEATURE_XMM2)) 613 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 614 615 if (boot_cpu_has(X86_FEATURE_DS)) { 616 unsigned int l1; 617 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 618 if (!(l1 & (1<<11))) 619 set_cpu_cap(c, X86_FEATURE_BTS); 620 if (!(l1 & (1<<12))) 621 set_cpu_cap(c, X86_FEATURE_PEBS); 622 } 623 624 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 625 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 626 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 627 628 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 629 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 630 set_cpu_bug(c, X86_BUG_MONITOR); 631 632 #ifdef CONFIG_X86_64 633 if (c->x86 == 15) 634 c->x86_cache_alignment = c->x86_clflush_size * 2; 635 if (c->x86 == 6) 636 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 637 #else 638 /* 639 * Names for the Pentium II/Celeron processors 640 * detectable only by also checking the cache size. 641 * Dixon is NOT a Celeron. 642 */ 643 if (c->x86 == 6) { 644 char *p = NULL; 645 646 switch (c->x86_model) { 647 case 5: 648 if (l2 == 0) 649 p = "Celeron (Covington)"; 650 else if (l2 == 256) 651 p = "Mobile Pentium II (Dixon)"; 652 break; 653 654 case 6: 655 if (l2 == 128) 656 p = "Celeron (Mendocino)"; 657 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 658 p = "Celeron-A"; 659 break; 660 661 case 8: 662 if (l2 == 128) 663 p = "Celeron (Coppermine)"; 664 break; 665 } 666 667 if (p) 668 strcpy(c->x86_model_id, p); 669 } 670 671 if (c->x86 == 15) 672 set_cpu_cap(c, X86_FEATURE_P4); 673 if (c->x86 == 6) 674 set_cpu_cap(c, X86_FEATURE_P3); 675 #endif 676 677 /* Work around errata */ 678 srat_detect_node(c); 679 680 if (cpu_has(c, X86_FEATURE_VMX)) 681 detect_vmx_virtcap(c); 682 683 init_intel_energy_perf(c); 684 685 init_intel_misc_features(c); 686 } 687 688 #ifdef CONFIG_X86_32 689 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 690 { 691 /* 692 * Intel PIII Tualatin. This comes in two flavours. 693 * One has 256kb of cache, the other 512. We have no way 694 * to determine which, so we use a boottime override 695 * for the 512kb model, and assume 256 otherwise. 696 */ 697 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 698 size = 256; 699 700 /* 701 * Intel Quark SoC X1000 contains a 4-way set associative 702 * 16K cache with a 16 byte cache line and 256 lines per tag 703 */ 704 if ((c->x86 == 5) && (c->x86_model == 9)) 705 size = 16; 706 return size; 707 } 708 #endif 709 710 #define TLB_INST_4K 0x01 711 #define TLB_INST_4M 0x02 712 #define TLB_INST_2M_4M 0x03 713 714 #define TLB_INST_ALL 0x05 715 #define TLB_INST_1G 0x06 716 717 #define TLB_DATA_4K 0x11 718 #define TLB_DATA_4M 0x12 719 #define TLB_DATA_2M_4M 0x13 720 #define TLB_DATA_4K_4M 0x14 721 722 #define TLB_DATA_1G 0x16 723 724 #define TLB_DATA0_4K 0x21 725 #define TLB_DATA0_4M 0x22 726 #define TLB_DATA0_2M_4M 0x23 727 728 #define STLB_4K 0x41 729 #define STLB_4K_2M 0x42 730 731 static const struct _tlb_table intel_tlb_table[] = { 732 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 733 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 734 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 735 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 736 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 737 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 738 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 739 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 740 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 741 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 742 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 743 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 744 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 745 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 746 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 747 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 748 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 749 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 750 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 751 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 752 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 753 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 754 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 755 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 756 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 757 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 758 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 759 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 760 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 761 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 762 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 763 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 764 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 765 { 0x00, 0, 0 } 766 }; 767 768 static void intel_tlb_lookup(const unsigned char desc) 769 { 770 unsigned char k; 771 if (desc == 0) 772 return; 773 774 /* look up this descriptor in the table */ 775 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 776 intel_tlb_table[k].descriptor != 0; k++) 777 ; 778 779 if (intel_tlb_table[k].tlb_type == 0) 780 return; 781 782 switch (intel_tlb_table[k].tlb_type) { 783 case STLB_4K: 784 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 785 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 786 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 787 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 788 break; 789 case STLB_4K_2M: 790 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 791 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 792 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 793 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 794 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 795 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 796 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 797 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 798 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 799 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 800 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 801 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 802 break; 803 case TLB_INST_ALL: 804 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 805 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 806 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 807 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 808 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 809 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 810 break; 811 case TLB_INST_4K: 812 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 813 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 814 break; 815 case TLB_INST_4M: 816 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 817 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 818 break; 819 case TLB_INST_2M_4M: 820 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 821 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 822 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 823 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 824 break; 825 case TLB_DATA_4K: 826 case TLB_DATA0_4K: 827 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 828 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 829 break; 830 case TLB_DATA_4M: 831 case TLB_DATA0_4M: 832 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 833 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 834 break; 835 case TLB_DATA_2M_4M: 836 case TLB_DATA0_2M_4M: 837 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 838 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 839 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 840 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 841 break; 842 case TLB_DATA_4K_4M: 843 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 844 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 845 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 846 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 847 break; 848 case TLB_DATA_1G: 849 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 850 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 851 break; 852 } 853 } 854 855 static void intel_detect_tlb(struct cpuinfo_x86 *c) 856 { 857 int i, j, n; 858 unsigned int regs[4]; 859 unsigned char *desc = (unsigned char *)regs; 860 861 if (c->cpuid_level < 2) 862 return; 863 864 /* Number of times to iterate */ 865 n = cpuid_eax(2) & 0xFF; 866 867 for (i = 0 ; i < n ; i++) { 868 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 869 870 /* If bit 31 is set, this is an unknown format */ 871 for (j = 0 ; j < 3 ; j++) 872 if (regs[j] & (1 << 31)) 873 regs[j] = 0; 874 875 /* Byte 0 is level count, not a descriptor */ 876 for (j = 1 ; j < 16 ; j++) 877 intel_tlb_lookup(desc[j]); 878 } 879 } 880 881 static const struct cpu_dev intel_cpu_dev = { 882 .c_vendor = "Intel", 883 .c_ident = { "GenuineIntel" }, 884 #ifdef CONFIG_X86_32 885 .legacy_models = { 886 { .family = 4, .model_names = 887 { 888 [0] = "486 DX-25/33", 889 [1] = "486 DX-50", 890 [2] = "486 SX", 891 [3] = "486 DX/2", 892 [4] = "486 SL", 893 [5] = "486 SX/2", 894 [7] = "486 DX/2-WB", 895 [8] = "486 DX/4", 896 [9] = "486 DX/4-WB" 897 } 898 }, 899 { .family = 5, .model_names = 900 { 901 [0] = "Pentium 60/66 A-step", 902 [1] = "Pentium 60/66", 903 [2] = "Pentium 75 - 200", 904 [3] = "OverDrive PODP5V83", 905 [4] = "Pentium MMX", 906 [7] = "Mobile Pentium 75 - 200", 907 [8] = "Mobile Pentium MMX", 908 [9] = "Quark SoC X1000", 909 } 910 }, 911 { .family = 6, .model_names = 912 { 913 [0] = "Pentium Pro A-step", 914 [1] = "Pentium Pro", 915 [3] = "Pentium II (Klamath)", 916 [4] = "Pentium II (Deschutes)", 917 [5] = "Pentium II (Deschutes)", 918 [6] = "Mobile Pentium II", 919 [7] = "Pentium III (Katmai)", 920 [8] = "Pentium III (Coppermine)", 921 [10] = "Pentium III (Cascades)", 922 [11] = "Pentium III (Tualatin)", 923 } 924 }, 925 { .family = 15, .model_names = 926 { 927 [0] = "Pentium 4 (Unknown)", 928 [1] = "Pentium 4 (Willamette)", 929 [2] = "Pentium 4 (Northwood)", 930 [4] = "Pentium 4 (Foster)", 931 [5] = "Pentium 4 (Foster)", 932 } 933 }, 934 }, 935 .legacy_cache_size = intel_size_cache, 936 #endif 937 .c_detect_tlb = intel_detect_tlb, 938 .c_early_init = early_init_intel, 939 .c_init = init_intel, 940 .c_bsp_resume = intel_bsp_resume, 941 .c_x86_vendor = X86_VENDOR_INTEL, 942 }; 943 944 cpu_dev_register(intel_cpu_dev); 945 946