1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct vm86; 11 12 #include <asm/math_emu.h> 13 #include <asm/segment.h> 14 #include <asm/types.h> 15 #include <uapi/asm/sigcontext.h> 16 #include <asm/current.h> 17 #include <asm/cpufeatures.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/special_insns.h> 25 #include <asm/fpu/types.h> 26 #include <asm/unwind_hints.h> 27 28 #include <linux/personality.h> 29 #include <linux/cache.h> 30 #include <linux/threads.h> 31 #include <linux/math64.h> 32 #include <linux/err.h> 33 #include <linux/irqflags.h> 34 #include <linux/mem_encrypt.h> 35 36 /* 37 * We handle most unaligned accesses in hardware. On the other hand 38 * unaligned DMA can be quite expensive on some Nehalem processors. 39 * 40 * Based on this we disable the IP header alignment in network drivers. 41 */ 42 #define NET_IP_ALIGN 0 43 44 #define HBP_NUM 4 45 46 /* 47 * These alignment constraints are for performance in the vSMP case, 48 * but in the task_struct case we must also meet hardware imposed 49 * alignment requirements of the FPU state: 50 */ 51 #ifdef CONFIG_X86_VSMP 52 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 53 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 54 #else 55 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 56 # define ARCH_MIN_MMSTRUCT_ALIGN 0 57 #endif 58 59 enum tlb_infos { 60 ENTRIES, 61 NR_INFO 62 }; 63 64 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 65 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 66 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 67 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 68 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 69 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 70 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 71 72 /* 73 * CPU type and hardware bug flags. Kept separately for each CPU. 74 * Members of this structure are referenced in head_32.S, so think twice 75 * before touching them. [mj] 76 */ 77 78 struct cpuinfo_x86 { 79 __u8 x86; /* CPU family */ 80 __u8 x86_vendor; /* CPU vendor */ 81 __u8 x86_model; 82 __u8 x86_stepping; 83 #ifdef CONFIG_X86_64 84 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 85 int x86_tlbsize; 86 #endif 87 __u8 x86_virt_bits; 88 __u8 x86_phys_bits; 89 /* CPUID returned core id bits: */ 90 __u8 x86_coreid_bits; 91 __u8 cu_id; 92 /* Max extended CPUID function supported: */ 93 __u32 extended_cpuid_level; 94 /* Maximum supported CPUID level, -1=no CPUID: */ 95 int cpuid_level; 96 __u32 x86_capability[NCAPINTS + NBUGINTS]; 97 char x86_vendor_id[16]; 98 char x86_model_id[64]; 99 /* in KB - valid for CPUS which support this call: */ 100 unsigned int x86_cache_size; 101 int x86_cache_alignment; /* In bytes */ 102 /* Cache QoS architectural values: */ 103 int x86_cache_max_rmid; /* max index */ 104 int x86_cache_occ_scale; /* scale to bytes */ 105 int x86_power; 106 unsigned long loops_per_jiffy; 107 /* cpuid returned max cores value: */ 108 u16 x86_max_cores; 109 u16 apicid; 110 u16 initial_apicid; 111 u16 x86_clflush_size; 112 /* number of cores as seen by the OS: */ 113 u16 booted_cores; 114 /* Physical processor id: */ 115 u16 phys_proc_id; 116 /* Logical processor id: */ 117 u16 logical_proc_id; 118 /* Core id: */ 119 u16 cpu_core_id; 120 u16 cpu_die_id; 121 u16 logical_die_id; 122 /* Index into per_cpu list: */ 123 u16 cpu_index; 124 u32 microcode; 125 /* Address space bits used by the cache internally */ 126 u8 x86_cache_bits; 127 unsigned initialized : 1; 128 } __randomize_layout; 129 130 struct cpuid_regs { 131 u32 eax, ebx, ecx, edx; 132 }; 133 134 enum cpuid_regs_idx { 135 CPUID_EAX = 0, 136 CPUID_EBX, 137 CPUID_ECX, 138 CPUID_EDX, 139 }; 140 141 #define X86_VENDOR_INTEL 0 142 #define X86_VENDOR_CYRIX 1 143 #define X86_VENDOR_AMD 2 144 #define X86_VENDOR_UMC 3 145 #define X86_VENDOR_CENTAUR 5 146 #define X86_VENDOR_TRANSMETA 7 147 #define X86_VENDOR_NSC 8 148 #define X86_VENDOR_HYGON 9 149 #define X86_VENDOR_NUM 10 150 151 #define X86_VENDOR_UNKNOWN 0xff 152 153 /* 154 * capabilities of CPUs 155 */ 156 extern struct cpuinfo_x86 boot_cpu_data; 157 extern struct cpuinfo_x86 new_cpu_data; 158 159 extern struct x86_hw_tss doublefault_tss; 160 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 161 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 162 163 #ifdef CONFIG_SMP 164 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 165 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 166 #else 167 #define cpu_info boot_cpu_data 168 #define cpu_data(cpu) boot_cpu_data 169 #endif 170 171 extern const struct seq_operations cpuinfo_op; 172 173 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 174 175 extern void cpu_detect(struct cpuinfo_x86 *c); 176 177 static inline unsigned long long l1tf_pfn_limit(void) 178 { 179 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 180 } 181 182 extern void early_cpu_init(void); 183 extern void identify_boot_cpu(void); 184 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 185 extern void print_cpu_info(struct cpuinfo_x86 *); 186 void print_cpu_msr(struct cpuinfo_x86 *); 187 188 #ifdef CONFIG_X86_32 189 extern int have_cpuid_p(void); 190 #else 191 static inline int have_cpuid_p(void) 192 { 193 return 1; 194 } 195 #endif 196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 197 unsigned int *ecx, unsigned int *edx) 198 { 199 /* ecx is often an input as well as an output. */ 200 asm volatile("cpuid" 201 : "=a" (*eax), 202 "=b" (*ebx), 203 "=c" (*ecx), 204 "=d" (*edx) 205 : "0" (*eax), "2" (*ecx) 206 : "memory"); 207 } 208 209 #define native_cpuid_reg(reg) \ 210 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 211 { \ 212 unsigned int eax = op, ebx, ecx = 0, edx; \ 213 \ 214 native_cpuid(&eax, &ebx, &ecx, &edx); \ 215 \ 216 return reg; \ 217 } 218 219 /* 220 * Native CPUID functions returning a single datum. 221 */ 222 native_cpuid_reg(eax) 223 native_cpuid_reg(ebx) 224 native_cpuid_reg(ecx) 225 native_cpuid_reg(edx) 226 227 /* 228 * Friendlier CR3 helpers. 229 */ 230 static inline unsigned long read_cr3_pa(void) 231 { 232 return __read_cr3() & CR3_ADDR_MASK; 233 } 234 235 static inline unsigned long native_read_cr3_pa(void) 236 { 237 return __native_read_cr3() & CR3_ADDR_MASK; 238 } 239 240 static inline void load_cr3(pgd_t *pgdir) 241 { 242 write_cr3(__sme_pa(pgdir)); 243 } 244 245 /* 246 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 247 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 248 * unrelated to the task-switch mechanism: 249 */ 250 #ifdef CONFIG_X86_32 251 /* This is the TSS defined by the hardware. */ 252 struct x86_hw_tss { 253 unsigned short back_link, __blh; 254 unsigned long sp0; 255 unsigned short ss0, __ss0h; 256 unsigned long sp1; 257 258 /* 259 * We don't use ring 1, so ss1 is a convenient scratch space in 260 * the same cacheline as sp0. We use ss1 to cache the value in 261 * MSR_IA32_SYSENTER_CS. When we context switch 262 * MSR_IA32_SYSENTER_CS, we first check if the new value being 263 * written matches ss1, and, if it's not, then we wrmsr the new 264 * value and update ss1. 265 * 266 * The only reason we context switch MSR_IA32_SYSENTER_CS is 267 * that we set it to zero in vm86 tasks to avoid corrupting the 268 * stack if we were to go through the sysenter path from vm86 269 * mode. 270 */ 271 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 272 273 unsigned short __ss1h; 274 unsigned long sp2; 275 unsigned short ss2, __ss2h; 276 unsigned long __cr3; 277 unsigned long ip; 278 unsigned long flags; 279 unsigned long ax; 280 unsigned long cx; 281 unsigned long dx; 282 unsigned long bx; 283 unsigned long sp; 284 unsigned long bp; 285 unsigned long si; 286 unsigned long di; 287 unsigned short es, __esh; 288 unsigned short cs, __csh; 289 unsigned short ss, __ssh; 290 unsigned short ds, __dsh; 291 unsigned short fs, __fsh; 292 unsigned short gs, __gsh; 293 unsigned short ldt, __ldth; 294 unsigned short trace; 295 unsigned short io_bitmap_base; 296 297 } __attribute__((packed)); 298 #else 299 struct x86_hw_tss { 300 u32 reserved1; 301 u64 sp0; 302 303 /* 304 * We store cpu_current_top_of_stack in sp1 so it's always accessible. 305 * Linux does not use ring 1, so sp1 is not otherwise needed. 306 */ 307 u64 sp1; 308 309 /* 310 * Since Linux does not use ring 2, the 'sp2' slot is unused by 311 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 312 * the user RSP value. 313 */ 314 u64 sp2; 315 316 u64 reserved2; 317 u64 ist[7]; 318 u32 reserved3; 319 u32 reserved4; 320 u16 reserved5; 321 u16 io_bitmap_base; 322 323 } __attribute__((packed)); 324 #endif 325 326 /* 327 * IO-bitmap sizes: 328 */ 329 #define IO_BITMAP_BITS 65536 330 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 331 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 332 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) 333 #define INVALID_IO_BITMAP_OFFSET 0x8000 334 335 struct entry_stack { 336 unsigned long words[64]; 337 }; 338 339 struct entry_stack_page { 340 struct entry_stack stack; 341 } __aligned(PAGE_SIZE); 342 343 struct tss_struct { 344 /* 345 * The fixed hardware portion. This must not cross a page boundary 346 * at risk of violating the SDM's advice and potentially triggering 347 * errata. 348 */ 349 struct x86_hw_tss x86_tss; 350 351 /* 352 * The extra 1 is there because the CPU will access an 353 * additional byte beyond the end of the IO permission 354 * bitmap. The extra byte must be all 1 bits, and must 355 * be within the limit. 356 */ 357 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 358 } __aligned(PAGE_SIZE); 359 360 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 361 362 /* 363 * sizeof(unsigned long) coming from an extra "long" at the end 364 * of the iobitmap. 365 * 366 * -1? seg base+limit should be pointing to the address of the 367 * last valid byte 368 */ 369 #define __KERNEL_TSS_LIMIT \ 370 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 371 372 /* Per CPU interrupt stacks */ 373 struct irq_stack { 374 char stack[IRQ_STACK_SIZE]; 375 } __aligned(IRQ_STACK_SIZE); 376 377 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 378 379 #ifdef CONFIG_X86_32 380 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 381 #else 382 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ 383 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 384 #endif 385 386 #ifdef CONFIG_X86_64 387 struct fixed_percpu_data { 388 /* 389 * GCC hardcodes the stack canary as %gs:40. Since the 390 * irq_stack is the object at %gs:0, we reserve the bottom 391 * 48 bytes of the irq stack for the canary. 392 */ 393 char gs_base[40]; 394 unsigned long stack_canary; 395 }; 396 397 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 398 DECLARE_INIT_PER_CPU(fixed_percpu_data); 399 400 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 401 { 402 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 403 } 404 405 DECLARE_PER_CPU(unsigned int, irq_count); 406 extern asmlinkage void ignore_sysret(void); 407 408 #if IS_ENABLED(CONFIG_KVM) 409 /* Save actual FS/GS selectors and bases to current->thread */ 410 void save_fsgs_for_kvm(void); 411 #endif 412 #else /* X86_64 */ 413 #ifdef CONFIG_STACKPROTECTOR 414 /* 415 * Make sure stack canary segment base is cached-aligned: 416 * "For Intel Atom processors, avoid non zero segment base address 417 * that is not aligned to cache line boundary at all cost." 418 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 419 */ 420 struct stack_canary { 421 char __pad[20]; /* canary at %gs:20 */ 422 unsigned long canary; 423 }; 424 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 425 #endif 426 /* Per CPU softirq stack pointer */ 427 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr); 428 #endif /* X86_64 */ 429 430 extern unsigned int fpu_kernel_xstate_size; 431 extern unsigned int fpu_user_xstate_size; 432 433 struct perf_event; 434 435 typedef struct { 436 unsigned long seg; 437 } mm_segment_t; 438 439 struct thread_struct { 440 /* Cached TLS descriptors: */ 441 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 442 #ifdef CONFIG_X86_32 443 unsigned long sp0; 444 #endif 445 unsigned long sp; 446 #ifdef CONFIG_X86_32 447 unsigned long sysenter_cs; 448 #else 449 unsigned short es; 450 unsigned short ds; 451 unsigned short fsindex; 452 unsigned short gsindex; 453 #endif 454 455 #ifdef CONFIG_X86_64 456 unsigned long fsbase; 457 unsigned long gsbase; 458 #else 459 /* 460 * XXX: this could presumably be unsigned short. Alternatively, 461 * 32-bit kernels could be taught to use fsindex instead. 462 */ 463 unsigned long fs; 464 unsigned long gs; 465 #endif 466 467 /* Save middle states of ptrace breakpoints */ 468 struct perf_event *ptrace_bps[HBP_NUM]; 469 /* Debug status used for traps, single steps, etc... */ 470 unsigned long debugreg6; 471 /* Keep track of the exact dr7 value set by the user */ 472 unsigned long ptrace_dr7; 473 /* Fault info: */ 474 unsigned long cr2; 475 unsigned long trap_nr; 476 unsigned long error_code; 477 #ifdef CONFIG_VM86 478 /* Virtual 86 mode info */ 479 struct vm86 *vm86; 480 #endif 481 /* IO permissions: */ 482 unsigned long *io_bitmap_ptr; 483 unsigned long iopl; 484 /* Max allowed port in the bitmap, in bytes: */ 485 unsigned io_bitmap_max; 486 487 mm_segment_t addr_limit; 488 489 unsigned int sig_on_uaccess_err:1; 490 unsigned int uaccess_err:1; /* uaccess failed */ 491 492 /* Floating point and extended processor state */ 493 struct fpu fpu; 494 /* 495 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 496 * the end. 497 */ 498 }; 499 500 /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 501 static inline void arch_thread_struct_whitelist(unsigned long *offset, 502 unsigned long *size) 503 { 504 *offset = offsetof(struct thread_struct, fpu.state); 505 *size = fpu_kernel_xstate_size; 506 } 507 508 /* 509 * Thread-synchronous status. 510 * 511 * This is different from the flags in that nobody else 512 * ever touches our thread-synchronous status, so we don't 513 * have to worry about atomic accesses. 514 */ 515 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 516 517 /* 518 * Set IOPL bits in EFLAGS from given mask 519 */ 520 static inline void native_set_iopl_mask(unsigned mask) 521 { 522 #ifdef CONFIG_X86_32 523 unsigned int reg; 524 525 asm volatile ("pushfl;" 526 "popl %0;" 527 "andl %1, %0;" 528 "orl %2, %0;" 529 "pushl %0;" 530 "popfl" 531 : "=&r" (reg) 532 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 533 #endif 534 } 535 536 static inline void 537 native_load_sp0(unsigned long sp0) 538 { 539 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 540 } 541 542 static inline void native_swapgs(void) 543 { 544 #ifdef CONFIG_X86_64 545 asm volatile("swapgs" ::: "memory"); 546 #endif 547 } 548 549 static inline unsigned long current_top_of_stack(void) 550 { 551 /* 552 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 553 * and around vm86 mode and sp0 on x86_64 is special because of the 554 * entry trampoline. 555 */ 556 return this_cpu_read_stable(cpu_current_top_of_stack); 557 } 558 559 static inline bool on_thread_stack(void) 560 { 561 return (unsigned long)(current_top_of_stack() - 562 current_stack_pointer) < THREAD_SIZE; 563 } 564 565 #ifdef CONFIG_PARAVIRT_XXL 566 #include <asm/paravirt.h> 567 #else 568 #define __cpuid native_cpuid 569 570 static inline void load_sp0(unsigned long sp0) 571 { 572 native_load_sp0(sp0); 573 } 574 575 #define set_iopl_mask native_set_iopl_mask 576 #endif /* CONFIG_PARAVIRT_XXL */ 577 578 /* Free all resources held by a thread. */ 579 extern void release_thread(struct task_struct *); 580 581 unsigned long get_wchan(struct task_struct *p); 582 583 /* 584 * Generic CPUID function 585 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 586 * resulting in stale register contents being returned. 587 */ 588 static inline void cpuid(unsigned int op, 589 unsigned int *eax, unsigned int *ebx, 590 unsigned int *ecx, unsigned int *edx) 591 { 592 *eax = op; 593 *ecx = 0; 594 __cpuid(eax, ebx, ecx, edx); 595 } 596 597 /* Some CPUID calls want 'count' to be placed in ecx */ 598 static inline void cpuid_count(unsigned int op, int count, 599 unsigned int *eax, unsigned int *ebx, 600 unsigned int *ecx, unsigned int *edx) 601 { 602 *eax = op; 603 *ecx = count; 604 __cpuid(eax, ebx, ecx, edx); 605 } 606 607 /* 608 * CPUID functions returning a single datum 609 */ 610 static inline unsigned int cpuid_eax(unsigned int op) 611 { 612 unsigned int eax, ebx, ecx, edx; 613 614 cpuid(op, &eax, &ebx, &ecx, &edx); 615 616 return eax; 617 } 618 619 static inline unsigned int cpuid_ebx(unsigned int op) 620 { 621 unsigned int eax, ebx, ecx, edx; 622 623 cpuid(op, &eax, &ebx, &ecx, &edx); 624 625 return ebx; 626 } 627 628 static inline unsigned int cpuid_ecx(unsigned int op) 629 { 630 unsigned int eax, ebx, ecx, edx; 631 632 cpuid(op, &eax, &ebx, &ecx, &edx); 633 634 return ecx; 635 } 636 637 static inline unsigned int cpuid_edx(unsigned int op) 638 { 639 unsigned int eax, ebx, ecx, edx; 640 641 cpuid(op, &eax, &ebx, &ecx, &edx); 642 643 return edx; 644 } 645 646 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 647 static __always_inline void rep_nop(void) 648 { 649 asm volatile("rep; nop" ::: "memory"); 650 } 651 652 static __always_inline void cpu_relax(void) 653 { 654 rep_nop(); 655 } 656 657 /* 658 * This function forces the icache and prefetched instruction stream to 659 * catch up with reality in two very specific cases: 660 * 661 * a) Text was modified using one virtual address and is about to be executed 662 * from the same physical page at a different virtual address. 663 * 664 * b) Text was modified on a different CPU, may subsequently be 665 * executed on this CPU, and you want to make sure the new version 666 * gets executed. This generally means you're calling this in a IPI. 667 * 668 * If you're calling this for a different reason, you're probably doing 669 * it wrong. 670 */ 671 static inline void sync_core(void) 672 { 673 /* 674 * There are quite a few ways to do this. IRET-to-self is nice 675 * because it works on every CPU, at any CPL (so it's compatible 676 * with paravirtualization), and it never exits to a hypervisor. 677 * The only down sides are that it's a bit slow (it seems to be 678 * a bit more than 2x slower than the fastest options) and that 679 * it unmasks NMIs. The "push %cs" is needed because, in 680 * paravirtual environments, __KERNEL_CS may not be a valid CS 681 * value when we do IRET directly. 682 * 683 * In case NMI unmasking or performance ever becomes a problem, 684 * the next best option appears to be MOV-to-CR2 and an 685 * unconditional jump. That sequence also works on all CPUs, 686 * but it will fault at CPL3 (i.e. Xen PV). 687 * 688 * CPUID is the conventional way, but it's nasty: it doesn't 689 * exist on some 486-like CPUs, and it usually exits to a 690 * hypervisor. 691 * 692 * Like all of Linux's memory ordering operations, this is a 693 * compiler barrier as well. 694 */ 695 #ifdef CONFIG_X86_32 696 asm volatile ( 697 "pushfl\n\t" 698 "pushl %%cs\n\t" 699 "pushl $1f\n\t" 700 "iret\n\t" 701 "1:" 702 : ASM_CALL_CONSTRAINT : : "memory"); 703 #else 704 unsigned int tmp; 705 706 asm volatile ( 707 UNWIND_HINT_SAVE 708 "mov %%ss, %0\n\t" 709 "pushq %q0\n\t" 710 "pushq %%rsp\n\t" 711 "addq $8, (%%rsp)\n\t" 712 "pushfq\n\t" 713 "mov %%cs, %0\n\t" 714 "pushq %q0\n\t" 715 "pushq $1f\n\t" 716 "iretq\n\t" 717 UNWIND_HINT_RESTORE 718 "1:" 719 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); 720 #endif 721 } 722 723 extern void select_idle_routine(const struct cpuinfo_x86 *c); 724 extern void amd_e400_c1e_apic_setup(void); 725 726 extern unsigned long boot_option_idle_override; 727 728 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 729 IDLE_POLL}; 730 731 extern void enable_sep_cpu(void); 732 extern int sysenter_setup(void); 733 734 735 /* Defined in head.S */ 736 extern struct desc_ptr early_gdt_descr; 737 738 extern void switch_to_new_gdt(int); 739 extern void load_direct_gdt(int); 740 extern void load_fixmap_gdt(int); 741 extern void load_percpu_segment(int); 742 extern void cpu_init(void); 743 744 static inline unsigned long get_debugctlmsr(void) 745 { 746 unsigned long debugctlmsr = 0; 747 748 #ifndef CONFIG_X86_DEBUGCTLMSR 749 if (boot_cpu_data.x86 < 6) 750 return 0; 751 #endif 752 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 753 754 return debugctlmsr; 755 } 756 757 static inline void update_debugctlmsr(unsigned long debugctlmsr) 758 { 759 #ifndef CONFIG_X86_DEBUGCTLMSR 760 if (boot_cpu_data.x86 < 6) 761 return; 762 #endif 763 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 764 } 765 766 extern void set_task_blockstep(struct task_struct *task, bool on); 767 768 /* Boot loader type from the setup header: */ 769 extern int bootloader_type; 770 extern int bootloader_version; 771 772 extern char ignore_fpu_irq; 773 774 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 775 #define ARCH_HAS_PREFETCHW 776 #define ARCH_HAS_SPINLOCK_PREFETCH 777 778 #ifdef CONFIG_X86_32 779 # define BASE_PREFETCH "" 780 # define ARCH_HAS_PREFETCH 781 #else 782 # define BASE_PREFETCH "prefetcht0 %P1" 783 #endif 784 785 /* 786 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 787 * 788 * It's not worth to care about 3dnow prefetches for the K6 789 * because they are microcoded there and very slow. 790 */ 791 static inline void prefetch(const void *x) 792 { 793 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 794 X86_FEATURE_XMM, 795 "m" (*(const char *)x)); 796 } 797 798 /* 799 * 3dnow prefetch to get an exclusive cache line. 800 * Useful for spinlocks to avoid one state transition in the 801 * cache coherency protocol: 802 */ 803 static inline void prefetchw(const void *x) 804 { 805 alternative_input(BASE_PREFETCH, "prefetchw %P1", 806 X86_FEATURE_3DNOWPREFETCH, 807 "m" (*(const char *)x)); 808 } 809 810 static inline void spin_lock_prefetch(const void *x) 811 { 812 prefetchw(x); 813 } 814 815 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 816 TOP_OF_KERNEL_STACK_PADDING) 817 818 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 819 820 #define task_pt_regs(task) \ 821 ({ \ 822 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 823 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 824 ((struct pt_regs *)__ptr) - 1; \ 825 }) 826 827 #ifdef CONFIG_X86_32 828 /* 829 * User space process size: 3GB (default). 830 */ 831 #define IA32_PAGE_OFFSET PAGE_OFFSET 832 #define TASK_SIZE PAGE_OFFSET 833 #define TASK_SIZE_LOW TASK_SIZE 834 #define TASK_SIZE_MAX TASK_SIZE 835 #define DEFAULT_MAP_WINDOW TASK_SIZE 836 #define STACK_TOP TASK_SIZE 837 #define STACK_TOP_MAX STACK_TOP 838 839 #define INIT_THREAD { \ 840 .sp0 = TOP_OF_INIT_STACK, \ 841 .sysenter_cs = __KERNEL_CS, \ 842 .io_bitmap_ptr = NULL, \ 843 .addr_limit = KERNEL_DS, \ 844 } 845 846 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 847 848 #else 849 /* 850 * User space process size. This is the first address outside the user range. 851 * There are a few constraints that determine this: 852 * 853 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical 854 * address, then that syscall will enter the kernel with a 855 * non-canonical return address, and SYSRET will explode dangerously. 856 * We avoid this particular problem by preventing anything executable 857 * from being mapped at the maximum canonical address. 858 * 859 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the 860 * CPUs malfunction if they execute code from the highest canonical page. 861 * They'll speculate right off the end of the canonical space, and 862 * bad things happen. This is worked around in the same way as the 863 * Intel problem. 864 * 865 * With page table isolation enabled, we map the LDT in ... [stay tuned] 866 */ 867 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE) 868 869 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE) 870 871 /* This decides where the kernel will search for a free chunk of vm 872 * space during mmap's. 873 */ 874 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 875 0xc0000000 : 0xFFFFe000) 876 877 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \ 878 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW) 879 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 880 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 881 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 882 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 883 884 #define STACK_TOP TASK_SIZE_LOW 885 #define STACK_TOP_MAX TASK_SIZE_MAX 886 887 #define INIT_THREAD { \ 888 .addr_limit = KERNEL_DS, \ 889 } 890 891 extern unsigned long KSTK_ESP(struct task_struct *task); 892 893 #endif /* CONFIG_X86_64 */ 894 895 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 896 unsigned long new_sp); 897 898 /* 899 * This decides where the kernel will search for a free chunk of vm 900 * space during mmap's. 901 */ 902 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 903 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 904 905 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 906 907 /* Get/set a process' ability to use the timestamp counter instruction */ 908 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 909 #define SET_TSC_CTL(val) set_tsc_mode((val)) 910 911 extern int get_tsc_mode(unsigned long adr); 912 extern int set_tsc_mode(unsigned int val); 913 914 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 915 916 /* Register/unregister a process' MPX related resource */ 917 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 918 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 919 920 #ifdef CONFIG_X86_INTEL_MPX 921 extern int mpx_enable_management(void); 922 extern int mpx_disable_management(void); 923 #else 924 static inline int mpx_enable_management(void) 925 { 926 return -EINVAL; 927 } 928 static inline int mpx_disable_management(void) 929 { 930 return -EINVAL; 931 } 932 #endif /* CONFIG_X86_INTEL_MPX */ 933 934 #ifdef CONFIG_CPU_SUP_AMD 935 extern u16 amd_get_nb_id(int cpu); 936 extern u32 amd_get_nodes_per_socket(void); 937 #else 938 static inline u16 amd_get_nb_id(int cpu) { return 0; } 939 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 940 #endif 941 942 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 943 { 944 uint32_t base, eax, signature[3]; 945 946 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 947 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 948 949 if (!memcmp(sig, signature, 12) && 950 (leaves == 0 || ((eax - base) >= leaves))) 951 return base; 952 } 953 954 return 0; 955 } 956 957 extern unsigned long arch_align_stack(unsigned long sp); 958 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 959 extern void free_kernel_image_pages(void *begin, void *end); 960 961 void default_idle(void); 962 #ifdef CONFIG_XEN 963 bool xen_set_default_idle(void); 964 #else 965 #define xen_set_default_idle 0 966 #endif 967 968 void stop_this_cpu(void *dummy); 969 void df_debug(struct pt_regs *regs, long error_code); 970 void microcode_check(void); 971 972 enum l1tf_mitigations { 973 L1TF_MITIGATION_OFF, 974 L1TF_MITIGATION_FLUSH_NOWARN, 975 L1TF_MITIGATION_FLUSH, 976 L1TF_MITIGATION_FLUSH_NOSMT, 977 L1TF_MITIGATION_FULL, 978 L1TF_MITIGATION_FULL_FORCE 979 }; 980 981 extern enum l1tf_mitigations l1tf_mitigation; 982 983 enum mds_mitigations { 984 MDS_MITIGATION_OFF, 985 MDS_MITIGATION_FULL, 986 MDS_MITIGATION_VMWERV, 987 }; 988 989 #endif /* _ASM_X86_PROCESSOR_H */ 990