1 /* 2 * timer.h: Definitions for the timer chips on the Sparc. 3 * 4 * Copyright (C) 1995 David S. Miller ([email protected]) 5 */ 6 7 8 #ifndef _SPARC_TIMER_H 9 #define _SPARC_TIMER_H 10 11 #include <asm/system.h> /* For SUN4M_NCPUS */ 12 #include <asm/btfixup.h> 13 14 /* Timer structures. The interrupt timer has two properties which 15 * are the counter (which is handled in do_timer in sched.c) and the limit. 16 * This limit is where the timer's counter 'wraps' around. Oddly enough, 17 * the sun4c timer when it hits the limit wraps back to 1 and not zero 18 * thus when calculating the value at which it will fire a microsecond you 19 * must adjust by one. Thanks SUN for designing such great hardware ;( 20 */ 21 22 /* Note that I am only going to use the timer that interrupts at 23 * Sparc IRQ 10. There is another one available that can fire at 24 * IRQ 14. Currently it is left untouched, we keep the PROM's limit 25 * register value and let the prom take these interrupts. This allows 26 * L1-A to work. 27 */ 28 29 struct sun4c_timer_info { 30 __volatile__ unsigned int cur_count10; 31 __volatile__ unsigned int timer_limit10; 32 __volatile__ unsigned int cur_count14; 33 __volatile__ unsigned int timer_limit14; 34 }; 35 36 #define SUN_TIMER_PHYSADDR 0xf3000000 37 38 /* A sun4m has two blocks of registers which are probably of the same 39 * structure. LSI Logic's L64851 is told to _decrement_ from the limit 40 * value. Aurora behaves similarly but its limit value is compacted in 41 * other fashion (it's wider). Documented fields are defined here. 42 */ 43 44 /* As with the interrupt register, we have two classes of timer registers 45 * which are per-cpu and master. Per-cpu timers only hit that cpu and are 46 * only level 14 ticks, master timer hits all cpus and is level 10. 47 */ 48 49 #define SUN4M_PRM_CNT_L 0x80000000 50 #define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00 51 52 struct sun4m_timer_percpu_info { 53 __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */ 54 __volatile__ unsigned int l14_cur_count; 55 56 /* This register appears to be write only and/or inaccessible 57 * on Uni-Processor sun4m machines. 58 */ 59 __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */ 60 61 __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */ 62 __volatile__ unsigned char space[PAGE_SIZE - 16]; 63 }; 64 65 struct sun4m_timer_regs { 66 struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS]; 67 volatile unsigned int l10_timer_limit; 68 volatile unsigned int l10_cur_count; 69 70 /* Again, this appears to be write only and/or inaccessible 71 * on uni-processor sun4m machines. 72 */ 73 volatile unsigned int l10_limit_noclear; 74 75 /* This register too, it must be magic. */ 76 volatile unsigned int foobar; 77 78 volatile unsigned int cfg; /* equals zero at boot time... */ 79 }; 80 81 #define SUN4D_PRM_CNT_L 0x80000000 82 #define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00 83 84 struct sun4d_timer_regs { 85 volatile unsigned int l10_timer_limit; 86 volatile unsigned int l10_cur_countx; 87 volatile unsigned int l10_limit_noclear; 88 volatile unsigned int ctrl; 89 volatile unsigned int l10_cur_count; 90 }; 91 92 extern struct sun4d_timer_regs *sun4d_timers; 93 94 extern __volatile__ unsigned int *master_l10_counter; 95 extern __volatile__ unsigned int *master_l10_limit; 96 97 /* FIXME: Make do_[gs]ettimeofday btfixup calls */ 98 BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv) 99 #define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv) 100 101 #endif /* !(_SPARC_TIMER_H) */ 102