1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #define KERN_VIRT_SIZE (UL(-1)) 17 #else 18 19 #define ADDRESS_SPACE_END (UL(-1)) 20 21 #ifdef CONFIG_64BIT 22 /* Leave 2GB for kernel and BPF at the end of the address space */ 23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 24 #else 25 #define KERNEL_LINK_ADDR PAGE_OFFSET 26 #endif 27 28 /* Number of entries in the page global directory */ 29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 30 /* Number of entries in the page table */ 31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 32 33 /* 34 * Half of the kernel address space (1/4 of the entries of the page global 35 * directory) is for the direct mapping. 36 */ 37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 38 39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 40 #define VMALLOC_END PAGE_OFFSET 41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 42 43 #define BPF_JIT_REGION_SIZE (SZ_128M) 44 #ifdef CONFIG_64BIT 45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 46 #define BPF_JIT_REGION_END (MODULES_END) 47 #else 48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 49 #define BPF_JIT_REGION_END (VMALLOC_END) 50 #endif 51 52 /* Modules always live before the kernel */ 53 #ifdef CONFIG_64BIT 54 /* This is used to define the end of the KASAN shadow region */ 55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 58 #else 59 #define MODULES_VADDR VMALLOC_START 60 #define MODULES_END VMALLOC_END 61 #endif 62 63 /* 64 * Roughly size the vmemmap space to be large enough to fit enough 65 * struct pages to map half the virtual address space. Then 66 * position vmemmap directly below the VMALLOC region. 67 */ 68 #define VA_BITS_SV32 32 69 #ifdef CONFIG_64BIT 70 #define VA_BITS_SV39 39 71 #define VA_BITS_SV48 48 72 #define VA_BITS_SV57 57 73 74 #define VA_BITS (pgtable_l5_enabled ? \ 75 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 76 #else 77 #define VA_BITS VA_BITS_SV32 78 #endif 79 80 #define VMEMMAP_SHIFT \ 81 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 82 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 83 #define VMEMMAP_END VMALLOC_START 84 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 85 86 /* 87 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 88 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 89 */ 90 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) 91 92 #define PCI_IO_SIZE SZ_16M 93 #define PCI_IO_END VMEMMAP_START 94 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 95 96 #define FIXADDR_TOP PCI_IO_START 97 #ifdef CONFIG_64BIT 98 #define MAX_FDT_SIZE PMD_SIZE 99 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 100 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 101 #else 102 #define MAX_FDT_SIZE PGDIR_SIZE 103 #define FIX_FDT_SIZE MAX_FDT_SIZE 104 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 105 #endif 106 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 107 108 #endif 109 110 #ifndef __ASSEMBLY__ 111 112 #include <asm/page.h> 113 #include <asm/tlbflush.h> 114 #include <linux/mm_types.h> 115 #include <asm/compat.h> 116 #include <asm/cpufeature.h> 117 118 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 119 120 #ifdef CONFIG_64BIT 121 #include <asm/pgtable-64.h> 122 123 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) 124 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) 125 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) 126 127 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 128 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 129 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 130 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 131 #else 132 #include <asm/pgtable-32.h> 133 #endif /* CONFIG_64BIT */ 134 135 #include <linux/page_table_check.h> 136 137 #ifdef CONFIG_XIP_KERNEL 138 #define XIP_FIXUP(addr) ({ \ 139 extern char _sdata[], _start[], _end[]; \ 140 uintptr_t __rom_start_data = CONFIG_XIP_PHYS_ADDR \ 141 + (uintptr_t)&_sdata - (uintptr_t)&_start; \ 142 uintptr_t __rom_end_data = CONFIG_XIP_PHYS_ADDR \ 143 + (uintptr_t)&_end - (uintptr_t)&_start; \ 144 uintptr_t __a = (uintptr_t)(addr); \ 145 (__a >= __rom_start_data && __a < __rom_end_data) ? \ 146 __a - __rom_start_data + CONFIG_PHYS_RAM_BASE : __a; \ 147 }) 148 #else 149 #define XIP_FIXUP(addr) (addr) 150 #endif /* CONFIG_XIP_KERNEL */ 151 152 struct pt_alloc_ops { 153 pte_t *(*get_pte_virt)(phys_addr_t pa); 154 phys_addr_t (*alloc_pte)(uintptr_t va); 155 #ifndef __PAGETABLE_PMD_FOLDED 156 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 157 phys_addr_t (*alloc_pmd)(uintptr_t va); 158 pud_t *(*get_pud_virt)(phys_addr_t pa); 159 phys_addr_t (*alloc_pud)(uintptr_t va); 160 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 161 phys_addr_t (*alloc_p4d)(uintptr_t va); 162 #endif 163 }; 164 165 extern struct pt_alloc_ops pt_ops __meminitdata; 166 167 #ifdef CONFIG_MMU 168 /* Number of PGD entries that a user-mode program can use */ 169 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 170 171 /* Page protection bits */ 172 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 173 174 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 175 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 176 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 177 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 178 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 179 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 180 _PAGE_EXEC | _PAGE_WRITE) 181 182 #define PAGE_COPY PAGE_READ 183 #define PAGE_COPY_EXEC PAGE_READ_EXEC 184 #define PAGE_SHARED PAGE_WRITE 185 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 186 187 #define _PAGE_KERNEL (_PAGE_READ \ 188 | _PAGE_WRITE \ 189 | _PAGE_PRESENT \ 190 | _PAGE_ACCESSED \ 191 | _PAGE_DIRTY \ 192 | _PAGE_GLOBAL) 193 194 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 195 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 196 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 197 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 198 | _PAGE_EXEC) 199 200 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 201 202 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 203 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 204 205 extern pgd_t swapper_pg_dir[]; 206 extern pgd_t trampoline_pg_dir[]; 207 extern pgd_t early_pg_dir[]; 208 209 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 210 static inline int pmd_present(pmd_t pmd) 211 { 212 /* 213 * Checking for _PAGE_LEAF is needed too because: 214 * When splitting a THP, split_huge_page() will temporarily clear 215 * the present bit, in this situation, pmd_present() and 216 * pmd_trans_huge() still needs to return true. 217 */ 218 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 219 } 220 #else 221 static inline int pmd_present(pmd_t pmd) 222 { 223 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 224 } 225 #endif 226 227 static inline int pmd_none(pmd_t pmd) 228 { 229 return (pmd_val(pmd) == 0); 230 } 231 232 static inline int pmd_bad(pmd_t pmd) 233 { 234 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 235 } 236 237 #define pmd_leaf pmd_leaf 238 static inline bool pmd_leaf(pmd_t pmd) 239 { 240 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 241 } 242 243 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 244 { 245 WRITE_ONCE(*pmdp, pmd); 246 } 247 248 static inline void pmd_clear(pmd_t *pmdp) 249 { 250 set_pmd(pmdp, __pmd(0)); 251 } 252 253 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 254 { 255 unsigned long prot_val = pgprot_val(prot); 256 257 ALT_THEAD_PMA(prot_val); 258 259 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 260 } 261 262 static inline unsigned long _pgd_pfn(pgd_t pgd) 263 { 264 return __page_val_to_pfn(pgd_val(pgd)); 265 } 266 267 static inline struct page *pmd_page(pmd_t pmd) 268 { 269 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 270 } 271 272 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 273 { 274 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 275 } 276 277 static inline pte_t pmd_pte(pmd_t pmd) 278 { 279 return __pte(pmd_val(pmd)); 280 } 281 282 static inline pte_t pud_pte(pud_t pud) 283 { 284 return __pte(pud_val(pud)); 285 } 286 287 #ifdef CONFIG_RISCV_ISA_SVNAPOT 288 289 static __always_inline bool has_svnapot(void) 290 { 291 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 292 } 293 294 static inline unsigned long pte_napot(pte_t pte) 295 { 296 return pte_val(pte) & _PAGE_NAPOT; 297 } 298 299 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 300 { 301 int pos = order - 1 + _PAGE_PFN_SHIFT; 302 unsigned long napot_bit = BIT(pos); 303 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 304 305 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 306 } 307 308 #else 309 310 static __always_inline bool has_svnapot(void) { return false; } 311 312 static inline unsigned long pte_napot(pte_t pte) 313 { 314 return 0; 315 } 316 317 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 318 319 /* Yields the page frame number (PFN) of a page table entry */ 320 static inline unsigned long pte_pfn(pte_t pte) 321 { 322 unsigned long res = __page_val_to_pfn(pte_val(pte)); 323 324 if (has_svnapot() && pte_napot(pte)) 325 res = res & (res - 1UL); 326 327 return res; 328 } 329 330 #define pte_page(x) pfn_to_page(pte_pfn(x)) 331 332 /* Constructs a page table entry */ 333 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 334 { 335 unsigned long prot_val = pgprot_val(prot); 336 337 ALT_THEAD_PMA(prot_val); 338 339 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 340 } 341 342 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 343 344 #define pte_pgprot pte_pgprot 345 static inline pgprot_t pte_pgprot(pte_t pte) 346 { 347 unsigned long pfn = pte_pfn(pte); 348 349 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 350 } 351 352 static inline int pte_present(pte_t pte) 353 { 354 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 355 } 356 357 #define pte_accessible pte_accessible 358 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 359 { 360 if (pte_val(a) & _PAGE_PRESENT) 361 return true; 362 363 if ((pte_val(a) & _PAGE_PROT_NONE) && 364 atomic_read(&mm->tlb_flush_pending)) 365 return true; 366 367 return false; 368 } 369 370 static inline int pte_none(pte_t pte) 371 { 372 return (pte_val(pte) == 0); 373 } 374 375 static inline int pte_write(pte_t pte) 376 { 377 return pte_val(pte) & _PAGE_WRITE; 378 } 379 380 static inline int pte_exec(pte_t pte) 381 { 382 return pte_val(pte) & _PAGE_EXEC; 383 } 384 385 static inline int pte_user(pte_t pte) 386 { 387 return pte_val(pte) & _PAGE_USER; 388 } 389 390 static inline int pte_huge(pte_t pte) 391 { 392 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 393 } 394 395 static inline int pte_dirty(pte_t pte) 396 { 397 return pte_val(pte) & _PAGE_DIRTY; 398 } 399 400 static inline int pte_young(pte_t pte) 401 { 402 return pte_val(pte) & _PAGE_ACCESSED; 403 } 404 405 static inline int pte_special(pte_t pte) 406 { 407 return pte_val(pte) & _PAGE_SPECIAL; 408 } 409 410 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 411 static inline int pte_devmap(pte_t pte) 412 { 413 return pte_val(pte) & _PAGE_DEVMAP; 414 } 415 #endif 416 417 /* static inline pte_t pte_rdprotect(pte_t pte) */ 418 419 static inline pte_t pte_wrprotect(pte_t pte) 420 { 421 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 422 } 423 424 /* static inline pte_t pte_mkread(pte_t pte) */ 425 426 static inline pte_t pte_mkwrite_novma(pte_t pte) 427 { 428 return __pte(pte_val(pte) | _PAGE_WRITE); 429 } 430 431 /* static inline pte_t pte_mkexec(pte_t pte) */ 432 433 static inline pte_t pte_mkdirty(pte_t pte) 434 { 435 return __pte(pte_val(pte) | _PAGE_DIRTY); 436 } 437 438 static inline pte_t pte_mkclean(pte_t pte) 439 { 440 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 441 } 442 443 static inline pte_t pte_mkyoung(pte_t pte) 444 { 445 return __pte(pte_val(pte) | _PAGE_ACCESSED); 446 } 447 448 static inline pte_t pte_mkold(pte_t pte) 449 { 450 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 451 } 452 453 static inline pte_t pte_mkspecial(pte_t pte) 454 { 455 return __pte(pte_val(pte) | _PAGE_SPECIAL); 456 } 457 458 static inline pte_t pte_mkdevmap(pte_t pte) 459 { 460 return __pte(pte_val(pte) | _PAGE_DEVMAP); 461 } 462 463 static inline pte_t pte_mkhuge(pte_t pte) 464 { 465 return pte; 466 } 467 468 #ifdef CONFIG_RISCV_ISA_SVNAPOT 469 #define pte_leaf_size(pte) (pte_napot(pte) ? \ 470 napot_cont_size(napot_cont_order(pte)) :\ 471 PAGE_SIZE) 472 #endif 473 474 #ifdef CONFIG_NUMA_BALANCING 475 /* 476 * See the comment in include/asm-generic/pgtable.h 477 */ 478 static inline int pte_protnone(pte_t pte) 479 { 480 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 481 } 482 483 static inline int pmd_protnone(pmd_t pmd) 484 { 485 return pte_protnone(pmd_pte(pmd)); 486 } 487 #endif 488 489 /* Modify page protection bits */ 490 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 491 { 492 unsigned long newprot_val = pgprot_val(newprot); 493 494 ALT_THEAD_PMA(newprot_val); 495 496 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 497 } 498 499 #define pgd_ERROR(e) \ 500 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 501 502 503 /* Commit new configuration to MMU hardware */ 504 static inline void update_mmu_cache_range(struct vm_fault *vmf, 505 struct vm_area_struct *vma, unsigned long address, 506 pte_t *ptep, unsigned int nr) 507 { 508 asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) 509 : : : : svvptc); 510 511 /* 512 * The kernel assumes that TLBs don't cache invalid entries, but 513 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 514 * cache flush; it is necessary even after writing invalid entries. 515 * Relying on flush_tlb_fix_spurious_fault would suffice, but 516 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 517 */ 518 while (nr--) 519 local_flush_tlb_page(address + nr * PAGE_SIZE); 520 521 svvptc:; 522 /* 523 * Svvptc guarantees that the new valid pte will be visible within 524 * a bounded timeframe, so when the uarch does not cache invalid 525 * entries, we don't have to do anything. 526 */ 527 } 528 #define update_mmu_cache(vma, addr, ptep) \ 529 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 530 531 #define update_mmu_tlb_range(vma, addr, ptep, nr) \ 532 update_mmu_cache_range(NULL, vma, addr, ptep, nr) 533 534 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 535 unsigned long address, pmd_t *pmdp) 536 { 537 pte_t *ptep = (pte_t *)pmdp; 538 539 update_mmu_cache(vma, address, ptep); 540 } 541 542 #define __HAVE_ARCH_PTE_SAME 543 static inline int pte_same(pte_t pte_a, pte_t pte_b) 544 { 545 return pte_val(pte_a) == pte_val(pte_b); 546 } 547 548 /* 549 * Certain architectures need to do special things when PTEs within 550 * a page table are directly modified. Thus, the following hook is 551 * made available. 552 */ 553 static inline void set_pte(pte_t *ptep, pte_t pteval) 554 { 555 WRITE_ONCE(*ptep, pteval); 556 } 557 558 void flush_icache_pte(struct mm_struct *mm, pte_t pte); 559 560 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval) 561 { 562 if (pte_present(pteval) && pte_exec(pteval)) 563 flush_icache_pte(mm, pteval); 564 565 set_pte(ptep, pteval); 566 } 567 568 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT 569 570 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 571 pte_t *ptep, pte_t pteval, unsigned int nr) 572 { 573 page_table_check_ptes_set(mm, ptep, pteval, nr); 574 575 for (;;) { 576 __set_pte_at(mm, ptep, pteval); 577 if (--nr == 0) 578 break; 579 ptep++; 580 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 581 } 582 } 583 #define set_ptes set_ptes 584 585 static inline void pte_clear(struct mm_struct *mm, 586 unsigned long addr, pte_t *ptep) 587 { 588 __set_pte_at(mm, ptep, __pte(0)); 589 } 590 591 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 592 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 593 pte_t *ptep, pte_t entry, int dirty); 594 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 595 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address, 596 pte_t *ptep); 597 598 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 599 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 600 unsigned long address, pte_t *ptep) 601 { 602 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 603 604 page_table_check_pte_clear(mm, pte); 605 606 return pte; 607 } 608 609 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 610 static inline void ptep_set_wrprotect(struct mm_struct *mm, 611 unsigned long address, pte_t *ptep) 612 { 613 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 614 } 615 616 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 617 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 618 unsigned long address, pte_t *ptep) 619 { 620 /* 621 * This comment is borrowed from x86, but applies equally to RISC-V: 622 * 623 * Clearing the accessed bit without a TLB flush 624 * doesn't cause data corruption. [ It could cause incorrect 625 * page aging and the (mistaken) reclaim of hot pages, but the 626 * chance of that should be relatively low. ] 627 * 628 * So as a performance optimization don't flush the TLB when 629 * clearing the accessed bit, it will eventually be flushed by 630 * a context switch or a VM operation anyway. [ In the rare 631 * event of it not getting flushed for a long time the delay 632 * shouldn't really matter because there's no real memory 633 * pressure for swapout to react to. ] 634 */ 635 return ptep_test_and_clear_young(vma, address, ptep); 636 } 637 638 #define pgprot_nx pgprot_nx 639 static inline pgprot_t pgprot_nx(pgprot_t _prot) 640 { 641 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC); 642 } 643 644 #define pgprot_noncached pgprot_noncached 645 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 646 { 647 unsigned long prot = pgprot_val(_prot); 648 649 prot &= ~_PAGE_MTMASK; 650 prot |= _PAGE_IO; 651 652 return __pgprot(prot); 653 } 654 655 #define pgprot_writecombine pgprot_writecombine 656 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 657 { 658 unsigned long prot = pgprot_val(_prot); 659 660 prot &= ~_PAGE_MTMASK; 661 prot |= _PAGE_NOCACHE; 662 663 return __pgprot(prot); 664 } 665 666 /* 667 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By 668 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in 669 * DT. 670 */ 671 #define arch_has_hw_pte_young arch_has_hw_pte_young 672 static inline bool arch_has_hw_pte_young(void) 673 { 674 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); 675 } 676 677 /* 678 * THP functions 679 */ 680 static inline pmd_t pte_pmd(pte_t pte) 681 { 682 return __pmd(pte_val(pte)); 683 } 684 685 static inline pud_t pte_pud(pte_t pte) 686 { 687 return __pud(pte_val(pte)); 688 } 689 690 static inline pmd_t pmd_mkhuge(pmd_t pmd) 691 { 692 return pmd; 693 } 694 695 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 696 { 697 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 698 } 699 700 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 701 702 static inline unsigned long pmd_pfn(pmd_t pmd) 703 { 704 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 705 } 706 707 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 708 709 #define pud_pfn pud_pfn 710 static inline unsigned long pud_pfn(pud_t pud) 711 { 712 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 713 } 714 715 #define pmd_pgprot pmd_pgprot 716 static inline pgprot_t pmd_pgprot(pmd_t pmd) 717 { 718 return pte_pgprot(pmd_pte(pmd)); 719 } 720 721 #define pud_pgprot pud_pgprot 722 static inline pgprot_t pud_pgprot(pud_t pud) 723 { 724 return pte_pgprot(pud_pte(pud)); 725 } 726 727 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 728 { 729 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 730 } 731 732 #define pmd_write pmd_write 733 static inline int pmd_write(pmd_t pmd) 734 { 735 return pte_write(pmd_pte(pmd)); 736 } 737 738 #define pud_write pud_write 739 static inline int pud_write(pud_t pud) 740 { 741 return pte_write(pud_pte(pud)); 742 } 743 744 #define pmd_dirty pmd_dirty 745 static inline int pmd_dirty(pmd_t pmd) 746 { 747 return pte_dirty(pmd_pte(pmd)); 748 } 749 750 #define pmd_young pmd_young 751 static inline int pmd_young(pmd_t pmd) 752 { 753 return pte_young(pmd_pte(pmd)); 754 } 755 756 static inline int pmd_user(pmd_t pmd) 757 { 758 return pte_user(pmd_pte(pmd)); 759 } 760 761 static inline pmd_t pmd_mkold(pmd_t pmd) 762 { 763 return pte_pmd(pte_mkold(pmd_pte(pmd))); 764 } 765 766 static inline pmd_t pmd_mkyoung(pmd_t pmd) 767 { 768 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 769 } 770 771 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 772 { 773 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 774 } 775 776 static inline pmd_t pmd_wrprotect(pmd_t pmd) 777 { 778 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 779 } 780 781 static inline pmd_t pmd_mkclean(pmd_t pmd) 782 { 783 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 784 } 785 786 static inline pmd_t pmd_mkdirty(pmd_t pmd) 787 { 788 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 789 } 790 791 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 792 { 793 return pte_pmd(pte_mkdevmap(pmd_pte(pmd))); 794 } 795 796 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 797 static inline bool pmd_special(pmd_t pmd) 798 { 799 return pte_special(pmd_pte(pmd)); 800 } 801 802 static inline pmd_t pmd_mkspecial(pmd_t pmd) 803 { 804 return pte_pmd(pte_mkspecial(pmd_pte(pmd))); 805 } 806 #endif 807 808 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 809 static inline bool pud_special(pud_t pud) 810 { 811 return pte_special(pud_pte(pud)); 812 } 813 814 static inline pud_t pud_mkspecial(pud_t pud) 815 { 816 return pte_pud(pte_mkspecial(pud_pte(pud))); 817 } 818 #endif 819 820 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 821 pmd_t *pmdp, pmd_t pmd) 822 { 823 page_table_check_pmd_set(mm, pmdp, pmd); 824 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd)); 825 } 826 827 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 828 pud_t *pudp, pud_t pud) 829 { 830 page_table_check_pud_set(mm, pudp, pud); 831 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud)); 832 } 833 834 #ifdef CONFIG_PAGE_TABLE_CHECK 835 static inline bool pte_user_accessible_page(pte_t pte) 836 { 837 return pte_present(pte) && pte_user(pte); 838 } 839 840 static inline bool pmd_user_accessible_page(pmd_t pmd) 841 { 842 return pmd_leaf(pmd) && pmd_user(pmd); 843 } 844 845 static inline bool pud_user_accessible_page(pud_t pud) 846 { 847 return pud_leaf(pud) && pud_user(pud); 848 } 849 #endif 850 851 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 852 static inline int pmd_trans_huge(pmd_t pmd) 853 { 854 return pmd_leaf(pmd); 855 } 856 857 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 858 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 859 unsigned long address, pmd_t *pmdp, 860 pmd_t entry, int dirty) 861 { 862 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 863 } 864 865 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 866 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 867 unsigned long address, pmd_t *pmdp) 868 { 869 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 870 } 871 872 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 873 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 874 unsigned long address, pmd_t *pmdp) 875 { 876 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 877 878 page_table_check_pmd_clear(mm, pmd); 879 880 return pmd; 881 } 882 883 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 884 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 885 unsigned long address, pmd_t *pmdp) 886 { 887 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 888 } 889 890 #define pmdp_establish pmdp_establish 891 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 892 unsigned long address, pmd_t *pmdp, pmd_t pmd) 893 { 894 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 895 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 896 } 897 898 #define pmdp_collapse_flush pmdp_collapse_flush 899 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 900 unsigned long address, pmd_t *pmdp); 901 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 902 903 /* 904 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 905 * are !pte_none() && !pte_present(). 906 * 907 * Format of swap PTE: 908 * bit 0: _PAGE_PRESENT (zero) 909 * bit 1 to 3: _PAGE_LEAF (zero) 910 * bit 5: _PAGE_PROT_NONE (zero) 911 * bit 6: exclusive marker 912 * bits 7 to 11: swap type 913 * bits 12 to XLEN-1: swap offset 914 */ 915 #define __SWP_TYPE_SHIFT 7 916 #define __SWP_TYPE_BITS 5 917 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 918 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 919 920 #define MAX_SWAPFILES_CHECK() \ 921 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 922 923 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 924 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 925 #define __swp_entry(type, offset) ((swp_entry_t) \ 926 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 927 ((offset) << __SWP_OFFSET_SHIFT) }) 928 929 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 930 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 931 932 static inline int pte_swp_exclusive(pte_t pte) 933 { 934 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 935 } 936 937 static inline pte_t pte_swp_mkexclusive(pte_t pte) 938 { 939 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 940 } 941 942 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 943 { 944 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 945 } 946 947 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 948 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 949 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 950 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 951 952 /* 953 * In the RV64 Linux scheme, we give the user half of the virtual-address space 954 * and give the kernel the other (upper) half. 955 */ 956 #ifdef CONFIG_64BIT 957 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 958 #else 959 #define KERN_VIRT_START FIXADDR_START 960 #endif 961 962 /* 963 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 964 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 965 * Task size is: 966 * - 0x9fc00000 (~2.5GB) for RV32. 967 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 968 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 969 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 970 * 971 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 972 * Instruction Set Manual Volume II: Privileged Architecture" states that 973 * "load and store effective addresses, which are 64bits, must have bits 974 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 975 * Similarly for SV57, bits 63–57 must be equal to bit 56. 976 */ 977 #ifdef CONFIG_64BIT 978 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 979 #define TASK_SIZE_MAX LONG_MAX 980 981 #ifdef CONFIG_COMPAT 982 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 983 #define TASK_SIZE (is_compat_task() ? \ 984 TASK_SIZE_32 : TASK_SIZE_64) 985 #else 986 #define TASK_SIZE TASK_SIZE_64 987 #endif 988 989 #else 990 #define TASK_SIZE FIXADDR_START 991 #endif 992 993 #else /* CONFIG_MMU */ 994 995 #define PAGE_SHARED __pgprot(0) 996 #define PAGE_KERNEL __pgprot(0) 997 #define swapper_pg_dir NULL 998 #define TASK_SIZE _AC(-1, UL) 999 #define VMALLOC_START _AC(0, UL) 1000 #define VMALLOC_END TASK_SIZE 1001 1002 #endif /* !CONFIG_MMU */ 1003 1004 extern char _start[]; 1005 extern void *_dtb_early_va; 1006 extern uintptr_t _dtb_early_pa; 1007 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 1008 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 1009 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 1010 #else 1011 #define dtb_early_va _dtb_early_va 1012 #define dtb_early_pa _dtb_early_pa 1013 #endif /* CONFIG_XIP_KERNEL */ 1014 extern u64 satp_mode; 1015 1016 void paging_init(void); 1017 void misc_mem_init(void); 1018 1019 /* 1020 * ZERO_PAGE is a global shared page that is always zero, 1021 * used for zero-mapped memory areas, etc. 1022 */ 1023 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 1024 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 1025 1026 /* 1027 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1028 * TLB flush will be required as a result of the "set". For example, use 1029 * in scenarios where it is known ahead of time that the routine is 1030 * setting non-present entries, or re-setting an existing entry to the 1031 * same value. Otherwise, use the typical "set" helpers and flush the 1032 * TLB. 1033 */ 1034 #define set_p4d_safe(p4dp, p4d) \ 1035 ({ \ 1036 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1037 set_p4d(p4dp, p4d); \ 1038 }) 1039 1040 #define set_pgd_safe(pgdp, pgd) \ 1041 ({ \ 1042 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1043 set_pgd(pgdp, pgd); \ 1044 }) 1045 #endif /* !__ASSEMBLY__ */ 1046 1047 #endif /* _ASM_RISCV_PGTABLE_H */ 1048