1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan ([email protected]) and 6 * Paul Mackerras ([email protected]) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas ([email protected]) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 #include <linux/uaccess.h> 41 #include <linux/elf-randomize.h> 42 43 #include <asm/pgtable.h> 44 #include <asm/io.h> 45 #include <asm/processor.h> 46 #include <asm/mmu.h> 47 #include <asm/prom.h> 48 #include <asm/machdep.h> 49 #include <asm/time.h> 50 #include <asm/runlatch.h> 51 #include <asm/syscalls.h> 52 #include <asm/switch_to.h> 53 #include <asm/tm.h> 54 #include <asm/debug.h> 55 #ifdef CONFIG_PPC64 56 #include <asm/firmware.h> 57 #endif 58 #include <asm/code-patching.h> 59 #include <asm/exec.h> 60 #include <asm/livepatch.h> 61 #include <asm/cpu_has_feature.h> 62 #include <asm/asm-prototypes.h> 63 64 #include <linux/kprobes.h> 65 #include <linux/kdebug.h> 66 67 /* Transactional Memory debug */ 68 #ifdef TM_DEBUG_SW 69 #define TM_DEBUG(x...) printk(KERN_INFO x) 70 #else 71 #define TM_DEBUG(x...) do { } while(0) 72 #endif 73 74 extern unsigned long _get_SP(void); 75 76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 77 static void check_if_tm_restore_required(struct task_struct *tsk) 78 { 79 /* 80 * If we are saving the current thread's registers, and the 81 * thread is in a transactional state, set the TIF_RESTORE_TM 82 * bit so that we know to restore the registers before 83 * returning to userspace. 84 */ 85 if (tsk == current && tsk->thread.regs && 86 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 87 !test_thread_flag(TIF_RESTORE_TM)) { 88 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; 89 set_thread_flag(TIF_RESTORE_TM); 90 } 91 } 92 #else 93 static inline void check_if_tm_restore_required(struct task_struct *tsk) { } 94 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 95 96 bool strict_msr_control; 97 EXPORT_SYMBOL(strict_msr_control); 98 99 static int __init enable_strict_msr_control(char *str) 100 { 101 strict_msr_control = true; 102 pr_info("Enabling strict facility control\n"); 103 104 return 0; 105 } 106 early_param("ppc_strict_facility_enable", enable_strict_msr_control); 107 108 void msr_check_and_set(unsigned long bits) 109 { 110 unsigned long oldmsr = mfmsr(); 111 unsigned long newmsr; 112 113 newmsr = oldmsr | bits; 114 115 #ifdef CONFIG_VSX 116 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 117 newmsr |= MSR_VSX; 118 #endif 119 120 if (oldmsr != newmsr) 121 mtmsr_isync(newmsr); 122 } 123 124 void __msr_check_and_clear(unsigned long bits) 125 { 126 unsigned long oldmsr = mfmsr(); 127 unsigned long newmsr; 128 129 newmsr = oldmsr & ~bits; 130 131 #ifdef CONFIG_VSX 132 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) 133 newmsr &= ~MSR_VSX; 134 #endif 135 136 if (oldmsr != newmsr) 137 mtmsr_isync(newmsr); 138 } 139 EXPORT_SYMBOL(__msr_check_and_clear); 140 141 #ifdef CONFIG_PPC_FPU 142 void __giveup_fpu(struct task_struct *tsk) 143 { 144 unsigned long msr; 145 146 save_fpu(tsk); 147 msr = tsk->thread.regs->msr; 148 msr &= ~MSR_FP; 149 #ifdef CONFIG_VSX 150 if (cpu_has_feature(CPU_FTR_VSX)) 151 msr &= ~MSR_VSX; 152 #endif 153 tsk->thread.regs->msr = msr; 154 } 155 156 void giveup_fpu(struct task_struct *tsk) 157 { 158 check_if_tm_restore_required(tsk); 159 160 msr_check_and_set(MSR_FP); 161 __giveup_fpu(tsk); 162 msr_check_and_clear(MSR_FP); 163 } 164 EXPORT_SYMBOL(giveup_fpu); 165 166 /* 167 * Make sure the floating-point register state in the 168 * the thread_struct is up to date for task tsk. 169 */ 170 void flush_fp_to_thread(struct task_struct *tsk) 171 { 172 if (tsk->thread.regs) { 173 /* 174 * We need to disable preemption here because if we didn't, 175 * another process could get scheduled after the regs->msr 176 * test but before we have finished saving the FP registers 177 * to the thread_struct. That process could take over the 178 * FPU, and then when we get scheduled again we would store 179 * bogus values for the remaining FP registers. 180 */ 181 preempt_disable(); 182 if (tsk->thread.regs->msr & MSR_FP) { 183 /* 184 * This should only ever be called for current or 185 * for a stopped child process. Since we save away 186 * the FP register state on context switch, 187 * there is something wrong if a stopped child appears 188 * to still have its FP state in the CPU registers. 189 */ 190 BUG_ON(tsk != current); 191 giveup_fpu(tsk); 192 } 193 preempt_enable(); 194 } 195 } 196 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 197 198 void enable_kernel_fp(void) 199 { 200 WARN_ON(preemptible()); 201 202 msr_check_and_set(MSR_FP); 203 204 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { 205 check_if_tm_restore_required(current); 206 __giveup_fpu(current); 207 } 208 } 209 EXPORT_SYMBOL(enable_kernel_fp); 210 211 static int restore_fp(struct task_struct *tsk) { 212 if (tsk->thread.load_fp) { 213 load_fp_state(¤t->thread.fp_state); 214 current->thread.load_fp++; 215 return 1; 216 } 217 return 0; 218 } 219 #else 220 static int restore_fp(struct task_struct *tsk) { return 0; } 221 #endif /* CONFIG_PPC_FPU */ 222 223 #ifdef CONFIG_ALTIVEC 224 #define loadvec(thr) ((thr).load_vec) 225 226 static void __giveup_altivec(struct task_struct *tsk) 227 { 228 unsigned long msr; 229 230 save_altivec(tsk); 231 msr = tsk->thread.regs->msr; 232 msr &= ~MSR_VEC; 233 #ifdef CONFIG_VSX 234 if (cpu_has_feature(CPU_FTR_VSX)) 235 msr &= ~MSR_VSX; 236 #endif 237 tsk->thread.regs->msr = msr; 238 } 239 240 void giveup_altivec(struct task_struct *tsk) 241 { 242 check_if_tm_restore_required(tsk); 243 244 msr_check_and_set(MSR_VEC); 245 __giveup_altivec(tsk); 246 msr_check_and_clear(MSR_VEC); 247 } 248 EXPORT_SYMBOL(giveup_altivec); 249 250 void enable_kernel_altivec(void) 251 { 252 WARN_ON(preemptible()); 253 254 msr_check_and_set(MSR_VEC); 255 256 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { 257 check_if_tm_restore_required(current); 258 __giveup_altivec(current); 259 } 260 } 261 EXPORT_SYMBOL(enable_kernel_altivec); 262 263 /* 264 * Make sure the VMX/Altivec register state in the 265 * the thread_struct is up to date for task tsk. 266 */ 267 void flush_altivec_to_thread(struct task_struct *tsk) 268 { 269 if (tsk->thread.regs) { 270 preempt_disable(); 271 if (tsk->thread.regs->msr & MSR_VEC) { 272 BUG_ON(tsk != current); 273 giveup_altivec(tsk); 274 } 275 preempt_enable(); 276 } 277 } 278 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 279 280 static int restore_altivec(struct task_struct *tsk) 281 { 282 if (cpu_has_feature(CPU_FTR_ALTIVEC) && tsk->thread.load_vec) { 283 load_vr_state(&tsk->thread.vr_state); 284 tsk->thread.used_vr = 1; 285 tsk->thread.load_vec++; 286 287 return 1; 288 } 289 return 0; 290 } 291 #else 292 #define loadvec(thr) 0 293 static inline int restore_altivec(struct task_struct *tsk) { return 0; } 294 #endif /* CONFIG_ALTIVEC */ 295 296 #ifdef CONFIG_VSX 297 static void __giveup_vsx(struct task_struct *tsk) 298 { 299 if (tsk->thread.regs->msr & MSR_FP) 300 __giveup_fpu(tsk); 301 if (tsk->thread.regs->msr & MSR_VEC) 302 __giveup_altivec(tsk); 303 tsk->thread.regs->msr &= ~MSR_VSX; 304 } 305 306 static void giveup_vsx(struct task_struct *tsk) 307 { 308 check_if_tm_restore_required(tsk); 309 310 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 311 __giveup_vsx(tsk); 312 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); 313 } 314 315 static void save_vsx(struct task_struct *tsk) 316 { 317 if (tsk->thread.regs->msr & MSR_FP) 318 save_fpu(tsk); 319 if (tsk->thread.regs->msr & MSR_VEC) 320 save_altivec(tsk); 321 } 322 323 void enable_kernel_vsx(void) 324 { 325 WARN_ON(preemptible()); 326 327 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); 328 329 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { 330 check_if_tm_restore_required(current); 331 if (current->thread.regs->msr & MSR_FP) 332 __giveup_fpu(current); 333 if (current->thread.regs->msr & MSR_VEC) 334 __giveup_altivec(current); 335 __giveup_vsx(current); 336 } 337 } 338 EXPORT_SYMBOL(enable_kernel_vsx); 339 340 void flush_vsx_to_thread(struct task_struct *tsk) 341 { 342 if (tsk->thread.regs) { 343 preempt_disable(); 344 if (tsk->thread.regs->msr & MSR_VSX) { 345 BUG_ON(tsk != current); 346 giveup_vsx(tsk); 347 } 348 preempt_enable(); 349 } 350 } 351 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 352 353 static int restore_vsx(struct task_struct *tsk) 354 { 355 if (cpu_has_feature(CPU_FTR_VSX)) { 356 tsk->thread.used_vsr = 1; 357 return 1; 358 } 359 360 return 0; 361 } 362 #else 363 static inline int restore_vsx(struct task_struct *tsk) { return 0; } 364 static inline void save_vsx(struct task_struct *tsk) { } 365 #endif /* CONFIG_VSX */ 366 367 #ifdef CONFIG_SPE 368 void giveup_spe(struct task_struct *tsk) 369 { 370 check_if_tm_restore_required(tsk); 371 372 msr_check_and_set(MSR_SPE); 373 __giveup_spe(tsk); 374 msr_check_and_clear(MSR_SPE); 375 } 376 EXPORT_SYMBOL(giveup_spe); 377 378 void enable_kernel_spe(void) 379 { 380 WARN_ON(preemptible()); 381 382 msr_check_and_set(MSR_SPE); 383 384 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { 385 check_if_tm_restore_required(current); 386 __giveup_spe(current); 387 } 388 } 389 EXPORT_SYMBOL(enable_kernel_spe); 390 391 void flush_spe_to_thread(struct task_struct *tsk) 392 { 393 if (tsk->thread.regs) { 394 preempt_disable(); 395 if (tsk->thread.regs->msr & MSR_SPE) { 396 BUG_ON(tsk != current); 397 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 398 giveup_spe(tsk); 399 } 400 preempt_enable(); 401 } 402 } 403 #endif /* CONFIG_SPE */ 404 405 static unsigned long msr_all_available; 406 407 static int __init init_msr_all_available(void) 408 { 409 #ifdef CONFIG_PPC_FPU 410 msr_all_available |= MSR_FP; 411 #endif 412 #ifdef CONFIG_ALTIVEC 413 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 414 msr_all_available |= MSR_VEC; 415 #endif 416 #ifdef CONFIG_VSX 417 if (cpu_has_feature(CPU_FTR_VSX)) 418 msr_all_available |= MSR_VSX; 419 #endif 420 #ifdef CONFIG_SPE 421 if (cpu_has_feature(CPU_FTR_SPE)) 422 msr_all_available |= MSR_SPE; 423 #endif 424 425 return 0; 426 } 427 early_initcall(init_msr_all_available); 428 429 void giveup_all(struct task_struct *tsk) 430 { 431 unsigned long usermsr; 432 433 if (!tsk->thread.regs) 434 return; 435 436 usermsr = tsk->thread.regs->msr; 437 438 if ((usermsr & msr_all_available) == 0) 439 return; 440 441 msr_check_and_set(msr_all_available); 442 443 #ifdef CONFIG_PPC_FPU 444 if (usermsr & MSR_FP) 445 __giveup_fpu(tsk); 446 #endif 447 #ifdef CONFIG_ALTIVEC 448 if (usermsr & MSR_VEC) 449 __giveup_altivec(tsk); 450 #endif 451 #ifdef CONFIG_VSX 452 if (usermsr & MSR_VSX) 453 __giveup_vsx(tsk); 454 #endif 455 #ifdef CONFIG_SPE 456 if (usermsr & MSR_SPE) 457 __giveup_spe(tsk); 458 #endif 459 460 msr_check_and_clear(msr_all_available); 461 } 462 EXPORT_SYMBOL(giveup_all); 463 464 void restore_math(struct pt_regs *regs) 465 { 466 unsigned long msr; 467 468 if (!current->thread.load_fp && !loadvec(current->thread)) 469 return; 470 471 msr = regs->msr; 472 msr_check_and_set(msr_all_available); 473 474 /* 475 * Only reload if the bit is not set in the user MSR, the bit BEING set 476 * indicates that the registers are hot 477 */ 478 if ((!(msr & MSR_FP)) && restore_fp(current)) 479 msr |= MSR_FP | current->thread.fpexc_mode; 480 481 if ((!(msr & MSR_VEC)) && restore_altivec(current)) 482 msr |= MSR_VEC; 483 484 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && 485 restore_vsx(current)) { 486 msr |= MSR_VSX; 487 } 488 489 msr_check_and_clear(msr_all_available); 490 491 regs->msr = msr; 492 } 493 494 void save_all(struct task_struct *tsk) 495 { 496 unsigned long usermsr; 497 498 if (!tsk->thread.regs) 499 return; 500 501 usermsr = tsk->thread.regs->msr; 502 503 if ((usermsr & msr_all_available) == 0) 504 return; 505 506 msr_check_and_set(msr_all_available); 507 508 /* 509 * Saving the way the register space is in hardware, save_vsx boils 510 * down to a save_fpu() and save_altivec() 511 */ 512 if (usermsr & MSR_VSX) { 513 save_vsx(tsk); 514 } else { 515 if (usermsr & MSR_FP) 516 save_fpu(tsk); 517 518 if (usermsr & MSR_VEC) 519 save_altivec(tsk); 520 } 521 522 if (usermsr & MSR_SPE) 523 __giveup_spe(tsk); 524 525 msr_check_and_clear(msr_all_available); 526 } 527 528 void flush_all_to_thread(struct task_struct *tsk) 529 { 530 if (tsk->thread.regs) { 531 preempt_disable(); 532 BUG_ON(tsk != current); 533 save_all(tsk); 534 535 #ifdef CONFIG_SPE 536 if (tsk->thread.regs->msr & MSR_SPE) 537 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 538 #endif 539 540 preempt_enable(); 541 } 542 } 543 EXPORT_SYMBOL(flush_all_to_thread); 544 545 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 546 void do_send_trap(struct pt_regs *regs, unsigned long address, 547 unsigned long error_code, int signal_code, int breakpt) 548 { 549 siginfo_t info; 550 551 current->thread.trap_nr = signal_code; 552 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 553 11, SIGSEGV) == NOTIFY_STOP) 554 return; 555 556 /* Deliver the signal to userspace */ 557 info.si_signo = SIGTRAP; 558 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 559 info.si_code = signal_code; 560 info.si_addr = (void __user *)address; 561 force_sig_info(SIGTRAP, &info, current); 562 } 563 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 564 void do_break (struct pt_regs *regs, unsigned long address, 565 unsigned long error_code) 566 { 567 siginfo_t info; 568 569 current->thread.trap_nr = TRAP_HWBKPT; 570 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 571 11, SIGSEGV) == NOTIFY_STOP) 572 return; 573 574 if (debugger_break_match(regs)) 575 return; 576 577 /* Clear the breakpoint */ 578 hw_breakpoint_disable(); 579 580 /* Deliver the signal to userspace */ 581 info.si_signo = SIGTRAP; 582 info.si_errno = 0; 583 info.si_code = TRAP_HWBKPT; 584 info.si_addr = (void __user *)address; 585 force_sig_info(SIGTRAP, &info, current); 586 } 587 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 588 589 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 590 591 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 592 /* 593 * Set the debug registers back to their default "safe" values. 594 */ 595 static void set_debug_reg_defaults(struct thread_struct *thread) 596 { 597 thread->debug.iac1 = thread->debug.iac2 = 0; 598 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 599 thread->debug.iac3 = thread->debug.iac4 = 0; 600 #endif 601 thread->debug.dac1 = thread->debug.dac2 = 0; 602 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 603 thread->debug.dvc1 = thread->debug.dvc2 = 0; 604 #endif 605 thread->debug.dbcr0 = 0; 606 #ifdef CONFIG_BOOKE 607 /* 608 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 609 */ 610 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 611 DBCR1_IAC3US | DBCR1_IAC4US; 612 /* 613 * Force Data Address Compare User/Supervisor bits to be User-only 614 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 615 */ 616 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 617 #else 618 thread->debug.dbcr1 = 0; 619 #endif 620 } 621 622 static void prime_debug_regs(struct debug_reg *debug) 623 { 624 /* 625 * We could have inherited MSR_DE from userspace, since 626 * it doesn't get cleared on exception entry. Make sure 627 * MSR_DE is clear before we enable any debug events. 628 */ 629 mtmsr(mfmsr() & ~MSR_DE); 630 631 mtspr(SPRN_IAC1, debug->iac1); 632 mtspr(SPRN_IAC2, debug->iac2); 633 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 634 mtspr(SPRN_IAC3, debug->iac3); 635 mtspr(SPRN_IAC4, debug->iac4); 636 #endif 637 mtspr(SPRN_DAC1, debug->dac1); 638 mtspr(SPRN_DAC2, debug->dac2); 639 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 640 mtspr(SPRN_DVC1, debug->dvc1); 641 mtspr(SPRN_DVC2, debug->dvc2); 642 #endif 643 mtspr(SPRN_DBCR0, debug->dbcr0); 644 mtspr(SPRN_DBCR1, debug->dbcr1); 645 #ifdef CONFIG_BOOKE 646 mtspr(SPRN_DBCR2, debug->dbcr2); 647 #endif 648 } 649 /* 650 * Unless neither the old or new thread are making use of the 651 * debug registers, set the debug registers from the values 652 * stored in the new thread. 653 */ 654 void switch_booke_debug_regs(struct debug_reg *new_debug) 655 { 656 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 657 || (new_debug->dbcr0 & DBCR0_IDM)) 658 prime_debug_regs(new_debug); 659 } 660 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 661 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 662 #ifndef CONFIG_HAVE_HW_BREAKPOINT 663 static void set_debug_reg_defaults(struct thread_struct *thread) 664 { 665 thread->hw_brk.address = 0; 666 thread->hw_brk.type = 0; 667 set_breakpoint(&thread->hw_brk); 668 } 669 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 670 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 671 672 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 673 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 674 { 675 mtspr(SPRN_DAC1, dabr); 676 #ifdef CONFIG_PPC_47x 677 isync(); 678 #endif 679 return 0; 680 } 681 #elif defined(CONFIG_PPC_BOOK3S) 682 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 683 { 684 mtspr(SPRN_DABR, dabr); 685 if (cpu_has_feature(CPU_FTR_DABRX)) 686 mtspr(SPRN_DABRX, dabrx); 687 return 0; 688 } 689 #else 690 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 691 { 692 return -EINVAL; 693 } 694 #endif 695 696 static inline int set_dabr(struct arch_hw_breakpoint *brk) 697 { 698 unsigned long dabr, dabrx; 699 700 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 701 dabrx = ((brk->type >> 3) & 0x7); 702 703 if (ppc_md.set_dabr) 704 return ppc_md.set_dabr(dabr, dabrx); 705 706 return __set_dabr(dabr, dabrx); 707 } 708 709 static inline int set_dawr(struct arch_hw_breakpoint *brk) 710 { 711 unsigned long dawr, dawrx, mrd; 712 713 dawr = brk->address; 714 715 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 716 << (63 - 58); //* read/write bits */ 717 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 718 << (63 - 59); //* translate */ 719 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 720 >> 3; //* PRIM bits */ 721 /* dawr length is stored in field MDR bits 48:53. Matches range in 722 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 723 0b111111=64DW. 724 brk->len is in bytes. 725 This aligns up to double word size, shifts and does the bias. 726 */ 727 mrd = ((brk->len + 7) >> 3) - 1; 728 dawrx |= (mrd & 0x3f) << (63 - 53); 729 730 if (ppc_md.set_dawr) 731 return ppc_md.set_dawr(dawr, dawrx); 732 mtspr(SPRN_DAWR, dawr); 733 mtspr(SPRN_DAWRX, dawrx); 734 return 0; 735 } 736 737 void __set_breakpoint(struct arch_hw_breakpoint *brk) 738 { 739 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); 740 741 if (cpu_has_feature(CPU_FTR_DAWR)) 742 set_dawr(brk); 743 else 744 set_dabr(brk); 745 } 746 747 void set_breakpoint(struct arch_hw_breakpoint *brk) 748 { 749 preempt_disable(); 750 __set_breakpoint(brk); 751 preempt_enable(); 752 } 753 754 #ifdef CONFIG_PPC64 755 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 756 #endif 757 758 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 759 struct arch_hw_breakpoint *b) 760 { 761 if (a->address != b->address) 762 return false; 763 if (a->type != b->type) 764 return false; 765 if (a->len != b->len) 766 return false; 767 return true; 768 } 769 770 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 771 static void tm_reclaim_thread(struct thread_struct *thr, 772 struct thread_info *ti, uint8_t cause) 773 { 774 unsigned long msr_diff = 0; 775 776 /* 777 * If FP/VSX registers have been already saved to the 778 * thread_struct, move them to the transact_fp array. 779 * We clear the TIF_RESTORE_TM bit since after the reclaim 780 * the thread will no longer be transactional. 781 */ 782 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 783 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr; 784 if (msr_diff & MSR_FP) 785 memcpy(&thr->transact_fp, &thr->fp_state, 786 sizeof(struct thread_fp_state)); 787 if (msr_diff & MSR_VEC) 788 memcpy(&thr->transact_vr, &thr->vr_state, 789 sizeof(struct thread_vr_state)); 790 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 791 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 792 } 793 794 /* 795 * Use the current MSR TM suspended bit to track if we have 796 * checkpointed state outstanding. 797 * On signal delivery, we'd normally reclaim the checkpointed 798 * state to obtain stack pointer (see:get_tm_stackpointer()). 799 * This will then directly return to userspace without going 800 * through __switch_to(). However, if the stack frame is bad, 801 * we need to exit this thread which calls __switch_to() which 802 * will again attempt to reclaim the already saved tm state. 803 * Hence we need to check that we've not already reclaimed 804 * this state. 805 * We do this using the current MSR, rather tracking it in 806 * some specific thread_struct bit, as it has the additional 807 * benefit of checking for a potential TM bad thing exception. 808 */ 809 if (!MSR_TM_SUSPENDED(mfmsr())) 810 return; 811 812 tm_reclaim(thr, thr->regs->msr, cause); 813 814 /* Having done the reclaim, we now have the checkpointed 815 * FP/VSX values in the registers. These might be valid 816 * even if we have previously called enable_kernel_fp() or 817 * flush_fp_to_thread(), so update thr->regs->msr to 818 * indicate their current validity. 819 */ 820 thr->regs->msr |= msr_diff; 821 } 822 823 void tm_reclaim_current(uint8_t cause) 824 { 825 tm_enable(); 826 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 827 } 828 829 static inline void tm_reclaim_task(struct task_struct *tsk) 830 { 831 /* We have to work out if we're switching from/to a task that's in the 832 * middle of a transaction. 833 * 834 * In switching we need to maintain a 2nd register state as 835 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 836 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 837 * (current) FPRs into oldtask->thread.transact_fpr[]. 838 * 839 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 840 */ 841 struct thread_struct *thr = &tsk->thread; 842 843 if (!thr->regs) 844 return; 845 846 if (!MSR_TM_ACTIVE(thr->regs->msr)) 847 goto out_and_saveregs; 848 849 /* Stash the original thread MSR, as giveup_fpu et al will 850 * modify it. We hold onto it to see whether the task used 851 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 852 * ckpt_regs.msr is already set. 853 */ 854 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 855 thr->ckpt_regs.msr = thr->regs->msr; 856 857 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 858 "ccr=%lx, msr=%lx, trap=%lx)\n", 859 tsk->pid, thr->regs->nip, 860 thr->regs->ccr, thr->regs->msr, 861 thr->regs->trap); 862 863 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 864 865 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 866 tsk->pid); 867 868 out_and_saveregs: 869 /* Always save the regs here, even if a transaction's not active. 870 * This context-switches a thread's TM info SPRs. We do it here to 871 * be consistent with the restore path (in recheckpoint) which 872 * cannot happen later in _switch(). 873 */ 874 tm_save_sprs(thr); 875 } 876 877 extern void __tm_recheckpoint(struct thread_struct *thread, 878 unsigned long orig_msr); 879 880 void tm_recheckpoint(struct thread_struct *thread, 881 unsigned long orig_msr) 882 { 883 unsigned long flags; 884 885 /* We really can't be interrupted here as the TEXASR registers can't 886 * change and later in the trecheckpoint code, we have a userspace R1. 887 * So let's hard disable over this region. 888 */ 889 local_irq_save(flags); 890 hard_irq_disable(); 891 892 /* The TM SPRs are restored here, so that TEXASR.FS can be set 893 * before the trecheckpoint and no explosion occurs. 894 */ 895 tm_restore_sprs(thread); 896 897 __tm_recheckpoint(thread, orig_msr); 898 899 local_irq_restore(flags); 900 } 901 902 static inline void tm_recheckpoint_new_task(struct task_struct *new) 903 { 904 unsigned long msr; 905 906 if (!cpu_has_feature(CPU_FTR_TM)) 907 return; 908 909 /* Recheckpoint the registers of the thread we're about to switch to. 910 * 911 * If the task was using FP, we non-lazily reload both the original and 912 * the speculative FP register states. This is because the kernel 913 * doesn't see if/when a TM rollback occurs, so if we take an FP 914 * unavoidable later, we are unable to determine which set of FP regs 915 * need to be restored. 916 */ 917 if (!new->thread.regs) 918 return; 919 920 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 921 tm_restore_sprs(&new->thread); 922 return; 923 } 924 msr = new->thread.ckpt_regs.msr; 925 /* Recheckpoint to restore original checkpointed register state. */ 926 TM_DEBUG("*** tm_recheckpoint of pid %d " 927 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 928 new->pid, new->thread.regs->msr, msr); 929 930 /* This loads the checkpointed FP/VEC state, if used */ 931 tm_recheckpoint(&new->thread, msr); 932 933 /* This loads the speculative FP/VEC state, if used */ 934 if (msr & MSR_FP) { 935 do_load_up_transact_fpu(&new->thread); 936 new->thread.regs->msr |= 937 (MSR_FP | new->thread.fpexc_mode); 938 } 939 #ifdef CONFIG_ALTIVEC 940 if (msr & MSR_VEC) { 941 do_load_up_transact_altivec(&new->thread); 942 new->thread.regs->msr |= MSR_VEC; 943 } 944 #endif 945 /* We may as well turn on VSX too since all the state is restored now */ 946 if (msr & MSR_VSX) 947 new->thread.regs->msr |= MSR_VSX; 948 949 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 950 "(kernel msr 0x%lx)\n", 951 new->pid, mfmsr()); 952 } 953 954 static inline void __switch_to_tm(struct task_struct *prev) 955 { 956 if (cpu_has_feature(CPU_FTR_TM)) { 957 tm_enable(); 958 tm_reclaim_task(prev); 959 } 960 } 961 962 /* 963 * This is called if we are on the way out to userspace and the 964 * TIF_RESTORE_TM flag is set. It checks if we need to reload 965 * FP and/or vector state and does so if necessary. 966 * If userspace is inside a transaction (whether active or 967 * suspended) and FP/VMX/VSX instructions have ever been enabled 968 * inside that transaction, then we have to keep them enabled 969 * and keep the FP/VMX/VSX state loaded while ever the transaction 970 * continues. The reason is that if we didn't, and subsequently 971 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 972 * we don't know whether it's the same transaction, and thus we 973 * don't know which of the checkpointed state and the transactional 974 * state to use. 975 */ 976 void restore_tm_state(struct pt_regs *regs) 977 { 978 unsigned long msr_diff; 979 980 clear_thread_flag(TIF_RESTORE_TM); 981 if (!MSR_TM_ACTIVE(regs->msr)) 982 return; 983 984 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; 985 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 986 987 restore_math(regs); 988 989 regs->msr |= msr_diff; 990 } 991 992 #else 993 #define tm_recheckpoint_new_task(new) 994 #define __switch_to_tm(prev) 995 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 996 997 static inline void save_sprs(struct thread_struct *t) 998 { 999 #ifdef CONFIG_ALTIVEC 1000 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1001 t->vrsave = mfspr(SPRN_VRSAVE); 1002 #endif 1003 #ifdef CONFIG_PPC_BOOK3S_64 1004 if (cpu_has_feature(CPU_FTR_DSCR)) 1005 t->dscr = mfspr(SPRN_DSCR); 1006 1007 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1008 t->bescr = mfspr(SPRN_BESCR); 1009 t->ebbhr = mfspr(SPRN_EBBHR); 1010 t->ebbrr = mfspr(SPRN_EBBRR); 1011 1012 t->fscr = mfspr(SPRN_FSCR); 1013 1014 /* 1015 * Note that the TAR is not available for use in the kernel. 1016 * (To provide this, the TAR should be backed up/restored on 1017 * exception entry/exit instead, and be in pt_regs. FIXME, 1018 * this should be in pt_regs anyway (for debug).) 1019 */ 1020 t->tar = mfspr(SPRN_TAR); 1021 } 1022 1023 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1024 /* Conditionally save Load Monitor registers, if enabled */ 1025 if (t->fscr & FSCR_LM) { 1026 t->lmrr = mfspr(SPRN_LMRR); 1027 t->lmser = mfspr(SPRN_LMSER); 1028 } 1029 } 1030 #endif 1031 } 1032 1033 static inline void restore_sprs(struct thread_struct *old_thread, 1034 struct thread_struct *new_thread) 1035 { 1036 #ifdef CONFIG_ALTIVEC 1037 if (cpu_has_feature(CPU_FTR_ALTIVEC) && 1038 old_thread->vrsave != new_thread->vrsave) 1039 mtspr(SPRN_VRSAVE, new_thread->vrsave); 1040 #endif 1041 #ifdef CONFIG_PPC_BOOK3S_64 1042 if (cpu_has_feature(CPU_FTR_DSCR)) { 1043 u64 dscr = get_paca()->dscr_default; 1044 if (new_thread->dscr_inherit) 1045 dscr = new_thread->dscr; 1046 1047 if (old_thread->dscr != dscr) 1048 mtspr(SPRN_DSCR, dscr); 1049 } 1050 1051 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 1052 if (old_thread->bescr != new_thread->bescr) 1053 mtspr(SPRN_BESCR, new_thread->bescr); 1054 if (old_thread->ebbhr != new_thread->ebbhr) 1055 mtspr(SPRN_EBBHR, new_thread->ebbhr); 1056 if (old_thread->ebbrr != new_thread->ebbrr) 1057 mtspr(SPRN_EBBRR, new_thread->ebbrr); 1058 1059 if (old_thread->fscr != new_thread->fscr) 1060 mtspr(SPRN_FSCR, new_thread->fscr); 1061 1062 if (old_thread->tar != new_thread->tar) 1063 mtspr(SPRN_TAR, new_thread->tar); 1064 } 1065 1066 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1067 /* Conditionally restore Load Monitor registers, if enabled */ 1068 if (new_thread->fscr & FSCR_LM) { 1069 if (old_thread->lmrr != new_thread->lmrr) 1070 mtspr(SPRN_LMRR, new_thread->lmrr); 1071 if (old_thread->lmser != new_thread->lmser) 1072 mtspr(SPRN_LMSER, new_thread->lmser); 1073 } 1074 } 1075 #endif 1076 } 1077 1078 struct task_struct *__switch_to(struct task_struct *prev, 1079 struct task_struct *new) 1080 { 1081 struct thread_struct *new_thread, *old_thread; 1082 struct task_struct *last; 1083 #ifdef CONFIG_PPC_BOOK3S_64 1084 struct ppc64_tlb_batch *batch; 1085 #endif 1086 1087 new_thread = &new->thread; 1088 old_thread = ¤t->thread; 1089 1090 WARN_ON(!irqs_disabled()); 1091 1092 #ifdef CONFIG_PPC64 1093 /* 1094 * Collect processor utilization data per process 1095 */ 1096 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 1097 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); 1098 long unsigned start_tb, current_tb; 1099 start_tb = old_thread->start_tb; 1100 cu->current_tb = current_tb = mfspr(SPRN_PURR); 1101 old_thread->accum_tb += (current_tb - start_tb); 1102 new_thread->start_tb = current_tb; 1103 } 1104 #endif /* CONFIG_PPC64 */ 1105 1106 #ifdef CONFIG_PPC_STD_MMU_64 1107 batch = this_cpu_ptr(&ppc64_tlb_batch); 1108 if (batch->active) { 1109 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 1110 if (batch->index) 1111 __flush_tlb_pending(batch); 1112 batch->active = 0; 1113 } 1114 #endif /* CONFIG_PPC_STD_MMU_64 */ 1115 1116 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1117 switch_booke_debug_regs(&new->thread.debug); 1118 #else 1119 /* 1120 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 1121 * schedule DABR 1122 */ 1123 #ifndef CONFIG_HAVE_HW_BREAKPOINT 1124 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) 1125 __set_breakpoint(&new->thread.hw_brk); 1126 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1127 #endif 1128 1129 /* 1130 * We need to save SPRs before treclaim/trecheckpoint as these will 1131 * change a number of them. 1132 */ 1133 save_sprs(&prev->thread); 1134 1135 __switch_to_tm(prev); 1136 1137 /* Save FPU, Altivec, VSX and SPE state */ 1138 giveup_all(prev); 1139 1140 /* 1141 * We can't take a PMU exception inside _switch() since there is a 1142 * window where the kernel stack SLB and the kernel stack are out 1143 * of sync. Hard disable here. 1144 */ 1145 hard_irq_disable(); 1146 1147 tm_recheckpoint_new_task(new); 1148 1149 /* 1150 * Call restore_sprs() before calling _switch(). If we move it after 1151 * _switch() then we miss out on calling it for new tasks. The reason 1152 * for this is we manually create a stack frame for new tasks that 1153 * directly returns through ret_from_fork() or 1154 * ret_from_kernel_thread(). See copy_thread() for details. 1155 */ 1156 restore_sprs(old_thread, new_thread); 1157 1158 last = _switch(old_thread, new_thread); 1159 1160 #ifdef CONFIG_PPC_STD_MMU_64 1161 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 1162 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 1163 batch = this_cpu_ptr(&ppc64_tlb_batch); 1164 batch->active = 1; 1165 } 1166 1167 if (current_thread_info()->task->thread.regs) 1168 restore_math(current_thread_info()->task->thread.regs); 1169 #endif /* CONFIG_PPC_STD_MMU_64 */ 1170 1171 return last; 1172 } 1173 1174 static int instructions_to_print = 16; 1175 1176 static void show_instructions(struct pt_regs *regs) 1177 { 1178 int i; 1179 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 1180 sizeof(int)); 1181 1182 printk("Instruction dump:"); 1183 1184 for (i = 0; i < instructions_to_print; i++) { 1185 int instr; 1186 1187 if (!(i % 8)) 1188 printk("\n"); 1189 1190 #if !defined(CONFIG_BOOKE) 1191 /* If executing with the IMMU off, adjust pc rather 1192 * than print XXXXXXXX. 1193 */ 1194 if (!(regs->msr & MSR_IR)) 1195 pc = (unsigned long)phys_to_virt(pc); 1196 #endif 1197 1198 if (!__kernel_text_address(pc) || 1199 probe_kernel_address((unsigned int __user *)pc, instr)) { 1200 printk(KERN_CONT "XXXXXXXX "); 1201 } else { 1202 if (regs->nip == pc) 1203 printk(KERN_CONT "<%08x> ", instr); 1204 else 1205 printk(KERN_CONT "%08x ", instr); 1206 } 1207 1208 pc += sizeof(int); 1209 } 1210 1211 printk("\n"); 1212 } 1213 1214 struct regbit { 1215 unsigned long bit; 1216 const char *name; 1217 }; 1218 1219 static struct regbit msr_bits[] = { 1220 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 1221 {MSR_SF, "SF"}, 1222 {MSR_HV, "HV"}, 1223 #endif 1224 {MSR_VEC, "VEC"}, 1225 {MSR_VSX, "VSX"}, 1226 #ifdef CONFIG_BOOKE 1227 {MSR_CE, "CE"}, 1228 #endif 1229 {MSR_EE, "EE"}, 1230 {MSR_PR, "PR"}, 1231 {MSR_FP, "FP"}, 1232 {MSR_ME, "ME"}, 1233 #ifdef CONFIG_BOOKE 1234 {MSR_DE, "DE"}, 1235 #else 1236 {MSR_SE, "SE"}, 1237 {MSR_BE, "BE"}, 1238 #endif 1239 {MSR_IR, "IR"}, 1240 {MSR_DR, "DR"}, 1241 {MSR_PMM, "PMM"}, 1242 #ifndef CONFIG_BOOKE 1243 {MSR_RI, "RI"}, 1244 {MSR_LE, "LE"}, 1245 #endif 1246 {0, NULL} 1247 }; 1248 1249 static void print_bits(unsigned long val, struct regbit *bits, const char *sep) 1250 { 1251 const char *s = ""; 1252 1253 for (; bits->bit; ++bits) 1254 if (val & bits->bit) { 1255 printk("%s%s", s, bits->name); 1256 s = sep; 1257 } 1258 } 1259 1260 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1261 static struct regbit msr_tm_bits[] = { 1262 {MSR_TS_T, "T"}, 1263 {MSR_TS_S, "S"}, 1264 {MSR_TM, "E"}, 1265 {0, NULL} 1266 }; 1267 1268 static void print_tm_bits(unsigned long val) 1269 { 1270 /* 1271 * This only prints something if at least one of the TM bit is set. 1272 * Inside the TM[], the output means: 1273 * E: Enabled (bit 32) 1274 * S: Suspended (bit 33) 1275 * T: Transactional (bit 34) 1276 */ 1277 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { 1278 printk(",TM["); 1279 print_bits(val, msr_tm_bits, ""); 1280 printk("]"); 1281 } 1282 } 1283 #else 1284 static void print_tm_bits(unsigned long val) {} 1285 #endif 1286 1287 static void print_msr_bits(unsigned long val) 1288 { 1289 printk("<"); 1290 print_bits(val, msr_bits, ","); 1291 print_tm_bits(val); 1292 printk(">"); 1293 } 1294 1295 #ifdef CONFIG_PPC64 1296 #define REG "%016lx" 1297 #define REGS_PER_LINE 4 1298 #define LAST_VOLATILE 13 1299 #else 1300 #define REG "%08lx" 1301 #define REGS_PER_LINE 8 1302 #define LAST_VOLATILE 12 1303 #endif 1304 1305 void show_regs(struct pt_regs * regs) 1306 { 1307 int i, trap; 1308 1309 show_regs_print_info(KERN_DEFAULT); 1310 1311 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 1312 regs->nip, regs->link, regs->ctr); 1313 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1314 regs, regs->trap, print_tainted(), init_utsname()->release); 1315 printk("MSR: "REG" ", regs->msr); 1316 print_msr_bits(regs->msr); 1317 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1318 trap = TRAP(regs); 1319 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1320 printk("CFAR: "REG" ", regs->orig_gpr3); 1321 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1322 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1323 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1324 #else 1325 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1326 #endif 1327 #ifdef CONFIG_PPC64 1328 printk("SOFTE: %ld ", regs->softe); 1329 #endif 1330 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1331 if (MSR_TM_ACTIVE(regs->msr)) 1332 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1333 #endif 1334 1335 for (i = 0; i < 32; i++) { 1336 if ((i % REGS_PER_LINE) == 0) 1337 printk("\nGPR%02d: ", i); 1338 printk(REG " ", regs->gpr[i]); 1339 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1340 break; 1341 } 1342 printk("\n"); 1343 #ifdef CONFIG_KALLSYMS 1344 /* 1345 * Lookup NIP late so we have the best change of getting the 1346 * above info out without failing 1347 */ 1348 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1349 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1350 #endif 1351 show_stack(current, (unsigned long *) regs->gpr[1]); 1352 if (!user_mode(regs)) 1353 show_instructions(regs); 1354 } 1355 1356 void flush_thread(void) 1357 { 1358 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1359 flush_ptrace_hw_breakpoint(current); 1360 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1361 set_debug_reg_defaults(¤t->thread); 1362 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1363 } 1364 1365 void 1366 release_thread(struct task_struct *t) 1367 { 1368 } 1369 1370 /* 1371 * this gets called so that we can store coprocessor state into memory and 1372 * copy the current task into the new thread. 1373 */ 1374 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1375 { 1376 flush_all_to_thread(src); 1377 /* 1378 * Flush TM state out so we can copy it. __switch_to_tm() does this 1379 * flush but it removes the checkpointed state from the current CPU and 1380 * transitions the CPU out of TM mode. Hence we need to call 1381 * tm_recheckpoint_new_task() (on the same task) to restore the 1382 * checkpointed state back and the TM mode. 1383 */ 1384 __switch_to_tm(src); 1385 tm_recheckpoint_new_task(src); 1386 1387 *dst = *src; 1388 1389 clear_task_ebb(dst); 1390 1391 return 0; 1392 } 1393 1394 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) 1395 { 1396 #ifdef CONFIG_PPC_STD_MMU_64 1397 unsigned long sp_vsid; 1398 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1399 1400 if (radix_enabled()) 1401 return; 1402 1403 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1404 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1405 << SLB_VSID_SHIFT_1T; 1406 else 1407 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1408 << SLB_VSID_SHIFT; 1409 sp_vsid |= SLB_VSID_KERNEL | llp; 1410 p->thread.ksp_vsid = sp_vsid; 1411 #endif 1412 } 1413 1414 /* 1415 * Copy a thread.. 1416 */ 1417 1418 /* 1419 * Copy architecture-specific thread state 1420 */ 1421 int copy_thread(unsigned long clone_flags, unsigned long usp, 1422 unsigned long kthread_arg, struct task_struct *p) 1423 { 1424 struct pt_regs *childregs, *kregs; 1425 extern void ret_from_fork(void); 1426 extern void ret_from_kernel_thread(void); 1427 void (*f)(void); 1428 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1429 struct thread_info *ti = task_thread_info(p); 1430 1431 klp_init_thread_info(ti); 1432 1433 /* Copy registers */ 1434 sp -= sizeof(struct pt_regs); 1435 childregs = (struct pt_regs *) sp; 1436 if (unlikely(p->flags & PF_KTHREAD)) { 1437 /* kernel thread */ 1438 memset(childregs, 0, sizeof(struct pt_regs)); 1439 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1440 /* function */ 1441 if (usp) 1442 childregs->gpr[14] = ppc_function_entry((void *)usp); 1443 #ifdef CONFIG_PPC64 1444 clear_tsk_thread_flag(p, TIF_32BIT); 1445 childregs->softe = 1; 1446 #endif 1447 childregs->gpr[15] = kthread_arg; 1448 p->thread.regs = NULL; /* no user register state */ 1449 ti->flags |= _TIF_RESTOREALL; 1450 f = ret_from_kernel_thread; 1451 } else { 1452 /* user thread */ 1453 struct pt_regs *regs = current_pt_regs(); 1454 CHECK_FULL_REGS(regs); 1455 *childregs = *regs; 1456 if (usp) 1457 childregs->gpr[1] = usp; 1458 p->thread.regs = childregs; 1459 childregs->gpr[3] = 0; /* Result from fork() */ 1460 if (clone_flags & CLONE_SETTLS) { 1461 #ifdef CONFIG_PPC64 1462 if (!is_32bit_task()) 1463 childregs->gpr[13] = childregs->gpr[6]; 1464 else 1465 #endif 1466 childregs->gpr[2] = childregs->gpr[6]; 1467 } 1468 1469 f = ret_from_fork; 1470 } 1471 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); 1472 sp -= STACK_FRAME_OVERHEAD; 1473 1474 /* 1475 * The way this works is that at some point in the future 1476 * some task will call _switch to switch to the new task. 1477 * That will pop off the stack frame created below and start 1478 * the new task running at ret_from_fork. The new task will 1479 * do some house keeping and then return from the fork or clone 1480 * system call, using the stack frame created above. 1481 */ 1482 ((unsigned long *)sp)[0] = 0; 1483 sp -= sizeof(struct pt_regs); 1484 kregs = (struct pt_regs *) sp; 1485 sp -= STACK_FRAME_OVERHEAD; 1486 p->thread.ksp = sp; 1487 #ifdef CONFIG_PPC32 1488 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1489 _ALIGN_UP(sizeof(struct thread_info), 16); 1490 #endif 1491 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1492 p->thread.ptrace_bps[0] = NULL; 1493 #endif 1494 1495 p->thread.fp_save_area = NULL; 1496 #ifdef CONFIG_ALTIVEC 1497 p->thread.vr_save_area = NULL; 1498 #endif 1499 1500 setup_ksp_vsid(p, sp); 1501 1502 #ifdef CONFIG_PPC64 1503 if (cpu_has_feature(CPU_FTR_DSCR)) { 1504 p->thread.dscr_inherit = current->thread.dscr_inherit; 1505 p->thread.dscr = mfspr(SPRN_DSCR); 1506 } 1507 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1508 p->thread.ppr = INIT_PPR; 1509 #endif 1510 kregs->nip = ppc_function_entry(f); 1511 return 0; 1512 } 1513 1514 /* 1515 * Set up a thread for executing a new program 1516 */ 1517 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1518 { 1519 #ifdef CONFIG_PPC64 1520 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1521 #endif 1522 1523 /* 1524 * If we exec out of a kernel thread then thread.regs will not be 1525 * set. Do it now. 1526 */ 1527 if (!current->thread.regs) { 1528 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1529 current->thread.regs = regs - 1; 1530 } 1531 1532 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1533 /* 1534 * Clear any transactional state, we're exec()ing. The cause is 1535 * not important as there will never be a recheckpoint so it's not 1536 * user visible. 1537 */ 1538 if (MSR_TM_SUSPENDED(mfmsr())) 1539 tm_reclaim_current(0); 1540 #endif 1541 1542 memset(regs->gpr, 0, sizeof(regs->gpr)); 1543 regs->ctr = 0; 1544 regs->link = 0; 1545 regs->xer = 0; 1546 regs->ccr = 0; 1547 regs->gpr[1] = sp; 1548 1549 /* 1550 * We have just cleared all the nonvolatile GPRs, so make 1551 * FULL_REGS(regs) return true. This is necessary to allow 1552 * ptrace to examine the thread immediately after exec. 1553 */ 1554 regs->trap &= ~1UL; 1555 1556 #ifdef CONFIG_PPC32 1557 regs->mq = 0; 1558 regs->nip = start; 1559 regs->msr = MSR_USER; 1560 #else 1561 if (!is_32bit_task()) { 1562 unsigned long entry; 1563 1564 if (is_elf2_task()) { 1565 /* Look ma, no function descriptors! */ 1566 entry = start; 1567 1568 /* 1569 * Ulrich says: 1570 * The latest iteration of the ABI requires that when 1571 * calling a function (at its global entry point), 1572 * the caller must ensure r12 holds the entry point 1573 * address (so that the function can quickly 1574 * establish addressability). 1575 */ 1576 regs->gpr[12] = start; 1577 /* Make sure that's restored on entry to userspace. */ 1578 set_thread_flag(TIF_RESTOREALL); 1579 } else { 1580 unsigned long toc; 1581 1582 /* start is a relocated pointer to the function 1583 * descriptor for the elf _start routine. The first 1584 * entry in the function descriptor is the entry 1585 * address of _start and the second entry is the TOC 1586 * value we need to use. 1587 */ 1588 __get_user(entry, (unsigned long __user *)start); 1589 __get_user(toc, (unsigned long __user *)start+1); 1590 1591 /* Check whether the e_entry function descriptor entries 1592 * need to be relocated before we can use them. 1593 */ 1594 if (load_addr != 0) { 1595 entry += load_addr; 1596 toc += load_addr; 1597 } 1598 regs->gpr[2] = toc; 1599 } 1600 regs->nip = entry; 1601 regs->msr = MSR_USER64; 1602 } else { 1603 regs->nip = start; 1604 regs->gpr[2] = 0; 1605 regs->msr = MSR_USER32; 1606 } 1607 #endif 1608 #ifdef CONFIG_VSX 1609 current->thread.used_vsr = 0; 1610 #endif 1611 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1612 current->thread.fp_save_area = NULL; 1613 #ifdef CONFIG_ALTIVEC 1614 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1615 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1616 current->thread.vr_save_area = NULL; 1617 current->thread.vrsave = 0; 1618 current->thread.used_vr = 0; 1619 #endif /* CONFIG_ALTIVEC */ 1620 #ifdef CONFIG_SPE 1621 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1622 current->thread.acc = 0; 1623 current->thread.spefscr = 0; 1624 current->thread.used_spe = 0; 1625 #endif /* CONFIG_SPE */ 1626 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1627 if (cpu_has_feature(CPU_FTR_TM)) 1628 regs->msr |= MSR_TM; 1629 current->thread.tm_tfhar = 0; 1630 current->thread.tm_texasr = 0; 1631 current->thread.tm_tfiar = 0; 1632 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1633 } 1634 EXPORT_SYMBOL(start_thread); 1635 1636 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1637 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1638 1639 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1640 { 1641 struct pt_regs *regs = tsk->thread.regs; 1642 1643 /* This is a bit hairy. If we are an SPE enabled processor 1644 * (have embedded fp) we store the IEEE exception enable flags in 1645 * fpexc_mode. fpexc_mode is also used for setting FP exception 1646 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1647 if (val & PR_FP_EXC_SW_ENABLE) { 1648 #ifdef CONFIG_SPE 1649 if (cpu_has_feature(CPU_FTR_SPE)) { 1650 /* 1651 * When the sticky exception bits are set 1652 * directly by userspace, it must call prctl 1653 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1654 * in the existing prctl settings) or 1655 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1656 * the bits being set). <fenv.h> functions 1657 * saving and restoring the whole 1658 * floating-point environment need to do so 1659 * anyway to restore the prctl settings from 1660 * the saved environment. 1661 */ 1662 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1663 tsk->thread.fpexc_mode = val & 1664 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1665 return 0; 1666 } else { 1667 return -EINVAL; 1668 } 1669 #else 1670 return -EINVAL; 1671 #endif 1672 } 1673 1674 /* on a CONFIG_SPE this does not hurt us. The bits that 1675 * __pack_fe01 use do not overlap with bits used for 1676 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1677 * on CONFIG_SPE implementations are reserved so writing to 1678 * them does not change anything */ 1679 if (val > PR_FP_EXC_PRECISE) 1680 return -EINVAL; 1681 tsk->thread.fpexc_mode = __pack_fe01(val); 1682 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1683 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1684 | tsk->thread.fpexc_mode; 1685 return 0; 1686 } 1687 1688 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1689 { 1690 unsigned int val; 1691 1692 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1693 #ifdef CONFIG_SPE 1694 if (cpu_has_feature(CPU_FTR_SPE)) { 1695 /* 1696 * When the sticky exception bits are set 1697 * directly by userspace, it must call prctl 1698 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1699 * in the existing prctl settings) or 1700 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1701 * the bits being set). <fenv.h> functions 1702 * saving and restoring the whole 1703 * floating-point environment need to do so 1704 * anyway to restore the prctl settings from 1705 * the saved environment. 1706 */ 1707 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1708 val = tsk->thread.fpexc_mode; 1709 } else 1710 return -EINVAL; 1711 #else 1712 return -EINVAL; 1713 #endif 1714 else 1715 val = __unpack_fe01(tsk->thread.fpexc_mode); 1716 return put_user(val, (unsigned int __user *) adr); 1717 } 1718 1719 int set_endian(struct task_struct *tsk, unsigned int val) 1720 { 1721 struct pt_regs *regs = tsk->thread.regs; 1722 1723 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1724 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1725 return -EINVAL; 1726 1727 if (regs == NULL) 1728 return -EINVAL; 1729 1730 if (val == PR_ENDIAN_BIG) 1731 regs->msr &= ~MSR_LE; 1732 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1733 regs->msr |= MSR_LE; 1734 else 1735 return -EINVAL; 1736 1737 return 0; 1738 } 1739 1740 int get_endian(struct task_struct *tsk, unsigned long adr) 1741 { 1742 struct pt_regs *regs = tsk->thread.regs; 1743 unsigned int val; 1744 1745 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1746 !cpu_has_feature(CPU_FTR_REAL_LE)) 1747 return -EINVAL; 1748 1749 if (regs == NULL) 1750 return -EINVAL; 1751 1752 if (regs->msr & MSR_LE) { 1753 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1754 val = PR_ENDIAN_LITTLE; 1755 else 1756 val = PR_ENDIAN_PPC_LITTLE; 1757 } else 1758 val = PR_ENDIAN_BIG; 1759 1760 return put_user(val, (unsigned int __user *)adr); 1761 } 1762 1763 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1764 { 1765 tsk->thread.align_ctl = val; 1766 return 0; 1767 } 1768 1769 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1770 { 1771 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1772 } 1773 1774 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1775 unsigned long nbytes) 1776 { 1777 unsigned long stack_page; 1778 unsigned long cpu = task_cpu(p); 1779 1780 /* 1781 * Avoid crashing if the stack has overflowed and corrupted 1782 * task_cpu(p), which is in the thread_info struct. 1783 */ 1784 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1785 stack_page = (unsigned long) hardirq_ctx[cpu]; 1786 if (sp >= stack_page + sizeof(struct thread_struct) 1787 && sp <= stack_page + THREAD_SIZE - nbytes) 1788 return 1; 1789 1790 stack_page = (unsigned long) softirq_ctx[cpu]; 1791 if (sp >= stack_page + sizeof(struct thread_struct) 1792 && sp <= stack_page + THREAD_SIZE - nbytes) 1793 return 1; 1794 } 1795 return 0; 1796 } 1797 1798 int validate_sp(unsigned long sp, struct task_struct *p, 1799 unsigned long nbytes) 1800 { 1801 unsigned long stack_page = (unsigned long)task_stack_page(p); 1802 1803 if (sp >= stack_page + sizeof(struct thread_struct) 1804 && sp <= stack_page + THREAD_SIZE - nbytes) 1805 return 1; 1806 1807 return valid_irq_stack(sp, p, nbytes); 1808 } 1809 1810 EXPORT_SYMBOL(validate_sp); 1811 1812 unsigned long get_wchan(struct task_struct *p) 1813 { 1814 unsigned long ip, sp; 1815 int count = 0; 1816 1817 if (!p || p == current || p->state == TASK_RUNNING) 1818 return 0; 1819 1820 sp = p->thread.ksp; 1821 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1822 return 0; 1823 1824 do { 1825 sp = *(unsigned long *)sp; 1826 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1827 return 0; 1828 if (count > 0) { 1829 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1830 if (!in_sched_functions(ip)) 1831 return ip; 1832 } 1833 } while (count++ < 16); 1834 return 0; 1835 } 1836 1837 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1838 1839 void show_stack(struct task_struct *tsk, unsigned long *stack) 1840 { 1841 unsigned long sp, ip, lr, newsp; 1842 int count = 0; 1843 int firstframe = 1; 1844 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1845 int curr_frame = current->curr_ret_stack; 1846 extern void return_to_handler(void); 1847 unsigned long rth = (unsigned long)return_to_handler; 1848 #endif 1849 1850 sp = (unsigned long) stack; 1851 if (tsk == NULL) 1852 tsk = current; 1853 if (sp == 0) { 1854 if (tsk == current) 1855 sp = current_stack_pointer(); 1856 else 1857 sp = tsk->thread.ksp; 1858 } 1859 1860 lr = 0; 1861 printk("Call Trace:\n"); 1862 do { 1863 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1864 return; 1865 1866 stack = (unsigned long *) sp; 1867 newsp = stack[0]; 1868 ip = stack[STACK_FRAME_LR_SAVE]; 1869 if (!firstframe || ip != lr) { 1870 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1871 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1872 if ((ip == rth) && curr_frame >= 0) { 1873 printk(" (%pS)", 1874 (void *)current->ret_stack[curr_frame].ret); 1875 curr_frame--; 1876 } 1877 #endif 1878 if (firstframe) 1879 printk(" (unreliable)"); 1880 printk("\n"); 1881 } 1882 firstframe = 0; 1883 1884 /* 1885 * See if this is an exception frame. 1886 * We look for the "regshere" marker in the current frame. 1887 */ 1888 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1889 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1890 struct pt_regs *regs = (struct pt_regs *) 1891 (sp + STACK_FRAME_OVERHEAD); 1892 lr = regs->link; 1893 printk("--- interrupt: %lx at %pS\n LR = %pS\n", 1894 regs->trap, (void *)regs->nip, (void *)lr); 1895 firstframe = 1; 1896 } 1897 1898 sp = newsp; 1899 } while (count++ < kstack_depth_to_print); 1900 } 1901 1902 #ifdef CONFIG_PPC64 1903 /* Called with hard IRQs off */ 1904 void notrace __ppc64_runlatch_on(void) 1905 { 1906 struct thread_info *ti = current_thread_info(); 1907 unsigned long ctrl; 1908 1909 ctrl = mfspr(SPRN_CTRLF); 1910 ctrl |= CTRL_RUNLATCH; 1911 mtspr(SPRN_CTRLT, ctrl); 1912 1913 ti->local_flags |= _TLF_RUNLATCH; 1914 } 1915 1916 /* Called with hard IRQs off */ 1917 void notrace __ppc64_runlatch_off(void) 1918 { 1919 struct thread_info *ti = current_thread_info(); 1920 unsigned long ctrl; 1921 1922 ti->local_flags &= ~_TLF_RUNLATCH; 1923 1924 ctrl = mfspr(SPRN_CTRLF); 1925 ctrl &= ~CTRL_RUNLATCH; 1926 mtspr(SPRN_CTRLT, ctrl); 1927 } 1928 #endif /* CONFIG_PPC64 */ 1929 1930 unsigned long arch_align_stack(unsigned long sp) 1931 { 1932 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1933 sp -= get_random_int() & ~PAGE_MASK; 1934 return sp & ~0xf; 1935 } 1936 1937 static inline unsigned long brk_rnd(void) 1938 { 1939 unsigned long rnd = 0; 1940 1941 /* 8MB for 32bit, 1GB for 64bit */ 1942 if (is_32bit_task()) 1943 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); 1944 else 1945 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); 1946 1947 return rnd << PAGE_SHIFT; 1948 } 1949 1950 unsigned long arch_randomize_brk(struct mm_struct *mm) 1951 { 1952 unsigned long base = mm->brk; 1953 unsigned long ret; 1954 1955 #ifdef CONFIG_PPC_STD_MMU_64 1956 /* 1957 * If we are using 1TB segments and we are allowed to randomise 1958 * the heap, we can put it above 1TB so it is backed by a 1TB 1959 * segment. Otherwise the heap will be in the bottom 1TB 1960 * which always uses 256MB segments and this may result in a 1961 * performance penalty. We don't need to worry about radix. For 1962 * radix, mmu_highuser_ssize remains unchanged from 256MB. 1963 */ 1964 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1965 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1966 #endif 1967 1968 ret = PAGE_ALIGN(base + brk_rnd()); 1969 1970 if (ret < mm->brk) 1971 return mm->brk; 1972 1973 return ret; 1974 } 1975 1976