1 /* 2 * Derived from "arch/i386/kernel/process.c" 3 * Copyright (C) 1995 Linus Torvalds 4 * 5 * Updated and modified by Cort Dougan ([email protected]) and 6 * Paul Mackerras ([email protected]) 7 * 8 * PowerPC version 9 * Copyright (C) 1995-1996 Gary Thomas ([email protected]) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/elf.h> 28 #include <linux/prctl.h> 29 #include <linux/init_task.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/mqueue.h> 33 #include <linux/hardirq.h> 34 #include <linux/utsname.h> 35 #include <linux/ftrace.h> 36 #include <linux/kernel_stat.h> 37 #include <linux/personality.h> 38 #include <linux/random.h> 39 #include <linux/hw_breakpoint.h> 40 41 #include <asm/pgtable.h> 42 #include <asm/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/processor.h> 45 #include <asm/mmu.h> 46 #include <asm/prom.h> 47 #include <asm/machdep.h> 48 #include <asm/time.h> 49 #include <asm/runlatch.h> 50 #include <asm/syscalls.h> 51 #include <asm/switch_to.h> 52 #include <asm/tm.h> 53 #include <asm/debug.h> 54 #ifdef CONFIG_PPC64 55 #include <asm/firmware.h> 56 #endif 57 #include <asm/code-patching.h> 58 #include <linux/kprobes.h> 59 #include <linux/kdebug.h> 60 61 /* Transactional Memory debug */ 62 #ifdef TM_DEBUG_SW 63 #define TM_DEBUG(x...) printk(KERN_INFO x) 64 #else 65 #define TM_DEBUG(x...) do { } while(0) 66 #endif 67 68 extern unsigned long _get_SP(void); 69 70 #ifndef CONFIG_SMP 71 struct task_struct *last_task_used_math = NULL; 72 struct task_struct *last_task_used_altivec = NULL; 73 struct task_struct *last_task_used_vsx = NULL; 74 struct task_struct *last_task_used_spe = NULL; 75 #endif 76 77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 78 void giveup_fpu_maybe_transactional(struct task_struct *tsk) 79 { 80 /* 81 * If we are saving the current thread's registers, and the 82 * thread is in a transactional state, set the TIF_RESTORE_TM 83 * bit so that we know to restore the registers before 84 * returning to userspace. 85 */ 86 if (tsk == current && tsk->thread.regs && 87 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 88 !test_thread_flag(TIF_RESTORE_TM)) { 89 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 90 set_thread_flag(TIF_RESTORE_TM); 91 } 92 93 giveup_fpu(tsk); 94 } 95 96 void giveup_altivec_maybe_transactional(struct task_struct *tsk) 97 { 98 /* 99 * If we are saving the current thread's registers, and the 100 * thread is in a transactional state, set the TIF_RESTORE_TM 101 * bit so that we know to restore the registers before 102 * returning to userspace. 103 */ 104 if (tsk == current && tsk->thread.regs && 105 MSR_TM_ACTIVE(tsk->thread.regs->msr) && 106 !test_thread_flag(TIF_RESTORE_TM)) { 107 tsk->thread.tm_orig_msr = tsk->thread.regs->msr; 108 set_thread_flag(TIF_RESTORE_TM); 109 } 110 111 giveup_altivec(tsk); 112 } 113 114 #else 115 #define giveup_fpu_maybe_transactional(tsk) giveup_fpu(tsk) 116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk) 117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 118 119 #ifdef CONFIG_PPC_FPU 120 /* 121 * Make sure the floating-point register state in the 122 * the thread_struct is up to date for task tsk. 123 */ 124 void flush_fp_to_thread(struct task_struct *tsk) 125 { 126 if (tsk->thread.regs) { 127 /* 128 * We need to disable preemption here because if we didn't, 129 * another process could get scheduled after the regs->msr 130 * test but before we have finished saving the FP registers 131 * to the thread_struct. That process could take over the 132 * FPU, and then when we get scheduled again we would store 133 * bogus values for the remaining FP registers. 134 */ 135 preempt_disable(); 136 if (tsk->thread.regs->msr & MSR_FP) { 137 #ifdef CONFIG_SMP 138 /* 139 * This should only ever be called for current or 140 * for a stopped child process. Since we save away 141 * the FP register state on context switch on SMP, 142 * there is something wrong if a stopped child appears 143 * to still have its FP state in the CPU registers. 144 */ 145 BUG_ON(tsk != current); 146 #endif 147 giveup_fpu_maybe_transactional(tsk); 148 } 149 preempt_enable(); 150 } 151 } 152 EXPORT_SYMBOL_GPL(flush_fp_to_thread); 153 #endif /* CONFIG_PPC_FPU */ 154 155 void enable_kernel_fp(void) 156 { 157 WARN_ON(preemptible()); 158 159 #ifdef CONFIG_SMP 160 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) 161 giveup_fpu_maybe_transactional(current); 162 else 163 giveup_fpu(NULL); /* just enables FP for kernel */ 164 #else 165 giveup_fpu_maybe_transactional(last_task_used_math); 166 #endif /* CONFIG_SMP */ 167 } 168 EXPORT_SYMBOL(enable_kernel_fp); 169 170 #ifdef CONFIG_ALTIVEC 171 void enable_kernel_altivec(void) 172 { 173 WARN_ON(preemptible()); 174 175 #ifdef CONFIG_SMP 176 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) 177 giveup_altivec_maybe_transactional(current); 178 else 179 giveup_altivec_notask(); 180 #else 181 giveup_altivec_maybe_transactional(last_task_used_altivec); 182 #endif /* CONFIG_SMP */ 183 } 184 EXPORT_SYMBOL(enable_kernel_altivec); 185 186 /* 187 * Make sure the VMX/Altivec register state in the 188 * the thread_struct is up to date for task tsk. 189 */ 190 void flush_altivec_to_thread(struct task_struct *tsk) 191 { 192 if (tsk->thread.regs) { 193 preempt_disable(); 194 if (tsk->thread.regs->msr & MSR_VEC) { 195 #ifdef CONFIG_SMP 196 BUG_ON(tsk != current); 197 #endif 198 giveup_altivec_maybe_transactional(tsk); 199 } 200 preempt_enable(); 201 } 202 } 203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread); 204 #endif /* CONFIG_ALTIVEC */ 205 206 #ifdef CONFIG_VSX 207 #if 0 208 /* not currently used, but some crazy RAID module might want to later */ 209 void enable_kernel_vsx(void) 210 { 211 WARN_ON(preemptible()); 212 213 #ifdef CONFIG_SMP 214 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) 215 giveup_vsx(current); 216 else 217 giveup_vsx(NULL); /* just enable vsx for kernel - force */ 218 #else 219 giveup_vsx(last_task_used_vsx); 220 #endif /* CONFIG_SMP */ 221 } 222 EXPORT_SYMBOL(enable_kernel_vsx); 223 #endif 224 225 void giveup_vsx(struct task_struct *tsk) 226 { 227 giveup_fpu_maybe_transactional(tsk); 228 giveup_altivec_maybe_transactional(tsk); 229 __giveup_vsx(tsk); 230 } 231 232 void flush_vsx_to_thread(struct task_struct *tsk) 233 { 234 if (tsk->thread.regs) { 235 preempt_disable(); 236 if (tsk->thread.regs->msr & MSR_VSX) { 237 #ifdef CONFIG_SMP 238 BUG_ON(tsk != current); 239 #endif 240 giveup_vsx(tsk); 241 } 242 preempt_enable(); 243 } 244 } 245 EXPORT_SYMBOL_GPL(flush_vsx_to_thread); 246 #endif /* CONFIG_VSX */ 247 248 #ifdef CONFIG_SPE 249 250 void enable_kernel_spe(void) 251 { 252 WARN_ON(preemptible()); 253 254 #ifdef CONFIG_SMP 255 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) 256 giveup_spe(current); 257 else 258 giveup_spe(NULL); /* just enable SPE for kernel - force */ 259 #else 260 giveup_spe(last_task_used_spe); 261 #endif /* __SMP __ */ 262 } 263 EXPORT_SYMBOL(enable_kernel_spe); 264 265 void flush_spe_to_thread(struct task_struct *tsk) 266 { 267 if (tsk->thread.regs) { 268 preempt_disable(); 269 if (tsk->thread.regs->msr & MSR_SPE) { 270 #ifdef CONFIG_SMP 271 BUG_ON(tsk != current); 272 #endif 273 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 274 giveup_spe(tsk); 275 } 276 preempt_enable(); 277 } 278 } 279 #endif /* CONFIG_SPE */ 280 281 #ifndef CONFIG_SMP 282 /* 283 * If we are doing lazy switching of CPU state (FP, altivec or SPE), 284 * and the current task has some state, discard it. 285 */ 286 void discard_lazy_cpu_state(void) 287 { 288 preempt_disable(); 289 if (last_task_used_math == current) 290 last_task_used_math = NULL; 291 #ifdef CONFIG_ALTIVEC 292 if (last_task_used_altivec == current) 293 last_task_used_altivec = NULL; 294 #endif /* CONFIG_ALTIVEC */ 295 #ifdef CONFIG_VSX 296 if (last_task_used_vsx == current) 297 last_task_used_vsx = NULL; 298 #endif /* CONFIG_VSX */ 299 #ifdef CONFIG_SPE 300 if (last_task_used_spe == current) 301 last_task_used_spe = NULL; 302 #endif 303 preempt_enable(); 304 } 305 #endif /* CONFIG_SMP */ 306 307 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 308 void do_send_trap(struct pt_regs *regs, unsigned long address, 309 unsigned long error_code, int signal_code, int breakpt) 310 { 311 siginfo_t info; 312 313 current->thread.trap_nr = signal_code; 314 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 315 11, SIGSEGV) == NOTIFY_STOP) 316 return; 317 318 /* Deliver the signal to userspace */ 319 info.si_signo = SIGTRAP; 320 info.si_errno = breakpt; /* breakpoint or watchpoint id */ 321 info.si_code = signal_code; 322 info.si_addr = (void __user *)address; 323 force_sig_info(SIGTRAP, &info, current); 324 } 325 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 326 void do_break (struct pt_regs *regs, unsigned long address, 327 unsigned long error_code) 328 { 329 siginfo_t info; 330 331 current->thread.trap_nr = TRAP_HWBKPT; 332 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 333 11, SIGSEGV) == NOTIFY_STOP) 334 return; 335 336 if (debugger_break_match(regs)) 337 return; 338 339 /* Clear the breakpoint */ 340 hw_breakpoint_disable(); 341 342 /* Deliver the signal to userspace */ 343 info.si_signo = SIGTRAP; 344 info.si_errno = 0; 345 info.si_code = TRAP_HWBKPT; 346 info.si_addr = (void __user *)address; 347 force_sig_info(SIGTRAP, &info, current); 348 } 349 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 350 351 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); 352 353 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 354 /* 355 * Set the debug registers back to their default "safe" values. 356 */ 357 static void set_debug_reg_defaults(struct thread_struct *thread) 358 { 359 thread->debug.iac1 = thread->debug.iac2 = 0; 360 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 361 thread->debug.iac3 = thread->debug.iac4 = 0; 362 #endif 363 thread->debug.dac1 = thread->debug.dac2 = 0; 364 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 365 thread->debug.dvc1 = thread->debug.dvc2 = 0; 366 #endif 367 thread->debug.dbcr0 = 0; 368 #ifdef CONFIG_BOOKE 369 /* 370 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 371 */ 372 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | 373 DBCR1_IAC3US | DBCR1_IAC4US; 374 /* 375 * Force Data Address Compare User/Supervisor bits to be User-only 376 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 377 */ 378 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 379 #else 380 thread->debug.dbcr1 = 0; 381 #endif 382 } 383 384 static void prime_debug_regs(struct debug_reg *debug) 385 { 386 /* 387 * We could have inherited MSR_DE from userspace, since 388 * it doesn't get cleared on exception entry. Make sure 389 * MSR_DE is clear before we enable any debug events. 390 */ 391 mtmsr(mfmsr() & ~MSR_DE); 392 393 mtspr(SPRN_IAC1, debug->iac1); 394 mtspr(SPRN_IAC2, debug->iac2); 395 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 396 mtspr(SPRN_IAC3, debug->iac3); 397 mtspr(SPRN_IAC4, debug->iac4); 398 #endif 399 mtspr(SPRN_DAC1, debug->dac1); 400 mtspr(SPRN_DAC2, debug->dac2); 401 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 402 mtspr(SPRN_DVC1, debug->dvc1); 403 mtspr(SPRN_DVC2, debug->dvc2); 404 #endif 405 mtspr(SPRN_DBCR0, debug->dbcr0); 406 mtspr(SPRN_DBCR1, debug->dbcr1); 407 #ifdef CONFIG_BOOKE 408 mtspr(SPRN_DBCR2, debug->dbcr2); 409 #endif 410 } 411 /* 412 * Unless neither the old or new thread are making use of the 413 * debug registers, set the debug registers from the values 414 * stored in the new thread. 415 */ 416 void switch_booke_debug_regs(struct debug_reg *new_debug) 417 { 418 if ((current->thread.debug.dbcr0 & DBCR0_IDM) 419 || (new_debug->dbcr0 & DBCR0_IDM)) 420 prime_debug_regs(new_debug); 421 } 422 EXPORT_SYMBOL_GPL(switch_booke_debug_regs); 423 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 424 #ifndef CONFIG_HAVE_HW_BREAKPOINT 425 static void set_debug_reg_defaults(struct thread_struct *thread) 426 { 427 thread->hw_brk.address = 0; 428 thread->hw_brk.type = 0; 429 set_breakpoint(&thread->hw_brk); 430 } 431 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ 432 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 433 434 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 435 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 436 { 437 mtspr(SPRN_DAC1, dabr); 438 #ifdef CONFIG_PPC_47x 439 isync(); 440 #endif 441 return 0; 442 } 443 #elif defined(CONFIG_PPC_BOOK3S) 444 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 445 { 446 mtspr(SPRN_DABR, dabr); 447 if (cpu_has_feature(CPU_FTR_DABRX)) 448 mtspr(SPRN_DABRX, dabrx); 449 return 0; 450 } 451 #else 452 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 453 { 454 return -EINVAL; 455 } 456 #endif 457 458 static inline int set_dabr(struct arch_hw_breakpoint *brk) 459 { 460 unsigned long dabr, dabrx; 461 462 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); 463 dabrx = ((brk->type >> 3) & 0x7); 464 465 if (ppc_md.set_dabr) 466 return ppc_md.set_dabr(dabr, dabrx); 467 468 return __set_dabr(dabr, dabrx); 469 } 470 471 static inline int set_dawr(struct arch_hw_breakpoint *brk) 472 { 473 unsigned long dawr, dawrx, mrd; 474 475 dawr = brk->address; 476 477 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ 478 << (63 - 58); //* read/write bits */ 479 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ 480 << (63 - 59); //* translate */ 481 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ 482 >> 3; //* PRIM bits */ 483 /* dawr length is stored in field MDR bits 48:53. Matches range in 484 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and 485 0b111111=64DW. 486 brk->len is in bytes. 487 This aligns up to double word size, shifts and does the bias. 488 */ 489 mrd = ((brk->len + 7) >> 3) - 1; 490 dawrx |= (mrd & 0x3f) << (63 - 53); 491 492 if (ppc_md.set_dawr) 493 return ppc_md.set_dawr(dawr, dawrx); 494 mtspr(SPRN_DAWR, dawr); 495 mtspr(SPRN_DAWRX, dawrx); 496 return 0; 497 } 498 499 int set_breakpoint(struct arch_hw_breakpoint *brk) 500 { 501 __get_cpu_var(current_brk) = *brk; 502 503 if (cpu_has_feature(CPU_FTR_DAWR)) 504 return set_dawr(brk); 505 506 return set_dabr(brk); 507 } 508 509 #ifdef CONFIG_PPC64 510 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 511 #endif 512 513 static inline bool hw_brk_match(struct arch_hw_breakpoint *a, 514 struct arch_hw_breakpoint *b) 515 { 516 if (a->address != b->address) 517 return false; 518 if (a->type != b->type) 519 return false; 520 if (a->len != b->len) 521 return false; 522 return true; 523 } 524 525 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 526 static void tm_reclaim_thread(struct thread_struct *thr, 527 struct thread_info *ti, uint8_t cause) 528 { 529 unsigned long msr_diff = 0; 530 531 /* 532 * If FP/VSX registers have been already saved to the 533 * thread_struct, move them to the transact_fp array. 534 * We clear the TIF_RESTORE_TM bit since after the reclaim 535 * the thread will no longer be transactional. 536 */ 537 if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { 538 msr_diff = thr->tm_orig_msr & ~thr->regs->msr; 539 if (msr_diff & MSR_FP) 540 memcpy(&thr->transact_fp, &thr->fp_state, 541 sizeof(struct thread_fp_state)); 542 if (msr_diff & MSR_VEC) 543 memcpy(&thr->transact_vr, &thr->vr_state, 544 sizeof(struct thread_vr_state)); 545 clear_ti_thread_flag(ti, TIF_RESTORE_TM); 546 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; 547 } 548 549 tm_reclaim(thr, thr->regs->msr, cause); 550 551 /* Having done the reclaim, we now have the checkpointed 552 * FP/VSX values in the registers. These might be valid 553 * even if we have previously called enable_kernel_fp() or 554 * flush_fp_to_thread(), so update thr->regs->msr to 555 * indicate their current validity. 556 */ 557 thr->regs->msr |= msr_diff; 558 } 559 560 void tm_reclaim_current(uint8_t cause) 561 { 562 tm_enable(); 563 tm_reclaim_thread(¤t->thread, current_thread_info(), cause); 564 } 565 566 static inline void tm_reclaim_task(struct task_struct *tsk) 567 { 568 /* We have to work out if we're switching from/to a task that's in the 569 * middle of a transaction. 570 * 571 * In switching we need to maintain a 2nd register state as 572 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the 573 * checkpointed (tbegin) state in ckpt_regs and saves the transactional 574 * (current) FPRs into oldtask->thread.transact_fpr[]. 575 * 576 * We also context switch (save) TFHAR/TEXASR/TFIAR in here. 577 */ 578 struct thread_struct *thr = &tsk->thread; 579 580 if (!thr->regs) 581 return; 582 583 if (!MSR_TM_ACTIVE(thr->regs->msr)) 584 goto out_and_saveregs; 585 586 /* Stash the original thread MSR, as giveup_fpu et al will 587 * modify it. We hold onto it to see whether the task used 588 * FP & vector regs. If the TIF_RESTORE_TM flag is set, 589 * tm_orig_msr is already set. 590 */ 591 if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) 592 thr->tm_orig_msr = thr->regs->msr; 593 594 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " 595 "ccr=%lx, msr=%lx, trap=%lx)\n", 596 tsk->pid, thr->regs->nip, 597 thr->regs->ccr, thr->regs->msr, 598 thr->regs->trap); 599 600 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); 601 602 TM_DEBUG("--- tm_reclaim on pid %d complete\n", 603 tsk->pid); 604 605 out_and_saveregs: 606 /* Always save the regs here, even if a transaction's not active. 607 * This context-switches a thread's TM info SPRs. We do it here to 608 * be consistent with the restore path (in recheckpoint) which 609 * cannot happen later in _switch(). 610 */ 611 tm_save_sprs(thr); 612 } 613 614 extern void __tm_recheckpoint(struct thread_struct *thread, 615 unsigned long orig_msr); 616 617 void tm_recheckpoint(struct thread_struct *thread, 618 unsigned long orig_msr) 619 { 620 unsigned long flags; 621 622 /* We really can't be interrupted here as the TEXASR registers can't 623 * change and later in the trecheckpoint code, we have a userspace R1. 624 * So let's hard disable over this region. 625 */ 626 local_irq_save(flags); 627 hard_irq_disable(); 628 629 /* The TM SPRs are restored here, so that TEXASR.FS can be set 630 * before the trecheckpoint and no explosion occurs. 631 */ 632 tm_restore_sprs(thread); 633 634 __tm_recheckpoint(thread, orig_msr); 635 636 local_irq_restore(flags); 637 } 638 639 static inline void tm_recheckpoint_new_task(struct task_struct *new) 640 { 641 unsigned long msr; 642 643 if (!cpu_has_feature(CPU_FTR_TM)) 644 return; 645 646 /* Recheckpoint the registers of the thread we're about to switch to. 647 * 648 * If the task was using FP, we non-lazily reload both the original and 649 * the speculative FP register states. This is because the kernel 650 * doesn't see if/when a TM rollback occurs, so if we take an FP 651 * unavoidable later, we are unable to determine which set of FP regs 652 * need to be restored. 653 */ 654 if (!new->thread.regs) 655 return; 656 657 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ 658 tm_restore_sprs(&new->thread); 659 return; 660 } 661 msr = new->thread.tm_orig_msr; 662 /* Recheckpoint to restore original checkpointed register state. */ 663 TM_DEBUG("*** tm_recheckpoint of pid %d " 664 "(new->msr 0x%lx, new->origmsr 0x%lx)\n", 665 new->pid, new->thread.regs->msr, msr); 666 667 /* This loads the checkpointed FP/VEC state, if used */ 668 tm_recheckpoint(&new->thread, msr); 669 670 /* This loads the speculative FP/VEC state, if used */ 671 if (msr & MSR_FP) { 672 do_load_up_transact_fpu(&new->thread); 673 new->thread.regs->msr |= 674 (MSR_FP | new->thread.fpexc_mode); 675 } 676 #ifdef CONFIG_ALTIVEC 677 if (msr & MSR_VEC) { 678 do_load_up_transact_altivec(&new->thread); 679 new->thread.regs->msr |= MSR_VEC; 680 } 681 #endif 682 /* We may as well turn on VSX too since all the state is restored now */ 683 if (msr & MSR_VSX) 684 new->thread.regs->msr |= MSR_VSX; 685 686 TM_DEBUG("*** tm_recheckpoint of pid %d complete " 687 "(kernel msr 0x%lx)\n", 688 new->pid, mfmsr()); 689 } 690 691 static inline void __switch_to_tm(struct task_struct *prev) 692 { 693 if (cpu_has_feature(CPU_FTR_TM)) { 694 tm_enable(); 695 tm_reclaim_task(prev); 696 } 697 } 698 699 /* 700 * This is called if we are on the way out to userspace and the 701 * TIF_RESTORE_TM flag is set. It checks if we need to reload 702 * FP and/or vector state and does so if necessary. 703 * If userspace is inside a transaction (whether active or 704 * suspended) and FP/VMX/VSX instructions have ever been enabled 705 * inside that transaction, then we have to keep them enabled 706 * and keep the FP/VMX/VSX state loaded while ever the transaction 707 * continues. The reason is that if we didn't, and subsequently 708 * got a FP/VMX/VSX unavailable interrupt inside a transaction, 709 * we don't know whether it's the same transaction, and thus we 710 * don't know which of the checkpointed state and the transactional 711 * state to use. 712 */ 713 void restore_tm_state(struct pt_regs *regs) 714 { 715 unsigned long msr_diff; 716 717 clear_thread_flag(TIF_RESTORE_TM); 718 if (!MSR_TM_ACTIVE(regs->msr)) 719 return; 720 721 msr_diff = current->thread.tm_orig_msr & ~regs->msr; 722 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; 723 if (msr_diff & MSR_FP) { 724 fp_enable(); 725 load_fp_state(¤t->thread.fp_state); 726 regs->msr |= current->thread.fpexc_mode; 727 } 728 if (msr_diff & MSR_VEC) { 729 vec_enable(); 730 load_vr_state(¤t->thread.vr_state); 731 } 732 regs->msr |= msr_diff; 733 } 734 735 #else 736 #define tm_recheckpoint_new_task(new) 737 #define __switch_to_tm(prev) 738 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 739 740 struct task_struct *__switch_to(struct task_struct *prev, 741 struct task_struct *new) 742 { 743 struct thread_struct *new_thread, *old_thread; 744 struct task_struct *last; 745 #ifdef CONFIG_PPC_BOOK3S_64 746 struct ppc64_tlb_batch *batch; 747 #endif 748 749 WARN_ON(!irqs_disabled()); 750 751 /* Back up the TAR across context switches. 752 * Note that the TAR is not available for use in the kernel. (To 753 * provide this, the TAR should be backed up/restored on exception 754 * entry/exit instead, and be in pt_regs. FIXME, this should be in 755 * pt_regs anyway (for debug).) 756 * Save the TAR here before we do treclaim/trecheckpoint as these 757 * will change the TAR. 758 */ 759 save_tar(&prev->thread); 760 761 __switch_to_tm(prev); 762 763 #ifdef CONFIG_SMP 764 /* avoid complexity of lazy save/restore of fpu 765 * by just saving it every time we switch out if 766 * this task used the fpu during the last quantum. 767 * 768 * If it tries to use the fpu again, it'll trap and 769 * reload its fp regs. So we don't have to do a restore 770 * every switch, just a save. 771 * -- Cort 772 */ 773 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) 774 giveup_fpu(prev); 775 #ifdef CONFIG_ALTIVEC 776 /* 777 * If the previous thread used altivec in the last quantum 778 * (thus changing altivec regs) then save them. 779 * We used to check the VRSAVE register but not all apps 780 * set it, so we don't rely on it now (and in fact we need 781 * to save & restore VSCR even if VRSAVE == 0). -- paulus 782 * 783 * On SMP we always save/restore altivec regs just to avoid the 784 * complexity of changing processors. 785 * -- Cort 786 */ 787 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) 788 giveup_altivec(prev); 789 #endif /* CONFIG_ALTIVEC */ 790 #ifdef CONFIG_VSX 791 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) 792 /* VMX and FPU registers are already save here */ 793 __giveup_vsx(prev); 794 #endif /* CONFIG_VSX */ 795 #ifdef CONFIG_SPE 796 /* 797 * If the previous thread used spe in the last quantum 798 * (thus changing spe regs) then save them. 799 * 800 * On SMP we always save/restore spe regs just to avoid the 801 * complexity of changing processors. 802 */ 803 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) 804 giveup_spe(prev); 805 #endif /* CONFIG_SPE */ 806 807 #else /* CONFIG_SMP */ 808 #ifdef CONFIG_ALTIVEC 809 /* Avoid the trap. On smp this this never happens since 810 * we don't set last_task_used_altivec -- Cort 811 */ 812 if (new->thread.regs && last_task_used_altivec == new) 813 new->thread.regs->msr |= MSR_VEC; 814 #endif /* CONFIG_ALTIVEC */ 815 #ifdef CONFIG_VSX 816 if (new->thread.regs && last_task_used_vsx == new) 817 new->thread.regs->msr |= MSR_VSX; 818 #endif /* CONFIG_VSX */ 819 #ifdef CONFIG_SPE 820 /* Avoid the trap. On smp this this never happens since 821 * we don't set last_task_used_spe 822 */ 823 if (new->thread.regs && last_task_used_spe == new) 824 new->thread.regs->msr |= MSR_SPE; 825 #endif /* CONFIG_SPE */ 826 827 #endif /* CONFIG_SMP */ 828 829 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 830 switch_booke_debug_regs(&new->thread.debug); 831 #else 832 /* 833 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would 834 * schedule DABR 835 */ 836 #ifndef CONFIG_HAVE_HW_BREAKPOINT 837 if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 838 set_breakpoint(&new->thread.hw_brk); 839 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 840 #endif 841 842 843 new_thread = &new->thread; 844 old_thread = ¤t->thread; 845 846 #ifdef CONFIG_PPC64 847 /* 848 * Collect processor utilization data per process 849 */ 850 if (firmware_has_feature(FW_FEATURE_SPLPAR)) { 851 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); 852 long unsigned start_tb, current_tb; 853 start_tb = old_thread->start_tb; 854 cu->current_tb = current_tb = mfspr(SPRN_PURR); 855 old_thread->accum_tb += (current_tb - start_tb); 856 new_thread->start_tb = current_tb; 857 } 858 #endif /* CONFIG_PPC64 */ 859 860 #ifdef CONFIG_PPC_BOOK3S_64 861 batch = &__get_cpu_var(ppc64_tlb_batch); 862 if (batch->active) { 863 current_thread_info()->local_flags |= _TLF_LAZY_MMU; 864 if (batch->index) 865 __flush_tlb_pending(batch); 866 batch->active = 0; 867 } 868 #endif /* CONFIG_PPC_BOOK3S_64 */ 869 870 /* 871 * We can't take a PMU exception inside _switch() since there is a 872 * window where the kernel stack SLB and the kernel stack are out 873 * of sync. Hard disable here. 874 */ 875 hard_irq_disable(); 876 877 tm_recheckpoint_new_task(new); 878 879 last = _switch(old_thread, new_thread); 880 881 #ifdef CONFIG_PPC_BOOK3S_64 882 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { 883 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; 884 batch = &__get_cpu_var(ppc64_tlb_batch); 885 batch->active = 1; 886 } 887 #endif /* CONFIG_PPC_BOOK3S_64 */ 888 889 return last; 890 } 891 892 static int instructions_to_print = 16; 893 894 static void show_instructions(struct pt_regs *regs) 895 { 896 int i; 897 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * 898 sizeof(int)); 899 900 printk("Instruction dump:"); 901 902 for (i = 0; i < instructions_to_print; i++) { 903 int instr; 904 905 if (!(i % 8)) 906 printk("\n"); 907 908 #if !defined(CONFIG_BOOKE) 909 /* If executing with the IMMU off, adjust pc rather 910 * than print XXXXXXXX. 911 */ 912 if (!(regs->msr & MSR_IR)) 913 pc = (unsigned long)phys_to_virt(pc); 914 #endif 915 916 /* We use __get_user here *only* to avoid an OOPS on a 917 * bad address because the pc *should* only be a 918 * kernel address. 919 */ 920 if (!__kernel_text_address(pc) || 921 __get_user(instr, (unsigned int __user *)pc)) { 922 printk(KERN_CONT "XXXXXXXX "); 923 } else { 924 if (regs->nip == pc) 925 printk(KERN_CONT "<%08x> ", instr); 926 else 927 printk(KERN_CONT "%08x ", instr); 928 } 929 930 pc += sizeof(int); 931 } 932 933 printk("\n"); 934 } 935 936 static struct regbit { 937 unsigned long bit; 938 const char *name; 939 } msr_bits[] = { 940 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) 941 {MSR_SF, "SF"}, 942 {MSR_HV, "HV"}, 943 #endif 944 {MSR_VEC, "VEC"}, 945 {MSR_VSX, "VSX"}, 946 #ifdef CONFIG_BOOKE 947 {MSR_CE, "CE"}, 948 #endif 949 {MSR_EE, "EE"}, 950 {MSR_PR, "PR"}, 951 {MSR_FP, "FP"}, 952 {MSR_ME, "ME"}, 953 #ifdef CONFIG_BOOKE 954 {MSR_DE, "DE"}, 955 #else 956 {MSR_SE, "SE"}, 957 {MSR_BE, "BE"}, 958 #endif 959 {MSR_IR, "IR"}, 960 {MSR_DR, "DR"}, 961 {MSR_PMM, "PMM"}, 962 #ifndef CONFIG_BOOKE 963 {MSR_RI, "RI"}, 964 {MSR_LE, "LE"}, 965 #endif 966 {0, NULL} 967 }; 968 969 static void printbits(unsigned long val, struct regbit *bits) 970 { 971 const char *sep = ""; 972 973 printk("<"); 974 for (; bits->bit; ++bits) 975 if (val & bits->bit) { 976 printk("%s%s", sep, bits->name); 977 sep = ","; 978 } 979 printk(">"); 980 } 981 982 #ifdef CONFIG_PPC64 983 #define REG "%016lx" 984 #define REGS_PER_LINE 4 985 #define LAST_VOLATILE 13 986 #else 987 #define REG "%08lx" 988 #define REGS_PER_LINE 8 989 #define LAST_VOLATILE 12 990 #endif 991 992 void show_regs(struct pt_regs * regs) 993 { 994 int i, trap; 995 996 show_regs_print_info(KERN_DEFAULT); 997 998 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", 999 regs->nip, regs->link, regs->ctr); 1000 printk("REGS: %p TRAP: %04lx %s (%s)\n", 1001 regs, regs->trap, print_tainted(), init_utsname()->release); 1002 printk("MSR: "REG" ", regs->msr); 1003 printbits(regs->msr, msr_bits); 1004 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 1005 trap = TRAP(regs); 1006 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) 1007 printk("CFAR: "REG" ", regs->orig_gpr3); 1008 if (trap == 0x200 || trap == 0x300 || trap == 0x600) 1009 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 1010 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); 1011 #else 1012 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); 1013 #endif 1014 #ifdef CONFIG_PPC64 1015 printk("SOFTE: %ld ", regs->softe); 1016 #endif 1017 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1018 if (MSR_TM_ACTIVE(regs->msr)) 1019 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); 1020 #endif 1021 1022 for (i = 0; i < 32; i++) { 1023 if ((i % REGS_PER_LINE) == 0) 1024 printk("\nGPR%02d: ", i); 1025 printk(REG " ", regs->gpr[i]); 1026 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 1027 break; 1028 } 1029 printk("\n"); 1030 #ifdef CONFIG_KALLSYMS 1031 /* 1032 * Lookup NIP late so we have the best change of getting the 1033 * above info out without failing 1034 */ 1035 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); 1036 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); 1037 #endif 1038 show_stack(current, (unsigned long *) regs->gpr[1]); 1039 if (!user_mode(regs)) 1040 show_instructions(regs); 1041 } 1042 1043 void exit_thread(void) 1044 { 1045 discard_lazy_cpu_state(); 1046 } 1047 1048 void flush_thread(void) 1049 { 1050 discard_lazy_cpu_state(); 1051 1052 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1053 flush_ptrace_hw_breakpoint(current); 1054 #else /* CONFIG_HAVE_HW_BREAKPOINT */ 1055 set_debug_reg_defaults(¤t->thread); 1056 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1057 } 1058 1059 void 1060 release_thread(struct task_struct *t) 1061 { 1062 } 1063 1064 /* 1065 * this gets called so that we can store coprocessor state into memory and 1066 * copy the current task into the new thread. 1067 */ 1068 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 1069 { 1070 flush_fp_to_thread(src); 1071 flush_altivec_to_thread(src); 1072 flush_vsx_to_thread(src); 1073 flush_spe_to_thread(src); 1074 /* 1075 * Flush TM state out so we can copy it. __switch_to_tm() does this 1076 * flush but it removes the checkpointed state from the current CPU and 1077 * transitions the CPU out of TM mode. Hence we need to call 1078 * tm_recheckpoint_new_task() (on the same task) to restore the 1079 * checkpointed state back and the TM mode. 1080 */ 1081 __switch_to_tm(src); 1082 tm_recheckpoint_new_task(src); 1083 1084 *dst = *src; 1085 1086 clear_task_ebb(dst); 1087 1088 return 0; 1089 } 1090 1091 /* 1092 * Copy a thread.. 1093 */ 1094 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ 1095 1096 int copy_thread(unsigned long clone_flags, unsigned long usp, 1097 unsigned long arg, struct task_struct *p) 1098 { 1099 struct pt_regs *childregs, *kregs; 1100 extern void ret_from_fork(void); 1101 extern void ret_from_kernel_thread(void); 1102 void (*f)(void); 1103 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; 1104 1105 /* Copy registers */ 1106 sp -= sizeof(struct pt_regs); 1107 childregs = (struct pt_regs *) sp; 1108 if (unlikely(p->flags & PF_KTHREAD)) { 1109 struct thread_info *ti = (void *)task_stack_page(p); 1110 memset(childregs, 0, sizeof(struct pt_regs)); 1111 childregs->gpr[1] = sp + sizeof(struct pt_regs); 1112 /* function */ 1113 if (usp) 1114 childregs->gpr[14] = ppc_function_entry((void *)usp); 1115 #ifdef CONFIG_PPC64 1116 clear_tsk_thread_flag(p, TIF_32BIT); 1117 childregs->softe = 1; 1118 #endif 1119 childregs->gpr[15] = arg; 1120 p->thread.regs = NULL; /* no user register state */ 1121 ti->flags |= _TIF_RESTOREALL; 1122 f = ret_from_kernel_thread; 1123 } else { 1124 struct pt_regs *regs = current_pt_regs(); 1125 CHECK_FULL_REGS(regs); 1126 *childregs = *regs; 1127 if (usp) 1128 childregs->gpr[1] = usp; 1129 p->thread.regs = childregs; 1130 childregs->gpr[3] = 0; /* Result from fork() */ 1131 if (clone_flags & CLONE_SETTLS) { 1132 #ifdef CONFIG_PPC64 1133 if (!is_32bit_task()) 1134 childregs->gpr[13] = childregs->gpr[6]; 1135 else 1136 #endif 1137 childregs->gpr[2] = childregs->gpr[6]; 1138 } 1139 1140 f = ret_from_fork; 1141 } 1142 sp -= STACK_FRAME_OVERHEAD; 1143 1144 /* 1145 * The way this works is that at some point in the future 1146 * some task will call _switch to switch to the new task. 1147 * That will pop off the stack frame created below and start 1148 * the new task running at ret_from_fork. The new task will 1149 * do some house keeping and then return from the fork or clone 1150 * system call, using the stack frame created above. 1151 */ 1152 ((unsigned long *)sp)[0] = 0; 1153 sp -= sizeof(struct pt_regs); 1154 kregs = (struct pt_regs *) sp; 1155 sp -= STACK_FRAME_OVERHEAD; 1156 p->thread.ksp = sp; 1157 #ifdef CONFIG_PPC32 1158 p->thread.ksp_limit = (unsigned long)task_stack_page(p) + 1159 _ALIGN_UP(sizeof(struct thread_info), 16); 1160 #endif 1161 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1162 p->thread.ptrace_bps[0] = NULL; 1163 #endif 1164 1165 p->thread.fp_save_area = NULL; 1166 #ifdef CONFIG_ALTIVEC 1167 p->thread.vr_save_area = NULL; 1168 #endif 1169 1170 #ifdef CONFIG_PPC_STD_MMU_64 1171 if (mmu_has_feature(MMU_FTR_SLB)) { 1172 unsigned long sp_vsid; 1173 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 1174 1175 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1176 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 1177 << SLB_VSID_SHIFT_1T; 1178 else 1179 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) 1180 << SLB_VSID_SHIFT; 1181 sp_vsid |= SLB_VSID_KERNEL | llp; 1182 p->thread.ksp_vsid = sp_vsid; 1183 } 1184 #endif /* CONFIG_PPC_STD_MMU_64 */ 1185 #ifdef CONFIG_PPC64 1186 if (cpu_has_feature(CPU_FTR_DSCR)) { 1187 p->thread.dscr_inherit = current->thread.dscr_inherit; 1188 p->thread.dscr = current->thread.dscr; 1189 } 1190 if (cpu_has_feature(CPU_FTR_HAS_PPR)) 1191 p->thread.ppr = INIT_PPR; 1192 #endif 1193 kregs->nip = ppc_function_entry(f); 1194 return 0; 1195 } 1196 1197 /* 1198 * Set up a thread for executing a new program 1199 */ 1200 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) 1201 { 1202 #ifdef CONFIG_PPC64 1203 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 1204 #endif 1205 1206 /* 1207 * If we exec out of a kernel thread then thread.regs will not be 1208 * set. Do it now. 1209 */ 1210 if (!current->thread.regs) { 1211 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; 1212 current->thread.regs = regs - 1; 1213 } 1214 1215 memset(regs->gpr, 0, sizeof(regs->gpr)); 1216 regs->ctr = 0; 1217 regs->link = 0; 1218 regs->xer = 0; 1219 regs->ccr = 0; 1220 regs->gpr[1] = sp; 1221 1222 /* 1223 * We have just cleared all the nonvolatile GPRs, so make 1224 * FULL_REGS(regs) return true. This is necessary to allow 1225 * ptrace to examine the thread immediately after exec. 1226 */ 1227 regs->trap &= ~1UL; 1228 1229 #ifdef CONFIG_PPC32 1230 regs->mq = 0; 1231 regs->nip = start; 1232 regs->msr = MSR_USER; 1233 #else 1234 if (!is_32bit_task()) { 1235 unsigned long entry; 1236 1237 if (is_elf2_task()) { 1238 /* Look ma, no function descriptors! */ 1239 entry = start; 1240 1241 /* 1242 * Ulrich says: 1243 * The latest iteration of the ABI requires that when 1244 * calling a function (at its global entry point), 1245 * the caller must ensure r12 holds the entry point 1246 * address (so that the function can quickly 1247 * establish addressability). 1248 */ 1249 regs->gpr[12] = start; 1250 /* Make sure that's restored on entry to userspace. */ 1251 set_thread_flag(TIF_RESTOREALL); 1252 } else { 1253 unsigned long toc; 1254 1255 /* start is a relocated pointer to the function 1256 * descriptor for the elf _start routine. The first 1257 * entry in the function descriptor is the entry 1258 * address of _start and the second entry is the TOC 1259 * value we need to use. 1260 */ 1261 __get_user(entry, (unsigned long __user *)start); 1262 __get_user(toc, (unsigned long __user *)start+1); 1263 1264 /* Check whether the e_entry function descriptor entries 1265 * need to be relocated before we can use them. 1266 */ 1267 if (load_addr != 0) { 1268 entry += load_addr; 1269 toc += load_addr; 1270 } 1271 regs->gpr[2] = toc; 1272 } 1273 regs->nip = entry; 1274 regs->msr = MSR_USER64; 1275 } else { 1276 regs->nip = start; 1277 regs->gpr[2] = 0; 1278 regs->msr = MSR_USER32; 1279 } 1280 #endif 1281 discard_lazy_cpu_state(); 1282 #ifdef CONFIG_VSX 1283 current->thread.used_vsr = 0; 1284 #endif 1285 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); 1286 current->thread.fp_save_area = NULL; 1287 #ifdef CONFIG_ALTIVEC 1288 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); 1289 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ 1290 current->thread.vr_save_area = NULL; 1291 current->thread.vrsave = 0; 1292 current->thread.used_vr = 0; 1293 #endif /* CONFIG_ALTIVEC */ 1294 #ifdef CONFIG_SPE 1295 memset(current->thread.evr, 0, sizeof(current->thread.evr)); 1296 current->thread.acc = 0; 1297 current->thread.spefscr = 0; 1298 current->thread.used_spe = 0; 1299 #endif /* CONFIG_SPE */ 1300 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1301 if (cpu_has_feature(CPU_FTR_TM)) 1302 regs->msr |= MSR_TM; 1303 current->thread.tm_tfhar = 0; 1304 current->thread.tm_texasr = 0; 1305 current->thread.tm_tfiar = 0; 1306 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1307 } 1308 1309 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ 1310 | PR_FP_EXC_RES | PR_FP_EXC_INV) 1311 1312 int set_fpexc_mode(struct task_struct *tsk, unsigned int val) 1313 { 1314 struct pt_regs *regs = tsk->thread.regs; 1315 1316 /* This is a bit hairy. If we are an SPE enabled processor 1317 * (have embedded fp) we store the IEEE exception enable flags in 1318 * fpexc_mode. fpexc_mode is also used for setting FP exception 1319 * mode (asyn, precise, disabled) for 'Classic' FP. */ 1320 if (val & PR_FP_EXC_SW_ENABLE) { 1321 #ifdef CONFIG_SPE 1322 if (cpu_has_feature(CPU_FTR_SPE)) { 1323 /* 1324 * When the sticky exception bits are set 1325 * directly by userspace, it must call prctl 1326 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1327 * in the existing prctl settings) or 1328 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1329 * the bits being set). <fenv.h> functions 1330 * saving and restoring the whole 1331 * floating-point environment need to do so 1332 * anyway to restore the prctl settings from 1333 * the saved environment. 1334 */ 1335 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1336 tsk->thread.fpexc_mode = val & 1337 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); 1338 return 0; 1339 } else { 1340 return -EINVAL; 1341 } 1342 #else 1343 return -EINVAL; 1344 #endif 1345 } 1346 1347 /* on a CONFIG_SPE this does not hurt us. The bits that 1348 * __pack_fe01 use do not overlap with bits used for 1349 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits 1350 * on CONFIG_SPE implementations are reserved so writing to 1351 * them does not change anything */ 1352 if (val > PR_FP_EXC_PRECISE) 1353 return -EINVAL; 1354 tsk->thread.fpexc_mode = __pack_fe01(val); 1355 if (regs != NULL && (regs->msr & MSR_FP) != 0) 1356 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) 1357 | tsk->thread.fpexc_mode; 1358 return 0; 1359 } 1360 1361 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) 1362 { 1363 unsigned int val; 1364 1365 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) 1366 #ifdef CONFIG_SPE 1367 if (cpu_has_feature(CPU_FTR_SPE)) { 1368 /* 1369 * When the sticky exception bits are set 1370 * directly by userspace, it must call prctl 1371 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE 1372 * in the existing prctl settings) or 1373 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in 1374 * the bits being set). <fenv.h> functions 1375 * saving and restoring the whole 1376 * floating-point environment need to do so 1377 * anyway to restore the prctl settings from 1378 * the saved environment. 1379 */ 1380 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); 1381 val = tsk->thread.fpexc_mode; 1382 } else 1383 return -EINVAL; 1384 #else 1385 return -EINVAL; 1386 #endif 1387 else 1388 val = __unpack_fe01(tsk->thread.fpexc_mode); 1389 return put_user(val, (unsigned int __user *) adr); 1390 } 1391 1392 int set_endian(struct task_struct *tsk, unsigned int val) 1393 { 1394 struct pt_regs *regs = tsk->thread.regs; 1395 1396 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || 1397 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) 1398 return -EINVAL; 1399 1400 if (regs == NULL) 1401 return -EINVAL; 1402 1403 if (val == PR_ENDIAN_BIG) 1404 regs->msr &= ~MSR_LE; 1405 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) 1406 regs->msr |= MSR_LE; 1407 else 1408 return -EINVAL; 1409 1410 return 0; 1411 } 1412 1413 int get_endian(struct task_struct *tsk, unsigned long adr) 1414 { 1415 struct pt_regs *regs = tsk->thread.regs; 1416 unsigned int val; 1417 1418 if (!cpu_has_feature(CPU_FTR_PPC_LE) && 1419 !cpu_has_feature(CPU_FTR_REAL_LE)) 1420 return -EINVAL; 1421 1422 if (regs == NULL) 1423 return -EINVAL; 1424 1425 if (regs->msr & MSR_LE) { 1426 if (cpu_has_feature(CPU_FTR_REAL_LE)) 1427 val = PR_ENDIAN_LITTLE; 1428 else 1429 val = PR_ENDIAN_PPC_LITTLE; 1430 } else 1431 val = PR_ENDIAN_BIG; 1432 1433 return put_user(val, (unsigned int __user *)adr); 1434 } 1435 1436 int set_unalign_ctl(struct task_struct *tsk, unsigned int val) 1437 { 1438 tsk->thread.align_ctl = val; 1439 return 0; 1440 } 1441 1442 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) 1443 { 1444 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); 1445 } 1446 1447 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, 1448 unsigned long nbytes) 1449 { 1450 unsigned long stack_page; 1451 unsigned long cpu = task_cpu(p); 1452 1453 /* 1454 * Avoid crashing if the stack has overflowed and corrupted 1455 * task_cpu(p), which is in the thread_info struct. 1456 */ 1457 if (cpu < NR_CPUS && cpu_possible(cpu)) { 1458 stack_page = (unsigned long) hardirq_ctx[cpu]; 1459 if (sp >= stack_page + sizeof(struct thread_struct) 1460 && sp <= stack_page + THREAD_SIZE - nbytes) 1461 return 1; 1462 1463 stack_page = (unsigned long) softirq_ctx[cpu]; 1464 if (sp >= stack_page + sizeof(struct thread_struct) 1465 && sp <= stack_page + THREAD_SIZE - nbytes) 1466 return 1; 1467 } 1468 return 0; 1469 } 1470 1471 int validate_sp(unsigned long sp, struct task_struct *p, 1472 unsigned long nbytes) 1473 { 1474 unsigned long stack_page = (unsigned long)task_stack_page(p); 1475 1476 if (sp >= stack_page + sizeof(struct thread_struct) 1477 && sp <= stack_page + THREAD_SIZE - nbytes) 1478 return 1; 1479 1480 return valid_irq_stack(sp, p, nbytes); 1481 } 1482 1483 EXPORT_SYMBOL(validate_sp); 1484 1485 unsigned long get_wchan(struct task_struct *p) 1486 { 1487 unsigned long ip, sp; 1488 int count = 0; 1489 1490 if (!p || p == current || p->state == TASK_RUNNING) 1491 return 0; 1492 1493 sp = p->thread.ksp; 1494 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1495 return 0; 1496 1497 do { 1498 sp = *(unsigned long *)sp; 1499 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) 1500 return 0; 1501 if (count > 0) { 1502 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; 1503 if (!in_sched_functions(ip)) 1504 return ip; 1505 } 1506 } while (count++ < 16); 1507 return 0; 1508 } 1509 1510 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; 1511 1512 void show_stack(struct task_struct *tsk, unsigned long *stack) 1513 { 1514 unsigned long sp, ip, lr, newsp; 1515 int count = 0; 1516 int firstframe = 1; 1517 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1518 int curr_frame = current->curr_ret_stack; 1519 extern void return_to_handler(void); 1520 unsigned long rth = (unsigned long)return_to_handler; 1521 unsigned long mrth = -1; 1522 #ifdef CONFIG_PPC64 1523 extern void mod_return_to_handler(void); 1524 rth = *(unsigned long *)rth; 1525 mrth = (unsigned long)mod_return_to_handler; 1526 mrth = *(unsigned long *)mrth; 1527 #endif 1528 #endif 1529 1530 sp = (unsigned long) stack; 1531 if (tsk == NULL) 1532 tsk = current; 1533 if (sp == 0) { 1534 if (tsk == current) 1535 asm("mr %0,1" : "=r" (sp)); 1536 else 1537 sp = tsk->thread.ksp; 1538 } 1539 1540 lr = 0; 1541 printk("Call Trace:\n"); 1542 do { 1543 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) 1544 return; 1545 1546 stack = (unsigned long *) sp; 1547 newsp = stack[0]; 1548 ip = stack[STACK_FRAME_LR_SAVE]; 1549 if (!firstframe || ip != lr) { 1550 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); 1551 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1552 if ((ip == rth || ip == mrth) && curr_frame >= 0) { 1553 printk(" (%pS)", 1554 (void *)current->ret_stack[curr_frame].ret); 1555 curr_frame--; 1556 } 1557 #endif 1558 if (firstframe) 1559 printk(" (unreliable)"); 1560 printk("\n"); 1561 } 1562 firstframe = 0; 1563 1564 /* 1565 * See if this is an exception frame. 1566 * We look for the "regshere" marker in the current frame. 1567 */ 1568 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) 1569 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { 1570 struct pt_regs *regs = (struct pt_regs *) 1571 (sp + STACK_FRAME_OVERHEAD); 1572 lr = regs->link; 1573 printk("--- Exception: %lx at %pS\n LR = %pS\n", 1574 regs->trap, (void *)regs->nip, (void *)lr); 1575 firstframe = 1; 1576 } 1577 1578 sp = newsp; 1579 } while (count++ < kstack_depth_to_print); 1580 } 1581 1582 #ifdef CONFIG_PPC64 1583 /* Called with hard IRQs off */ 1584 void notrace __ppc64_runlatch_on(void) 1585 { 1586 struct thread_info *ti = current_thread_info(); 1587 unsigned long ctrl; 1588 1589 ctrl = mfspr(SPRN_CTRLF); 1590 ctrl |= CTRL_RUNLATCH; 1591 mtspr(SPRN_CTRLT, ctrl); 1592 1593 ti->local_flags |= _TLF_RUNLATCH; 1594 } 1595 1596 /* Called with hard IRQs off */ 1597 void notrace __ppc64_runlatch_off(void) 1598 { 1599 struct thread_info *ti = current_thread_info(); 1600 unsigned long ctrl; 1601 1602 ti->local_flags &= ~_TLF_RUNLATCH; 1603 1604 ctrl = mfspr(SPRN_CTRLF); 1605 ctrl &= ~CTRL_RUNLATCH; 1606 mtspr(SPRN_CTRLT, ctrl); 1607 } 1608 #endif /* CONFIG_PPC64 */ 1609 1610 unsigned long arch_align_stack(unsigned long sp) 1611 { 1612 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1613 sp -= get_random_int() & ~PAGE_MASK; 1614 return sp & ~0xf; 1615 } 1616 1617 static inline unsigned long brk_rnd(void) 1618 { 1619 unsigned long rnd = 0; 1620 1621 /* 8MB for 32bit, 1GB for 64bit */ 1622 if (is_32bit_task()) 1623 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); 1624 else 1625 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); 1626 1627 return rnd << PAGE_SHIFT; 1628 } 1629 1630 unsigned long arch_randomize_brk(struct mm_struct *mm) 1631 { 1632 unsigned long base = mm->brk; 1633 unsigned long ret; 1634 1635 #ifdef CONFIG_PPC_STD_MMU_64 1636 /* 1637 * If we are using 1TB segments and we are allowed to randomise 1638 * the heap, we can put it above 1TB so it is backed by a 1TB 1639 * segment. Otherwise the heap will be in the bottom 1TB 1640 * which always uses 256MB segments and this may result in a 1641 * performance penalty. 1642 */ 1643 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) 1644 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); 1645 #endif 1646 1647 ret = PAGE_ALIGN(base + brk_rnd()); 1648 1649 if (ret < mm->brk) 1650 return mm->brk; 1651 1652 return ret; 1653 } 1654 1655 unsigned long randomize_et_dyn(unsigned long base) 1656 { 1657 unsigned long ret = PAGE_ALIGN(base + brk_rnd()); 1658 1659 if (ret < base) 1660 return base; 1661 1662 return ret; 1663 } 1664