1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Boot code and exception vectors for Book3E processors 4 * 5 * Copyright (C) 2007 Ben. Herrenschmidt ([email protected]), IBM Corp. 6 */ 7 8#include <linux/threads.h> 9#include <asm/reg.h> 10#include <asm/page.h> 11#include <asm/ppc_asm.h> 12#include <asm/asm-offsets.h> 13#include <asm/cputable.h> 14#include <asm/setup.h> 15#include <asm/thread_info.h> 16#include <asm/reg_a2.h> 17#include <asm/exception-64e.h> 18#include <asm/bug.h> 19#include <asm/irqflags.h> 20#include <asm/ptrace.h> 21#include <asm/ppc-opcode.h> 22#include <asm/mmu.h> 23#include <asm/hw_irq.h> 24#include <asm/kvm_asm.h> 25#include <asm/kvm_booke_hv_asm.h> 26#include <asm/feature-fixups.h> 27#include <asm/context_tracking.h> 28 29/* 64e interrupt returns always use SRR registers */ 30#define fast_interrupt_return fast_interrupt_return_srr 31#define interrupt_return interrupt_return_srr 32 33/* XXX This will ultimately add space for a special exception save 34 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 35 * when taking special interrupts. For now we don't support that, 36 * special interrupts from within a non-standard level will probably 37 * blow you up 38 */ 39#define SPECIAL_EXC_SRR0 0 40#define SPECIAL_EXC_SRR1 1 41#define SPECIAL_EXC_SPRG_GEN 2 42#define SPECIAL_EXC_SPRG_TLB 3 43#define SPECIAL_EXC_MAS0 4 44#define SPECIAL_EXC_MAS1 5 45#define SPECIAL_EXC_MAS2 6 46#define SPECIAL_EXC_MAS3 7 47#define SPECIAL_EXC_MAS6 8 48#define SPECIAL_EXC_MAS7 9 49#define SPECIAL_EXC_MAS5 10 /* E.HV only */ 50#define SPECIAL_EXC_MAS8 11 /* E.HV only */ 51#define SPECIAL_EXC_IRQHAPPENED 12 52#define SPECIAL_EXC_DEAR 13 53#define SPECIAL_EXC_ESR 14 54#define SPECIAL_EXC_SOFTE 15 55#define SPECIAL_EXC_CSRR0 16 56#define SPECIAL_EXC_CSRR1 17 57/* must be even to keep 16-byte stack alignment */ 58#define SPECIAL_EXC_END 18 59 60#define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) 61#define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) 62 63#define SPECIAL_EXC_STORE(reg, name) \ 64 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 65 66#define SPECIAL_EXC_LOAD(reg, name) \ 67 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 68 69special_reg_save: 70 /* 71 * We only need (or have stack space) to save this stuff if 72 * we interrupted the kernel. 73 */ 74 ld r3,_MSR(r1) 75 andi. r3,r3,MSR_PR 76 bnelr 77 78 /* 79 * Advance to the next TLB exception frame for handler 80 * types that don't do it automatically. 81 */ 82 LOAD_REG_ADDR(r11,extlb_level_exc) 83 lwz r12,0(r11) 84 mfspr r10,SPRN_SPRG_TLB_EXFRAME 85 add r10,r10,r12 86 mtspr SPRN_SPRG_TLB_EXFRAME,r10 87 88 /* 89 * Save registers needed to allow nesting of certain exceptions 90 * (such as TLB misses) inside special exception levels 91 */ 92 mfspr r10,SPRN_SRR0 93 SPECIAL_EXC_STORE(r10,SRR0) 94 mfspr r10,SPRN_SRR1 95 SPECIAL_EXC_STORE(r10,SRR1) 96 mfspr r10,SPRN_SPRG_GEN_SCRATCH 97 SPECIAL_EXC_STORE(r10,SPRG_GEN) 98 mfspr r10,SPRN_SPRG_TLB_SCRATCH 99 SPECIAL_EXC_STORE(r10,SPRG_TLB) 100 mfspr r10,SPRN_MAS0 101 SPECIAL_EXC_STORE(r10,MAS0) 102 mfspr r10,SPRN_MAS1 103 SPECIAL_EXC_STORE(r10,MAS1) 104 mfspr r10,SPRN_MAS2 105 SPECIAL_EXC_STORE(r10,MAS2) 106 mfspr r10,SPRN_MAS3 107 SPECIAL_EXC_STORE(r10,MAS3) 108 mfspr r10,SPRN_MAS6 109 SPECIAL_EXC_STORE(r10,MAS6) 110 mfspr r10,SPRN_MAS7 111 SPECIAL_EXC_STORE(r10,MAS7) 112BEGIN_FTR_SECTION 113 mfspr r10,SPRN_MAS5 114 SPECIAL_EXC_STORE(r10,MAS5) 115 mfspr r10,SPRN_MAS8 116 SPECIAL_EXC_STORE(r10,MAS8) 117 118 /* MAS5/8 could have inappropriate values if we interrupted KVM code */ 119 li r10,0 120 mtspr SPRN_MAS5,r10 121 mtspr SPRN_MAS8,r10 122END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 123 mfspr r10,SPRN_DEAR 124 SPECIAL_EXC_STORE(r10,DEAR) 125 mfspr r10,SPRN_ESR 126 SPECIAL_EXC_STORE(r10,ESR) 127 128 ld r10,_NIP(r1) 129 SPECIAL_EXC_STORE(r10,CSRR0) 130 ld r10,_MSR(r1) 131 SPECIAL_EXC_STORE(r10,CSRR1) 132 133 blr 134 135ret_from_level_except: 136 ld r3,_MSR(r1) 137 andi. r3,r3,MSR_PR 138 beq 1f 139 REST_NVGPRS(r1) 140 b interrupt_return 1411: 142 143 LOAD_REG_ADDR(r11,extlb_level_exc) 144 lwz r12,0(r11) 145 mfspr r10,SPRN_SPRG_TLB_EXFRAME 146 sub r10,r10,r12 147 mtspr SPRN_SPRG_TLB_EXFRAME,r10 148 149 /* 150 * It's possible that the special level exception interrupted a 151 * TLB miss handler, and inserted the same entry that the 152 * interrupted handler was about to insert. On CPUs without TLB 153 * write conditional, this can result in a duplicate TLB entry. 154 * Wipe all non-bolted entries to be safe. 155 * 156 * Note that this doesn't protect against any TLB misses 157 * we may take accessing the stack from here to the end of 158 * the special level exception. It's not clear how we can 159 * reasonably protect against that, but only CPUs with 160 * neither TLB write conditional nor bolted kernel memory 161 * are affected. Do any such CPUs even exist? 162 */ 163 PPC_TLBILX_ALL(0,R0) 164 165 REST_NVGPRS(r1) 166 167 SPECIAL_EXC_LOAD(r10,SRR0) 168 mtspr SPRN_SRR0,r10 169 SPECIAL_EXC_LOAD(r10,SRR1) 170 mtspr SPRN_SRR1,r10 171 SPECIAL_EXC_LOAD(r10,SPRG_GEN) 172 mtspr SPRN_SPRG_GEN_SCRATCH,r10 173 SPECIAL_EXC_LOAD(r10,SPRG_TLB) 174 mtspr SPRN_SPRG_TLB_SCRATCH,r10 175 SPECIAL_EXC_LOAD(r10,MAS0) 176 mtspr SPRN_MAS0,r10 177 SPECIAL_EXC_LOAD(r10,MAS1) 178 mtspr SPRN_MAS1,r10 179 SPECIAL_EXC_LOAD(r10,MAS2) 180 mtspr SPRN_MAS2,r10 181 SPECIAL_EXC_LOAD(r10,MAS3) 182 mtspr SPRN_MAS3,r10 183 SPECIAL_EXC_LOAD(r10,MAS6) 184 mtspr SPRN_MAS6,r10 185 SPECIAL_EXC_LOAD(r10,MAS7) 186 mtspr SPRN_MAS7,r10 187BEGIN_FTR_SECTION 188 SPECIAL_EXC_LOAD(r10,MAS5) 189 mtspr SPRN_MAS5,r10 190 SPECIAL_EXC_LOAD(r10,MAS8) 191 mtspr SPRN_MAS8,r10 192END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 193 194 SPECIAL_EXC_LOAD(r10,DEAR) 195 mtspr SPRN_DEAR,r10 196 SPECIAL_EXC_LOAD(r10,ESR) 197 mtspr SPRN_ESR,r10 198 199 stdcx. r0,0,r1 /* to clear the reservation */ 200 201 REST_4GPRS(2, r1) 202 REST_4GPRS(6, r1) 203 204 ld r10,_CTR(r1) 205 ld r11,_XER(r1) 206 mtctr r10 207 mtxer r11 208 209 blr 210 211.macro ret_from_level srr0 srr1 paca_ex scratch 212 bl ret_from_level_except 213 214 ld r10,_LINK(r1) 215 ld r11,_CCR(r1) 216 ld r0,GPR13(r1) 217 mtlr r10 218 mtcr r11 219 220 ld r10,GPR10(r1) 221 ld r11,GPR11(r1) 222 ld r12,GPR12(r1) 223 mtspr \scratch,r0 224 225 std r10,\paca_ex+EX_R10(r13); 226 std r11,\paca_ex+EX_R11(r13); 227 ld r10,_NIP(r1) 228 ld r11,_MSR(r1) 229 ld r0,GPR0(r1) 230 ld r1,GPR1(r1) 231 mtspr \srr0,r10 232 mtspr \srr1,r11 233 ld r10,\paca_ex+EX_R10(r13) 234 ld r11,\paca_ex+EX_R11(r13) 235 mfspr r13,\scratch 236.endm 237 238ret_from_crit_except: 239 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH 240 rfci 241 242ret_from_mc_except: 243 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH 244 rfmci 245 246/* Exception prolog code for all exceptions */ 247#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 248 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 249 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 250 std r10,PACA_EX##type+EX_R10(r13); \ 251 std r11,PACA_EX##type+EX_R11(r13); \ 252 mfcr r10; /* save CR */ \ 253 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 254 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 255 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 256 addition; /* additional code for that exc. */ \ 257 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 258 type##_SET_KSTACK; /* get special stack if necessary */\ 259 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 260 beq 1f; /* branch around if supervisor */ \ 261 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 2621: type##_BTB_FLUSH \ 263 cmpdi cr1,r1,0; /* check if SP makes sense */ \ 264 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 265 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 266 267/* Exception type-specific macros */ 268#define GEN_SET_KSTACK \ 269 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 270#define SPRN_GEN_SRR0 SPRN_SRR0 271#define SPRN_GEN_SRR1 SPRN_SRR1 272 273#define GDBELL_SET_KSTACK GEN_SET_KSTACK 274#define SPRN_GDBELL_SRR0 SPRN_GSRR0 275#define SPRN_GDBELL_SRR1 SPRN_GSRR1 276 277#define CRIT_SET_KSTACK \ 278 ld r1,PACA_CRIT_STACK(r13); \ 279 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 280#define SPRN_CRIT_SRR0 SPRN_CSRR0 281#define SPRN_CRIT_SRR1 SPRN_CSRR1 282 283#define DBG_SET_KSTACK \ 284 ld r1,PACA_DBG_STACK(r13); \ 285 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 286#define SPRN_DBG_SRR0 SPRN_DSRR0 287#define SPRN_DBG_SRR1 SPRN_DSRR1 288 289#define MC_SET_KSTACK \ 290 ld r1,PACA_MC_STACK(r13); \ 291 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 292#define SPRN_MC_SRR0 SPRN_MCSRR0 293#define SPRN_MC_SRR1 SPRN_MCSRR1 294 295#ifdef CONFIG_PPC_FSL_BOOK3E 296#define GEN_BTB_FLUSH \ 297 START_BTB_FLUSH_SECTION \ 298 beq 1f; \ 299 BTB_FLUSH(r10) \ 300 1: \ 301 END_BTB_FLUSH_SECTION 302 303#define CRIT_BTB_FLUSH \ 304 START_BTB_FLUSH_SECTION \ 305 BTB_FLUSH(r10) \ 306 END_BTB_FLUSH_SECTION 307 308#define DBG_BTB_FLUSH CRIT_BTB_FLUSH 309#define MC_BTB_FLUSH CRIT_BTB_FLUSH 310#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH 311#else 312#define GEN_BTB_FLUSH 313#define CRIT_BTB_FLUSH 314#define DBG_BTB_FLUSH 315#define MC_BTB_FLUSH 316#define GDBELL_BTB_FLUSH 317#endif 318 319#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 320 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 321 322#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 323 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 324 325#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 326 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 327 328#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 329 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 330 331#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 332 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 333 334/* Variants of the "addition" argument for the prolog 335 */ 336#define PROLOG_ADDITION_NONE_GEN(n) 337#define PROLOG_ADDITION_NONE_GDBELL(n) 338#define PROLOG_ADDITION_NONE_CRIT(n) 339#define PROLOG_ADDITION_NONE_DBG(n) 340#define PROLOG_ADDITION_NONE_MC(n) 341 342#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 343 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \ 344 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \ 345 bne masked_interrupt_book3e_##n; \ 346 /* Kernel code below __end_soft_masked is implicitly masked */ \ 347 andi. r10,r11,MSR_PR; \ 348 bne 1f; /* user -> not masked */ \ 349 std r14,PACA_EXGEN+EX_R14(r13); \ 350 LOAD_REG_IMMEDIATE_SYM(r14, r10, __end_soft_masked); \ 351 mfspr r10,SPRN_SRR0; \ 352 cmpld r10,r14; \ 353 ld r14,PACA_EXGEN+EX_R14(r13); \ 354 blt masked_interrupt_book3e_##n; \ 3551: 356 357/* 358 * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is 359 * called, because that does SAVE_NVGPRS which must see the original register 360 * values, otherwise the scratch values might be restored when exiting the 361 * interrupt. 362 */ 363#define PROLOG_ADDITION_2REGS_GEN(n) \ 364 std r14,PACA_EXGEN+EX_R14(r13); \ 365 std r15,PACA_EXGEN+EX_R15(r13) 366 367#define PROLOG_ADDITION_1REG_GEN(n) \ 368 std r14,PACA_EXGEN+EX_R14(r13); 369 370#define PROLOG_ADDITION_2REGS_CRIT(n) \ 371 std r14,PACA_EXCRIT+EX_R14(r13); \ 372 std r15,PACA_EXCRIT+EX_R15(r13) 373 374#define PROLOG_ADDITION_2REGS_DBG(n) \ 375 std r14,PACA_EXDBG+EX_R14(r13); \ 376 std r15,PACA_EXDBG+EX_R15(r13) 377 378#define PROLOG_ADDITION_2REGS_MC(n) \ 379 std r14,PACA_EXMC+EX_R14(r13); \ 380 std r15,PACA_EXMC+EX_R15(r13) 381 382 383/* Core exception code for all exceptions except TLB misses. */ 384#define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 385exc_##n##_common: \ 386 std r0,GPR0(r1); /* save r0 in stackframe */ \ 387 std r2,GPR2(r1); /* save r2 in stackframe */ \ 388 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 389 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 390 std r9,GPR9(r1); /* save r9 in stackframe */ \ 391 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 392 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 393 beq 2f; /* if from kernel mode */ \ 3942: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 395 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 396 mfspr r5,scratch; /* get back r13 */ \ 397 std r12,GPR12(r1); /* save r12 in stackframe */ \ 398 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 399 mflr r6; /* save LR in stackframe */ \ 400 mfctr r7; /* save CTR in stackframe */ \ 401 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 402 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 403 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 404 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ 405 ld r12,exception_marker@toc(r2); \ 406 li r0,0; \ 407 std r3,GPR10(r1); /* save r10 to stackframe */ \ 408 std r4,GPR11(r1); /* save r11 to stackframe */ \ 409 std r5,GPR13(r1); /* save it to stackframe */ \ 410 std r6,_LINK(r1); \ 411 std r7,_CTR(r1); \ 412 std r8,_XER(r1); \ 413 li r3,(n); /* regs.trap vector */ \ 414 std r9,0(r1); /* store stack frame back link */ \ 415 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 416 std r9,GPR1(r1); /* store stack frame back link */ \ 417 std r11,SOFTE(r1); /* and save it to stackframe */ \ 418 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 419 std r3,_TRAP(r1); /* set trap number */ \ 420 std r0,RESULT(r1); /* clear regs->result */ \ 421 SAVE_NVGPRS(r1); 422 423#define EXCEPTION_COMMON(n) \ 424 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) 425#define EXCEPTION_COMMON_CRIT(n) \ 426 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) 427#define EXCEPTION_COMMON_MC(n) \ 428 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) 429#define EXCEPTION_COMMON_DBG(n) \ 430 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) 431 432/* XXX FIXME: Restore r14/r15 when necessary */ 433#define BAD_STACK_TRAMPOLINE(n) \ 434exc_##n##_bad_stack: \ 435 li r1,(n); /* get exception number */ \ 436 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 437 b bad_stack_book3e; /* bad stack error */ 438 439/* WARNING: If you change the layout of this stub, make sure you check 440 * the debug exception handler which handles single stepping 441 * into exceptions from userspace, and the MM code in 442 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 443 * and would need to be updated if that branch is moved 444 */ 445#define EXCEPTION_STUB(loc, label) \ 446 . = interrupt_base_book3e + loc; \ 447 nop; /* To make debug interrupts happy */ \ 448 b exc_##label##_book3e; 449 450#define ACK_NONE(r) 451#define ACK_DEC(r) \ 452 lis r,TSR_DIS@h; \ 453 mtspr SPRN_TSR,r 454#define ACK_FIT(r) \ 455 lis r,TSR_FIS@h; \ 456 mtspr SPRN_TSR,r 457 458/* Used by asynchronous interrupt that may happen in the idle loop. 459 * 460 * This check if the thread was in the idle loop, and if yes, returns 461 * to the caller rather than the PC. This is to avoid a race if 462 * interrupts happen before the wait instruction. 463 */ 464#define CHECK_NAPPING() \ 465 ld r11, PACA_THREAD_INFO(r13); \ 466 ld r10,TI_LOCAL_FLAGS(r11); \ 467 andi. r9,r10,_TLF_NAPPING; \ 468 beq+ 1f; \ 469 ld r8,_LINK(r1); \ 470 rlwinm r7,r10,0,~_TLF_NAPPING; \ 471 std r8,_NIP(r1); \ 472 std r7,TI_LOCAL_FLAGS(r11); \ 4731: 474 475 476#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 477 START_EXCEPTION(label); \ 478 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 479 EXCEPTION_COMMON(trapnum) \ 480 ack(r8); \ 481 CHECK_NAPPING(); \ 482 addi r3,r1,STACK_FRAME_OVERHEAD; \ 483 bl hdlr; \ 484 b interrupt_return 485 486/* This value is used to mark exception frames on the stack. */ 487 .section ".toc","aw" 488exception_marker: 489 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 490 491 492/* 493 * And here we have the exception vectors ! 494 */ 495 496 .text 497 .balign 0x1000 498 .globl interrupt_base_book3e 499interrupt_base_book3e: /* fake trap */ 500 EXCEPTION_STUB(0x000, machine_check) 501 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ 502 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 503 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 504 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 505 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 506 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 507 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 508 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 509 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 510 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 511 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 512 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 513 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 514 EXCEPTION_STUB(0x1c0, data_tlb_miss) 515 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 516 EXCEPTION_STUB(0x200, altivec_unavailable) 517 EXCEPTION_STUB(0x220, altivec_assist) 518 EXCEPTION_STUB(0x260, perfmon) 519 EXCEPTION_STUB(0x280, doorbell) 520 EXCEPTION_STUB(0x2a0, doorbell_crit) 521 EXCEPTION_STUB(0x2c0, guest_doorbell) 522 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 523 EXCEPTION_STUB(0x300, hypercall) 524 EXCEPTION_STUB(0x320, ehpriv) 525 EXCEPTION_STUB(0x340, lrat_error) 526 527 .globl __end_interrupts 528__end_interrupts: 529 530/* Critical Input Interrupt */ 531 START_EXCEPTION(critical_input); 532 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 533 PROLOG_ADDITION_NONE) 534 EXCEPTION_COMMON_CRIT(0x100) 535 bl special_reg_save 536 CHECK_NAPPING(); 537 addi r3,r1,STACK_FRAME_OVERHEAD 538 bl unknown_nmi_exception 539 b ret_from_crit_except 540 541/* Machine Check Interrupt */ 542 START_EXCEPTION(machine_check); 543 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, 544 PROLOG_ADDITION_NONE) 545 EXCEPTION_COMMON_MC(0x000) 546 bl special_reg_save 547 CHECK_NAPPING(); 548 addi r3,r1,STACK_FRAME_OVERHEAD 549 bl machine_check_exception 550 b ret_from_mc_except 551 552/* Data Storage Interrupt */ 553 START_EXCEPTION(data_storage) 554 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 555 PROLOG_ADDITION_2REGS) 556 mfspr r14,SPRN_DEAR 557 mfspr r15,SPRN_ESR 558 std r14,_DAR(r1) 559 std r15,_DSISR(r1) 560 ld r14,PACA_EXGEN+EX_R14(r13) 561 ld r15,PACA_EXGEN+EX_R15(r13) 562 EXCEPTION_COMMON(0x300) 563 b storage_fault_common 564 565/* Instruction Storage Interrupt */ 566 START_EXCEPTION(instruction_storage); 567 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 568 PROLOG_ADDITION_2REGS) 569 li r15,0 570 mr r14,r10 571 std r14,_DAR(r1) 572 std r15,_DSISR(r1) 573 ld r14,PACA_EXGEN+EX_R14(r13) 574 ld r15,PACA_EXGEN+EX_R15(r13) 575 EXCEPTION_COMMON(0x400) 576 b storage_fault_common 577 578/* External Input Interrupt */ 579 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 580 external_input, do_IRQ, ACK_NONE) 581 582/* Alignment */ 583 START_EXCEPTION(alignment); 584 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 585 PROLOG_ADDITION_2REGS) 586 mfspr r14,SPRN_DEAR 587 mfspr r15,SPRN_ESR 588 std r14,_DAR(r1) 589 std r15,_DSISR(r1) 590 ld r14,PACA_EXGEN+EX_R14(r13) 591 ld r15,PACA_EXGEN+EX_R15(r13) 592 EXCEPTION_COMMON(0x600) 593 b alignment_more /* no room, go out of line */ 594 595/* Program Interrupt */ 596 START_EXCEPTION(program); 597 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 598 PROLOG_ADDITION_1REG) 599 mfspr r14,SPRN_ESR 600 std r14,_DSISR(r1) 601 ld r14,PACA_EXGEN+EX_R14(r13) 602 EXCEPTION_COMMON(0x700) 603 addi r3,r1,STACK_FRAME_OVERHEAD 604 bl program_check_exception 605 REST_NVGPRS(r1) 606 b interrupt_return 607 608/* Floating Point Unavailable Interrupt */ 609 START_EXCEPTION(fp_unavailable); 610 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 611 PROLOG_ADDITION_NONE) 612 /* we can probably do a shorter exception entry for that one... */ 613 EXCEPTION_COMMON(0x800) 614 ld r12,_MSR(r1) 615 andi. r0,r12,MSR_PR; 616 beq- 1f 617 bl load_up_fpu 618 b fast_interrupt_return 6191: addi r3,r1,STACK_FRAME_OVERHEAD 620 bl kernel_fp_unavailable_exception 621 b interrupt_return 622 623/* Altivec Unavailable Interrupt */ 624 START_EXCEPTION(altivec_unavailable); 625 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 626 PROLOG_ADDITION_NONE) 627 /* we can probably do a shorter exception entry for that one... */ 628 EXCEPTION_COMMON(0x200) 629#ifdef CONFIG_ALTIVEC 630BEGIN_FTR_SECTION 631 ld r12,_MSR(r1) 632 andi. r0,r12,MSR_PR; 633 beq- 1f 634 bl load_up_altivec 635 b fast_interrupt_return 6361: 637END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 638#endif 639 addi r3,r1,STACK_FRAME_OVERHEAD 640 bl altivec_unavailable_exception 641 b interrupt_return 642 643/* AltiVec Assist */ 644 START_EXCEPTION(altivec_assist); 645 NORMAL_EXCEPTION_PROLOG(0x220, 646 BOOKE_INTERRUPT_ALTIVEC_ASSIST, 647 PROLOG_ADDITION_NONE) 648 EXCEPTION_COMMON(0x220) 649 addi r3,r1,STACK_FRAME_OVERHEAD 650#ifdef CONFIG_ALTIVEC 651BEGIN_FTR_SECTION 652 bl altivec_assist_exception 653END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 654 REST_NVGPRS(r1) 655#else 656 bl unknown_exception 657#endif 658 b interrupt_return 659 660 661/* Decrementer Interrupt */ 662 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 663 decrementer, timer_interrupt, ACK_DEC) 664 665/* Fixed Interval Timer Interrupt */ 666 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 667 fixed_interval, unknown_exception, ACK_FIT) 668 669/* Watchdog Timer Interrupt */ 670 START_EXCEPTION(watchdog); 671 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 672 PROLOG_ADDITION_NONE) 673 EXCEPTION_COMMON_CRIT(0x9f0) 674 bl special_reg_save 675 CHECK_NAPPING(); 676 addi r3,r1,STACK_FRAME_OVERHEAD 677#ifdef CONFIG_BOOKE_WDT 678 bl WatchdogException 679#else 680 bl unknown_nmi_exception 681#endif 682 b ret_from_crit_except 683 684/* System Call Interrupt */ 685 START_EXCEPTION(system_call) 686 mr r9,r13 /* keep a copy of userland r13 */ 687 mfspr r11,SPRN_SRR0 /* get return address */ 688 mfspr r12,SPRN_SRR1 /* get previous MSR */ 689 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 690 b system_call_common 691 692/* Auxiliary Processor Unavailable Interrupt */ 693 START_EXCEPTION(ap_unavailable); 694 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 695 PROLOG_ADDITION_NONE) 696 EXCEPTION_COMMON(0xf20) 697 addi r3,r1,STACK_FRAME_OVERHEAD 698 bl unknown_exception 699 b interrupt_return 700 701/* Debug exception as a critical interrupt*/ 702 START_EXCEPTION(debug_crit); 703 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 704 PROLOG_ADDITION_2REGS) 705 706 /* 707 * If there is a single step or branch-taken exception in an 708 * exception entry sequence, it was probably meant to apply to 709 * the code where the exception occurred (since exception entry 710 * doesn't turn off DE automatically). We simulate the effect 711 * of turning off DE on entry to an exception handler by turning 712 * off DE in the CSRR1 value and clearing the debug status. 713 */ 714 715 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 716 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 717 beq+ 1f 718 719#ifdef CONFIG_RELOCATABLE 720 ld r15,PACATOC(r13) 721 ld r14,interrupt_base_book3e@got(r15) 722 ld r15,__end_interrupts@got(r15) 723 cmpld cr0,r10,r14 724 cmpld cr1,r10,r15 725#else 726 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e) 727 cmpld cr0, r10, r14 728 LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts) 729 cmpld cr1, r10, r14 730#endif 731 blt+ cr0,1f 732 bge+ cr1,1f 733 734 /* here it looks like we got an inappropriate debug exception. */ 735 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 736 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 737 mtspr SPRN_DBSR,r14 738 mtspr SPRN_CSRR1,r11 739 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 740 ld r1,PACA_EXCRIT+EX_R1(r13) 741 ld r14,PACA_EXCRIT+EX_R14(r13) 742 ld r15,PACA_EXCRIT+EX_R15(r13) 743 mtcr r10 744 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 745 ld r11,PACA_EXCRIT+EX_R11(r13) 746 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 747 rfci 748 749 /* Normal debug exception */ 750 /* XXX We only handle coming from userspace for now since we can't 751 * quite save properly an interrupted kernel state yet 752 */ 7531: andi. r14,r11,MSR_PR; /* check for userspace again */ 754 beq kernel_dbg_exc; /* if from kernel mode */ 755 756 /* Now we mash up things to make it look like we are coming on a 757 * normal exception 758 */ 759 mfspr r14,SPRN_DBSR 760 std r14,_DSISR(r1) 761 ld r14,PACA_EXCRIT+EX_R14(r13) 762 ld r15,PACA_EXCRIT+EX_R15(r13) 763 EXCEPTION_COMMON_CRIT(0xd00) 764 addi r3,r1,STACK_FRAME_OVERHEAD 765 bl DebugException 766 REST_NVGPRS(r1) 767 b interrupt_return 768 769kernel_dbg_exc: 770 b . /* NYI */ 771 772/* Debug exception as a debug interrupt*/ 773 START_EXCEPTION(debug_debug); 774 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 775 PROLOG_ADDITION_2REGS) 776 777 /* 778 * If there is a single step or branch-taken exception in an 779 * exception entry sequence, it was probably meant to apply to 780 * the code where the exception occurred (since exception entry 781 * doesn't turn off DE automatically). We simulate the effect 782 * of turning off DE on entry to an exception handler by turning 783 * off DE in the DSRR1 value and clearing the debug status. 784 */ 785 786 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 787 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 788 beq+ 1f 789 790#ifdef CONFIG_RELOCATABLE 791 ld r15,PACATOC(r13) 792 ld r14,interrupt_base_book3e@got(r15) 793 ld r15,__end_interrupts@got(r15) 794 cmpld cr0,r10,r14 795 cmpld cr1,r10,r15 796#else 797 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e) 798 cmpld cr0, r10, r14 799 LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts) 800 cmpld cr1, r10, r14 801#endif 802 blt+ cr0,1f 803 bge+ cr1,1f 804 805 /* here it looks like we got an inappropriate debug exception. */ 806 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 807 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 808 mtspr SPRN_DBSR,r14 809 mtspr SPRN_DSRR1,r11 810 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 811 ld r1,PACA_EXDBG+EX_R1(r13) 812 ld r14,PACA_EXDBG+EX_R14(r13) 813 ld r15,PACA_EXDBG+EX_R15(r13) 814 mtcr r10 815 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 816 ld r11,PACA_EXDBG+EX_R11(r13) 817 mfspr r13,SPRN_SPRG_DBG_SCRATCH 818 rfdi 819 820 /* Normal debug exception */ 821 /* XXX We only handle coming from userspace for now since we can't 822 * quite save properly an interrupted kernel state yet 823 */ 8241: andi. r14,r11,MSR_PR; /* check for userspace again */ 825 beq kernel_dbg_exc; /* if from kernel mode */ 826 827 /* Now we mash up things to make it look like we are coming on a 828 * normal exception 829 */ 830 mfspr r14,SPRN_DBSR 831 std r14,_DSISR(r1) 832 ld r14,PACA_EXDBG+EX_R14(r13) 833 ld r15,PACA_EXDBG+EX_R15(r13) 834 EXCEPTION_COMMON_DBG(0xd08) 835 addi r3,r1,STACK_FRAME_OVERHEAD 836 bl DebugException 837 REST_NVGPRS(r1) 838 b interrupt_return 839 840 START_EXCEPTION(perfmon); 841 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 842 PROLOG_ADDITION_NONE) 843 EXCEPTION_COMMON(0x260) 844 CHECK_NAPPING() 845 addi r3,r1,STACK_FRAME_OVERHEAD 846 bl performance_monitor_exception 847 b interrupt_return 848 849/* Doorbell interrupt */ 850 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 851 doorbell, doorbell_exception, ACK_NONE) 852 853/* Doorbell critical Interrupt */ 854 START_EXCEPTION(doorbell_crit); 855 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 856 PROLOG_ADDITION_NONE) 857 EXCEPTION_COMMON_CRIT(0x2a0) 858 bl special_reg_save 859 CHECK_NAPPING(); 860 addi r3,r1,STACK_FRAME_OVERHEAD 861 bl unknown_nmi_exception 862 b ret_from_crit_except 863 864/* 865 * Guest doorbell interrupt 866 * This general exception use GSRRx save/restore registers 867 */ 868 START_EXCEPTION(guest_doorbell); 869 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 870 PROLOG_ADDITION_NONE) 871 EXCEPTION_COMMON(0x2c0) 872 addi r3,r1,STACK_FRAME_OVERHEAD 873 bl unknown_exception 874 b interrupt_return 875 876/* Guest Doorbell critical Interrupt */ 877 START_EXCEPTION(guest_doorbell_crit); 878 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 879 PROLOG_ADDITION_NONE) 880 EXCEPTION_COMMON_CRIT(0x2e0) 881 bl special_reg_save 882 CHECK_NAPPING(); 883 addi r3,r1,STACK_FRAME_OVERHEAD 884 bl unknown_nmi_exception 885 b ret_from_crit_except 886 887/* Hypervisor call */ 888 START_EXCEPTION(hypercall); 889 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 890 PROLOG_ADDITION_NONE) 891 EXCEPTION_COMMON(0x310) 892 addi r3,r1,STACK_FRAME_OVERHEAD 893 bl unknown_exception 894 b interrupt_return 895 896/* Embedded Hypervisor priviledged */ 897 START_EXCEPTION(ehpriv); 898 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 899 PROLOG_ADDITION_NONE) 900 EXCEPTION_COMMON(0x320) 901 addi r3,r1,STACK_FRAME_OVERHEAD 902 bl unknown_exception 903 b interrupt_return 904 905/* LRAT Error interrupt */ 906 START_EXCEPTION(lrat_error); 907 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, 908 PROLOG_ADDITION_NONE) 909 EXCEPTION_COMMON(0x340) 910 addi r3,r1,STACK_FRAME_OVERHEAD 911 bl unknown_exception 912 b interrupt_return 913 914.macro SEARCH_RESTART_TABLE 915#ifdef CONFIG_RELOCATABLE 916 ld r11,PACATOC(r13) 917 ld r14,__start___restart_table@got(r11) 918 ld r15,__stop___restart_table@got(r11) 919#else 920 LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table) 921 LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table) 922#endif 923300: 924 cmpd r14,r15 925 beq 302f 926 ld r11,0(r14) 927 cmpld r10,r11 928 blt 301f 929 ld r11,8(r14) 930 cmpld r10,r11 931 bge 301f 932 ld r11,16(r14) 933 b 303f 934301: 935 addi r14,r14,24 936 b 300b 937302: 938 li r11,0 939303: 940.endm 941 942/* 943 * An interrupt came in while soft-disabled; We mark paca->irq_happened 944 * accordingly and if the interrupt is level sensitive, we hard disable 945 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so 946 * keep these in synch. 947 */ 948 949.macro masked_interrupt_book3e paca_irq full_mask 950 std r14,PACA_EXGEN+EX_R14(r13) 951 std r15,PACA_EXGEN+EX_R15(r13) 952 953 lbz r10,PACAIRQHAPPENED(r13) 954 .if \full_mask == 1 955 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS 956 .else 957 ori r10,r10,\paca_irq 958 .endif 959 stb r10,PACAIRQHAPPENED(r13) 960 961 .if \full_mask == 1 962 xori r11,r11,MSR_EE /* clear MSR_EE */ 963 mtspr SPRN_SRR1,r11 964 .endif 965 966 mfspr r10,SPRN_SRR0 967 SEARCH_RESTART_TABLE 968 cmpdi r11,0 969 beq 1f 970 mtspr SPRN_SRR0,r11 /* return to restart address */ 9711: 972 973 lwz r11,PACA_EXGEN+EX_CR(r13) 974 mtcr r11 975 ld r10,PACA_EXGEN+EX_R10(r13) 976 ld r11,PACA_EXGEN+EX_R11(r13) 977 ld r14,PACA_EXGEN+EX_R14(r13) 978 ld r15,PACA_EXGEN+EX_R15(r13) 979 mfspr r13,SPRN_SPRG_GEN_SCRATCH 980 rfi 981 b . 982.endm 983 984masked_interrupt_book3e_0x500: 985 masked_interrupt_book3e PACA_IRQ_EE 1 986 987masked_interrupt_book3e_0x900: 988 ACK_DEC(r10); 989 masked_interrupt_book3e PACA_IRQ_DEC 0 990 991masked_interrupt_book3e_0x980: 992 ACK_FIT(r10); 993 masked_interrupt_book3e PACA_IRQ_DEC 0 994 995masked_interrupt_book3e_0x280: 996masked_interrupt_book3e_0x2c0: 997 masked_interrupt_book3e PACA_IRQ_DBELL 0 998 999/* 1000 * This is called from 0x300 and 0x400 handlers after the prologs with 1001 * r14 and r15 containing the fault address and error code, with the 1002 * original values stashed away in the PACA 1003 */ 1004storage_fault_common: 1005 addi r3,r1,STACK_FRAME_OVERHEAD 1006 bl do_page_fault 1007 b interrupt_return 1008 1009/* 1010 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 1011 * continues here. 1012 */ 1013alignment_more: 1014 addi r3,r1,STACK_FRAME_OVERHEAD 1015 bl alignment_exception 1016 REST_NVGPRS(r1) 1017 b interrupt_return 1018 1019/* 1020 * Trampolines used when spotting a bad kernel stack pointer in 1021 * the exception entry code. 1022 * 1023 * TODO: move some bits like SRR0 read to trampoline, pass PACA 1024 * index around, etc... to handle crit & mcheck 1025 */ 1026BAD_STACK_TRAMPOLINE(0x000) 1027BAD_STACK_TRAMPOLINE(0x100) 1028BAD_STACK_TRAMPOLINE(0x200) 1029BAD_STACK_TRAMPOLINE(0x220) 1030BAD_STACK_TRAMPOLINE(0x260) 1031BAD_STACK_TRAMPOLINE(0x280) 1032BAD_STACK_TRAMPOLINE(0x2a0) 1033BAD_STACK_TRAMPOLINE(0x2c0) 1034BAD_STACK_TRAMPOLINE(0x2e0) 1035BAD_STACK_TRAMPOLINE(0x300) 1036BAD_STACK_TRAMPOLINE(0x310) 1037BAD_STACK_TRAMPOLINE(0x320) 1038BAD_STACK_TRAMPOLINE(0x340) 1039BAD_STACK_TRAMPOLINE(0x400) 1040BAD_STACK_TRAMPOLINE(0x500) 1041BAD_STACK_TRAMPOLINE(0x600) 1042BAD_STACK_TRAMPOLINE(0x700) 1043BAD_STACK_TRAMPOLINE(0x800) 1044BAD_STACK_TRAMPOLINE(0x900) 1045BAD_STACK_TRAMPOLINE(0x980) 1046BAD_STACK_TRAMPOLINE(0x9f0) 1047BAD_STACK_TRAMPOLINE(0xa00) 1048BAD_STACK_TRAMPOLINE(0xb00) 1049BAD_STACK_TRAMPOLINE(0xc00) 1050BAD_STACK_TRAMPOLINE(0xd00) 1051BAD_STACK_TRAMPOLINE(0xd08) 1052BAD_STACK_TRAMPOLINE(0xe00) 1053BAD_STACK_TRAMPOLINE(0xf00) 1054BAD_STACK_TRAMPOLINE(0xf20) 1055 1056 .globl bad_stack_book3e 1057bad_stack_book3e: 1058 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 1059 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 1060 ld r1,PACAEMERGSP(r13) 1061 subi r1,r1,64+INT_FRAME_SIZE 1062 std r10,_NIP(r1) 1063 std r11,_MSR(r1) 1064 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 1065 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 1066 std r10,GPR1(r1) 1067 std r11,_CCR(r1) 1068 mfspr r10,SPRN_DEAR 1069 mfspr r11,SPRN_ESR 1070 std r10,_DAR(r1) 1071 std r11,_DSISR(r1) 1072 std r0,GPR0(r1); /* save r0 in stackframe */ \ 1073 std r2,GPR2(r1); /* save r2 in stackframe */ \ 1074 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 1075 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 1076 std r9,GPR9(r1); /* save r9 in stackframe */ \ 1077 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1078 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1079 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1080 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1081 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1082 std r12,GPR12(r1); /* save r12 in stackframe */ \ 1083 std r5,GPR13(r1); /* save it to stackframe */ \ 1084 mflr r10 1085 mfctr r11 1086 mfxer r12 1087 std r10,_LINK(r1) 1088 std r11,_CTR(r1) 1089 std r12,_XER(r1) 1090 SAVE_10GPRS(14,r1) 1091 SAVE_8GPRS(24,r1) 1092 lhz r12,PACA_TRAP_SAVE(r13) 1093 std r12,_TRAP(r1) 1094 addi r11,r1,INT_FRAME_SIZE 1095 std r11,0(r1) 1096 li r12,0 1097 std r12,0(r11) 1098 ld r2,PACATOC(r13) 10991: addi r3,r1,STACK_FRAME_OVERHEAD 1100 bl kernel_bad_stack 1101 b 1b 1102 1103/* 1104 * Setup the initial TLB for a core. This current implementation 1105 * assume that whatever we are running off will not conflict with 1106 * the new mapping at PAGE_OFFSET. 1107 */ 1108_GLOBAL(initial_tlb_book3e) 1109 1110 /* Look for the first TLB with IPROT set */ 1111 mfspr r4,SPRN_TLB0CFG 1112 andi. r3,r4,TLBnCFG_IPROT 1113 lis r3,MAS0_TLBSEL(0)@h 1114 bne found_iprot 1115 1116 mfspr r4,SPRN_TLB1CFG 1117 andi. r3,r4,TLBnCFG_IPROT 1118 lis r3,MAS0_TLBSEL(1)@h 1119 bne found_iprot 1120 1121 mfspr r4,SPRN_TLB2CFG 1122 andi. r3,r4,TLBnCFG_IPROT 1123 lis r3,MAS0_TLBSEL(2)@h 1124 bne found_iprot 1125 1126 lis r3,MAS0_TLBSEL(3)@h 1127 mfspr r4,SPRN_TLB3CFG 1128 /* fall through */ 1129 1130found_iprot: 1131 andi. r5,r4,TLBnCFG_HES 1132 bne have_hes 1133 1134 mflr r8 /* save LR */ 1135/* 1. Find the index of the entry we're executing in 1136 * 1137 * r3 = MAS0_TLBSEL (for the iprot array) 1138 * r4 = SPRN_TLBnCFG 1139 */ 1140 bl invstr /* Find our address */ 1141invstr: mflr r6 /* Make it accessible */ 1142 mfmsr r7 1143 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 1144 mfspr r7,SPRN_PID 1145 slwi r7,r7,16 1146 or r7,r7,r5 1147 mtspr SPRN_MAS6,r7 1148 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 1149 1150 mfspr r3,SPRN_MAS0 1151 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 1152 1153 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 1154 oris r7,r7,MAS1_IPROT@h 1155 mtspr SPRN_MAS1,r7 1156 tlbwe 1157 1158/* 2. Invalidate all entries except the entry we're executing in 1159 * 1160 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1161 * r4 = SPRN_TLBnCFG 1162 * r5 = ESEL of entry we are running in 1163 */ 1164 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 1165 li r6,0 /* Set Entry counter to 0 */ 11661: mr r7,r3 /* Set MAS0(TLBSEL) */ 1167 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1168 mtspr SPRN_MAS0,r7 1169 tlbre 1170 mfspr r7,SPRN_MAS1 1171 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 1172 cmpw r5,r6 1173 beq skpinv /* Dont update the current execution TLB */ 1174 mtspr SPRN_MAS1,r7 1175 tlbwe 1176 isync 1177skpinv: addi r6,r6,1 /* Increment */ 1178 cmpw r6,r4 /* Are we done? */ 1179 bne 1b /* If not, repeat */ 1180 1181 /* Invalidate all TLBs */ 1182 PPC_TLBILX_ALL(0,R0) 1183 sync 1184 isync 1185 1186/* 3. Setup a temp mapping and jump to it 1187 * 1188 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1189 * r5 = ESEL of entry we are running in 1190 */ 1191 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 1192 addi r7,r7,0x1 1193 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 1194 mtspr SPRN_MAS0,r4 1195 tlbre 1196 1197 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 1198 mtspr SPRN_MAS0,r4 1199 1200 mfspr r7,SPRN_MAS1 1201 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 1202 mtspr SPRN_MAS1,r6 1203 1204 tlbwe 1205 1206 mfmsr r6 1207 xori r6,r6,MSR_IS 1208 mtspr SPRN_SRR1,r6 1209 bl 1f /* Find our address */ 12101: mflr r6 1211 addi r6,r6,(2f - 1b) 1212 mtspr SPRN_SRR0,r6 1213 rfi 12142: 1215 1216/* 4. Clear out PIDs & Search info 1217 * 1218 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1219 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1220 * r5 = MAS3 1221 */ 1222 li r6,0 1223 mtspr SPRN_MAS6,r6 1224 mtspr SPRN_PID,r6 1225 1226/* 5. Invalidate mapping we started in 1227 * 1228 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1229 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1230 * r5 = MAS3 1231 */ 1232 mtspr SPRN_MAS0,r3 1233 tlbre 1234 mfspr r6,SPRN_MAS1 1235 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ 1236 mtspr SPRN_MAS1,r6 1237 tlbwe 1238 sync 1239 isync 1240 1241/* 6. Setup KERNELBASE mapping in TLB[0] 1242 * 1243 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1244 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1245 * r5 = MAS3 1246 */ 1247 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1248 mtspr SPRN_MAS0,r3 1249 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1250 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1251 mtspr SPRN_MAS1,r6 1252 1253 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED) 1254 mtspr SPRN_MAS2,r6 1255 1256 rlwinm r5,r5,0,0,25 1257 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1258 mtspr SPRN_MAS3,r5 1259 li r5,-1 1260 rlwinm r5,r5,0,0,25 1261 1262 tlbwe 1263 1264/* 7. Jump to KERNELBASE mapping 1265 * 1266 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1267 */ 1268 /* Now we branch the new virtual address mapped by this entry */ 1269 bl 1f /* Find our address */ 12701: mflr r6 1271 addi r6,r6,(2f - 1b) 1272 tovirt(r6,r6) 1273 lis r7,MSR_KERNEL@h 1274 ori r7,r7,MSR_KERNEL@l 1275 mtspr SPRN_SRR0,r6 1276 mtspr SPRN_SRR1,r7 1277 rfi /* start execution out of TLB1[0] entry */ 12782: 1279 1280/* 8. Clear out the temp mapping 1281 * 1282 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1283 */ 1284 mtspr SPRN_MAS0,r4 1285 tlbre 1286 mfspr r5,SPRN_MAS1 1287 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ 1288 mtspr SPRN_MAS1,r5 1289 tlbwe 1290 sync 1291 isync 1292 1293 /* We translate LR and return */ 1294 tovirt(r8,r8) 1295 mtlr r8 1296 blr 1297 1298have_hes: 1299 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1300 * kernel linear mapping. We also set MAS8 once for all here though 1301 * that will have to be made dependent on whether we are running under 1302 * a hypervisor I suppose. 1303 */ 1304 1305 /* BEWARE, MAGIC 1306 * This code is called as an ordinary function on the boot CPU. But to 1307 * avoid duplication, this code is also used in SCOM bringup of 1308 * secondary CPUs. We read the code between the initial_tlb_code_start 1309 * and initial_tlb_code_end labels one instruction at a time and RAM it 1310 * into the new core via SCOM. That doesn't process branches, so there 1311 * must be none between those two labels. It also means if this code 1312 * ever takes any parameters, the SCOM code must also be updated to 1313 * provide them. 1314 */ 1315 .globl a2_tlbinit_code_start 1316a2_tlbinit_code_start: 1317 1318 ori r11,r3,MAS0_WQ_ALLWAYS 1319 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1320 mtspr SPRN_MAS0,r11 1321 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1322 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1323 mtspr SPRN_MAS1,r3 1324 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1325 mtspr SPRN_MAS2,r3 1326 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1327 mtspr SPRN_MAS7_MAS3,r3 1328 li r3,0 1329 mtspr SPRN_MAS8,r3 1330 1331 /* Write the TLB entry */ 1332 tlbwe 1333 1334 .globl a2_tlbinit_after_linear_map 1335a2_tlbinit_after_linear_map: 1336 1337 /* Now we branch the new virtual address mapped by this entry */ 1338#ifdef CONFIG_RELOCATABLE 1339 ld r5,PACATOC(r13) 1340 ld r3,1f@got(r5) 1341#else 1342 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f) 1343#endif 1344 mtctr r3 1345 bctr 1346 13471: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1348 * else (including IPROTed things left by firmware) 1349 * r4 = TLBnCFG 1350 * r3 = current address (more or less) 1351 */ 1352 1353 li r5,0 1354 mtspr SPRN_MAS6,r5 1355 tlbsx 0,r3 1356 1357 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1358 rlwinm r10,r4,8,0xff 1359 addi r10,r10,-1 /* Get inner loop mask */ 1360 1361 li r3,1 1362 1363 mfspr r5,SPRN_MAS1 1364 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1365 1366 mfspr r6,SPRN_MAS2 1367 rldicr r6,r6,0,51 /* Extract EPN */ 1368 1369 mfspr r7,SPRN_MAS0 1370 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1371 1372 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1373 13742: add r4,r3,r8 1375 and r4,r4,r10 1376 1377 rlwimi r7,r4,16,MAS0_ESEL_MASK 1378 1379 mtspr SPRN_MAS0,r7 1380 mtspr SPRN_MAS1,r5 1381 mtspr SPRN_MAS2,r6 1382 tlbwe 1383 1384 addi r3,r3,1 1385 and. r4,r3,r10 1386 1387 bne 3f 1388 addis r6,r6,(1<<30)@h 13893: 1390 cmpw r3,r9 1391 blt 2b 1392 1393 .globl a2_tlbinit_after_iprot_flush 1394a2_tlbinit_after_iprot_flush: 1395 1396 PPC_TLBILX(0,0,R0) 1397 sync 1398 isync 1399 1400 .globl a2_tlbinit_code_end 1401a2_tlbinit_code_end: 1402 1403 /* We translate LR and return */ 1404 mflr r3 1405 tovirt(r3,r3) 1406 mtlr r3 1407 blr 1408 1409/* 1410 * Main entry (boot CPU, thread 0) 1411 * 1412 * We enter here from head_64.S, possibly after the prom_init trampoline 1413 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1414 * mode. Anything else is as it was left by the bootloader 1415 * 1416 * Initial requirements of this port: 1417 * 1418 * - Kernel loaded at 0 physical 1419 * - A good lump of memory mapped 0:0 by UTLB entry 0 1420 * - MSR:IS & MSR:DS set to 0 1421 * 1422 * Note that some of the above requirements will be relaxed in the future 1423 * as the kernel becomes smarter at dealing with different initial conditions 1424 * but for now you have to be careful 1425 */ 1426_GLOBAL(start_initialization_book3e) 1427 mflr r28 1428 1429 /* First, we need to setup some initial TLBs to map the kernel 1430 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1431 * and always use AS 0, so we just set it up to match our link 1432 * address and never use 0 based addresses. 1433 */ 1434 bl initial_tlb_book3e 1435 1436 /* Init global core bits */ 1437 bl init_core_book3e 1438 1439 /* Init per-thread bits */ 1440 bl init_thread_book3e 1441 1442 /* Return to common init code */ 1443 tovirt(r28,r28) 1444 mtlr r28 1445 blr 1446 1447 1448/* 1449 * Secondary core/processor entry 1450 * 1451 * This is entered for thread 0 of a secondary core, all other threads 1452 * are expected to be stopped. It's similar to start_initialization_book3e 1453 * except that it's generally entered from the holding loop in head_64.S 1454 * after CPUs have been gathered by Open Firmware. 1455 * 1456 * We assume we are in 32 bits mode running with whatever TLB entry was 1457 * set for us by the firmware or POR engine. 1458 */ 1459_GLOBAL(book3e_secondary_core_init_tlb_set) 1460 li r4,1 1461 b generic_secondary_smp_init 1462 1463_GLOBAL(book3e_secondary_core_init) 1464 mflr r28 1465 1466 /* Do we need to setup initial TLB entry ? */ 1467 cmplwi r4,0 1468 bne 2f 1469 1470 /* Setup TLB for this core */ 1471 bl initial_tlb_book3e 1472 1473 /* We can return from the above running at a different 1474 * address, so recalculate r2 (TOC) 1475 */ 1476 bl relative_toc 1477 1478 /* Init global core bits */ 14792: bl init_core_book3e 1480 1481 /* Init per-thread bits */ 14823: bl init_thread_book3e 1483 1484 /* Return to common init code at proper virtual address. 1485 * 1486 * Due to various previous assumptions, we know we entered this 1487 * function at either the final PAGE_OFFSET mapping or using a 1488 * 1:1 mapping at 0, so we don't bother doing a complicated check 1489 * here, we just ensure the return address has the right top bits. 1490 * 1491 * Note that if we ever want to be smarter about where we can be 1492 * started from, we have to be careful that by the time we reach 1493 * the code below we may already be running at a different location 1494 * than the one we were called from since initial_tlb_book3e can 1495 * have moved us already. 1496 */ 1497 cmpdi cr0,r28,0 1498 blt 1f 1499 lis r3,PAGE_OFFSET@highest 1500 sldi r3,r3,32 1501 or r28,r28,r3 15021: mtlr r28 1503 blr 1504 1505_GLOBAL(book3e_secondary_thread_init) 1506 mflr r28 1507 b 3b 1508 1509 .globl init_core_book3e 1510init_core_book3e: 1511 /* Establish the interrupt vector base */ 1512 tovirt(r2,r2) 1513 LOAD_REG_ADDR(r3, interrupt_base_book3e) 1514 mtspr SPRN_IVPR,r3 1515 sync 1516 blr 1517 1518init_thread_book3e: 1519 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1520 mtspr SPRN_EPCR,r3 1521 1522 /* Make sure interrupts are off */ 1523 wrteei 0 1524 1525 /* disable all timers and clear out status */ 1526 li r3,0 1527 mtspr SPRN_TCR,r3 1528 mfspr r3,SPRN_TSR 1529 mtspr SPRN_TSR,r3 1530 1531 blr 1532 1533_GLOBAL(__setup_base_ivors) 1534 SET_IVOR(0, 0x020) /* Critical Input */ 1535 SET_IVOR(1, 0x000) /* Machine Check */ 1536 SET_IVOR(2, 0x060) /* Data Storage */ 1537 SET_IVOR(3, 0x080) /* Instruction Storage */ 1538 SET_IVOR(4, 0x0a0) /* External Input */ 1539 SET_IVOR(5, 0x0c0) /* Alignment */ 1540 SET_IVOR(6, 0x0e0) /* Program */ 1541 SET_IVOR(7, 0x100) /* FP Unavailable */ 1542 SET_IVOR(8, 0x120) /* System Call */ 1543 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1544 SET_IVOR(10, 0x160) /* Decrementer */ 1545 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1546 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1547 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1548 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1549 SET_IVOR(15, 0x040) /* Debug */ 1550 1551 sync 1552 1553 blr 1554 1555_GLOBAL(setup_altivec_ivors) 1556 SET_IVOR(32, 0x200) /* AltiVec Unavailable */ 1557 SET_IVOR(33, 0x220) /* AltiVec Assist */ 1558 blr 1559 1560_GLOBAL(setup_perfmon_ivor) 1561 SET_IVOR(35, 0x260) /* Performance Monitor */ 1562 blr 1563 1564_GLOBAL(setup_doorbell_ivors) 1565 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1566 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1567 blr 1568 1569_GLOBAL(setup_ehv_ivors) 1570 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1571 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1572 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1573 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1574 blr 1575 1576_GLOBAL(setup_lrat_ivor) 1577 SET_IVOR(42, 0x340) /* LRAT Error */ 1578 blr 1579