1*2874c5fdSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-or-later */ 22e974251SOlof Johansson/* 32e974251SOlof Johansson * This file contains low level CPU setup functions. 42e974251SOlof Johansson * Copyright (C) 2003 Benjamin Herrenschmidt ([email protected]) 52e974251SOlof Johansson */ 62e974251SOlof Johansson 72e974251SOlof Johansson#include <asm/processor.h> 82e974251SOlof Johansson#include <asm/page.h> 92e974251SOlof Johansson#include <asm/cputable.h> 102e974251SOlof Johansson#include <asm/ppc_asm.h> 112e974251SOlof Johansson#include <asm/asm-offsets.h> 122e974251SOlof Johansson#include <asm/cache.h> 132e974251SOlof Johansson 14f39b7a55SOlof Johansson_GLOBAL(__cpu_preinit_ppc970) 15f39b7a55SOlof Johansson /* Do nothing if not running in HV mode */ 162e974251SOlof Johansson mfmsr r0 172e974251SOlof Johansson rldicl. r0,r0,4,63 182e974251SOlof Johansson beqlr 192e974251SOlof Johansson 202e974251SOlof Johansson /* Make sure HID4:rm_ci is off before MMU is turned off, that large 212e974251SOlof Johansson * pages are enabled with HID4:61 and clear HID5:DCBZ_size and 222e974251SOlof Johansson * HID5:DCBZ32_ill 232e974251SOlof Johansson */ 242e974251SOlof Johansson li r0,0 252e974251SOlof Johansson mfspr r3,SPRN_HID4 262e974251SOlof Johansson rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 272e974251SOlof Johansson rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */ 282e974251SOlof Johansson sync 292e974251SOlof Johansson mtspr SPRN_HID4,r3 302e974251SOlof Johansson isync 312e974251SOlof Johansson sync 322e974251SOlof Johansson mfspr r3,SPRN_HID5 332e974251SOlof Johansson rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */ 342e974251SOlof Johansson sync 352e974251SOlof Johansson mtspr SPRN_HID5,r3 362e974251SOlof Johansson isync 372e974251SOlof Johansson sync 382e974251SOlof Johansson 392e974251SOlof Johansson /* Setup some basic HID1 features */ 402e974251SOlof Johansson mfspr r0,SPRN_HID1 412e974251SOlof Johansson li r3,0x1200 /* enable i-fetch cacheability */ 422e974251SOlof Johansson sldi r3,r3,44 /* and prefetch */ 432e974251SOlof Johansson or r0,r0,r3 442e974251SOlof Johansson mtspr SPRN_HID1,r0 452e974251SOlof Johansson mtspr SPRN_HID1,r0 462e974251SOlof Johansson isync 472e974251SOlof Johansson 482e974251SOlof Johansson /* Clear HIOR */ 492e974251SOlof Johansson li r0,0 502e974251SOlof Johansson sync 512e974251SOlof Johansson mtspr SPRN_HIOR,0 /* Clear interrupt prefix */ 522e974251SOlof Johansson isync 532e974251SOlof Johansson blr 542e974251SOlof Johansson 552e974251SOlof Johansson/* Definitions for the table use to save CPU states */ 562e974251SOlof Johansson#define CS_HID0 0 572e974251SOlof Johansson#define CS_HID1 8 582e974251SOlof Johansson#define CS_HID4 16 592e974251SOlof Johansson#define CS_HID5 24 602e974251SOlof Johansson#define CS_SIZE 32 612e974251SOlof Johansson 622e974251SOlof Johansson .data 632e974251SOlof Johansson .balign L1_CACHE_BYTES,0 642e974251SOlof Johanssoncpu_state_storage: 652e974251SOlof Johansson .space CS_SIZE 662e974251SOlof Johansson .balign L1_CACHE_BYTES,0 672e974251SOlof Johansson .text 682e974251SOlof Johansson 692e974251SOlof Johansson 70f39b7a55SOlof Johansson_GLOBAL(__setup_cpu_ppc970) 71f39b7a55SOlof Johansson /* Do nothing if not running in HV mode */ 722e974251SOlof Johansson mfmsr r0 732e974251SOlof Johansson rldicl. r0,r0,4,63 74969391c5SPaul Mackerras beq no_hv_mode 75f39b7a55SOlof Johansson 76f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 77f39b7a55SOlof Johansson li r11,5 /* clear DOZE and SLEEP */ 78f39b7a55SOlof Johansson rldimi r0,r11,52,8 /* set NAP and DPM */ 79ea0763a7SPaul Mackerras li r11,0 80ea0763a7SPaul Mackerras rldimi r0,r11,32,31 /* clear EN_ATTN */ 815b43d20aSOlof Johansson b load_hids /* Jump to shared code */ 825b43d20aSOlof Johansson 835b43d20aSOlof Johansson 845b43d20aSOlof Johansson_GLOBAL(__setup_cpu_ppc970MP) 855b43d20aSOlof Johansson /* Do nothing if not running in HV mode */ 865b43d20aSOlof Johansson mfmsr r0 875b43d20aSOlof Johansson rldicl. r0,r0,4,63 88969391c5SPaul Mackerras beq no_hv_mode 895b43d20aSOlof Johansson 905b43d20aSOlof Johansson mfspr r0,SPRN_HID0 915b43d20aSOlof Johansson li r11,0x15 /* clear DOZE and SLEEP */ 925b43d20aSOlof Johansson rldimi r0,r11,52,6 /* set DEEPNAP, NAP and DPM */ 935b43d20aSOlof Johansson li r11,0 945b43d20aSOlof Johansson rldimi r0,r11,32,31 /* clear EN_ATTN */ 955b43d20aSOlof Johansson 965b43d20aSOlof Johanssonload_hids: 97f39b7a55SOlof Johansson mtspr SPRN_HID0,r0 98f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 99f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 100f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 101f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 102f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 103f39b7a55SOlof Johansson mfspr r0,SPRN_HID0 104f39b7a55SOlof Johansson sync 105f39b7a55SOlof Johansson isync 106f39b7a55SOlof Johansson 107969391c5SPaul Mackerras /* Try to set LPES = 01 in HID4 */ 108969391c5SPaul Mackerras mfspr r0,SPRN_HID4 109969391c5SPaul Mackerras clrldi r0,r0,1 /* clear LPES0 */ 110969391c5SPaul Mackerras ori r0,r0,HID4_LPES1 /* set LPES1 */ 111969391c5SPaul Mackerras sync 112969391c5SPaul Mackerras mtspr SPRN_HID4,r0 113969391c5SPaul Mackerras isync 114969391c5SPaul Mackerras 115f39b7a55SOlof Johansson /* Save away cpu state */ 116e31aa453SPaul Mackerras LOAD_REG_ADDR(r5,cpu_state_storage) 1172e974251SOlof Johansson 1182e974251SOlof Johansson /* Save HID0,1,4 and 5 */ 1192e974251SOlof Johansson mfspr r3,SPRN_HID0 1202e974251SOlof Johansson std r3,CS_HID0(r5) 1212e974251SOlof Johansson mfspr r3,SPRN_HID1 1222e974251SOlof Johansson std r3,CS_HID1(r5) 123969391c5SPaul Mackerras mfspr r4,SPRN_HID4 124969391c5SPaul Mackerras std r4,CS_HID4(r5) 1252e974251SOlof Johansson mfspr r3,SPRN_HID5 1262e974251SOlof Johansson std r3,CS_HID5(r5) 1272e974251SOlof Johansson 128969391c5SPaul Mackerras /* See if we successfully set LPES1 to 1; if not we are in Apple mode */ 129969391c5SPaul Mackerras andi. r4,r4,HID4_LPES1 130969391c5SPaul Mackerras bnelr 131969391c5SPaul Mackerras 132969391c5SPaul Mackerrasno_hv_mode: 133969391c5SPaul Mackerras /* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */ 134969391c5SPaul Mackerras ld r5,CPU_SPEC_FEATURES(r4) 135969391c5SPaul Mackerras LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) 136969391c5SPaul Mackerras andc r5,r5,r6 137969391c5SPaul Mackerras std r5,CPU_SPEC_FEATURES(r4) 1382e974251SOlof Johansson blr 1392e974251SOlof Johansson 1402e974251SOlof Johansson/* Called with no MMU context (typically MSR:IR/DR off) to 1412e974251SOlof Johansson * restore CPU state as backed up by the previous 1422e974251SOlof Johansson * function. This does not include cache setting 1432e974251SOlof Johansson */ 144f39b7a55SOlof Johansson_GLOBAL(__restore_cpu_ppc970) 145f39b7a55SOlof Johansson /* Do nothing if not running in HV mode */ 1462e974251SOlof Johansson mfmsr r0 1472e974251SOlof Johansson rldicl. r0,r0,4,63 1482e974251SOlof Johansson beqlr 1492e974251SOlof Johansson 150e31aa453SPaul Mackerras LOAD_REG_ADDR(r5,cpu_state_storage) 1512e974251SOlof Johansson /* Before accessing memory, we make sure rm_ci is clear */ 1522e974251SOlof Johansson li r0,0 1532e974251SOlof Johansson mfspr r3,SPRN_HID4 1542e974251SOlof Johansson rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 1552e974251SOlof Johansson sync 1562e974251SOlof Johansson mtspr SPRN_HID4,r3 1572e974251SOlof Johansson isync 1582e974251SOlof Johansson sync 1592e974251SOlof Johansson 1602e974251SOlof Johansson /* Clear interrupt prefix */ 1612e974251SOlof Johansson li r0,0 1622e974251SOlof Johansson sync 1632e974251SOlof Johansson mtspr SPRN_HIOR,0 1642e974251SOlof Johansson isync 1652e974251SOlof Johansson 1662e974251SOlof Johansson /* Restore HID0 */ 1672e974251SOlof Johansson ld r3,CS_HID0(r5) 1682e974251SOlof Johansson sync 1692e974251SOlof Johansson isync 1702e974251SOlof Johansson mtspr SPRN_HID0,r3 1712e974251SOlof Johansson mfspr r3,SPRN_HID0 1722e974251SOlof Johansson mfspr r3,SPRN_HID0 1732e974251SOlof Johansson mfspr r3,SPRN_HID0 1742e974251SOlof Johansson mfspr r3,SPRN_HID0 1752e974251SOlof Johansson mfspr r3,SPRN_HID0 1762e974251SOlof Johansson mfspr r3,SPRN_HID0 1772e974251SOlof Johansson sync 1782e974251SOlof Johansson isync 1792e974251SOlof Johansson 1802e974251SOlof Johansson /* Restore HID1 */ 1812e974251SOlof Johansson ld r3,CS_HID1(r5) 1822e974251SOlof Johansson sync 1832e974251SOlof Johansson isync 1842e974251SOlof Johansson mtspr SPRN_HID1,r3 1852e974251SOlof Johansson mtspr SPRN_HID1,r3 1862e974251SOlof Johansson sync 1872e974251SOlof Johansson isync 1882e974251SOlof Johansson 1892e974251SOlof Johansson /* Restore HID4 */ 1902e974251SOlof Johansson ld r3,CS_HID4(r5) 1912e974251SOlof Johansson sync 1922e974251SOlof Johansson isync 1932e974251SOlof Johansson mtspr SPRN_HID4,r3 1942e974251SOlof Johansson sync 1952e974251SOlof Johansson isync 1962e974251SOlof Johansson 1972e974251SOlof Johansson /* Restore HID5 */ 1982e974251SOlof Johansson ld r3,CS_HID5(r5) 1992e974251SOlof Johansson sync 2002e974251SOlof Johansson isync 2012e974251SOlof Johansson mtspr SPRN_HID5,r3 2022e974251SOlof Johansson sync 2032e974251SOlof Johansson isync 2042e974251SOlof Johansson blr 2052e974251SOlof Johansson 206