xref: /linux-6.15/arch/parisc/kernel/perf_asm.S (revision 6ab3d562) 
1
2/*    low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
3 *
4 *    Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
5 *    Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
6 *
7 *    This program is free software; you can redistribute it and/or modify
8 *    it under the terms of the GNU General Public License as published by
9 *    the Free Software Foundation; either version 2 of the License, or
10 *    (at your option) any later version.
11 *
12 *    This program is distributed in the hope that it will be useful,
13 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
14 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 *    GNU General Public License for more details.
16 *
17 *    You should have received a copy of the GNU General Public License
18 *    along with this program; if not, write to the Free Software
19 *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 */
21
22#include <asm/assembly.h>
23
24#ifdef CONFIG_64BIT
25	.level		2.0w
26#endif /* CONFIG_64BIT */
27
28#define MTDIAG_1(gr)    .word 0x14201840 + gr*0x10000
29#define MTDIAG_2(gr)    .word 0x14401840 + gr*0x10000
30#define MFDIAG_1(gr)    .word 0x142008A0 + gr
31#define MFDIAG_2(gr)    .word 0x144008A0 + gr
32#define STDIAG(dr)      .word 0x14000AA0 + dr*0x200000
33#define SFDIAG(dr)      .word 0x14000BA0 + dr*0x200000
34#define DR2_SLOW_RET    53
35
36
37;
38; Enable the performance counters
39;
40; The coprocessor only needs to be enabled when
41; starting/stopping the coprocessor with the pmenb/pmdis.
42;
43	.text
44	.align 32
45
46	.export perf_intrigue_enable_perf_counters,code
47perf_intrigue_enable_perf_counters:
48	.proc
49	.callinfo  frame=0,NO_CALLS
50	.entry
51
52	ldi     0x20,%r25                ; load up perfmon bit
53	mfctl   ccr,%r26                 ; get coprocessor register
54	or      %r25,%r26,%r26             ; set bit
55	mtctl   %r26,ccr                 ; turn on performance coprocessor
56	pmenb                           ; enable performance monitor
57	ssm     0,0                     ; dummy op to ensure completion
58	sync                            ; follow ERS
59	andcm   %r26,%r25,%r26             ; clear bit now
60	mtctl   %r26,ccr                 ; turn off performance coprocessor
61	nop                             ; NOPs as specified in ERS
62	nop
63	nop
64	nop
65	nop
66	nop
67	nop
68	bve    (%r2)
69	nop
70	.exit
71	.procend
72
73	.export perf_intrigue_disable_perf_counters,code
74perf_intrigue_disable_perf_counters:
75	.proc
76	.callinfo  frame=0,NO_CALLS
77	.entry
78	ldi     0x20,%r25                ; load up perfmon bit
79	mfctl   ccr,%r26                 ; get coprocessor register
80	or      %r25,%r26,%r26             ; set bit
81	mtctl   %r26,ccr                 ; turn on performance coprocessor
82	pmdis                           ; disable performance monitor
83	ssm     0,0                     ; dummy op to ensure completion
84	andcm   %r26,%r25,%r26             ; clear bit now
85	bve    (%r2)
86	mtctl   %r26,ccr                 ; turn off performance coprocessor
87	.exit
88	.procend
89
90;***********************************************************************
91;*
92;* Name: perf_rdr_shift_in_W
93;*
94;* Description:
95;*	This routine shifts data in from the RDR in arg0 and returns
96;*	the result in ret0.  If the RDR is <= 64 bits in length, it
97;*	is shifted shifted backup immediately.  This is to compensate
98;*	for RDR10 which has bits that preclude PDC stack operations
99;*	when they are in the wrong state.
100;*
101;* Arguments:
102;*	arg0 : rdr to be read
103;*	arg1 : bit length of rdr
104;*
105;* Returns:
106;*	ret0 = next 64 bits of rdr data from staging register
107;*
108;* Register usage:
109;*	arg0 : rdr to be read
110;*	arg1 : bit length of rdr
111;*	%r24  - original DR2 value
112;*	%r1   - scratch
113;*  %r29  - scratch
114;*
115;* Returns:
116;*	ret0 = RDR data (right justified)
117;*
118;***********************************************************************
119
120	.export perf_rdr_shift_in_W,code
121perf_rdr_shift_in_W:
122	.proc
123	.callinfo frame=0,NO_CALLS
124	.entry
125;
126; read(shift in) the RDR.
127;
128
129; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
130; shifting is done, from or to, remote diagnose registers.
131;
132
133	depdi,z		1,DR2_SLOW_RET,1,%r29
134	MFDIAG_2	(24)
135	or		    %r24,%r29,%r29
136	MTDIAG_2	(29)			; set DR2_SLOW_RET
137
138	nop
139	nop
140	nop
141	nop
142
143;
144; Cacheline start (32-byte cacheline)
145;
146	nop
147	nop
148	nop
149	extrd,u		arg1,63,6,%r1	; setup shift amount by bits to move
150
151	mtsar		%r1
152	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
153	blr  		%r1,%r0		; branch to 8-instruction sequence
154	nop
155
156;
157; Cacheline start (32-byte cacheline)
158;
159
160	;
161	; RDR 0 sequence
162	;
163	SFDIAG		(0)
164	ssm		    0,0
165	MFDIAG_1	(28)
166	shrpd		ret0,%r0,%sar,%r1
167	MTDIAG_1	(1)			; mtdiag %dr1, %r1
168	STDIAG		(0)
169	ssm		    0,0
170	b,n         perf_rdr_shift_in_W_leave
171
172	;
173	; RDR 1 sequence
174	;
175	sync
176	ssm		    0,0
177	SFDIAG		(1)
178	ssm		    0,0
179	MFDIAG_1	(28)
180	ssm		    0,0
181	b,n         perf_rdr_shift_in_W_leave
182	nop
183
184	;
185	; RDR 2 read sequence
186	;
187	SFDIAG		(2)
188	ssm		    0,0
189	MFDIAG_1	(28)
190	shrpd		ret0,%r0,%sar,%r1
191	MTDIAG_1	(1)
192	STDIAG		(2)
193	ssm		    0,0
194	b,n         perf_rdr_shift_in_W_leave
195
196	;
197	; RDR 3 read sequence
198	;
199	b,n         perf_rdr_shift_in_W_leave
200	nop
201	nop
202	nop
203	nop
204	nop
205	nop
206	nop
207
208	;
209	; RDR 4 read sequence
210	;
211	sync
212	ssm		0,0
213	SFDIAG		(4)
214	ssm		0,0
215	MFDIAG_1	(28)
216	b,n         perf_rdr_shift_in_W_leave
217	ssm		0,0
218	nop
219
220	;
221	; RDR 5 read sequence
222	;
223	sync
224	ssm		0,0
225	SFDIAG		(5)
226	ssm		0,0
227	MFDIAG_1	(28)
228	b,n         perf_rdr_shift_in_W_leave
229	ssm		0,0
230	nop
231
232	;
233	; RDR 6 read sequence
234	;
235	sync
236	ssm		0,0
237	SFDIAG		(6)
238	ssm		0,0
239	MFDIAG_1	(28)
240	b,n         perf_rdr_shift_in_W_leave
241	ssm		0,0
242	nop
243
244	;
245	; RDR 7 read sequence
246	;
247	b,n         perf_rdr_shift_in_W_leave
248	nop
249	nop
250	nop
251	nop
252	nop
253	nop
254	nop
255
256	;
257	; RDR 8 read sequence
258	;
259	b,n         perf_rdr_shift_in_W_leave
260	nop
261	nop
262	nop
263	nop
264	nop
265	nop
266	nop
267
268	;
269	; RDR 9 read sequence
270	;
271	b,n         perf_rdr_shift_in_W_leave
272	nop
273	nop
274	nop
275	nop
276	nop
277	nop
278	nop
279
280	;
281	; RDR 10 read sequence
282	;
283	SFDIAG		(10)
284	ssm		0,0
285	MFDIAG_1	(28)
286	shrpd		ret0,%r0,%sar,%r1
287	MTDIAG_1	(1)
288	STDIAG		(10)
289	ssm		0,0
290	b,n         perf_rdr_shift_in_W_leave
291
292	;
293	; RDR 11 read sequence
294	;
295	SFDIAG		(11)
296	ssm		0,0
297	MFDIAG_1	(28)
298	shrpd		ret0,%r0,%sar,%r1
299	MTDIAG_1	(1)
300	STDIAG		(11)
301	ssm		0,0
302	b,n         perf_rdr_shift_in_W_leave
303
304	;
305	; RDR 12 read sequence
306	;
307	b,n         perf_rdr_shift_in_W_leave
308	nop
309	nop
310	nop
311	nop
312	nop
313	nop
314	nop
315
316	;
317	; RDR 13 read sequence
318	;
319	sync
320	ssm		0,0
321	SFDIAG		(13)
322	ssm		0,0
323	MFDIAG_1	(28)
324	b,n         perf_rdr_shift_in_W_leave
325	ssm		0,0
326	nop
327
328	;
329	; RDR 14 read sequence
330	;
331	SFDIAG		(14)
332	ssm		0,0
333	MFDIAG_1	(28)
334	shrpd		ret0,%r0,%sar,%r1
335	MTDIAG_1	(1)
336	STDIAG		(14)
337	ssm		0,0
338	b,n         perf_rdr_shift_in_W_leave
339
340	;
341	; RDR 15 read sequence
342	;
343	sync
344	ssm		0,0
345	SFDIAG		(15)
346	ssm		0,0
347	MFDIAG_1	(28)
348	ssm		0,0
349	b,n         perf_rdr_shift_in_W_leave
350	nop
351
352	;
353	; RDR 16 read sequence
354	;
355	sync
356	ssm		0,0
357	SFDIAG		(16)
358	ssm		0,0
359	MFDIAG_1	(28)
360	b,n         perf_rdr_shift_in_W_leave
361	ssm		0,0
362	nop
363
364	;
365	; RDR 17 read sequence
366	;
367	SFDIAG		(17)
368	ssm		0,0
369	MFDIAG_1	(28)
370	shrpd		ret0,%r0,%sar,%r1
371	MTDIAG_1	(1)
372	STDIAG		(17)
373	ssm		0,0
374	b,n         perf_rdr_shift_in_W_leave
375
376	;
377	; RDR 18 read sequence
378	;
379	SFDIAG		(18)
380	ssm		0,0
381	MFDIAG_1	(28)
382	shrpd		ret0,%r0,%sar,%r1
383	MTDIAG_1	(1)
384	STDIAG		(18)
385	ssm		0,0
386	b,n         perf_rdr_shift_in_W_leave
387
388	;
389	; RDR 19 read sequence
390	;
391	b,n         perf_rdr_shift_in_W_leave
392	nop
393	nop
394	nop
395	nop
396	nop
397	nop
398	nop
399
400	;
401	; RDR 20 read sequence
402	;
403	sync
404	ssm		0,0
405	SFDIAG		(20)
406	ssm		0,0
407	MFDIAG_1	(28)
408	b,n         perf_rdr_shift_in_W_leave
409	ssm		0,0
410	nop
411
412	;
413	; RDR 21 read sequence
414	;
415	sync
416	ssm		0,0
417	SFDIAG		(21)
418	ssm		0,0
419	MFDIAG_1	(28)
420	b,n         perf_rdr_shift_in_W_leave
421	ssm		0,0
422	nop
423
424	;
425	; RDR 22 read sequence
426	;
427	sync
428	ssm		0,0
429	SFDIAG		(22)
430	ssm		0,0
431	MFDIAG_1	(28)
432	b,n         perf_rdr_shift_in_W_leave
433	ssm		0,0
434	nop
435
436	;
437	; RDR 23 read sequence
438	;
439	sync
440	ssm		0,0
441	SFDIAG		(23)
442	ssm		0,0
443	MFDIAG_1	(28)
444	b,n         perf_rdr_shift_in_W_leave
445	ssm		0,0
446	nop
447
448	;
449	; RDR 24 read sequence
450	;
451	sync
452	ssm		0,0
453	SFDIAG		(24)
454	ssm		0,0
455	MFDIAG_1	(28)
456	b,n         perf_rdr_shift_in_W_leave
457	ssm		0,0
458	nop
459
460	;
461	; RDR 25 read sequence
462	;
463	sync
464	ssm		0,0
465	SFDIAG		(25)
466	ssm		0,0
467	MFDIAG_1	(28)
468	b,n         perf_rdr_shift_in_W_leave
469	ssm		0,0
470	nop
471
472	;
473	; RDR 26 read sequence
474	;
475	SFDIAG		(26)
476	ssm		0,0
477	MFDIAG_1	(28)
478	shrpd		ret0,%r0,%sar,%r1
479	MTDIAG_1	(1)
480	STDIAG		(26)
481	ssm		0,0
482	b,n         perf_rdr_shift_in_W_leave
483
484	;
485	; RDR 27 read sequence
486	;
487	SFDIAG		(27)
488	ssm		0,0
489	MFDIAG_1	(28)
490	shrpd		ret0,%r0,%sar,%r1
491	MTDIAG_1	(1)
492	STDIAG		(27)
493	ssm		0,0
494	b,n         perf_rdr_shift_in_W_leave
495
496	;
497	; RDR 28 read sequence
498	;
499	sync
500	ssm		0,0
501	SFDIAG		(28)
502	ssm		0,0
503	MFDIAG_1	(28)
504	b,n         perf_rdr_shift_in_W_leave
505	ssm		0,0
506	nop
507
508	;
509	; RDR 29 read sequence
510	;
511	sync
512	ssm		0,0
513	SFDIAG		(29)
514	ssm		0,0
515	MFDIAG_1	(28)
516	b,n         perf_rdr_shift_in_W_leave
517	ssm		0,0
518	nop
519
520	;
521	; RDR 30 read sequence
522	;
523	SFDIAG		(30)
524	ssm		0,0
525	MFDIAG_1	(28)
526	shrpd		ret0,%r0,%sar,%r1
527	MTDIAG_1	(1)
528	STDIAG		(30)
529	ssm		0,0
530	b,n         perf_rdr_shift_in_W_leave
531
532	;
533	; RDR 31 read sequence
534	;
535	sync
536	ssm		0,0
537	SFDIAG		(31)
538	ssm		0,0
539	MFDIAG_1	(28)
540	nop
541	ssm		0,0
542	nop
543
544	;
545	; Fallthrough
546	;
547
548perf_rdr_shift_in_W_leave:
549	bve		    (%r2)
550	.exit
551	MTDIAG_2	(24)			; restore DR2
552	.procend
553
554
555;***********************************************************************
556;*
557;* Name: perf_rdr_shift_out_W
558;*
559;* Description:
560;*	This routine moves data to the RDR's.  The double-word that
561;*	arg1 points to is loaded and moved into the staging register.
562;*	Then the STDIAG instruction for the RDR # in arg0 is called
563;*	to move the data to the RDR.
564;*
565;* Arguments:
566;*	arg0 = rdr number
567;*	arg1 = 64-bit value to write
568;*	%r24 - DR2 | DR2_SLOW_RET
569;*	%r23 - original DR2 value
570;*
571;* Returns:
572;*	None
573;*
574;* Register usage:
575;*
576;***********************************************************************
577
578	.export perf_rdr_shift_out_W,code
579perf_rdr_shift_out_W:
580	.proc
581	.callinfo frame=0,NO_CALLS
582	.entry
583;
584; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
585; shifting is done, from or to, the remote diagnose registers.
586;
587
588	depdi,z		1,DR2_SLOW_RET,1,%r24
589	MFDIAG_2	(23)
590	or		%r24,%r23,%r24
591	MTDIAG_2	(24)		; set DR2_SLOW_RET
592	MTDIAG_1	(25)		; data to the staging register
593	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
594	blr		    %r1,%r0	; branch to 8-instruction sequence
595	nop
596
597	;
598	; RDR 0 write sequence
599	;
600	sync				; RDR 0 write sequence
601	ssm		0,0
602	STDIAG		(0)
603	ssm		0,0
604	b,n         perf_rdr_shift_out_W_leave
605	nop
606	ssm		0,0
607	nop
608
609	;
610	; RDR 1 write sequence
611	;
612	sync
613	ssm		0,0
614	STDIAG		(1)
615	ssm		0,0
616	b,n         perf_rdr_shift_out_W_leave
617	nop
618	ssm		0,0
619	nop
620
621	;
622	; RDR 2 write sequence
623	;
624	sync
625	ssm		0,0
626	STDIAG		(2)
627	ssm		0,0
628	b,n         perf_rdr_shift_out_W_leave
629	nop
630	ssm		0,0
631	nop
632
633	;
634	; RDR 3 write sequence
635	;
636	sync
637	ssm		0,0
638	STDIAG		(3)
639	ssm		0,0
640	b,n         perf_rdr_shift_out_W_leave
641	nop
642	ssm		0,0
643	nop
644
645	;
646	; RDR 4 write sequence
647	;
648	sync
649	ssm		0,0
650	STDIAG		(4)
651	ssm		0,0
652	b,n         perf_rdr_shift_out_W_leave
653	nop
654	ssm		0,0
655	nop
656
657	;
658	; RDR 5 write sequence
659	;
660	sync
661	ssm		0,0
662	STDIAG		(5)
663	ssm		0,0
664	b,n         perf_rdr_shift_out_W_leave
665	nop
666	ssm		0,0
667	nop
668
669	;
670	; RDR 6 write sequence
671	;
672	sync
673	ssm		0,0
674	STDIAG		(6)
675	ssm		0,0
676	b,n         perf_rdr_shift_out_W_leave
677	nop
678	ssm		0,0
679	nop
680
681	;
682	; RDR 7 write sequence
683	;
684	sync
685	ssm		0,0
686	STDIAG		(7)
687	ssm		0,0
688	b,n         perf_rdr_shift_out_W_leave
689	nop
690	ssm		0,0
691	nop
692
693	;
694	; RDR 8 write sequence
695	;
696	sync
697	ssm		0,0
698	STDIAG		(8)
699	ssm		0,0
700	b,n         perf_rdr_shift_out_W_leave
701	nop
702	ssm		0,0
703	nop
704
705	;
706	; RDR 9 write sequence
707	;
708	sync
709	ssm		0,0
710	STDIAG		(9)
711	ssm		0,0
712	b,n         perf_rdr_shift_out_W_leave
713	nop
714	ssm		0,0
715	nop
716
717	;
718	; RDR 10 write sequence
719	;
720	sync
721	ssm		0,0
722	STDIAG		(10)
723	STDIAG		(26)
724	ssm		0,0
725	b,n         perf_rdr_shift_out_W_leave
726	ssm		0,0
727	nop
728
729	;
730	; RDR 11 write sequence
731	;
732	sync
733	ssm		0,0
734	STDIAG		(11)
735	STDIAG		(27)
736	ssm		0,0
737	b,n         perf_rdr_shift_out_W_leave
738	ssm		0,0
739	nop
740
741	;
742	; RDR 12 write sequence
743	;
744	sync
745	ssm		0,0
746	STDIAG		(12)
747	ssm		0,0
748	b,n         perf_rdr_shift_out_W_leave
749	nop
750	ssm		0,0
751	nop
752
753	;
754	; RDR 13 write sequence
755	;
756	sync
757	ssm		0,0
758	STDIAG		(13)
759	ssm		0,0
760	b,n         perf_rdr_shift_out_W_leave
761	nop
762	ssm		0,0
763	nop
764
765	;
766	; RDR 14 write sequence
767	;
768	sync
769	ssm		0,0
770	STDIAG		(14)
771	ssm		0,0
772	b,n         perf_rdr_shift_out_W_leave
773	nop
774	ssm		0,0
775	nop
776
777	;
778	; RDR 15 write sequence
779	;
780	sync
781	ssm		0,0
782	STDIAG		(15)
783	ssm		0,0
784	b,n         perf_rdr_shift_out_W_leave
785	nop
786	ssm		0,0
787	nop
788
789	;
790	; RDR 16 write sequence
791	;
792	sync
793	ssm		0,0
794	STDIAG		(16)
795	ssm		0,0
796	b,n         perf_rdr_shift_out_W_leave
797	nop
798	ssm		0,0
799	nop
800
801	;
802	; RDR 17 write sequence
803	;
804	sync
805	ssm		0,0
806	STDIAG		(17)
807	ssm		0,0
808	b,n         perf_rdr_shift_out_W_leave
809	nop
810	ssm		0,0
811	nop
812
813	;
814	; RDR 18 write sequence
815	;
816	sync
817	ssm		0,0
818	STDIAG		(18)
819	ssm		0,0
820	b,n         perf_rdr_shift_out_W_leave
821	nop
822	ssm		0,0
823	nop
824
825	;
826	; RDR 19 write sequence
827	;
828	sync
829	ssm		0,0
830	STDIAG		(19)
831	ssm		0,0
832	b,n         perf_rdr_shift_out_W_leave
833	nop
834	ssm		0,0
835	nop
836
837	;
838	; RDR 20 write sequence
839	;
840	sync
841	ssm		0,0
842	STDIAG		(20)
843	ssm		0,0
844	b,n         perf_rdr_shift_out_W_leave
845	nop
846	ssm		0,0
847	nop
848
849	;
850	; RDR 21 write sequence
851	;
852	sync
853	ssm		0,0
854	STDIAG		(21)
855	ssm		0,0
856	b,n         perf_rdr_shift_out_W_leave
857	nop
858	ssm		0,0
859	nop
860
861	;
862	; RDR 22 write sequence
863	;
864	sync
865	ssm		0,0
866	STDIAG		(22)
867	ssm		0,0
868	b,n         perf_rdr_shift_out_W_leave
869	nop
870	ssm		0,0
871	nop
872
873	;
874	; RDR 23 write sequence
875	;
876	sync
877	ssm		0,0
878	STDIAG		(23)
879	ssm		0,0
880	b,n         perf_rdr_shift_out_W_leave
881	nop
882	ssm		0,0
883	nop
884
885	;
886	; RDR 24 write sequence
887	;
888	sync
889	ssm		0,0
890	STDIAG		(24)
891	ssm		0,0
892	b,n         perf_rdr_shift_out_W_leave
893	nop
894	ssm		0,0
895	nop
896
897	;
898	; RDR 25 write sequence
899	;
900	sync
901	ssm		0,0
902	STDIAG		(25)
903	ssm		0,0
904	b,n         perf_rdr_shift_out_W_leave
905	nop
906	ssm		0,0
907	nop
908
909	;
910	; RDR 26 write sequence
911	;
912	sync
913	ssm		0,0
914	STDIAG		(10)
915	STDIAG		(26)
916	ssm		0,0
917	b,n         perf_rdr_shift_out_W_leave
918	ssm		0,0
919	nop
920
921	;
922	; RDR 27 write sequence
923	;
924	sync
925	ssm		0,0
926	STDIAG		(11)
927	STDIAG		(27)
928	ssm		0,0
929	b,n         perf_rdr_shift_out_W_leave
930	ssm		0,0
931	nop
932
933	;
934	; RDR 28 write sequence
935	;
936	sync
937	ssm		0,0
938	STDIAG		(28)
939	ssm		0,0
940	b,n         perf_rdr_shift_out_W_leave
941	nop
942	ssm		0,0
943	nop
944
945	;
946	; RDR 29 write sequence
947	;
948	sync
949	ssm		0,0
950	STDIAG		(29)
951	ssm		0,0
952	b,n         perf_rdr_shift_out_W_leave
953	nop
954	ssm		0,0
955	nop
956
957	;
958	; RDR 30 write sequence
959	;
960	sync
961	ssm		0,0
962	STDIAG		(30)
963	ssm		0,0
964	b,n         perf_rdr_shift_out_W_leave
965	nop
966	ssm		0,0
967	nop
968
969	;
970	; RDR 31 write sequence
971	;
972	sync
973	ssm		0,0
974	STDIAG		(31)
975	ssm		0,0
976	b,n         perf_rdr_shift_out_W_leave
977	nop
978	ssm		0,0
979	nop
980
981perf_rdr_shift_out_W_leave:
982	bve		(%r2)
983	.exit
984	MTDIAG_2	(23)			; restore DR2
985	.procend
986
987
988;***********************************************************************
989;*
990;* Name: rdr_shift_in_U
991;*
992;* Description:
993;*	This routine shifts data in from the RDR in arg0 and returns
994;*	the result in ret0.  If the RDR is <= 64 bits in length, it
995;*	is shifted shifted backup immediately.  This is to compensate
996;*	for RDR10 which has bits that preclude PDC stack operations
997;*	when they are in the wrong state.
998;*
999;* Arguments:
1000;*	arg0 : rdr to be read
1001;*	arg1 : bit length of rdr
1002;*
1003;* Returns:
1004;*	ret0 = next 64 bits of rdr data from staging register
1005;*
1006;* Register usage:
1007;*	arg0 : rdr to be read
1008;*	arg1 : bit length of rdr
1009;*	%r24 - original DR2 value
1010;*	%r23 - DR2 | DR2_SLOW_RET
1011;*	%r1  - scratch
1012;*
1013;***********************************************************************
1014
1015	.export perf_rdr_shift_in_U,code
1016perf_rdr_shift_in_U:
1017	.proc
1018	.callinfo frame=0,NO_CALLS
1019	.entry
1020
1021; read(shift in) the RDR.
1022;
1023; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1024; shifting is done, from or to, remote diagnose registers.
1025
1026	depdi,z		1,DR2_SLOW_RET,1,%r29
1027	MFDIAG_2	(24)
1028	or			%r24,%r29,%r29
1029	MTDIAG_2	(29)			; set DR2_SLOW_RET
1030
1031	nop
1032	nop
1033	nop
1034	nop
1035
1036;
1037; Start of next 32-byte cacheline
1038;
1039	nop
1040	nop
1041	nop
1042	extrd,u		arg1,63,6,%r1
1043
1044	mtsar		%r1
1045	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1046	blr 		%r1,%r0		; branch to 8-instruction sequence
1047	nop
1048
1049;
1050; Start of next 32-byte cacheline
1051;
1052	SFDIAG		(0)		; RDR 0 read sequence
1053	ssm		0,0
1054	MFDIAG_1	(28)
1055	shrpd		ret0,%r0,%sar,%r1
1056	MTDIAG_1	(1)
1057	STDIAG		(0)
1058	ssm		0,0
1059	b,n         perf_rdr_shift_in_U_leave
1060
1061	SFDIAG		(1)		; RDR 1 read sequence
1062	ssm		0,0
1063	MFDIAG_1	(28)
1064	shrpd		ret0,%r0,%sar,%r1
1065	MTDIAG_1	(1)
1066	STDIAG		(1)
1067	ssm		0,0
1068	b,n         perf_rdr_shift_in_U_leave
1069
1070	sync				; RDR 2 read sequence
1071	ssm		0,0
1072	SFDIAG		(4)
1073	ssm		0,0
1074	MFDIAG_1	(28)
1075	b,n         perf_rdr_shift_in_U_leave
1076	ssm		0,0
1077	nop
1078
1079	sync				; RDR 3 read sequence
1080	ssm		0,0
1081	SFDIAG		(3)
1082	ssm		0,0
1083	MFDIAG_1	(28)
1084	b,n         perf_rdr_shift_in_U_leave
1085	ssm		0,0
1086	nop
1087
1088	sync				; RDR 4 read sequence
1089	ssm		0,0
1090	SFDIAG		(4)
1091	ssm		0,0
1092	MFDIAG_1	(28)
1093	b,n         perf_rdr_shift_in_U_leave
1094	ssm		0,0
1095	nop
1096
1097	sync				; RDR 5 read sequence
1098	ssm		0,0
1099	SFDIAG		(5)
1100	ssm		0,0
1101	MFDIAG_1	(28)
1102	b,n         perf_rdr_shift_in_U_leave
1103	ssm		0,0
1104	nop
1105
1106	sync				; RDR 6 read sequence
1107	ssm		0,0
1108	SFDIAG		(6)
1109	ssm		0,0
1110	MFDIAG_1	(28)
1111	b,n         perf_rdr_shift_in_U_leave
1112	ssm		0,0
1113	nop
1114
1115	sync				; RDR 7 read sequence
1116	ssm		0,0
1117	SFDIAG		(7)
1118	ssm		0,0
1119	MFDIAG_1	(28)
1120	b,n         perf_rdr_shift_in_U_leave
1121	ssm		0,0
1122	nop
1123
1124	b,n         perf_rdr_shift_in_U_leave
1125	nop
1126	nop
1127	nop
1128	nop
1129	nop
1130	nop
1131	nop
1132
1133	SFDIAG		(9)		; RDR 9 read sequence
1134	ssm		0,0
1135	MFDIAG_1	(28)
1136	shrpd		ret0,%r0,%sar,%r1
1137	MTDIAG_1	(1)
1138	STDIAG		(9)
1139	ssm		0,0
1140	b,n         perf_rdr_shift_in_U_leave
1141
1142	SFDIAG		(10)		; RDR 10 read sequence
1143	ssm		0,0
1144	MFDIAG_1	(28)
1145	shrpd		ret0,%r0,%sar,%r1
1146	MTDIAG_1	(1)
1147	STDIAG		(10)
1148	ssm		0,0
1149	b,n         perf_rdr_shift_in_U_leave
1150
1151	SFDIAG		(11)		; RDR 11 read sequence
1152	ssm		0,0
1153	MFDIAG_1	(28)
1154	shrpd		ret0,%r0,%sar,%r1
1155	MTDIAG_1	(1)
1156	STDIAG		(11)
1157	ssm		0,0
1158	b,n         perf_rdr_shift_in_U_leave
1159
1160	SFDIAG		(12)		; RDR 12 read sequence
1161	ssm		0,0
1162	MFDIAG_1	(28)
1163	shrpd		ret0,%r0,%sar,%r1
1164	MTDIAG_1	(1)
1165	STDIAG		(12)
1166	ssm		0,0
1167	b,n         perf_rdr_shift_in_U_leave
1168
1169	SFDIAG		(13)		; RDR 13 read sequence
1170	ssm		0,0
1171	MFDIAG_1	(28)
1172	shrpd		ret0,%r0,%sar,%r1
1173	MTDIAG_1	(1)
1174	STDIAG		(13)
1175	ssm		0,0
1176	b,n         perf_rdr_shift_in_U_leave
1177
1178	SFDIAG		(14)		; RDR 14 read sequence
1179	ssm		0,0
1180	MFDIAG_1	(28)
1181	shrpd		ret0,%r0,%sar,%r1
1182	MTDIAG_1	(1)
1183	STDIAG		(14)
1184	ssm		0,0
1185	b,n         perf_rdr_shift_in_U_leave
1186
1187	SFDIAG		(15)		; RDR 15 read sequence
1188	ssm		0,0
1189	MFDIAG_1	(28)
1190	shrpd		ret0,%r0,%sar,%r1
1191	MTDIAG_1	(1)
1192	STDIAG		(15)
1193	ssm		0,0
1194	b,n         perf_rdr_shift_in_U_leave
1195
1196	sync				; RDR 16 read sequence
1197	ssm		0,0
1198	SFDIAG		(16)
1199	ssm		0,0
1200	MFDIAG_1	(28)
1201	b,n         perf_rdr_shift_in_U_leave
1202	ssm		0,0
1203	nop
1204
1205	SFDIAG		(17)		; RDR 17 read sequence
1206	ssm		0,0
1207	MFDIAG_1	(28)
1208	shrpd		ret0,%r0,%sar,%r1
1209	MTDIAG_1	(1)
1210	STDIAG		(17)
1211	ssm		0,0
1212	b,n         perf_rdr_shift_in_U_leave
1213
1214	SFDIAG		(18)		; RDR 18 read sequence
1215	ssm		0,0
1216	MFDIAG_1	(28)
1217	shrpd		ret0,%r0,%sar,%r1
1218	MTDIAG_1	(1)
1219	STDIAG		(18)
1220	ssm		0,0
1221	b,n         perf_rdr_shift_in_U_leave
1222
1223	b,n         perf_rdr_shift_in_U_leave
1224	nop
1225	nop
1226	nop
1227	nop
1228	nop
1229	nop
1230	nop
1231
1232	sync				; RDR 20 read sequence
1233	ssm		0,0
1234	SFDIAG		(20)
1235	ssm		0,0
1236	MFDIAG_1	(28)
1237	b,n         perf_rdr_shift_in_U_leave
1238	ssm		0,0
1239	nop
1240
1241	sync				; RDR 21 read sequence
1242	ssm		0,0
1243	SFDIAG		(21)
1244	ssm		0,0
1245	MFDIAG_1	(28)
1246	b,n         perf_rdr_shift_in_U_leave
1247	ssm		0,0
1248	nop
1249
1250	sync				; RDR 22 read sequence
1251	ssm		0,0
1252	SFDIAG		(22)
1253	ssm		0,0
1254	MFDIAG_1	(28)
1255	b,n         perf_rdr_shift_in_U_leave
1256	ssm		0,0
1257	nop
1258
1259	sync				; RDR 23 read sequence
1260	ssm		0,0
1261	SFDIAG		(23)
1262	ssm		0,0
1263	MFDIAG_1	(28)
1264	b,n         perf_rdr_shift_in_U_leave
1265	ssm		0,0
1266	nop
1267
1268	sync				; RDR 24 read sequence
1269	ssm		0,0
1270	SFDIAG		(24)
1271	ssm		0,0
1272	MFDIAG_1	(28)
1273	b,n         perf_rdr_shift_in_U_leave
1274	ssm		0,0
1275	nop
1276
1277	sync				; RDR 25 read sequence
1278	ssm		0,0
1279	SFDIAG		(25)
1280	ssm		0,0
1281	MFDIAG_1	(28)
1282	b,n         perf_rdr_shift_in_U_leave
1283	ssm		0,0
1284	nop
1285
1286	SFDIAG		(26)		; RDR 26 read sequence
1287	ssm		0,0
1288	MFDIAG_1	(28)
1289	shrpd		ret0,%r0,%sar,%r1
1290	MTDIAG_1	(1)
1291	STDIAG		(26)
1292	ssm		0,0
1293	b,n         perf_rdr_shift_in_U_leave
1294
1295	SFDIAG		(27)		; RDR 27 read sequence
1296	ssm		0,0
1297	MFDIAG_1	(28)
1298	shrpd		ret0,%r0,%sar,%r1
1299	MTDIAG_1	(1)
1300	STDIAG		(27)
1301	ssm		0,0
1302	b,n         perf_rdr_shift_in_U_leave
1303
1304	sync				; RDR 28 read sequence
1305	ssm		0,0
1306	SFDIAG		(28)
1307	ssm		0,0
1308	MFDIAG_1	(28)
1309	b,n         perf_rdr_shift_in_U_leave
1310	ssm		0,0
1311	nop
1312
1313	b,n         perf_rdr_shift_in_U_leave
1314	nop
1315	nop
1316	nop
1317	nop
1318	nop
1319	nop
1320	nop
1321
1322	SFDIAG		(30)		; RDR 30 read sequence
1323	ssm		0,0
1324	MFDIAG_1	(28)
1325	shrpd		ret0,%r0,%sar,%r1
1326	MTDIAG_1	(1)
1327	STDIAG		(30)
1328	ssm		0,0
1329	b,n         perf_rdr_shift_in_U_leave
1330
1331	SFDIAG		(31)		; RDR 31 read sequence
1332	ssm		0,0
1333	MFDIAG_1	(28)
1334	shrpd		ret0,%r0,%sar,%r1
1335	MTDIAG_1	(1)
1336	STDIAG		(31)
1337	ssm		0,0
1338	b,n         perf_rdr_shift_in_U_leave
1339	nop
1340
1341perf_rdr_shift_in_U_leave:
1342	bve		    (%r2)
1343	.exit
1344	MTDIAG_2	(24)			; restore DR2
1345	.procend
1346
1347;***********************************************************************
1348;*
1349;* Name: rdr_shift_out_U
1350;*
1351;* Description:
1352;*	This routine moves data to the RDR's.  The double-word that
1353;*	arg1 points to is loaded and moved into the staging register.
1354;*	Then the STDIAG instruction for the RDR # in arg0 is called
1355;*	to move the data to the RDR.
1356;*
1357;* Arguments:
1358;*	arg0 = rdr target
1359;*	arg1 = buffer pointer
1360;*
1361;* Returns:
1362;*	None
1363;*
1364;* Register usage:
1365;*	arg0 = rdr target
1366;*	arg1 = buffer pointer
1367;*	%r24 - DR2 | DR2_SLOW_RET
1368;*	%r23 - original DR2 value
1369;*
1370;***********************************************************************
1371
1372	.export perf_rdr_shift_out_U,code
1373perf_rdr_shift_out_U:
1374	.proc
1375	.callinfo frame=0,NO_CALLS
1376	.entry
1377
1378;
1379; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1380; shifting is done, from or to, the remote diagnose registers.
1381;
1382
1383	depdi,z		1,DR2_SLOW_RET,1,%r24
1384	MFDIAG_2	(23)
1385	or		%r24,%r23,%r24
1386	MTDIAG_2	(24)		; set DR2_SLOW_RET
1387
1388	MTDIAG_1	(25)		; data to the staging register
1389	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1390	blr		%r1,%r0		; branch to 8-instruction sequence
1391	nop
1392
1393;
1394; 32-byte cachline aligned
1395;
1396
1397	sync				; RDR 0 write sequence
1398	ssm		0,0
1399	STDIAG		(0)
1400	ssm		0,0
1401	b,n         perf_rdr_shift_out_U_leave
1402	nop
1403	ssm		0,0
1404	nop
1405
1406	sync				; RDR 1 write sequence
1407	ssm		0,0
1408	STDIAG		(1)
1409	ssm		0,0
1410	b,n         perf_rdr_shift_out_U_leave
1411	nop
1412	ssm		0,0
1413	nop
1414
1415	sync				; RDR 2 write sequence
1416	ssm		0,0
1417	STDIAG		(2)
1418	ssm		0,0
1419	b,n         perf_rdr_shift_out_U_leave
1420	nop
1421	ssm		0,0
1422	nop
1423
1424	sync				; RDR 3 write sequence
1425	ssm		0,0
1426	STDIAG		(3)
1427	ssm		0,0
1428	b,n         perf_rdr_shift_out_U_leave
1429	nop
1430	ssm		0,0
1431	nop
1432
1433	sync				; RDR 4 write sequence
1434	ssm		0,0
1435	STDIAG		(4)
1436	ssm		0,0
1437	b,n         perf_rdr_shift_out_U_leave
1438	nop
1439	ssm		0,0
1440	nop
1441
1442	sync				; RDR 5 write sequence
1443	ssm		0,0
1444	STDIAG		(5)
1445	ssm		0,0
1446	b,n         perf_rdr_shift_out_U_leave
1447	nop
1448	ssm		0,0
1449	nop
1450
1451	sync				; RDR 6 write sequence
1452	ssm		0,0
1453	STDIAG		(6)
1454	ssm		0,0
1455	b,n         perf_rdr_shift_out_U_leave
1456	nop
1457	ssm		0,0
1458	nop
1459
1460	sync				; RDR 7 write sequence
1461	ssm		0,0
1462	STDIAG		(7)
1463	ssm		0,0
1464	b,n         perf_rdr_shift_out_U_leave
1465	nop
1466	ssm		0,0
1467	nop
1468
1469	sync				; RDR 8 write sequence
1470	ssm		0,0
1471	STDIAG		(8)
1472	ssm		0,0
1473	b,n         perf_rdr_shift_out_U_leave
1474	nop
1475	ssm		0,0
1476	nop
1477
1478	sync				; RDR 9 write sequence
1479	ssm		0,0
1480	STDIAG		(9)
1481	ssm		0,0
1482	b,n         perf_rdr_shift_out_U_leave
1483	nop
1484	ssm		0,0
1485	nop
1486
1487	sync				; RDR 10 write sequence
1488	ssm		0,0
1489	STDIAG		(10)
1490	ssm		0,0
1491	b,n         perf_rdr_shift_out_U_leave
1492	nop
1493	ssm		0,0
1494	nop
1495
1496	sync				; RDR 11 write sequence
1497	ssm		0,0
1498	STDIAG		(11)
1499	ssm		0,0
1500	b,n         perf_rdr_shift_out_U_leave
1501	nop
1502	ssm		0,0
1503	nop
1504
1505	sync				; RDR 12 write sequence
1506	ssm		0,0
1507	STDIAG		(12)
1508	ssm		0,0
1509	b,n         perf_rdr_shift_out_U_leave
1510	nop
1511	ssm		0,0
1512	nop
1513
1514	sync				; RDR 13 write sequence
1515	ssm		0,0
1516	STDIAG		(13)
1517	ssm		0,0
1518	b,n         perf_rdr_shift_out_U_leave
1519	nop
1520	ssm		0,0
1521	nop
1522
1523	sync				; RDR 14 write sequence
1524	ssm		0,0
1525	STDIAG		(14)
1526	ssm		0,0
1527	b,n         perf_rdr_shift_out_U_leave
1528	nop
1529	ssm		0,0
1530	nop
1531
1532	sync				; RDR 15 write sequence
1533	ssm		0,0
1534	STDIAG		(15)
1535	ssm		0,0
1536	b,n         perf_rdr_shift_out_U_leave
1537	nop
1538	ssm		0,0
1539	nop
1540
1541	sync				; RDR 16 write sequence
1542	ssm		0,0
1543	STDIAG		(16)
1544	ssm		0,0
1545	b,n         perf_rdr_shift_out_U_leave
1546	nop
1547	ssm		0,0
1548	nop
1549
1550	sync				; RDR 17 write sequence
1551	ssm		0,0
1552	STDIAG		(17)
1553	ssm		0,0
1554	b,n         perf_rdr_shift_out_U_leave
1555	nop
1556	ssm		0,0
1557	nop
1558
1559	sync				; RDR 18 write sequence
1560	ssm		0,0
1561	STDIAG		(18)
1562	ssm		0,0
1563	b,n         perf_rdr_shift_out_U_leave
1564	nop
1565	ssm		0,0
1566	nop
1567
1568	sync				; RDR 19 write sequence
1569	ssm		0,0
1570	STDIAG		(19)
1571	ssm		0,0
1572	b,n         perf_rdr_shift_out_U_leave
1573	nop
1574	ssm		0,0
1575	nop
1576
1577	sync				; RDR 20 write sequence
1578	ssm		0,0
1579	STDIAG		(20)
1580	ssm		0,0
1581	b,n         perf_rdr_shift_out_U_leave
1582	nop
1583	ssm		0,0
1584	nop
1585
1586	sync				; RDR 21 write sequence
1587	ssm		0,0
1588	STDIAG		(21)
1589	ssm		0,0
1590	b,n         perf_rdr_shift_out_U_leave
1591	nop
1592	ssm		0,0
1593	nop
1594
1595	sync				; RDR 22 write sequence
1596	ssm		0,0
1597	STDIAG		(22)
1598	ssm		0,0
1599	b,n         perf_rdr_shift_out_U_leave
1600	nop
1601	ssm		0,0
1602	nop
1603
1604	sync				; RDR 23 write sequence
1605	ssm		0,0
1606	STDIAG		(23)
1607	ssm		0,0
1608	b,n         perf_rdr_shift_out_U_leave
1609	nop
1610	ssm		0,0
1611	nop
1612
1613	sync				; RDR 24 write sequence
1614	ssm		0,0
1615	STDIAG		(24)
1616	ssm		0,0
1617	b,n         perf_rdr_shift_out_U_leave
1618	nop
1619	ssm		0,0
1620	nop
1621
1622	sync				; RDR 25 write sequence
1623	ssm		0,0
1624	STDIAG		(25)
1625	ssm		0,0
1626	b,n         perf_rdr_shift_out_U_leave
1627	nop
1628	ssm		0,0
1629	nop
1630
1631	sync				; RDR 26 write sequence
1632	ssm		0,0
1633	STDIAG		(26)
1634	ssm		0,0
1635	b,n         perf_rdr_shift_out_U_leave
1636	nop
1637	ssm		0,0
1638	nop
1639
1640	sync				; RDR 27 write sequence
1641	ssm		0,0
1642	STDIAG		(27)
1643	ssm		0,0
1644	b,n         perf_rdr_shift_out_U_leave
1645	nop
1646	ssm		0,0
1647	nop
1648
1649	sync				; RDR 28 write sequence
1650	ssm		0,0
1651	STDIAG		(28)
1652	ssm		0,0
1653	b,n         perf_rdr_shift_out_U_leave
1654	nop
1655	ssm		0,0
1656	nop
1657
1658	sync				; RDR 29 write sequence
1659	ssm		0,0
1660	STDIAG		(29)
1661	ssm		0,0
1662	b,n         perf_rdr_shift_out_U_leave
1663	nop
1664	ssm		0,0
1665	nop
1666
1667	sync				; RDR 30 write sequence
1668	ssm		0,0
1669	STDIAG		(30)
1670	ssm		0,0
1671	b,n         perf_rdr_shift_out_U_leave
1672	nop
1673	ssm		0,0
1674	nop
1675
1676	sync				; RDR 31 write sequence
1677	ssm		0,0
1678	STDIAG		(31)
1679	ssm		0,0
1680	b,n         perf_rdr_shift_out_U_leave
1681	nop
1682	ssm		0,0
1683	nop
1684
1685perf_rdr_shift_out_U_leave:
1686	bve		(%r2)
1687	.exit
1688	MTDIAG_2	(23)			; restore DR2
1689	.procend
1690
1691